1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * NXP XCVR ALSA SoC Digital Audio Interface (DAI) driver 4 * 5 * Copyright 2019 NXP 6 */ 7 8 #ifndef __FSL_XCVR_H 9 #define __FSL_XCVR_H 10 11 #define FSL_XCVR_MODE_SPDIF 0 12 #define FSL_XCVR_MODE_ARC 1 13 #define FSL_XCVR_MODE_EARC 2 14 15 /* XCVR Registers */ 16 #define FSL_XCVR_REG_OFFSET 0x800 /* regs offset */ 17 #define FSL_XCVR_FIFO_SIZE 0x80 /* 128 */ 18 #define FSL_XCVR_FIFO_WMK_RX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */ 19 #define FSL_XCVR_FIFO_WMK_TX (FSL_XCVR_FIFO_SIZE >> 1) /* 64 */ 20 #define FSL_XCVR_MAXBURST_RX (FSL_XCVR_FIFO_WMK_RX >> 2) /* 16 */ 21 #define FSL_XCVR_MAXBURST_TX (FSL_XCVR_FIFO_WMK_TX >> 2) /* 16 */ 22 23 #define FSL_XCVR_RX_FIFO_ADDR 0x0C00 24 #define FSL_XCVR_TX_FIFO_ADDR 0x0E00 25 26 #define FSL_XCVR_VERSION 0x00 /* Version */ 27 #define FSL_XCVR_EXT_CTRL 0x10 /* Control */ 28 #define FSL_XCVR_EXT_STATUS 0x20 /* Status */ 29 #define FSL_XCVR_EXT_IER0 0x30 /* Interrupt en 0 */ 30 #define FSL_XCVR_EXT_IER1 0x40 /* Interrupt en 1 */ 31 #define FSL_XCVR_EXT_ISR 0x50 /* Interrupt status */ 32 #define FSL_XCVR_EXT_ISR_SET 0x54 /* Interrupt status */ 33 #define FSL_XCVR_EXT_ISR_CLR 0x58 /* Interrupt status */ 34 #define FSL_XCVR_EXT_ISR_TOG 0x5C /* Interrupt status */ 35 #define FSL_XCVR_IER 0x70 /* Interrupt en for M0+ */ 36 #define FSL_XCVR_ISR 0x80 /* Interrupt status */ 37 #define FSL_XCVR_ISR_SET 0x84 /* Interrupt status set */ 38 #define FSL_XCVR_ISR_CLR 0x88 /* Interrupt status clear */ 39 #define FSL_XCVR_ISR_TOG 0x8C /* Interrupt status toggle */ 40 #define FSL_XCVR_PHY_AI_CTRL 0x90 41 #define FSL_XCVR_PHY_AI_CTRL_SET 0x94 42 #define FSL_XCVR_PHY_AI_CTRL_CLR 0x98 43 #define FSL_XCVR_PHY_AI_CTRL_TOG 0x9C 44 #define FSL_XCVR_PHY_AI_WDATA 0xA0 45 #define FSL_XCVR_PHY_AI_RDATA 0xA4 46 #define FSL_XCVR_CLK_CTRL 0xB0 47 #define FSL_XCVR_RX_DPTH_CTRL 0x180 /* RX datapath ctrl reg */ 48 #define FSL_XCVR_RX_DPTH_CTRL_SET 0x184 49 #define FSL_XCVR_RX_DPTH_CTRL_CLR 0x188 50 #define FSL_XCVR_RX_DPTH_CTRL_TOG 0x18c 51 52 #define FSL_XCVR_TX_DPTH_CTRL 0x220 /* TX datapath ctrl reg */ 53 #define FSL_XCVR_TX_DPTH_CTRL_SET 0x224 54 #define FSL_XCVR_TX_DPTH_CTRL_CLR 0x228 55 #define FSL_XCVR_TX_DPTH_CTRL_TOG 0x22C 56 #define FSL_XCVR_TX_CS_DATA_0 0x230 /* TX channel status bits regs */ 57 #define FSL_XCVR_TX_CS_DATA_1 0x234 58 #define FSL_XCVR_TX_CS_DATA_2 0x238 59 #define FSL_XCVR_TX_CS_DATA_3 0x23C 60 #define FSL_XCVR_TX_CS_DATA_4 0x240 61 #define FSL_XCVR_TX_CS_DATA_5 0x244 62 #define FSL_XCVR_DEBUG_REG_0 0x2E0 63 #define FSL_XCVR_DEBUG_REG_1 0x2F0 64 65 #define FSL_XCVR_MAX_REG FSL_XCVR_DEBUG_REG_1 66 67 #define FSL_XCVR_EXT_CTRL_CORE_RESET BIT(31) 68 69 #define FSL_XCVR_EXT_CTRL_RX_CMDC_RESET BIT(30) 70 #define FSL_XCVR_EXT_CTRL_TX_CMDC_RESET BIT(29) 71 #define FSL_XCVR_EXT_CTRL_CMDC_RESET(t) (t ? BIT(29) : BIT(30)) 72 73 #define FSL_XCVR_EXT_CTRL_RX_DPTH_RESET BIT(28) 74 #define FSL_XCVR_EXT_CTRL_TX_DPTH_RESET BIT(27) 75 #define FSL_XCVR_EXT_CTRL_DPTH_RESET(t) (t ? BIT(27) : BIT(28)) 76 77 #define FSL_XCVR_EXT_CTRL_TX_RX_MODE BIT(26) 78 #define FSL_XCVR_EXT_CTRL_DMA_RD_DIS BIT(25) 79 #define FSL_XCVR_EXT_CTRL_DMA_WR_DIS BIT(24) 80 #define FSL_XCVR_EXT_CTRL_DMA_DIS(t) (t ? BIT(24) : BIT(25)) 81 #define FSL_XCVR_EXT_CTRL_SPDIF_MODE BIT(23) 82 #define FSL_XCVR_EXT_CTRL_SLEEP_MODE BIT(21) 83 84 #define FSL_XCVR_EXT_CTRL_TX_FWM_SHFT 0 85 #define FSL_XCVR_EXT_CTRL_TX_FWM_MASK GENMASK(6, 0) 86 #define FSL_XCVR_EXT_CTRL_TX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_TX_FWM_SHFT) \ 87 & FSL_XCVR_EXT_CTRL_TX_FWM_MASK) 88 #define FSL_XCVR_EXT_CTRL_RX_FWM_SHFT 8 89 #define FSL_XCVR_EXT_CTRL_RX_FWM_MASK GENMASK(14, 8) 90 #define FSL_XCVR_EXT_CTRL_RX_FWM(i) (((i) << FSL_XCVR_EXT_CTRL_RX_FWM_SHFT) \ 91 & FSL_XCVR_EXT_CTRL_RX_FWM_MASK) 92 #define FSL_XCVR_EXT_CTRL_PAGE_SHFT 16 93 #define FSL_XCVR_EXT_CTRL_PAGE_MASK GENMASK(19, 16) 94 #define FSL_XCVR_EXT_CTRL_PAGE(i) (((i) << FSL_XCVR_EXT_CTRL_PAGE_SHFT) \ 95 & FSL_XCVR_EXT_CTRL_PAGE_MASK) 96 97 #define FSL_XCVR_EXT_STUS_NT_FIFO_ENTR GENMASK(7, 0) 98 #define FSL_XCVR_EXT_STUS_NR_FIFO_ENTR GENMASK(15, 8) 99 #define FSL_XCVR_EXT_STUS_CM0_SLEEPING BIT(16) 100 #define FSL_XCVR_EXT_STUS_CM0_DEEP_SLP BIT(17) 101 #define FSL_XCVR_EXT_STUS_CM0_SLP_HACK BIT(18) 102 #define FSL_XCVR_EXT_STUS_RX_CMDC_RSTO BIT(23) 103 #define FSL_XCVR_EXT_STUS_TX_CMDC_RSTO BIT(24) 104 #define FSL_XCVR_EXT_STUS_RX_CMDC_COTO BIT(25) 105 #define FSL_XCVR_EXT_STUS_TX_CMDC_COTO BIT(26) 106 #define FSL_XCVR_EXT_STUS_HB_STATUS BIT(27) 107 #define FSL_XCVR_EXT_STUS_NEW_UD4_REC BIT(28) 108 #define FSL_XCVR_EXT_STUS_NEW_UD5_REC BIT(29) 109 #define FSL_XCVR_EXT_STUS_NEW_UD6_REC BIT(30) 110 #define FSL_XCVR_EXT_STUS_HPD_INPUT BIT(31) 111 112 #define FSL_XCVR_IRQ_NEW_CS BIT(0) 113 #define FSL_XCVR_IRQ_NEW_UD BIT(1) 114 #define FSL_XCVR_IRQ_MUTE BIT(2) 115 #define FSL_XCVR_IRQ_CMDC_RESP_TO BIT(3) 116 #define FSL_XCVR_IRQ_ECC_ERR BIT(4) 117 #define FSL_XCVR_IRQ_PREAMBLE_MISMATCH BIT(5) 118 #define FSL_XCVR_IRQ_FIFO_UOFL_ERR BIT(6) 119 #define FSL_XCVR_IRQ_HOST_WAKEUP BIT(7) 120 #define FSL_XCVR_IRQ_HOST_OHPD BIT(8) 121 #define FSL_XCVR_IRQ_DMAC_NO_DATA_REC BIT(9) 122 #define FSL_XCVR_IRQ_DMAC_FMT_CHG_DET BIT(10) 123 #define FSL_XCVR_IRQ_HB_STATE_CHG BIT(11) 124 #define FSL_XCVR_IRQ_CMDC_STATUS_UPD BIT(12) 125 #define FSL_XCVR_IRQ_TEMP_UPD BIT(13) 126 #define FSL_XCVR_IRQ_DMA_RD_REQ BIT(14) 127 #define FSL_XCVR_IRQ_DMA_WR_REQ BIT(15) 128 #define FSL_XCVR_IRQ_DMAC_BME_BIT_ERR BIT(16) 129 #define FSL_XCVR_IRQ_PREAMBLE_MATCH BIT(17) 130 #define FSL_XCVR_IRQ_M_W_PRE_MISMATCH BIT(18) 131 #define FSL_XCVR_IRQ_B_PRE_MISMATCH BIT(19) 132 #define FSL_XCVR_IRQ_UNEXP_PRE_REC BIT(20) 133 #define FSL_XCVR_IRQ_ARC_MODE BIT(21) 134 #define FSL_XCVR_IRQ_CH_UD_OFLOW BIT(22) 135 #define FSL_XCVR_IRQ_EARC_ALL (FSL_XCVR_IRQ_NEW_CS | \ 136 FSL_XCVR_IRQ_NEW_UD | \ 137 FSL_XCVR_IRQ_MUTE | \ 138 FSL_XCVR_IRQ_FIFO_UOFL_ERR | \ 139 FSL_XCVR_IRQ_HOST_WAKEUP | \ 140 FSL_XCVR_IRQ_ARC_MODE) 141 142 #define FSL_XCVR_ISR_CMDC_TX_EN BIT(3) 143 #define FSL_XCVR_ISR_HPD_TGL BIT(15) 144 #define FSL_XCVR_ISR_DMAC_SPARE_INT BIT(19) 145 #define FSL_XCVR_ISR_SET_SPDIF_RX_INT BIT(20) 146 #define FSL_XCVR_ISR_SET_SPDIF_TX_INT BIT(21) 147 #define FSL_XCVR_ISR_SET_SPDIF_MODE(t) (t ? BIT(21) : BIT(20)) 148 #define FSL_XCVR_ISR_SET_ARC_CM_INT BIT(22) 149 #define FSL_XCVR_ISR_SET_ARC_SE_INT BIT(23) 150 151 #define FSL_XCVR_PHY_AI_ADDR_MASK GENMASK(7, 0) 152 #define FSL_XCVR_PHY_AI_RESETN BIT(15) 153 #define FSL_XCVR_PHY_AI_TOG_PLL BIT(24) 154 #define FSL_XCVR_PHY_AI_TOG_DONE_PLL BIT(25) 155 #define FSL_XCVR_PHY_AI_TOG_PHY BIT(26) 156 #define FSL_XCVR_PHY_AI_TOG_DONE_PHY BIT(27) 157 #define FSL_XCVR_PHY_AI_RW_MASK BIT(31) 158 159 #define FSL_XCVR_RX_DPTH_CTRL_PAPB_FIFO_STATUS BIT(0) 160 #define FSL_XCVR_RX_DPTH_CTRL_DIS_PRE_ERR_CHK BIT(1) 161 #define FSL_XCVR_RX_DPTH_CTRL_DIS_NOD_REC_CHK BIT(2) 162 #define FSL_XCVR_RX_DPTH_CTRL_ECC_VUC_BIT_CHK BIT(3) 163 #define FSL_XCVR_RX_DPTH_CTRL_EN_CMP_PAR_CALC BIT(4) 164 #define FSL_XCVR_RX_DPTH_CTRL_RST_PKT_CNT_FIFO BIT(5) 165 #define FSL_XCVR_RX_DPTH_CTRL_STORE_FMT BIT(6) 166 #define FSL_XCVR_RX_DPTH_CTRL_EN_PAR_CALC BIT(7) 167 #define FSL_XCVR_RX_DPTH_CTRL_UDR BIT(8) 168 #define FSL_XCVR_RX_DPTH_CTRL_CSR BIT(9) 169 #define FSL_XCVR_RX_DPTH_CTRL_UDA BIT(10) 170 #define FSL_XCVR_RX_DPTH_CTRL_CSA BIT(11) 171 #define FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO BIT(12) 172 #define FSL_XCVR_RX_DPTH_CTRL_DIS_B_PRE_ERR_CHK BIT(13) 173 #define FSL_XCVR_RX_DPTH_CTRL_PABS BIT(19) 174 #define FSL_XCVR_RX_DPTH_CTRL_DTS_CDS BIT(20) 175 #define FSL_XCVR_RX_DPTH_CTRL_BLKC BIT(21) 176 #define FSL_XCVR_RX_DPTH_CTRL_MUTE_CTRL BIT(22) 177 #define FSL_XCVR_RX_DPTH_CTRL_MUTE_MODE BIT(23) 178 #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_CTRL BIT(24) 179 #define FSL_XCVR_RX_DPTH_CTRL_FMT_CHG_MODE BIT(25) 180 #define FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL BIT(26) 181 #define FSL_XCVR_RX_DPTH_CTRL_LAYB_MODE BIT(27) 182 #define FSL_XCVR_RX_DPTH_CTRL_PRC BIT(28) 183 #define FSL_XCVR_RX_DPTH_CTRL_COMP BIT(29) 184 #define FSL_XCVR_RX_DPTH_CTRL_FSM GENMASK(31, 30) 185 186 #define FSL_XCVR_TX_DPTH_CTRL_CS_ACK BIT(0) 187 #define FSL_XCVR_TX_DPTH_CTRL_UD_ACK BIT(1) 188 #define FSL_XCVR_TX_DPTH_CTRL_CS_MOD BIT(2) 189 #define FSL_XCVR_TX_DPTH_CTRL_UD_MOD BIT(3) 190 #define FSL_XCVR_TX_DPTH_CTRL_VLD_MOD BIT(4) 191 #define FSL_XCVR_TX_DPTH_CTRL_FRM_VLD BIT(5) 192 #define FSL_XCVR_TX_DPTH_CTRL_EN_PARITY BIT(6) 193 #define FSL_XCVR_TX_DPTH_CTRL_EN_PREAMBLE BIT(7) 194 #define FSL_XCVR_TX_DPTH_CTRL_EN_ECC_INTER BIT(8) 195 #define FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM BIT(10) 196 #define FSL_XCVR_TX_DPTH_CTRL_FRM_FMT BIT(11) 197 #define FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX BIT(14) 198 #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_STR BIT(15) 199 #define FSL_XCVR_TX_DPTH_CTRL_ADD_CYC_TX_OE_END BIT(16) 200 #define FSL_XCVR_TX_DPTH_CTRL_CLK_RATIO BIT(29) 201 #define FSL_XCVR_TX_DPTH_CTRL_TM_NO_PRE_BME GENMASK(31, 30) 202 203 #define FSL_XCVR_PHY_AI_CTRL_AI_RESETN BIT(15) 204 205 #define FSL_XCVR_PLL_CTRL0 0x00 206 #define FSL_XCVR_PLL_CTRL0_SET 0x04 207 #define FSL_XCVR_PLL_CTRL0_CLR 0x08 208 #define FSL_XCVR_PLL_NUM 0x20 209 #define FSL_XCVR_PLL_DEN 0x30 210 #define FSL_XCVR_PLL_PDIV 0x40 211 #define FSL_XCVR_PLL_BANDGAP_SET 0x54 212 #define FSL_XCVR_PHY_CTRL 0x00 213 #define FSL_XCVR_PHY_CTRL_SET 0x04 214 #define FSL_XCVR_PHY_CTRL_CLR 0x08 215 #define FSL_XCVR_PHY_CTRL2 0x70 216 #define FSL_XCVR_PHY_CTRL2_SET 0x74 217 #define FSL_XCVR_PHY_CTRL2_CLR 0x78 218 219 #define FSL_XCVR_PLL_BANDGAP_EN_VBG BIT(0) 220 #define FSL_XCVR_PLL_CTRL0_HROFF BIT(13) 221 #define FSL_XCVR_PLL_CTRL0_PWP BIT(14) 222 #define FSL_XCVR_PLL_CTRL0_CM0_EN BIT(24) 223 #define FSL_XCVR_PLL_CTRL0_CM1_EN BIT(25) 224 #define FSL_XCVR_PLL_CTRL0_CM2_EN BIT(26) 225 #define FSL_XCVR_PLL_PDIVx(v, i) ((v & 0x7) << (4 * i)) 226 227 #define FSL_XCVR_PHY_CTRL_PHY_EN BIT(0) 228 #define FSL_XCVR_PHY_CTRL_RX_CM_EN BIT(1) 229 #define FSL_XCVR_PHY_CTRL_TSDIFF_OE BIT(5) 230 #define FSL_XCVR_PHY_CTRL_SPDIF_EN BIT(8) 231 #define FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN BIT(9) 232 #define FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN BIT(10) 233 #define FSL_XCVR_PHY_CTRL_TX_CLK_MASK GENMASK(26, 25) 234 #define FSL_XCVR_PHY_CTRL_TX_CLK_HDMI_SS BIT(25) 235 #define FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS BIT(26) 236 #define FSL_XCVR_PHY_CTRL2_EARC_TXMS BIT(14) 237 238 #define FSL_XCVR_CS_DATA_0_FS_MASK GENMASK(31, 24) 239 #define FSL_XCVR_CS_DATA_0_FS_32000 0x3000000 240 #define FSL_XCVR_CS_DATA_0_FS_44100 0x0000000 241 #define FSL_XCVR_CS_DATA_0_FS_48000 0x2000000 242 #define FSL_XCVR_CS_DATA_0_FS_64000 0xB000000 243 #define FSL_XCVR_CS_DATA_0_FS_88200 0x8000000 244 #define FSL_XCVR_CS_DATA_0_FS_96000 0xA000000 245 #define FSL_XCVR_CS_DATA_0_FS_176400 0xC000000 246 #define FSL_XCVR_CS_DATA_0_FS_192000 0xE000000 247 248 #define FSL_XCVR_CS_DATA_0_CH_MASK 0x3A 249 #define FSL_XCVR_CS_DATA_0_CH_U2LPCM 0x00 250 #define FSL_XCVR_CS_DATA_0_CH_UMLPCM 0x20 251 #define FSL_XCVR_CS_DATA_0_CH_U1BAUD 0x30 252 253 #define FSL_XCVR_CS_DATA_1_CH_MASK 0xF000 254 #define FSL_XCVR_CS_DATA_1_CH_2 0x0000 255 #define FSL_XCVR_CS_DATA_1_CH_8 0x7000 256 #define FSL_XCVR_CS_DATA_1_CH_16 0xB000 257 #define FSL_XCVR_CS_DATA_1_CH_32 0x3000 258 259 /* Data memory structures */ 260 #define FSL_XCVR_RX_CS_CTRL_0 0x20 /* First RX CS control register */ 261 #define FSL_XCVR_RX_CS_CTRL_1 0x24 /* Second RX CS control register */ 262 #define FSL_XCVR_RX_CS_BUFF_0 0x80 /* First RX CS buffer */ 263 #define FSL_XCVR_RX_CS_BUFF_1 0xA0 /* Second RX CS buffer */ 264 #define FSL_XCVR_CAP_DATA_STR 0x300 /* Capabilities data structure */ 265 266 #endif /* __FSL_XCVR_H */ 267