1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/bitrev.h> 5 #include <linux/clk.h> 6 #include <linux/firmware.h> 7 #include <linux/interrupt.h> 8 #include <linux/module.h> 9 #include <linux/of_platform.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/regmap.h> 12 #include <linux/reset.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_iec958.h> 15 #include <sound/pcm_params.h> 16 17 #include "fsl_xcvr.h" 18 #include "imx-pcm.h" 19 20 #define FSL_XCVR_CAPDS_SIZE 256 21 22 struct fsl_xcvr_soc_data { 23 const char *fw_name; 24 bool spdif_only; 25 bool use_edma; 26 }; 27 28 struct fsl_xcvr { 29 const struct fsl_xcvr_soc_data *soc_data; 30 struct platform_device *pdev; 31 struct regmap *regmap; 32 struct clk *ipg_clk; 33 struct clk *pll_ipg_clk; 34 struct clk *phy_clk; 35 struct clk *spba_clk; 36 struct reset_control *reset; 37 u8 streams; 38 u32 mode; 39 u32 arc_mode; 40 void __iomem *ram_addr; 41 struct snd_dmaengine_dai_dma_data dma_prms_rx; 42 struct snd_dmaengine_dai_dma_data dma_prms_tx; 43 struct snd_aes_iec958 rx_iec958; 44 struct snd_aes_iec958 tx_iec958; 45 u8 cap_ds[FSL_XCVR_CAPDS_SIZE]; 46 }; 47 48 static const struct fsl_xcvr_pll_conf { 49 u8 mfi; /* min=0x18, max=0x38 */ 50 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */ 51 u32 mfd; /* unsigned int */ 52 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */ 53 } fsl_xcvr_pll_cfg[] = { 54 { .mfi = 54, .mfn = 1, .mfd = 6, .fout = 1300000000, }, /* 1.3 GHz */ 55 { .mfi = 32, .mfn = 96, .mfd = 125, .fout = 786432000, }, /* 8000 Hz */ 56 { .mfi = 30, .mfn = 66, .mfd = 625, .fout = 722534400, }, /* 11025 Hz */ 57 { .mfi = 29, .mfn = 1, .mfd = 6, .fout = 700000000, }, /* 700 MHz */ 58 }; 59 60 /* 61 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio 62 * stream. Todo: to check how this case can be considered below 63 */ 64 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; 65 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_channels_constr = { 66 .count = ARRAY_SIZE(fsl_xcvr_earc_channels), 67 .list = fsl_xcvr_earc_channels, 68 }; 69 70 static const u32 fsl_xcvr_earc_rates[] = { 71 32000, 44100, 48000, 64000, 88200, 96000, 72 128000, 176400, 192000, 256000, 352800, 384000, 73 512000, 705600, 768000, 1024000, 1411200, 1536000, 74 }; 75 static const struct snd_pcm_hw_constraint_list fsl_xcvr_earc_rates_constr = { 76 .count = ARRAY_SIZE(fsl_xcvr_earc_rates), 77 .list = fsl_xcvr_earc_rates, 78 }; 79 80 static const u32 fsl_xcvr_spdif_channels[] = { 2, }; 81 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_channels_constr = { 82 .count = ARRAY_SIZE(fsl_xcvr_spdif_channels), 83 .list = fsl_xcvr_spdif_channels, 84 }; 85 86 static const u32 fsl_xcvr_spdif_rates[] = { 87 32000, 44100, 48000, 88200, 96000, 176400, 192000, 88 }; 89 static const struct snd_pcm_hw_constraint_list fsl_xcvr_spdif_rates_constr = { 90 .count = ARRAY_SIZE(fsl_xcvr_spdif_rates), 91 .list = fsl_xcvr_spdif_rates, 92 }; 93 94 static int fsl_xcvr_arc_mode_put(struct snd_kcontrol *kcontrol, 95 struct snd_ctl_elem_value *ucontrol) 96 { 97 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 98 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 99 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 100 unsigned int *item = ucontrol->value.enumerated.item; 101 102 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); 103 104 return 0; 105 } 106 107 static int fsl_xcvr_arc_mode_get(struct snd_kcontrol *kcontrol, 108 struct snd_ctl_elem_value *ucontrol) 109 { 110 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 111 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 112 113 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; 114 115 return 0; 116 } 117 118 static const u32 fsl_xcvr_phy_arc_cfg[] = { 119 FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN, FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN, 120 }; 121 122 static const char * const fsl_xcvr_arc_mode[] = { "Single Ended", "Common", }; 123 static const struct soc_enum fsl_xcvr_arc_mode_enum = 124 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_arc_mode), fsl_xcvr_arc_mode); 125 static struct snd_kcontrol_new fsl_xcvr_arc_mode_kctl = 126 SOC_ENUM_EXT("ARC Mode", fsl_xcvr_arc_mode_enum, 127 fsl_xcvr_arc_mode_get, fsl_xcvr_arc_mode_put); 128 129 /* Capabilities data structure, bytes */ 130 static int fsl_xcvr_type_capds_bytes_info(struct snd_kcontrol *kcontrol, 131 struct snd_ctl_elem_info *uinfo) 132 { 133 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 134 uinfo->count = FSL_XCVR_CAPDS_SIZE; 135 136 return 0; 137 } 138 139 static int fsl_xcvr_capds_get(struct snd_kcontrol *kcontrol, 140 struct snd_ctl_elem_value *ucontrol) 141 { 142 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 143 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 144 145 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); 146 147 return 0; 148 } 149 150 static int fsl_xcvr_capds_put(struct snd_kcontrol *kcontrol, 151 struct snd_ctl_elem_value *ucontrol) 152 { 153 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 154 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 155 156 memcpy(xcvr->cap_ds, ucontrol->value.bytes.data, FSL_XCVR_CAPDS_SIZE); 157 158 return 0; 159 } 160 161 static struct snd_kcontrol_new fsl_xcvr_earc_capds_kctl = { 162 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 163 .name = "Capabilities Data Structure", 164 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 165 .info = fsl_xcvr_type_capds_bytes_info, 166 .get = fsl_xcvr_capds_get, 167 .put = fsl_xcvr_capds_put, 168 }; 169 170 static int fsl_xcvr_activate_ctl(struct snd_soc_dai *dai, const char *name, 171 bool active) 172 { 173 struct snd_soc_card *card = dai->component->card; 174 struct snd_kcontrol *kctl; 175 bool enabled; 176 177 kctl = snd_soc_card_get_kcontrol(card, name); 178 if (kctl == NULL) 179 return -ENOENT; 180 181 enabled = ((kctl->vd[0].access & SNDRV_CTL_ELEM_ACCESS_WRITE) != 0); 182 if (active == enabled) 183 return 0; /* nothing to do */ 184 185 if (active) 186 kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_WRITE; 187 else 188 kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_WRITE; 189 190 snd_ctl_notify(card->snd_card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id); 191 192 return 1; 193 } 194 195 static int fsl_xcvr_mode_put(struct snd_kcontrol *kcontrol, 196 struct snd_ctl_elem_value *ucontrol) 197 { 198 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 199 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 200 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 201 unsigned int *item = ucontrol->value.enumerated.item; 202 struct snd_soc_card *card = dai->component->card; 203 struct snd_soc_pcm_runtime *rtd; 204 205 xcvr->mode = snd_soc_enum_item_to_val(e, item[0]); 206 207 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 208 (xcvr->mode == FSL_XCVR_MODE_ARC)); 209 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 210 (xcvr->mode == FSL_XCVR_MODE_EARC)); 211 /* Allow playback for SPDIF only */ 212 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 213 rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_count = 214 (xcvr->mode == FSL_XCVR_MODE_SPDIF ? 1 : 0); 215 return 0; 216 } 217 218 static int fsl_xcvr_mode_get(struct snd_kcontrol *kcontrol, 219 struct snd_ctl_elem_value *ucontrol) 220 { 221 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 222 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 223 224 ucontrol->value.enumerated.item[0] = xcvr->mode; 225 226 return 0; 227 } 228 229 static const char * const fsl_xcvr_mode[] = { "SPDIF", "ARC RX", "eARC", }; 230 static const struct soc_enum fsl_xcvr_mode_enum = 231 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(fsl_xcvr_mode), fsl_xcvr_mode); 232 static struct snd_kcontrol_new fsl_xcvr_mode_kctl = 233 SOC_ENUM_EXT("XCVR Mode", fsl_xcvr_mode_enum, 234 fsl_xcvr_mode_get, fsl_xcvr_mode_put); 235 236 /** phy: true => phy, false => pll */ 237 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) 238 { 239 struct device *dev = &xcvr->pdev->dev; 240 u32 val, idx, tidx; 241 int ret; 242 243 idx = BIT(phy ? 26 : 24); 244 tidx = BIT(phy ? 27 : 25); 245 246 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF); 247 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg); 248 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data); 249 regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx); 250 251 ret = regmap_read_poll_timeout(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, val, 252 (val & idx) == ((val & tidx) >> 1), 253 10, 10000); 254 if (ret) 255 dev_err(dev, "AI timeout: failed to set %s reg 0x%02x=0x%08x\n", 256 phy ? "PHY" : "PLL", reg, data); 257 return ret; 258 } 259 260 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) 261 { 262 struct device *dev = &xcvr->pdev->dev; 263 u32 i, div = 0, log2; 264 int ret; 265 266 if (xcvr->soc_data->spdif_only) 267 return 0; 268 269 for (i = 0; i < ARRAY_SIZE(fsl_xcvr_pll_cfg); i++) { 270 if (fsl_xcvr_pll_cfg[i].fout % freq == 0) { 271 div = fsl_xcvr_pll_cfg[i].fout / freq; 272 break; 273 } 274 } 275 276 if (!div || i >= ARRAY_SIZE(fsl_xcvr_pll_cfg)) 277 return -EINVAL; 278 279 log2 = ilog2(div); 280 281 /* Release AI interface from reset */ 282 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 283 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 284 if (ret < 0) { 285 dev_err(dev, "Error while setting IER0: %d\n", ret); 286 return ret; 287 } 288 289 /* PLL: BANDGAP_SET: EN_VBG (enable bandgap) */ 290 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_BANDGAP_SET, 291 FSL_XCVR_PLL_BANDGAP_EN_VBG, 0); 292 293 /* PLL: CTRL0: DIV_INTEGER */ 294 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0, fsl_xcvr_pll_cfg[i].mfi, 0); 295 /* PLL: NUMERATOR: MFN */ 296 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_NUM, fsl_xcvr_pll_cfg[i].mfn, 0); 297 /* PLL: DENOMINATOR: MFD */ 298 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_DEN, fsl_xcvr_pll_cfg[i].mfd, 0); 299 /* PLL: CTRL0_SET: HOLD_RING_OFF, POWER_UP */ 300 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 301 FSL_XCVR_PLL_CTRL0_HROFF | FSL_XCVR_PLL_CTRL0_PWP, 0); 302 udelay(25); 303 /* PLL: CTRL0: Clear Hold Ring Off */ 304 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_CLR, 305 FSL_XCVR_PLL_CTRL0_HROFF, 0); 306 udelay(100); 307 if (tx) { /* TX is enabled for SPDIF only */ 308 /* PLL: POSTDIV: PDIV0 */ 309 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 310 FSL_XCVR_PLL_PDIVx(log2, 0), 0); 311 /* PLL: CTRL_SET: CLKMUX0_EN */ 312 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 313 FSL_XCVR_PLL_CTRL0_CM0_EN, 0); 314 } else if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC RX */ 315 /* PLL: POSTDIV: PDIV1 */ 316 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 317 FSL_XCVR_PLL_PDIVx(log2, 1), 0); 318 /* PLL: CTRL_SET: CLKMUX1_EN */ 319 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 320 FSL_XCVR_PLL_CTRL0_CM1_EN, 0); 321 } else { /* SPDIF / ARC RX */ 322 /* PLL: POSTDIV: PDIV2 */ 323 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_PDIV, 324 FSL_XCVR_PLL_PDIVx(log2, 2), 0); 325 /* PLL: CTRL_SET: CLKMUX2_EN */ 326 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PLL_CTRL0_SET, 327 FSL_XCVR_PLL_CTRL0_CM2_EN, 0); 328 } 329 330 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 331 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 332 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 333 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 334 FSL_XCVR_PHY_CTRL_PHY_EN, 1); 335 /* PHY: CTRL2_SET: EARC_TX_MODE */ 336 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, 337 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); 338 } else if (!tx) { /* SPDIF / ARC RX mode */ 339 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 340 /* PHY: CTRL_SET: SPDIF_EN */ 341 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 342 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); 343 else /* PHY: CTRL_SET: ARC RX setup */ 344 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 345 FSL_XCVR_PHY_CTRL_PHY_EN | 346 FSL_XCVR_PHY_CTRL_RX_CM_EN | 347 fsl_xcvr_phy_arc_cfg[xcvr->arc_mode], 1); 348 } 349 350 dev_dbg(dev, "PLL Fexp: %u, Fout: %u, mfi: %u, mfn: %u, mfd: %d, div: %u, pdiv0: %u\n", 351 freq, fsl_xcvr_pll_cfg[i].fout, fsl_xcvr_pll_cfg[i].mfi, 352 fsl_xcvr_pll_cfg[i].mfn, fsl_xcvr_pll_cfg[i].mfd, div, log2); 353 return 0; 354 } 355 356 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) 357 { 358 struct device *dev = &xcvr->pdev->dev; 359 int ret; 360 361 freq = xcvr->soc_data->spdif_only ? freq / 10 : freq; 362 clk_disable_unprepare(xcvr->phy_clk); 363 ret = clk_set_rate(xcvr->phy_clk, freq); 364 if (ret < 0) { 365 dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret); 366 return ret; 367 } 368 ret = clk_prepare_enable(xcvr->phy_clk); 369 if (ret) { 370 dev_err(dev, "failed to start PHY clock: %d\n", ret); 371 return ret; 372 } 373 374 if (xcvr->soc_data->spdif_only) 375 return 0; 376 /* Release AI interface from reset */ 377 ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, 378 FSL_XCVR_PHY_AI_CTRL_AI_RESETN); 379 if (ret < 0) { 380 dev_err(dev, "Error while setting IER0: %d\n", ret); 381 return ret; 382 } 383 384 if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */ 385 /* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */ 386 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 387 FSL_XCVR_PHY_CTRL_TSDIFF_OE | 388 FSL_XCVR_PHY_CTRL_PHY_EN, 1); 389 /* PHY: CTRL2_SET: EARC_TX_MODE */ 390 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL2_SET, 391 FSL_XCVR_PHY_CTRL2_EARC_TXMS, 1); 392 } else { /* SPDIF mode */ 393 /* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */ 394 fsl_xcvr_ai_write(xcvr, FSL_XCVR_PHY_CTRL_SET, 395 FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS | 396 FSL_XCVR_PHY_CTRL_SPDIF_EN, 1); 397 } 398 399 dev_dbg(dev, "PLL Fexp: %u\n", freq); 400 401 return 0; 402 } 403 404 #define FSL_XCVR_SPDIF_RX_FREQ 175000000 405 static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, 406 struct snd_soc_dai *dai) 407 { 408 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 409 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 410 u32 m_ctl = 0, v_ctl = 0; 411 u32 r = substream->runtime->rate, ch = substream->runtime->channels; 412 u32 fout = 32 * r * ch * 10 * 2; 413 int ret = 0; 414 415 switch (xcvr->mode) { 416 case FSL_XCVR_MODE_SPDIF: 417 case FSL_XCVR_MODE_ARC: 418 if (tx) { 419 ret = fsl_xcvr_en_aud_pll(xcvr, fout); 420 if (ret < 0) { 421 dev_err(dai->dev, "Failed to set TX freq %u: %d\n", 422 fout, ret); 423 return ret; 424 } 425 426 ret = regmap_write(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, 427 FSL_XCVR_TX_DPTH_CTRL_FRM_FMT); 428 if (ret < 0) { 429 dev_err(dai->dev, "Failed to set TX_DPTH: %d\n", ret); 430 return ret; 431 } 432 433 /** 434 * set SPDIF MODE - this flag is used to gate 435 * SPDIF output, useless for SPDIF RX 436 */ 437 m_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 438 v_ctl |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 439 } else { 440 /** 441 * Clear RX FIFO, flip RX FIFO bits, 442 * disable eARC related HW mode detects 443 */ 444 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, 445 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 446 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO | 447 FSL_XCVR_RX_DPTH_CTRL_COMP | 448 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 449 if (ret < 0) { 450 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 451 return ret; 452 } 453 454 ret = fsl_xcvr_en_phy_pll(xcvr, FSL_XCVR_SPDIF_RX_FREQ, tx); 455 if (ret < 0) { 456 dev_err(dai->dev, "Failed to set RX freq %u: %d\n", 457 FSL_XCVR_SPDIF_RX_FREQ, ret); 458 return ret; 459 } 460 } 461 break; 462 case FSL_XCVR_MODE_EARC: 463 if (!tx) { 464 /** Clear RX FIFO, flip RX FIFO bits */ 465 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_SET, 466 FSL_XCVR_RX_DPTH_CTRL_STORE_FMT | 467 FSL_XCVR_RX_DPTH_CTRL_CLR_RX_FIFO); 468 if (ret < 0) { 469 dev_err(dai->dev, "Failed to set RX_DPTH: %d\n", ret); 470 return ret; 471 } 472 473 /** Enable eARC related HW mode detects */ 474 ret = regmap_write(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL_CLR, 475 FSL_XCVR_RX_DPTH_CTRL_COMP | 476 FSL_XCVR_RX_DPTH_CTRL_LAYB_CTRL); 477 if (ret < 0) { 478 dev_err(dai->dev, "Failed to clr TX_DPTH: %d\n", ret); 479 return ret; 480 } 481 } 482 483 /* clear CMDC RESET */ 484 m_ctl |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 485 /* set TX_RX_MODE */ 486 m_ctl |= FSL_XCVR_EXT_CTRL_TX_RX_MODE; 487 v_ctl |= (tx ? FSL_XCVR_EXT_CTRL_TX_RX_MODE : 0); 488 break; 489 } 490 491 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 492 FSL_XCVR_IRQ_EARC_ALL, FSL_XCVR_IRQ_EARC_ALL); 493 if (ret < 0) { 494 dev_err(dai->dev, "Error while setting IER0: %d\n", ret); 495 return ret; 496 } 497 498 /* set DPATH RESET */ 499 m_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx); 500 v_ctl |= FSL_XCVR_EXT_CTRL_DPTH_RESET(tx); 501 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, m_ctl, v_ctl); 502 if (ret < 0) { 503 dev_err(dai->dev, "Error while setting EXT_CTRL: %d\n", ret); 504 return ret; 505 } 506 507 return 0; 508 } 509 510 static int fsl_xcvr_constr(const struct snd_pcm_substream *substream, 511 const struct snd_pcm_hw_constraint_list *channels, 512 const struct snd_pcm_hw_constraint_list *rates) 513 { 514 struct snd_pcm_runtime *rt = substream->runtime; 515 int ret; 516 517 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 518 channels); 519 if (ret < 0) 520 return ret; 521 522 ret = snd_pcm_hw_constraint_list(rt, 0, SNDRV_PCM_HW_PARAM_RATE, 523 rates); 524 if (ret < 0) 525 return ret; 526 527 return 0; 528 } 529 530 static int fsl_xcvr_startup(struct snd_pcm_substream *substream, 531 struct snd_soc_dai *dai) 532 { 533 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 534 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 535 int ret = 0; 536 537 if (xcvr->streams & BIT(substream->stream)) { 538 dev_err(dai->dev, "%sX busy\n", tx ? "T" : "R"); 539 return -EBUSY; 540 } 541 542 /* 543 * EDMA controller needs period size to be a multiple of 544 * tx/rx maxburst 545 */ 546 if (xcvr->soc_data->use_edma) 547 snd_pcm_hw_constraint_step(substream->runtime, 0, 548 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 549 tx ? xcvr->dma_prms_tx.maxburst : 550 xcvr->dma_prms_rx.maxburst); 551 552 switch (xcvr->mode) { 553 case FSL_XCVR_MODE_SPDIF: 554 case FSL_XCVR_MODE_ARC: 555 ret = fsl_xcvr_constr(substream, &fsl_xcvr_spdif_channels_constr, 556 &fsl_xcvr_spdif_rates_constr); 557 break; 558 case FSL_XCVR_MODE_EARC: 559 ret = fsl_xcvr_constr(substream, &fsl_xcvr_earc_channels_constr, 560 &fsl_xcvr_earc_rates_constr); 561 break; 562 } 563 if (ret < 0) 564 return ret; 565 566 xcvr->streams |= BIT(substream->stream); 567 568 if (!xcvr->soc_data->spdif_only) { 569 /* Disable XCVR controls if there is stream started */ 570 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, false); 571 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, false); 572 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, false); 573 } 574 575 return 0; 576 } 577 578 static void fsl_xcvr_shutdown(struct snd_pcm_substream *substream, 579 struct snd_soc_dai *dai) 580 { 581 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 582 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 583 u32 mask = 0, val = 0; 584 int ret; 585 586 xcvr->streams &= ~BIT(substream->stream); 587 588 /* Enable XCVR controls if there is no stream started */ 589 if (!xcvr->streams) { 590 if (!xcvr->soc_data->spdif_only) { 591 fsl_xcvr_activate_ctl(dai, fsl_xcvr_mode_kctl.name, true); 592 fsl_xcvr_activate_ctl(dai, fsl_xcvr_arc_mode_kctl.name, 593 (xcvr->mode == FSL_XCVR_MODE_ARC)); 594 fsl_xcvr_activate_ctl(dai, fsl_xcvr_earc_capds_kctl.name, 595 (xcvr->mode == FSL_XCVR_MODE_EARC)); 596 } 597 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 598 FSL_XCVR_IRQ_EARC_ALL, 0); 599 if (ret < 0) { 600 dev_err(dai->dev, "Failed to set IER0: %d\n", ret); 601 return; 602 } 603 604 /* clear SPDIF MODE */ 605 if (xcvr->mode == FSL_XCVR_MODE_SPDIF) 606 mask |= FSL_XCVR_EXT_CTRL_SPDIF_MODE; 607 } 608 609 if (xcvr->mode == FSL_XCVR_MODE_EARC) { 610 /* set CMDC RESET */ 611 mask |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 612 val |= FSL_XCVR_EXT_CTRL_CMDC_RESET(tx); 613 } 614 615 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 616 if (ret < 0) { 617 dev_err(dai->dev, "Err setting DPATH RESET: %d\n", ret); 618 return; 619 } 620 } 621 622 static int fsl_xcvr_trigger(struct snd_pcm_substream *substream, int cmd, 623 struct snd_soc_dai *dai) 624 { 625 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 626 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 627 int ret; 628 629 switch (cmd) { 630 case SNDRV_PCM_TRIGGER_START: 631 case SNDRV_PCM_TRIGGER_RESUME: 632 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 633 if (tx) { 634 switch (xcvr->mode) { 635 case FSL_XCVR_MODE_EARC: 636 /* set isr_cmdc_tx_en, w1c */ 637 ret = regmap_write(xcvr->regmap, 638 FSL_XCVR_ISR_SET, 639 FSL_XCVR_ISR_CMDC_TX_EN); 640 if (ret < 0) { 641 dev_err(dai->dev, "err updating isr %d\n", ret); 642 return ret; 643 } 644 fallthrough; 645 case FSL_XCVR_MODE_SPDIF: 646 ret = regmap_write(xcvr->regmap, 647 FSL_XCVR_TX_DPTH_CTRL_SET, 648 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 649 if (ret < 0) { 650 dev_err(dai->dev, "Failed to start DATA_TX: %d\n", ret); 651 return ret; 652 } 653 break; 654 } 655 } 656 657 /* enable DMA RD/WR */ 658 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 659 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 0); 660 if (ret < 0) { 661 dev_err(dai->dev, "Failed to enable DMA: %d\n", ret); 662 return ret; 663 } 664 665 /* clear DPATH RESET */ 666 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 667 FSL_XCVR_EXT_CTRL_DPTH_RESET(tx), 668 0); 669 if (ret < 0) { 670 dev_err(dai->dev, "Failed to clear DPATH RESET: %d\n", ret); 671 return ret; 672 } 673 674 break; 675 case SNDRV_PCM_TRIGGER_STOP: 676 case SNDRV_PCM_TRIGGER_SUSPEND: 677 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 678 /* disable DMA RD/WR */ 679 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 680 FSL_XCVR_EXT_CTRL_DMA_DIS(tx), 681 FSL_XCVR_EXT_CTRL_DMA_DIS(tx)); 682 if (ret < 0) { 683 dev_err(dai->dev, "Failed to disable DMA: %d\n", ret); 684 return ret; 685 } 686 687 if (tx) { 688 switch (xcvr->mode) { 689 case FSL_XCVR_MODE_SPDIF: 690 ret = regmap_write(xcvr->regmap, 691 FSL_XCVR_TX_DPTH_CTRL_CLR, 692 FSL_XCVR_TX_DPTH_CTRL_STRT_DATA_TX); 693 if (ret < 0) { 694 dev_err(dai->dev, "Failed to stop DATA_TX: %d\n", ret); 695 return ret; 696 } 697 if (xcvr->soc_data->spdif_only) 698 break; 699 else 700 fallthrough; 701 case FSL_XCVR_MODE_EARC: 702 /* clear ISR_CMDC_TX_EN, W1C */ 703 ret = regmap_write(xcvr->regmap, 704 FSL_XCVR_ISR_CLR, 705 FSL_XCVR_ISR_CMDC_TX_EN); 706 if (ret < 0) { 707 dev_err(dai->dev, 708 "Err updating ISR %d\n", ret); 709 return ret; 710 } 711 break; 712 } 713 } 714 break; 715 default: 716 return -EINVAL; 717 } 718 719 return 0; 720 } 721 722 static int fsl_xcvr_load_firmware(struct fsl_xcvr *xcvr) 723 { 724 struct device *dev = &xcvr->pdev->dev; 725 const struct firmware *fw; 726 int ret = 0, rem, off, out, page = 0, size = FSL_XCVR_REG_OFFSET; 727 u32 mask, val; 728 729 ret = request_firmware(&fw, xcvr->soc_data->fw_name, dev); 730 if (ret) { 731 dev_err(dev, "failed to request firmware.\n"); 732 return ret; 733 } 734 735 rem = fw->size; 736 737 /* RAM is 20KiB = 16KiB code + 4KiB data => max 10 pages 2KiB each */ 738 if (rem > 16384) { 739 dev_err(dev, "FW size %d is bigger than 16KiB.\n", rem); 740 release_firmware(fw); 741 return -ENOMEM; 742 } 743 744 for (page = 0; page < 10; page++) { 745 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 746 FSL_XCVR_EXT_CTRL_PAGE_MASK, 747 FSL_XCVR_EXT_CTRL_PAGE(page)); 748 if (ret < 0) { 749 dev_err(dev, "FW: failed to set page %d, err=%d\n", 750 page, ret); 751 goto err_firmware; 752 } 753 754 off = page * size; 755 out = min(rem, size); 756 /* IPG clock is assumed to be running, otherwise it will hang */ 757 if (out > 0) { 758 /* write firmware into code memory */ 759 memcpy_toio(xcvr->ram_addr, fw->data + off, out); 760 rem -= out; 761 if (rem == 0) { 762 /* last part of firmware written */ 763 /* clean remaining part of code memory page */ 764 memset_io(xcvr->ram_addr + out, 0, size - out); 765 } 766 } else { 767 /* clean current page, including data memory */ 768 memset_io(xcvr->ram_addr, 0, size); 769 } 770 } 771 772 err_firmware: 773 release_firmware(fw); 774 if (ret < 0) 775 return ret; 776 777 /* configure watermarks */ 778 mask = FSL_XCVR_EXT_CTRL_RX_FWM_MASK | FSL_XCVR_EXT_CTRL_TX_FWM_MASK; 779 val = FSL_XCVR_EXT_CTRL_RX_FWM(FSL_XCVR_FIFO_WMK_RX); 780 val |= FSL_XCVR_EXT_CTRL_TX_FWM(FSL_XCVR_FIFO_WMK_TX); 781 /* disable DMA RD/WR */ 782 mask |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 783 val |= FSL_XCVR_EXT_CTRL_DMA_RD_DIS | FSL_XCVR_EXT_CTRL_DMA_WR_DIS; 784 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 785 mask |= FSL_XCVR_EXT_CTRL_PAGE_MASK; 786 val |= FSL_XCVR_EXT_CTRL_PAGE(8); 787 788 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, mask, val); 789 if (ret < 0) { 790 dev_err(dev, "Failed to set watermarks: %d\n", ret); 791 return ret; 792 } 793 794 /* Store Capabilities Data Structure into Data RAM */ 795 memcpy_toio(xcvr->ram_addr + FSL_XCVR_CAP_DATA_STR, xcvr->cap_ds, 796 FSL_XCVR_CAPDS_SIZE); 797 return 0; 798 } 799 800 static int fsl_xcvr_type_iec958_info(struct snd_kcontrol *kcontrol, 801 struct snd_ctl_elem_info *uinfo) 802 { 803 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 804 uinfo->count = 1; 805 806 return 0; 807 } 808 809 static int fsl_xcvr_type_iec958_bytes_info(struct snd_kcontrol *kcontrol, 810 struct snd_ctl_elem_info *uinfo) 811 { 812 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 813 uinfo->count = sizeof_field(struct snd_aes_iec958, status); 814 815 return 0; 816 } 817 818 static int fsl_xcvr_rx_cs_get(struct snd_kcontrol *kcontrol, 819 struct snd_ctl_elem_value *ucontrol) 820 { 821 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 822 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 823 824 memcpy(ucontrol->value.iec958.status, xcvr->rx_iec958.status, 24); 825 826 return 0; 827 } 828 829 static int fsl_xcvr_tx_cs_get(struct snd_kcontrol *kcontrol, 830 struct snd_ctl_elem_value *ucontrol) 831 { 832 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 833 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 834 835 memcpy(ucontrol->value.iec958.status, xcvr->tx_iec958.status, 24); 836 837 return 0; 838 } 839 840 static int fsl_xcvr_tx_cs_put(struct snd_kcontrol *kcontrol, 841 struct snd_ctl_elem_value *ucontrol) 842 { 843 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 844 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 845 846 memcpy(xcvr->tx_iec958.status, ucontrol->value.iec958.status, 24); 847 848 return 0; 849 } 850 851 static struct snd_kcontrol_new fsl_xcvr_rx_ctls[] = { 852 /* Channel status controller */ 853 { 854 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 855 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 856 .access = SNDRV_CTL_ELEM_ACCESS_READ, 857 .info = fsl_xcvr_type_iec958_info, 858 .get = fsl_xcvr_rx_cs_get, 859 }, 860 /* Capture channel status, bytes */ 861 { 862 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 863 .name = "Capture Channel Status", 864 .access = SNDRV_CTL_ELEM_ACCESS_READ, 865 .info = fsl_xcvr_type_iec958_bytes_info, 866 .get = fsl_xcvr_rx_cs_get, 867 }, 868 }; 869 870 static struct snd_kcontrol_new fsl_xcvr_tx_ctls[] = { 871 /* Channel status controller */ 872 { 873 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 874 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 875 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 876 .info = fsl_xcvr_type_iec958_info, 877 .get = fsl_xcvr_tx_cs_get, 878 .put = fsl_xcvr_tx_cs_put, 879 }, 880 /* Playback channel status, bytes */ 881 { 882 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 883 .name = "Playback Channel Status", 884 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 885 .info = fsl_xcvr_type_iec958_bytes_info, 886 .get = fsl_xcvr_tx_cs_get, 887 .put = fsl_xcvr_tx_cs_put, 888 }, 889 }; 890 891 static const struct snd_soc_dai_ops fsl_xcvr_dai_ops = { 892 .prepare = fsl_xcvr_prepare, 893 .startup = fsl_xcvr_startup, 894 .shutdown = fsl_xcvr_shutdown, 895 .trigger = fsl_xcvr_trigger, 896 }; 897 898 static int fsl_xcvr_dai_probe(struct snd_soc_dai *dai) 899 { 900 struct fsl_xcvr *xcvr = snd_soc_dai_get_drvdata(dai); 901 902 snd_soc_dai_init_dma_data(dai, &xcvr->dma_prms_tx, &xcvr->dma_prms_rx); 903 904 if (xcvr->soc_data->spdif_only) 905 xcvr->mode = FSL_XCVR_MODE_SPDIF; 906 else { 907 snd_soc_add_dai_controls(dai, &fsl_xcvr_mode_kctl, 1); 908 snd_soc_add_dai_controls(dai, &fsl_xcvr_arc_mode_kctl, 1); 909 snd_soc_add_dai_controls(dai, &fsl_xcvr_earc_capds_kctl, 1); 910 } 911 snd_soc_add_dai_controls(dai, fsl_xcvr_tx_ctls, 912 ARRAY_SIZE(fsl_xcvr_tx_ctls)); 913 snd_soc_add_dai_controls(dai, fsl_xcvr_rx_ctls, 914 ARRAY_SIZE(fsl_xcvr_rx_ctls)); 915 return 0; 916 } 917 918 static struct snd_soc_dai_driver fsl_xcvr_dai = { 919 .probe = fsl_xcvr_dai_probe, 920 .ops = &fsl_xcvr_dai_ops, 921 .playback = { 922 .stream_name = "CPU-Playback", 923 .channels_min = 1, 924 .channels_max = 32, 925 .rate_min = 32000, 926 .rate_max = 1536000, 927 .rates = SNDRV_PCM_RATE_KNOT, 928 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 929 }, 930 .capture = { 931 .stream_name = "CPU-Capture", 932 .channels_min = 1, 933 .channels_max = 32, 934 .rate_min = 32000, 935 .rate_max = 1536000, 936 .rates = SNDRV_PCM_RATE_KNOT, 937 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 938 }, 939 }; 940 941 static const struct snd_soc_component_driver fsl_xcvr_comp = { 942 .name = "fsl-xcvr-dai", 943 .legacy_dai_naming = 1, 944 }; 945 946 static const struct reg_default fsl_xcvr_reg_defaults[] = { 947 { FSL_XCVR_VERSION, 0x00000000 }, 948 { FSL_XCVR_EXT_CTRL, 0xF8204040 }, 949 { FSL_XCVR_EXT_STATUS, 0x00000000 }, 950 { FSL_XCVR_EXT_IER0, 0x00000000 }, 951 { FSL_XCVR_EXT_IER1, 0x00000000 }, 952 { FSL_XCVR_EXT_ISR, 0x00000000 }, 953 { FSL_XCVR_EXT_ISR_SET, 0x00000000 }, 954 { FSL_XCVR_EXT_ISR_CLR, 0x00000000 }, 955 { FSL_XCVR_EXT_ISR_TOG, 0x00000000 }, 956 { FSL_XCVR_IER, 0x00000000 }, 957 { FSL_XCVR_ISR, 0x00000000 }, 958 { FSL_XCVR_ISR_SET, 0x00000000 }, 959 { FSL_XCVR_ISR_CLR, 0x00000000 }, 960 { FSL_XCVR_ISR_TOG, 0x00000000 }, 961 { FSL_XCVR_CLK_CTRL, 0x0000018F }, 962 { FSL_XCVR_RX_DPTH_CTRL, 0x00040CC1 }, 963 { FSL_XCVR_RX_DPTH_CTRL_SET, 0x00040CC1 }, 964 { FSL_XCVR_RX_DPTH_CTRL_CLR, 0x00040CC1 }, 965 { FSL_XCVR_RX_DPTH_CTRL_TOG, 0x00040CC1 }, 966 { FSL_XCVR_RX_DPTH_CNTR_CTRL, 0x00000000 }, 967 { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 968 { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 969 { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 970 { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 }, 971 { FSL_XCVR_RX_DPTH_BCR, 0x00000000 }, 972 { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 }, 973 { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 }, 974 { FSL_XCVR_TX_DPTH_CTRL, 0x00000000 }, 975 { FSL_XCVR_TX_DPTH_CTRL_SET, 0x00000000 }, 976 { FSL_XCVR_TX_DPTH_CTRL_CLR, 0x00000000 }, 977 { FSL_XCVR_TX_DPTH_CTRL_TOG, 0x00000000 }, 978 { FSL_XCVR_TX_CS_DATA_0, 0x00000000 }, 979 { FSL_XCVR_TX_CS_DATA_1, 0x00000000 }, 980 { FSL_XCVR_TX_CS_DATA_2, 0x00000000 }, 981 { FSL_XCVR_TX_CS_DATA_3, 0x00000000 }, 982 { FSL_XCVR_TX_CS_DATA_4, 0x00000000 }, 983 { FSL_XCVR_TX_CS_DATA_5, 0x00000000 }, 984 { FSL_XCVR_TX_DPTH_CNTR_CTRL, 0x00000000 }, 985 { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 }, 986 { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 }, 987 { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 }, 988 { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 }, 989 { FSL_XCVR_TX_DPTH_BCR, 0x00000000 }, 990 { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 }, 991 { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 }, 992 { FSL_XCVR_DEBUG_REG_0, 0x00000000 }, 993 { FSL_XCVR_DEBUG_REG_1, 0x00000000 }, 994 }; 995 996 static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg) 997 { 998 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 999 1000 if (xcvr->soc_data->spdif_only) 1001 if ((reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) || 1002 reg > FSL_XCVR_TX_DPTH_BCRR) 1003 return false; 1004 switch (reg) { 1005 case FSL_XCVR_VERSION: 1006 case FSL_XCVR_EXT_CTRL: 1007 case FSL_XCVR_EXT_STATUS: 1008 case FSL_XCVR_EXT_IER0: 1009 case FSL_XCVR_EXT_IER1: 1010 case FSL_XCVR_EXT_ISR: 1011 case FSL_XCVR_EXT_ISR_SET: 1012 case FSL_XCVR_EXT_ISR_CLR: 1013 case FSL_XCVR_EXT_ISR_TOG: 1014 case FSL_XCVR_IER: 1015 case FSL_XCVR_ISR: 1016 case FSL_XCVR_ISR_SET: 1017 case FSL_XCVR_ISR_CLR: 1018 case FSL_XCVR_ISR_TOG: 1019 case FSL_XCVR_PHY_AI_CTRL: 1020 case FSL_XCVR_PHY_AI_CTRL_SET: 1021 case FSL_XCVR_PHY_AI_CTRL_CLR: 1022 case FSL_XCVR_PHY_AI_CTRL_TOG: 1023 case FSL_XCVR_PHY_AI_RDATA: 1024 case FSL_XCVR_CLK_CTRL: 1025 case FSL_XCVR_RX_DPTH_CTRL: 1026 case FSL_XCVR_RX_DPTH_CTRL_SET: 1027 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1028 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1029 case FSL_XCVR_RX_CS_DATA_0: 1030 case FSL_XCVR_RX_CS_DATA_1: 1031 case FSL_XCVR_RX_CS_DATA_2: 1032 case FSL_XCVR_RX_CS_DATA_3: 1033 case FSL_XCVR_RX_CS_DATA_4: 1034 case FSL_XCVR_RX_CS_DATA_5: 1035 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1036 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1037 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1038 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1039 case FSL_XCVR_RX_DPTH_TSCR: 1040 case FSL_XCVR_RX_DPTH_BCR: 1041 case FSL_XCVR_RX_DPTH_BCTR: 1042 case FSL_XCVR_RX_DPTH_BCRR: 1043 case FSL_XCVR_TX_DPTH_CTRL: 1044 case FSL_XCVR_TX_DPTH_CTRL_SET: 1045 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1046 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1047 case FSL_XCVR_TX_CS_DATA_0: 1048 case FSL_XCVR_TX_CS_DATA_1: 1049 case FSL_XCVR_TX_CS_DATA_2: 1050 case FSL_XCVR_TX_CS_DATA_3: 1051 case FSL_XCVR_TX_CS_DATA_4: 1052 case FSL_XCVR_TX_CS_DATA_5: 1053 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1054 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1055 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1056 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1057 case FSL_XCVR_TX_DPTH_TSCR: 1058 case FSL_XCVR_TX_DPTH_BCR: 1059 case FSL_XCVR_TX_DPTH_BCTR: 1060 case FSL_XCVR_TX_DPTH_BCRR: 1061 case FSL_XCVR_DEBUG_REG_0: 1062 case FSL_XCVR_DEBUG_REG_1: 1063 return true; 1064 default: 1065 return false; 1066 } 1067 } 1068 1069 static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg) 1070 { 1071 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1072 1073 if (xcvr->soc_data->spdif_only) 1074 if (reg >= FSL_XCVR_IER && reg <= FSL_XCVR_PHY_AI_RDATA) 1075 return false; 1076 switch (reg) { 1077 case FSL_XCVR_EXT_CTRL: 1078 case FSL_XCVR_EXT_IER0: 1079 case FSL_XCVR_EXT_IER1: 1080 case FSL_XCVR_EXT_ISR: 1081 case FSL_XCVR_EXT_ISR_SET: 1082 case FSL_XCVR_EXT_ISR_CLR: 1083 case FSL_XCVR_EXT_ISR_TOG: 1084 case FSL_XCVR_IER: 1085 case FSL_XCVR_ISR_SET: 1086 case FSL_XCVR_ISR_CLR: 1087 case FSL_XCVR_ISR_TOG: 1088 case FSL_XCVR_PHY_AI_CTRL: 1089 case FSL_XCVR_PHY_AI_CTRL_SET: 1090 case FSL_XCVR_PHY_AI_CTRL_CLR: 1091 case FSL_XCVR_PHY_AI_CTRL_TOG: 1092 case FSL_XCVR_PHY_AI_WDATA: 1093 case FSL_XCVR_CLK_CTRL: 1094 case FSL_XCVR_RX_DPTH_CTRL: 1095 case FSL_XCVR_RX_DPTH_CTRL_SET: 1096 case FSL_XCVR_RX_DPTH_CTRL_CLR: 1097 case FSL_XCVR_RX_DPTH_CTRL_TOG: 1098 case FSL_XCVR_RX_DPTH_CNTR_CTRL: 1099 case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET: 1100 case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR: 1101 case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG: 1102 case FSL_XCVR_TX_DPTH_CTRL_SET: 1103 case FSL_XCVR_TX_DPTH_CTRL_CLR: 1104 case FSL_XCVR_TX_DPTH_CTRL_TOG: 1105 case FSL_XCVR_TX_CS_DATA_0: 1106 case FSL_XCVR_TX_CS_DATA_1: 1107 case FSL_XCVR_TX_CS_DATA_2: 1108 case FSL_XCVR_TX_CS_DATA_3: 1109 case FSL_XCVR_TX_CS_DATA_4: 1110 case FSL_XCVR_TX_CS_DATA_5: 1111 case FSL_XCVR_TX_DPTH_CNTR_CTRL: 1112 case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET: 1113 case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR: 1114 case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG: 1115 return true; 1116 default: 1117 return false; 1118 } 1119 } 1120 1121 static bool fsl_xcvr_volatile_reg(struct device *dev, unsigned int reg) 1122 { 1123 return fsl_xcvr_readable_reg(dev, reg); 1124 } 1125 1126 static const struct regmap_config fsl_xcvr_regmap_cfg = { 1127 .reg_bits = 32, 1128 .reg_stride = 4, 1129 .val_bits = 32, 1130 .max_register = FSL_XCVR_MAX_REG, 1131 .reg_defaults = fsl_xcvr_reg_defaults, 1132 .num_reg_defaults = ARRAY_SIZE(fsl_xcvr_reg_defaults), 1133 .readable_reg = fsl_xcvr_readable_reg, 1134 .volatile_reg = fsl_xcvr_volatile_reg, 1135 .writeable_reg = fsl_xcvr_writeable_reg, 1136 .cache_type = REGCACHE_FLAT, 1137 }; 1138 1139 static irqreturn_t irq0_isr(int irq, void *devid) 1140 { 1141 struct fsl_xcvr *xcvr = (struct fsl_xcvr *)devid; 1142 struct device *dev = &xcvr->pdev->dev; 1143 struct regmap *regmap = xcvr->regmap; 1144 void __iomem *reg_ctrl, *reg_buff; 1145 u32 isr, isr_clr = 0, val, i; 1146 1147 regmap_read(regmap, FSL_XCVR_EXT_ISR, &isr); 1148 1149 if (isr & FSL_XCVR_IRQ_NEW_CS) { 1150 dev_dbg(dev, "Received new CS block\n"); 1151 isr_clr |= FSL_XCVR_IRQ_NEW_CS; 1152 if (!xcvr->soc_data->spdif_only) { 1153 /* Data RAM is 4KiB, last two pages: 8 and 9. Select page 8. */ 1154 regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1155 FSL_XCVR_EXT_CTRL_PAGE_MASK, 1156 FSL_XCVR_EXT_CTRL_PAGE(8)); 1157 1158 /* Find updated CS buffer */ 1159 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_0; 1160 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_0; 1161 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1162 if (!val) { 1163 reg_ctrl = xcvr->ram_addr + FSL_XCVR_RX_CS_CTRL_1; 1164 reg_buff = xcvr->ram_addr + FSL_XCVR_RX_CS_BUFF_1; 1165 memcpy_fromio(&val, reg_ctrl, sizeof(val)); 1166 } 1167 1168 if (val) { 1169 /* copy CS buffer */ 1170 memcpy_fromio(&xcvr->rx_iec958.status, reg_buff, 1171 sizeof(xcvr->rx_iec958.status)); 1172 for (i = 0; i < 6; i++) { 1173 val = *(u32 *)(xcvr->rx_iec958.status + i*4); 1174 *(u32 *)(xcvr->rx_iec958.status + i*4) = 1175 bitrev32(val); 1176 } 1177 /* clear CS control register */ 1178 memset_io(reg_ctrl, 0, sizeof(val)); 1179 } 1180 } 1181 } 1182 if (isr & FSL_XCVR_IRQ_NEW_UD) { 1183 dev_dbg(dev, "Received new UD block\n"); 1184 isr_clr |= FSL_XCVR_IRQ_NEW_UD; 1185 } 1186 if (isr & FSL_XCVR_IRQ_MUTE) { 1187 dev_dbg(dev, "HW mute bit detected\n"); 1188 isr_clr |= FSL_XCVR_IRQ_MUTE; 1189 } 1190 if (isr & FSL_XCVR_IRQ_FIFO_UOFL_ERR) { 1191 dev_dbg(dev, "RX/TX FIFO full/empty\n"); 1192 isr_clr |= FSL_XCVR_IRQ_FIFO_UOFL_ERR; 1193 } 1194 if (isr & FSL_XCVR_IRQ_ARC_MODE) { 1195 dev_dbg(dev, "CMDC SM falls out of eARC mode\n"); 1196 isr_clr |= FSL_XCVR_IRQ_ARC_MODE; 1197 } 1198 if (isr & FSL_XCVR_IRQ_DMA_RD_REQ) { 1199 dev_dbg(dev, "DMA read request\n"); 1200 isr_clr |= FSL_XCVR_IRQ_DMA_RD_REQ; 1201 } 1202 if (isr & FSL_XCVR_IRQ_DMA_WR_REQ) { 1203 dev_dbg(dev, "DMA write request\n"); 1204 isr_clr |= FSL_XCVR_IRQ_DMA_WR_REQ; 1205 } 1206 1207 if (isr_clr) { 1208 regmap_write(regmap, FSL_XCVR_EXT_ISR_CLR, isr_clr); 1209 return IRQ_HANDLED; 1210 } 1211 1212 return IRQ_NONE; 1213 } 1214 1215 static const struct fsl_xcvr_soc_data fsl_xcvr_imx8mp_data = { 1216 .fw_name = "imx/xcvr/xcvr-imx8mp.bin", 1217 }; 1218 1219 static const struct fsl_xcvr_soc_data fsl_xcvr_imx93_data = { 1220 .spdif_only = true, 1221 .use_edma = true, 1222 }; 1223 1224 static const struct of_device_id fsl_xcvr_dt_ids[] = { 1225 { .compatible = "fsl,imx8mp-xcvr", .data = &fsl_xcvr_imx8mp_data }, 1226 { .compatible = "fsl,imx93-xcvr", .data = &fsl_xcvr_imx93_data}, 1227 { /* sentinel */ } 1228 }; 1229 MODULE_DEVICE_TABLE(of, fsl_xcvr_dt_ids); 1230 1231 static int fsl_xcvr_probe(struct platform_device *pdev) 1232 { 1233 struct device *dev = &pdev->dev; 1234 struct fsl_xcvr *xcvr; 1235 struct resource *rx_res, *tx_res; 1236 void __iomem *regs; 1237 int ret, irq; 1238 1239 xcvr = devm_kzalloc(dev, sizeof(*xcvr), GFP_KERNEL); 1240 if (!xcvr) 1241 return -ENOMEM; 1242 1243 xcvr->pdev = pdev; 1244 xcvr->soc_data = of_device_get_match_data(&pdev->dev); 1245 1246 xcvr->ipg_clk = devm_clk_get(dev, "ipg"); 1247 if (IS_ERR(xcvr->ipg_clk)) { 1248 dev_err(dev, "failed to get ipg clock\n"); 1249 return PTR_ERR(xcvr->ipg_clk); 1250 } 1251 1252 xcvr->phy_clk = devm_clk_get(dev, "phy"); 1253 if (IS_ERR(xcvr->phy_clk)) { 1254 dev_err(dev, "failed to get phy clock\n"); 1255 return PTR_ERR(xcvr->phy_clk); 1256 } 1257 1258 xcvr->spba_clk = devm_clk_get(dev, "spba"); 1259 if (IS_ERR(xcvr->spba_clk)) { 1260 dev_err(dev, "failed to get spba clock\n"); 1261 return PTR_ERR(xcvr->spba_clk); 1262 } 1263 1264 xcvr->pll_ipg_clk = devm_clk_get(dev, "pll_ipg"); 1265 if (IS_ERR(xcvr->pll_ipg_clk)) { 1266 dev_err(dev, "failed to get pll_ipg clock\n"); 1267 return PTR_ERR(xcvr->pll_ipg_clk); 1268 } 1269 1270 xcvr->ram_addr = devm_platform_ioremap_resource_byname(pdev, "ram"); 1271 if (IS_ERR(xcvr->ram_addr)) 1272 return PTR_ERR(xcvr->ram_addr); 1273 1274 regs = devm_platform_ioremap_resource_byname(pdev, "regs"); 1275 if (IS_ERR(regs)) 1276 return PTR_ERR(regs); 1277 1278 xcvr->regmap = devm_regmap_init_mmio_clk(dev, NULL, regs, 1279 &fsl_xcvr_regmap_cfg); 1280 if (IS_ERR(xcvr->regmap)) { 1281 dev_err(dev, "failed to init XCVR regmap: %ld\n", 1282 PTR_ERR(xcvr->regmap)); 1283 return PTR_ERR(xcvr->regmap); 1284 } 1285 1286 xcvr->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 1287 if (IS_ERR(xcvr->reset)) { 1288 dev_err(dev, "failed to get XCVR reset control\n"); 1289 return PTR_ERR(xcvr->reset); 1290 } 1291 1292 /* get IRQs */ 1293 irq = platform_get_irq(pdev, 0); 1294 if (irq < 0) 1295 return irq; 1296 1297 ret = devm_request_irq(dev, irq, irq0_isr, 0, pdev->name, xcvr); 1298 if (ret) { 1299 dev_err(dev, "failed to claim IRQ0: %i\n", ret); 1300 return ret; 1301 } 1302 1303 rx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rxfifo"); 1304 tx_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "txfifo"); 1305 if (!rx_res || !tx_res) { 1306 dev_err(dev, "could not find rxfifo or txfifo resource\n"); 1307 return -EINVAL; 1308 } 1309 xcvr->dma_prms_rx.chan_name = "rx"; 1310 xcvr->dma_prms_tx.chan_name = "tx"; 1311 xcvr->dma_prms_rx.addr = rx_res->start; 1312 xcvr->dma_prms_tx.addr = tx_res->start; 1313 xcvr->dma_prms_rx.maxburst = FSL_XCVR_MAXBURST_RX; 1314 xcvr->dma_prms_tx.maxburst = FSL_XCVR_MAXBURST_TX; 1315 1316 platform_set_drvdata(pdev, xcvr); 1317 pm_runtime_enable(dev); 1318 regcache_cache_only(xcvr->regmap, true); 1319 1320 /* 1321 * Register platform component before registering cpu dai for there 1322 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1323 */ 1324 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1325 if (ret) { 1326 pm_runtime_disable(dev); 1327 dev_err(dev, "failed to pcm register\n"); 1328 return ret; 1329 } 1330 1331 ret = devm_snd_soc_register_component(dev, &fsl_xcvr_comp, 1332 &fsl_xcvr_dai, 1); 1333 if (ret) { 1334 pm_runtime_disable(dev); 1335 dev_err(dev, "failed to register component %s\n", 1336 fsl_xcvr_comp.name); 1337 } 1338 1339 return ret; 1340 } 1341 1342 static int fsl_xcvr_remove(struct platform_device *pdev) 1343 { 1344 pm_runtime_disable(&pdev->dev); 1345 return 0; 1346 } 1347 1348 static __maybe_unused int fsl_xcvr_runtime_suspend(struct device *dev) 1349 { 1350 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1351 int ret; 1352 1353 /* 1354 * Clear interrupts, when streams starts or resumes after 1355 * suspend, interrupts are enabled in prepare(), so no need 1356 * to enable interrupts in resume(). 1357 */ 1358 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_IER0, 1359 FSL_XCVR_IRQ_EARC_ALL, 0); 1360 if (ret < 0) 1361 dev_err(dev, "Failed to clear IER0: %d\n", ret); 1362 1363 if (!xcvr->soc_data->spdif_only) { 1364 /* Assert M0+ reset */ 1365 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1366 FSL_XCVR_EXT_CTRL_CORE_RESET, 1367 FSL_XCVR_EXT_CTRL_CORE_RESET); 1368 if (ret < 0) 1369 dev_err(dev, "Failed to assert M0+ core: %d\n", ret); 1370 } 1371 1372 regcache_cache_only(xcvr->regmap, true); 1373 1374 clk_disable_unprepare(xcvr->spba_clk); 1375 clk_disable_unprepare(xcvr->phy_clk); 1376 clk_disable_unprepare(xcvr->pll_ipg_clk); 1377 clk_disable_unprepare(xcvr->ipg_clk); 1378 1379 return 0; 1380 } 1381 1382 static __maybe_unused int fsl_xcvr_runtime_resume(struct device *dev) 1383 { 1384 struct fsl_xcvr *xcvr = dev_get_drvdata(dev); 1385 int ret; 1386 1387 ret = reset_control_assert(xcvr->reset); 1388 if (ret < 0) { 1389 dev_err(dev, "Failed to assert M0+ reset: %d\n", ret); 1390 return ret; 1391 } 1392 1393 ret = clk_prepare_enable(xcvr->ipg_clk); 1394 if (ret) { 1395 dev_err(dev, "failed to start IPG clock.\n"); 1396 return ret; 1397 } 1398 1399 ret = clk_prepare_enable(xcvr->pll_ipg_clk); 1400 if (ret) { 1401 dev_err(dev, "failed to start PLL IPG clock.\n"); 1402 goto stop_ipg_clk; 1403 } 1404 1405 ret = clk_prepare_enable(xcvr->phy_clk); 1406 if (ret) { 1407 dev_err(dev, "failed to start PHY clock: %d\n", ret); 1408 goto stop_pll_ipg_clk; 1409 } 1410 1411 ret = clk_prepare_enable(xcvr->spba_clk); 1412 if (ret) { 1413 dev_err(dev, "failed to start SPBA clock.\n"); 1414 goto stop_phy_clk; 1415 } 1416 1417 regcache_cache_only(xcvr->regmap, false); 1418 regcache_mark_dirty(xcvr->regmap); 1419 ret = regcache_sync(xcvr->regmap); 1420 1421 if (ret) { 1422 dev_err(dev, "failed to sync regcache.\n"); 1423 goto stop_spba_clk; 1424 } 1425 1426 if (xcvr->soc_data->spdif_only) 1427 return 0; 1428 1429 ret = reset_control_deassert(xcvr->reset); 1430 if (ret) { 1431 dev_err(dev, "failed to deassert M0+ reset.\n"); 1432 goto stop_spba_clk; 1433 } 1434 1435 ret = fsl_xcvr_load_firmware(xcvr); 1436 if (ret) { 1437 dev_err(dev, "failed to load firmware.\n"); 1438 goto stop_spba_clk; 1439 } 1440 1441 /* Release M0+ reset */ 1442 ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL, 1443 FSL_XCVR_EXT_CTRL_CORE_RESET, 0); 1444 if (ret < 0) { 1445 dev_err(dev, "M0+ core release failed: %d\n", ret); 1446 goto stop_spba_clk; 1447 } 1448 1449 /* Let M0+ core complete firmware initialization */ 1450 msleep(50); 1451 1452 return 0; 1453 1454 stop_spba_clk: 1455 clk_disable_unprepare(xcvr->spba_clk); 1456 stop_phy_clk: 1457 clk_disable_unprepare(xcvr->phy_clk); 1458 stop_pll_ipg_clk: 1459 clk_disable_unprepare(xcvr->pll_ipg_clk); 1460 stop_ipg_clk: 1461 clk_disable_unprepare(xcvr->ipg_clk); 1462 1463 return ret; 1464 } 1465 1466 static const struct dev_pm_ops fsl_xcvr_pm_ops = { 1467 SET_RUNTIME_PM_OPS(fsl_xcvr_runtime_suspend, 1468 fsl_xcvr_runtime_resume, 1469 NULL) 1470 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1471 pm_runtime_force_resume) 1472 }; 1473 1474 static struct platform_driver fsl_xcvr_driver = { 1475 .probe = fsl_xcvr_probe, 1476 .driver = { 1477 .name = "fsl,imx8mp-audio-xcvr", 1478 .pm = &fsl_xcvr_pm_ops, 1479 .of_match_table = fsl_xcvr_dt_ids, 1480 }, 1481 .remove = fsl_xcvr_remove, 1482 }; 1483 module_platform_driver(fsl_xcvr_driver); 1484 1485 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 1486 MODULE_DESCRIPTION("NXP Audio Transceiver (XCVR) driver"); 1487 MODULE_LICENSE("GPL v2"); 1488