1 /* 2 * fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 and i.MX SoC 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 */ 11 12 #ifndef _MPC8610_I2S_H 13 #define _MPC8610_I2S_H 14 15 /* -- SSI Register Map -- */ 16 17 /* SSI Transmit Data Register 0 */ 18 #define REG_SSI_STX0 0x00 19 /* SSI Transmit Data Register 1 */ 20 #define REG_SSI_STX1 0x04 21 /* SSI Receive Data Register 0 */ 22 #define REG_SSI_SRX0 0x08 23 /* SSI Receive Data Register 1 */ 24 #define REG_SSI_SRX1 0x0c 25 /* SSI Control Register */ 26 #define REG_SSI_SCR 0x10 27 /* SSI Interrupt Status Register */ 28 #define REG_SSI_SISR 0x14 29 /* SSI Interrupt Enable Register */ 30 #define REG_SSI_SIER 0x18 31 /* SSI Transmit Configuration Register */ 32 #define REG_SSI_STCR 0x1c 33 /* SSI Receive Configuration Register */ 34 #define REG_SSI_SRCR 0x20 35 #define REG_SSI_SxCR(tx) ((tx) ? REG_SSI_STCR : REG_SSI_SRCR) 36 /* SSI Transmit Clock Control Register */ 37 #define REG_SSI_STCCR 0x24 38 /* SSI Receive Clock Control Register */ 39 #define REG_SSI_SRCCR 0x28 40 #define REG_SSI_SxCCR(tx) ((tx) ? REG_SSI_STCCR : REG_SSI_SRCCR) 41 /* SSI FIFO Control/Status Register */ 42 #define REG_SSI_SFCSR 0x2c 43 /* 44 * SSI Test Register (Intended for debugging purposes only) 45 * 46 * Note: STR is not documented in recent IMX datasheet, but 47 * is described in IMX51 reference manual at section 56.3.3.14 48 */ 49 #define REG_SSI_STR 0x30 50 /* 51 * SSI Option Register (Intended for internal use only) 52 * 53 * Note: SOR is not documented in recent IMX datasheet, but 54 * is described in IMX51 reference manual at section 56.3.3.15 55 */ 56 #define REG_SSI_SOR 0x34 57 /* SSI AC97 Control Register */ 58 #define REG_SSI_SACNT 0x38 59 /* SSI AC97 Command Address Register */ 60 #define REG_SSI_SACADD 0x3c 61 /* SSI AC97 Command Data Register */ 62 #define REG_SSI_SACDAT 0x40 63 /* SSI AC97 Tag Register */ 64 #define REG_SSI_SATAG 0x44 65 /* SSI Transmit Time Slot Mask Register */ 66 #define REG_SSI_STMSK 0x48 67 /* SSI Receive Time Slot Mask Register */ 68 #define REG_SSI_SRMSK 0x4c 69 #define REG_SSI_SxMSK(tx) ((tx) ? REG_SSI_STMSK : REG_SSI_SRMSK) 70 /* 71 * SSI AC97 Channel Status Register 72 * 73 * The status could be changed by: 74 * 1) Writing a '1' bit at some position in SACCEN sets relevant bit in SACCST 75 * 2) Writing a '1' bit at some position in SACCDIS unsets the relevant bit 76 * 3) Receivng a '1' in SLOTREQ bit from external CODEC via AC Link 77 */ 78 #define REG_SSI_SACCST 0x50 79 /* SSI AC97 Channel Enable Register -- Set bits in SACCST */ 80 #define REG_SSI_SACCEN 0x54 81 /* SSI AC97 Channel Disable Register -- Clear bits in SACCST */ 82 #define REG_SSI_SACCDIS 0x58 83 84 /* -- SSI Register Field Maps -- */ 85 86 /* SSI Control Register -- REG_SSI_SCR 0x10 */ 87 #define SSI_SCR_SYNC_TX_FS 0x00001000 88 #define SSI_SCR_RFR_CLK_DIS 0x00000800 89 #define SSI_SCR_TFR_CLK_DIS 0x00000400 90 #define SSI_SCR_TCH_EN 0x00000100 91 #define SSI_SCR_SYS_CLK_EN 0x00000080 92 #define SSI_SCR_I2S_MODE_MASK 0x00000060 93 #define SSI_SCR_I2S_MODE_NORMAL 0x00000000 94 #define SSI_SCR_I2S_MODE_MASTER 0x00000020 95 #define SSI_SCR_I2S_MODE_SLAVE 0x00000040 96 #define SSI_SCR_SYN 0x00000010 97 #define SSI_SCR_NET 0x00000008 98 #define SSI_SCR_I2S_NET_MASK (SSI_SCR_NET | SSI_SCR_I2S_MODE_MASK) 99 #define SSI_SCR_RE 0x00000004 100 #define SSI_SCR_TE 0x00000002 101 #define SSI_SCR_SSIEN 0x00000001 102 103 /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */ 104 #define SSI_SISR_RFRC 0x01000000 105 #define SSI_SISR_TFRC 0x00800000 106 #define SSI_SISR_CMDAU 0x00040000 107 #define SSI_SISR_CMDDU 0x00020000 108 #define SSI_SISR_RXT 0x00010000 109 #define SSI_SISR_RDR1 0x00008000 110 #define SSI_SISR_RDR0 0x00004000 111 #define SSI_SISR_TDE1 0x00002000 112 #define SSI_SISR_TDE0 0x00001000 113 #define SSI_SISR_ROE1 0x00000800 114 #define SSI_SISR_ROE0 0x00000400 115 #define SSI_SISR_TUE1 0x00000200 116 #define SSI_SISR_TUE0 0x00000100 117 #define SSI_SISR_TFS 0x00000080 118 #define SSI_SISR_RFS 0x00000040 119 #define SSI_SISR_TLS 0x00000020 120 #define SSI_SISR_RLS 0x00000010 121 #define SSI_SISR_RFF1 0x00000008 122 #define SSI_SISR_RFF0 0x00000004 123 #define SSI_SISR_TFE1 0x00000002 124 #define SSI_SISR_TFE0 0x00000001 125 126 /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */ 127 #define SSI_SIER_RFRC_EN 0x01000000 128 #define SSI_SIER_TFRC_EN 0x00800000 129 #define SSI_SIER_RDMAE 0x00400000 130 #define SSI_SIER_RIE 0x00200000 131 #define SSI_SIER_TDMAE 0x00100000 132 #define SSI_SIER_TIE 0x00080000 133 #define SSI_SIER_CMDAU_EN 0x00040000 134 #define SSI_SIER_CMDDU_EN 0x00020000 135 #define SSI_SIER_RXT_EN 0x00010000 136 #define SSI_SIER_RDR1_EN 0x00008000 137 #define SSI_SIER_RDR0_EN 0x00004000 138 #define SSI_SIER_TDE1_EN 0x00002000 139 #define SSI_SIER_TDE0_EN 0x00001000 140 #define SSI_SIER_ROE1_EN 0x00000800 141 #define SSI_SIER_ROE0_EN 0x00000400 142 #define SSI_SIER_TUE1_EN 0x00000200 143 #define SSI_SIER_TUE0_EN 0x00000100 144 #define SSI_SIER_TFS_EN 0x00000080 145 #define SSI_SIER_RFS_EN 0x00000040 146 #define SSI_SIER_TLS_EN 0x00000020 147 #define SSI_SIER_RLS_EN 0x00000010 148 #define SSI_SIER_RFF1_EN 0x00000008 149 #define SSI_SIER_RFF0_EN 0x00000004 150 #define SSI_SIER_TFE1_EN 0x00000002 151 #define SSI_SIER_TFE0_EN 0x00000001 152 153 /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */ 154 #define SSI_STCR_TXBIT0 0x00000200 155 #define SSI_STCR_TFEN1 0x00000100 156 #define SSI_STCR_TFEN0 0x00000080 157 #define SSI_STCR_TFDIR 0x00000040 158 #define SSI_STCR_TXDIR 0x00000020 159 #define SSI_STCR_TSHFD 0x00000010 160 #define SSI_STCR_TSCKP 0x00000008 161 #define SSI_STCR_TFSI 0x00000004 162 #define SSI_STCR_TFSL 0x00000002 163 #define SSI_STCR_TEFS 0x00000001 164 165 /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */ 166 #define SSI_SRCR_RXEXT 0x00000400 167 #define SSI_SRCR_RXBIT0 0x00000200 168 #define SSI_SRCR_RFEN1 0x00000100 169 #define SSI_SRCR_RFEN0 0x00000080 170 #define SSI_SRCR_RFDIR 0x00000040 171 #define SSI_SRCR_RXDIR 0x00000020 172 #define SSI_SRCR_RSHFD 0x00000010 173 #define SSI_SRCR_RSCKP 0x00000008 174 #define SSI_SRCR_RFSI 0x00000004 175 #define SSI_SRCR_RFSL 0x00000002 176 #define SSI_SRCR_REFS 0x00000001 177 178 /* 179 * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24 180 * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28 181 */ 182 #define SSI_SxCCR_DIV2_SHIFT 18 183 #define SSI_SxCCR_DIV2 0x00040000 184 #define SSI_SxCCR_PSR_SHIFT 17 185 #define SSI_SxCCR_PSR 0x00020000 186 #define SSI_SxCCR_WL_SHIFT 13 187 #define SSI_SxCCR_WL_MASK 0x0001E000 188 #define SSI_SxCCR_WL(x) \ 189 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK) 190 #define SSI_SxCCR_DC_SHIFT 8 191 #define SSI_SxCCR_DC_MASK 0x00001F00 192 #define SSI_SxCCR_DC(x) \ 193 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK) 194 #define SSI_SxCCR_PM_SHIFT 0 195 #define SSI_SxCCR_PM_MASK 0x000000FF 196 #define SSI_SxCCR_PM(x) \ 197 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK) 198 199 /* 200 * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c 201 * 202 * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only 203 * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write 204 */ 205 #define SSI_SFCSR_RFCNT1_SHIFT 28 206 #define SSI_SFCSR_RFCNT1_MASK 0xF0000000 207 #define SSI_SFCSR_RFCNT1(x) \ 208 (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT) 209 #define SSI_SFCSR_TFCNT1_SHIFT 24 210 #define SSI_SFCSR_TFCNT1_MASK 0x0F000000 211 #define SSI_SFCSR_TFCNT1(x) \ 212 (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT) 213 #define SSI_SFCSR_RFWM1_SHIFT 20 214 #define SSI_SFCSR_RFWM1_MASK 0x00F00000 215 #define SSI_SFCSR_RFWM1(x) \ 216 (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK) 217 #define SSI_SFCSR_TFWM1_SHIFT 16 218 #define SSI_SFCSR_TFWM1_MASK 0x000F0000 219 #define SSI_SFCSR_TFWM1(x) \ 220 (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK) 221 #define SSI_SFCSR_RFCNT0_SHIFT 12 222 #define SSI_SFCSR_RFCNT0_MASK 0x0000F000 223 #define SSI_SFCSR_RFCNT0(x) \ 224 (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT) 225 #define SSI_SFCSR_TFCNT0_SHIFT 8 226 #define SSI_SFCSR_TFCNT0_MASK 0x00000F00 227 #define SSI_SFCSR_TFCNT0(x) \ 228 (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT) 229 #define SSI_SFCSR_RFWM0_SHIFT 4 230 #define SSI_SFCSR_RFWM0_MASK 0x000000F0 231 #define SSI_SFCSR_RFWM0(x) \ 232 (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK) 233 #define SSI_SFCSR_TFWM0_SHIFT 0 234 #define SSI_SFCSR_TFWM0_MASK 0x0000000F 235 #define SSI_SFCSR_TFWM0(x) \ 236 (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK) 237 238 /* SSI Test Register -- REG_SSI_STR 0x30 */ 239 #define SSI_STR_TEST 0x00008000 240 #define SSI_STR_RCK2TCK 0x00004000 241 #define SSI_STR_RFS2TFS 0x00002000 242 #define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F) 243 #define SSI_STR_TXD2RXD 0x00000080 244 #define SSI_STR_TCK2RCK 0x00000040 245 #define SSI_STR_TFS2RFS 0x00000020 246 #define SSI_STR_TXSTATE(x) ((x) & 0x1F) 247 248 /* SSI Option Register -- REG_SSI_SOR 0x34 */ 249 #define SSI_SOR_CLKOFF 0x00000040 250 #define SSI_SOR_RX_CLR 0x00000020 251 #define SSI_SOR_TX_CLR 0x00000010 252 #define SSI_SOR_xX_CLR(tx) ((tx) ? SSI_SOR_TX_CLR : SSI_SOR_RX_CLR) 253 #define SSI_SOR_INIT 0x00000008 254 #define SSI_SOR_WAIT_SHIFT 1 255 #define SSI_SOR_WAIT_MASK 0x00000006 256 #define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT) 257 #define SSI_SOR_SYNRST 0x00000001 258 259 /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */ 260 #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) 261 #define SSI_SACNT_WR 0x00000010 262 #define SSI_SACNT_RD 0x00000008 263 #define SSI_SACNT_RDWR_MASK 0x00000018 264 #define SSI_SACNT_TIF 0x00000004 265 #define SSI_SACNT_FV 0x00000002 266 #define SSI_SACNT_AC97EN 0x00000001 267 268 269 struct device; 270 271 #if IS_ENABLED(CONFIG_DEBUG_FS) 272 273 struct fsl_ssi_dbg { 274 struct dentry *dbg_dir; 275 struct dentry *dbg_stats; 276 277 struct { 278 unsigned int rfrc; 279 unsigned int tfrc; 280 unsigned int cmdau; 281 unsigned int cmddu; 282 unsigned int rxt; 283 unsigned int rdr1; 284 unsigned int rdr0; 285 unsigned int tde1; 286 unsigned int tde0; 287 unsigned int roe1; 288 unsigned int roe0; 289 unsigned int tue1; 290 unsigned int tue0; 291 unsigned int tfs; 292 unsigned int rfs; 293 unsigned int tls; 294 unsigned int rls; 295 unsigned int rff1; 296 unsigned int rff0; 297 unsigned int tfe1; 298 unsigned int tfe0; 299 } stats; 300 }; 301 302 void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr); 303 304 int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev); 305 306 void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg); 307 308 #else 309 310 struct fsl_ssi_dbg { 311 }; 312 313 static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr) 314 { 315 } 316 317 static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, 318 struct device *dev) 319 { 320 return 0; 321 } 322 323 static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg) 324 { 325 } 326 #endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */ 327 328 #endif 329