1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/ctype.h> 39 #include <linux/device.h> 40 #include <linux/delay.h> 41 #include <linux/mutex.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/of.h> 45 #include <linux/of_address.h> 46 #include <linux/of_irq.h> 47 #include <linux/of_platform.h> 48 49 #include <sound/core.h> 50 #include <sound/pcm.h> 51 #include <sound/pcm_params.h> 52 #include <sound/initval.h> 53 #include <sound/soc.h> 54 #include <sound/dmaengine_pcm.h> 55 56 #include "fsl_ssi.h" 57 #include "imx-pcm.h" 58 59 /** 60 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 61 * 62 * The SSI has a limitation in that the samples must be in the same byte 63 * order as the host CPU. This is because when multiple bytes are written 64 * to the STX register, the bytes and bits must be written in the same 65 * order. The STX is a shift register, so all the bits need to be aligned 66 * (bit-endianness must match byte-endianness). Processors typically write 67 * the bits within a byte in the same order that the bytes of a word are 68 * written in. So if the host CPU is big-endian, then only big-endian 69 * samples will be written to STX properly. 70 */ 71 #ifdef __BIG_ENDIAN 72 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 73 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 74 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 75 #else 76 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 77 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 78 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 79 #endif 80 81 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 82 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 83 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 84 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 85 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 86 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 87 88 enum fsl_ssi_type { 89 FSL_SSI_MCP8610, 90 FSL_SSI_MX21, 91 FSL_SSI_MX35, 92 FSL_SSI_MX51, 93 }; 94 95 struct fsl_ssi_reg_val { 96 u32 sier; 97 u32 srcr; 98 u32 stcr; 99 u32 scr; 100 }; 101 102 struct fsl_ssi_rxtx_reg_val { 103 struct fsl_ssi_reg_val rx; 104 struct fsl_ssi_reg_val tx; 105 }; 106 107 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 108 { 109 switch (reg) { 110 case CCSR_SSI_SACCEN: 111 case CCSR_SSI_SACCDIS: 112 return false; 113 default: 114 return true; 115 } 116 } 117 118 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 119 { 120 switch (reg) { 121 case CCSR_SSI_STX0: 122 case CCSR_SSI_STX1: 123 case CCSR_SSI_SRX0: 124 case CCSR_SSI_SRX1: 125 case CCSR_SSI_SISR: 126 case CCSR_SSI_SFCSR: 127 case CCSR_SSI_SACNT: 128 case CCSR_SSI_SACADD: 129 case CCSR_SSI_SACDAT: 130 case CCSR_SSI_SATAG: 131 case CCSR_SSI_SACCST: 132 case CCSR_SSI_SOR: 133 return true; 134 default: 135 return false; 136 } 137 } 138 139 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 140 { 141 switch (reg) { 142 case CCSR_SSI_SRX0: 143 case CCSR_SSI_SRX1: 144 case CCSR_SSI_SISR: 145 case CCSR_SSI_SACADD: 146 case CCSR_SSI_SACDAT: 147 case CCSR_SSI_SATAG: 148 return true; 149 default: 150 return false; 151 } 152 } 153 154 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 155 { 156 switch (reg) { 157 case CCSR_SSI_SRX0: 158 case CCSR_SSI_SRX1: 159 case CCSR_SSI_SACCST: 160 return false; 161 default: 162 return true; 163 } 164 } 165 166 static const struct regmap_config fsl_ssi_regconfig = { 167 .max_register = CCSR_SSI_SACCDIS, 168 .reg_bits = 32, 169 .val_bits = 32, 170 .reg_stride = 4, 171 .val_format_endian = REGMAP_ENDIAN_NATIVE, 172 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1, 173 .readable_reg = fsl_ssi_readable_reg, 174 .volatile_reg = fsl_ssi_volatile_reg, 175 .precious_reg = fsl_ssi_precious_reg, 176 .writeable_reg = fsl_ssi_writeable_reg, 177 .cache_type = REGCACHE_FLAT, 178 }; 179 180 struct fsl_ssi_soc_data { 181 bool imx; 182 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 183 bool offline_config; 184 u32 sisr_write_mask; 185 }; 186 187 /** 188 * fsl_ssi_private: per-SSI private data 189 * 190 * @reg: Pointer to the regmap registers 191 * @irq: IRQ of this SSI 192 * @cpu_dai_drv: CPU DAI driver for this device 193 * 194 * @dai_fmt: DAI configuration this device is currently used with 195 * @i2s_mode: i2s and network mode configuration of the device. Is used to 196 * switch between normal and i2s/network mode 197 * mode depending on the number of channels 198 * @use_dma: DMA is used or FIQ with stream filter 199 * @use_dual_fifo: DMA with support for both FIFOs used 200 * @fifo_deph: Depth of the SSI FIFOs 201 * @slot_width: width of each DAI slot 202 * @slots: number of slots 203 * @rxtx_reg_val: Specific register settings for receive/transmit configuration 204 * 205 * @clk: SSI clock 206 * @baudclk: SSI baud clock for master mode 207 * @baudclk_streams: Active streams that are using baudclk 208 * 209 * @dma_params_tx: DMA transmit parameters 210 * @dma_params_rx: DMA receive parameters 211 * @ssi_phys: physical address of the SSI registers 212 * 213 * @fiq_params: FIQ stream filtering parameters 214 * 215 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card 216 * 217 * @dbg_stats: Debugging statistics 218 * 219 * @soc: SoC specific data 220 * 221 * @fifo_watermark: the FIFO watermark setting. Notifies DMA when 222 * there are @fifo_watermark or fewer words in TX fifo or 223 * @fifo_watermark or more empty words in RX fifo. 224 * @dma_maxburst: max number of words to transfer in one go. So far, 225 * this is always the same as fifo_watermark. 226 */ 227 struct fsl_ssi_private { 228 struct regmap *regs; 229 int irq; 230 struct snd_soc_dai_driver cpu_dai_drv; 231 232 unsigned int dai_fmt; 233 u8 i2s_mode; 234 bool use_dma; 235 bool use_dual_fifo; 236 bool has_ipg_clk_name; 237 unsigned int fifo_depth; 238 unsigned int slot_width; 239 unsigned int slots; 240 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 241 242 struct clk *clk; 243 struct clk *baudclk; 244 unsigned int baudclk_streams; 245 246 /* regcache for volatile regs */ 247 u32 regcache_sfcsr; 248 u32 regcache_sacnt; 249 250 /* DMA params */ 251 struct snd_dmaengine_dai_dma_data dma_params_tx; 252 struct snd_dmaengine_dai_dma_data dma_params_rx; 253 dma_addr_t ssi_phys; 254 255 /* params for non-dma FIQ stream filtered mode */ 256 struct imx_pcm_fiq_params fiq_params; 257 258 /* Used when using fsl-ssi as sound-card. This is only used by ppc and 259 * should be replaced with simple-sound-card. */ 260 struct platform_device *pdev; 261 262 struct fsl_ssi_dbg dbg_stats; 263 264 const struct fsl_ssi_soc_data *soc; 265 struct device *dev; 266 267 u32 fifo_watermark; 268 u32 dma_maxburst; 269 270 struct mutex ac97_reg_lock; 271 }; 272 273 /* 274 * imx51 and later SoCs have a slightly different IP that allows the 275 * SSI configuration while the SSI unit is running. 276 * 277 * More important, it is necessary on those SoCs to configure the 278 * sperate TX/RX DMA bits just before starting the stream 279 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 280 * sends any DMA requests to the SDMA unit, otherwise it is not defined 281 * how the SDMA unit handles the DMA request. 282 * 283 * SDMA units are present on devices starting at imx35 but the imx35 284 * reference manual states that the DMA bits should not be changed 285 * while the SSI unit is running (SSIEN). So we support the necessary 286 * online configuration of fsl-ssi starting at imx51. 287 */ 288 289 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 290 .imx = false, 291 .offline_config = true, 292 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 293 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 294 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 295 }; 296 297 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 298 .imx = true, 299 .imx21regs = true, 300 .offline_config = true, 301 .sisr_write_mask = 0, 302 }; 303 304 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 305 .imx = true, 306 .offline_config = true, 307 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 308 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 309 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 310 }; 311 312 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 313 .imx = true, 314 .offline_config = false, 315 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 316 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 317 }; 318 319 static const struct of_device_id fsl_ssi_ids[] = { 320 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 321 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 322 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 323 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 324 {} 325 }; 326 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 327 328 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 329 { 330 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 331 SND_SOC_DAIFMT_AC97; 332 } 333 334 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) 335 { 336 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 337 SND_SOC_DAIFMT_CBS_CFS; 338 } 339 340 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) 341 { 342 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 343 SND_SOC_DAIFMT_CBM_CFS; 344 } 345 /** 346 * fsl_ssi_isr: SSI interrupt handler 347 * 348 * Although it's possible to use the interrupt handler to send and receive 349 * data to/from the SSI, we use the DMA instead. Programming is more 350 * complicated, but the performance is much better. 351 * 352 * This interrupt handler is used only to gather statistics. 353 * 354 * @irq: IRQ of the SSI device 355 * @dev_id: pointer to the ssi_private structure for this SSI device 356 */ 357 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 358 { 359 struct fsl_ssi_private *ssi_private = dev_id; 360 struct regmap *regs = ssi_private->regs; 361 __be32 sisr; 362 __be32 sisr2; 363 364 /* We got an interrupt, so read the status register to see what we 365 were interrupted for. We mask it with the Interrupt Enable register 366 so that we only check for events that we're interested in. 367 */ 368 regmap_read(regs, CCSR_SSI_SISR, &sisr); 369 370 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 371 /* Clear the bits that we set */ 372 if (sisr2) 373 regmap_write(regs, CCSR_SSI_SISR, sisr2); 374 375 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 376 377 return IRQ_HANDLED; 378 } 379 380 /* 381 * Enable/Disable all rx/tx config flags at once. 382 */ 383 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 384 bool enable) 385 { 386 struct regmap *regs = ssi_private->regs; 387 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 388 389 if (enable) { 390 regmap_update_bits(regs, CCSR_SSI_SIER, 391 vals->rx.sier | vals->tx.sier, 392 vals->rx.sier | vals->tx.sier); 393 regmap_update_bits(regs, CCSR_SSI_SRCR, 394 vals->rx.srcr | vals->tx.srcr, 395 vals->rx.srcr | vals->tx.srcr); 396 regmap_update_bits(regs, CCSR_SSI_STCR, 397 vals->rx.stcr | vals->tx.stcr, 398 vals->rx.stcr | vals->tx.stcr); 399 } else { 400 regmap_update_bits(regs, CCSR_SSI_SRCR, 401 vals->rx.srcr | vals->tx.srcr, 0); 402 regmap_update_bits(regs, CCSR_SSI_STCR, 403 vals->rx.stcr | vals->tx.stcr, 0); 404 regmap_update_bits(regs, CCSR_SSI_SIER, 405 vals->rx.sier | vals->tx.sier, 0); 406 } 407 } 408 409 /* 410 * Clear RX or TX FIFO to remove samples from the previous 411 * stream session which may be still present in the FIFO and 412 * may introduce bad samples and/or channel slipping. 413 * 414 * Note: The SOR is not documented in recent IMX datasheet, but 415 * is described in IMX51 reference manual at section 56.3.3.15. 416 */ 417 static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private, 418 bool is_rx) 419 { 420 if (is_rx) { 421 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 422 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR); 423 } else { 424 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 425 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR); 426 } 427 } 428 429 /* 430 * Calculate the bits that have to be disabled for the current stream that is 431 * getting disabled. This keeps the bits enabled that are necessary for the 432 * second stream to work if 'stream_active' is true. 433 * 434 * Detailed calculation: 435 * These are the values that need to be active after disabling. For non-active 436 * second stream, this is 0: 437 * vals_stream * !!stream_active 438 * 439 * The following computes the overall differences between the setup for the 440 * to-disable stream and the active stream, a simple XOR: 441 * vals_disable ^ (vals_stream * !!(stream_active)) 442 * 443 * The full expression adds a mask on all values we care about 444 */ 445 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 446 ((vals_disable) & \ 447 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 448 449 /* 450 * Enable/Disable a ssi configuration. You have to pass either 451 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 452 */ 453 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 454 struct fsl_ssi_reg_val *vals) 455 { 456 struct regmap *regs = ssi_private->regs; 457 struct fsl_ssi_reg_val *avals; 458 int nr_active_streams; 459 u32 scr_val; 460 int keep_active; 461 462 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 463 464 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 465 !!(scr_val & CCSR_SSI_SCR_RE); 466 467 if (nr_active_streams - 1 > 0) 468 keep_active = 1; 469 else 470 keep_active = 0; 471 472 /* Find the other direction values rx or tx which we do not want to 473 * modify */ 474 if (&ssi_private->rxtx_reg_val.rx == vals) 475 avals = &ssi_private->rxtx_reg_val.tx; 476 else 477 avals = &ssi_private->rxtx_reg_val.rx; 478 479 /* If vals should be disabled, start with disabling the unit */ 480 if (!enable) { 481 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 482 keep_active); 483 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 484 } 485 486 /* 487 * We are running on a SoC which does not support online SSI 488 * reconfiguration, so we have to enable all necessary flags at once 489 * even if we do not use them later (capture and playback configuration) 490 */ 491 if (ssi_private->soc->offline_config) { 492 if ((enable && !nr_active_streams) || 493 (!enable && !keep_active)) 494 fsl_ssi_rxtx_config(ssi_private, enable); 495 496 goto config_done; 497 } 498 499 /* 500 * Configure single direction units while the SSI unit is running 501 * (online configuration) 502 */ 503 if (enable) { 504 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE); 505 506 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 507 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 508 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 509 } else { 510 u32 sier; 511 u32 srcr; 512 u32 stcr; 513 514 /* 515 * Disabling the necessary flags for one of rx/tx while the 516 * other stream is active is a little bit more difficult. We 517 * have to disable only those flags that differ between both 518 * streams (rx XOR tx) and that are set in the stream that is 519 * disabled now. Otherwise we could alter flags of the other 520 * stream 521 */ 522 523 /* These assignments are simply vals without bits set in avals*/ 524 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 525 keep_active); 526 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 527 keep_active); 528 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 529 keep_active); 530 531 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 532 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 533 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 534 } 535 536 config_done: 537 /* Enabling of subunits is done after configuration */ 538 if (enable) { 539 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { 540 /* 541 * Be sure the Tx FIFO is filled when TE is set. 542 * Otherwise, there are some chances to start the 543 * playback with some void samples inserted first, 544 * generating a channel slip. 545 * 546 * First, SSIEN must be set, to let the FIFO be filled. 547 * 548 * Notes: 549 * - Limit this fix to the DMA case until FIQ cases can 550 * be tested. 551 * - Limit the length of the busy loop to not lock the 552 * system too long, even if 1-2 loops are sufficient 553 * in general. 554 */ 555 int i; 556 int max_loop = 100; 557 regmap_update_bits(regs, CCSR_SSI_SCR, 558 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); 559 for (i = 0; i < max_loop; i++) { 560 u32 sfcsr; 561 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); 562 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) 563 break; 564 } 565 if (i == max_loop) { 566 dev_err(ssi_private->dev, 567 "Timeout waiting TX FIFO filling\n"); 568 } 569 } 570 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 571 } 572 } 573 574 575 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 576 { 577 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 578 } 579 580 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 581 { 582 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 583 } 584 585 /* 586 * Setup rx/tx register values used to enable/disable the streams. These will 587 * be used later in fsl_ssi_config to setup the streams without the need to 588 * check for all different SSI modes. 589 */ 590 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 591 { 592 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 593 594 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 595 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 596 reg->rx.scr = 0; 597 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 598 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 599 reg->tx.scr = 0; 600 601 if (!fsl_ssi_is_ac97(ssi_private)) { 602 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 603 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 604 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 605 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 606 } 607 608 if (ssi_private->use_dma) { 609 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 610 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 611 } else { 612 reg->rx.sier |= CCSR_SSI_SIER_RIE; 613 reg->tx.sier |= CCSR_SSI_SIER_TIE; 614 } 615 616 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 617 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 618 } 619 620 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 621 { 622 struct regmap *regs = ssi_private->regs; 623 624 /* 625 * Setup the clock control register 626 */ 627 regmap_write(regs, CCSR_SSI_STCCR, 628 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 629 regmap_write(regs, CCSR_SSI_SRCCR, 630 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 631 632 /* 633 * Enable AC97 mode and startup the SSI 634 */ 635 regmap_write(regs, CCSR_SSI_SACNT, 636 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 637 638 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 639 if (!ssi_private->soc->imx21regs) { 640 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 641 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 642 } 643 644 /* 645 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 646 * codec before a stream is started. 647 */ 648 regmap_update_bits(regs, CCSR_SSI_SCR, 649 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 650 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 651 652 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 653 } 654 655 /** 656 * fsl_ssi_startup: create a new substream 657 * 658 * This is the first function called when a stream is opened. 659 * 660 * If this is the first stream open, then grab the IRQ and program most of 661 * the SSI registers. 662 */ 663 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 664 struct snd_soc_dai *dai) 665 { 666 struct snd_soc_pcm_runtime *rtd = substream->private_data; 667 struct fsl_ssi_private *ssi_private = 668 snd_soc_dai_get_drvdata(rtd->cpu_dai); 669 int ret; 670 671 ret = clk_prepare_enable(ssi_private->clk); 672 if (ret) 673 return ret; 674 675 /* When using dual fifo mode, it is safer to ensure an even period 676 * size. If appearing to an odd number while DMA always starts its 677 * task from fifo0, fifo1 would be neglected at the end of each 678 * period. But SSI would still access fifo1 with an invalid data. 679 */ 680 if (ssi_private->use_dual_fifo) 681 snd_pcm_hw_constraint_step(substream->runtime, 0, 682 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 683 684 return 0; 685 } 686 687 /** 688 * fsl_ssi_shutdown: shutdown the SSI 689 * 690 */ 691 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 692 struct snd_soc_dai *dai) 693 { 694 struct snd_soc_pcm_runtime *rtd = substream->private_data; 695 struct fsl_ssi_private *ssi_private = 696 snd_soc_dai_get_drvdata(rtd->cpu_dai); 697 698 clk_disable_unprepare(ssi_private->clk); 699 700 } 701 702 /** 703 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock 704 * 705 * Note: This function can be only called when using SSI as DAI master 706 * 707 * Quick instruction for parameters: 708 * freq: Output BCLK frequency = samplerate * slots * slot_width 709 * (In 2-channel I2S Master mode, slot_width is fixed 32) 710 */ 711 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 712 struct snd_soc_dai *cpu_dai, 713 struct snd_pcm_hw_params *hw_params) 714 { 715 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 716 struct regmap *regs = ssi_private->regs; 717 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 718 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 719 unsigned long clkrate, baudrate, tmprate; 720 unsigned int slots = params_channels(hw_params); 721 unsigned int slot_width = 32; 722 u64 sub, savesub = 100000; 723 unsigned int freq; 724 bool baudclk_is_used; 725 726 /* Override slots and slot_width if being specifically set... */ 727 if (ssi_private->slots) 728 slots = ssi_private->slots; 729 /* ...but keep 32 bits if slots is 2 -- I2S Master mode */ 730 if (ssi_private->slot_width && slots != 2) 731 slot_width = ssi_private->slot_width; 732 733 /* Generate bit clock based on the slot number and slot width */ 734 freq = slots * slot_width * params_rate(hw_params); 735 736 /* Don't apply it to any non-baudclk circumstance */ 737 if (IS_ERR(ssi_private->baudclk)) 738 return -EINVAL; 739 740 /* 741 * Hardware limitation: The bclk rate must be 742 * never greater than 1/5 IPG clock rate 743 */ 744 if (freq * 5 > clk_get_rate(ssi_private->clk)) { 745 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n"); 746 return -EINVAL; 747 } 748 749 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); 750 751 /* It should be already enough to divide clock by setting pm alone */ 752 psr = 0; 753 div2 = 0; 754 755 factor = (div2 + 1) * (7 * psr + 1) * 2; 756 757 for (i = 0; i < 255; i++) { 758 tmprate = freq * factor * (i + 1); 759 760 if (baudclk_is_used) 761 clkrate = clk_get_rate(ssi_private->baudclk); 762 else 763 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 764 765 clkrate /= factor; 766 afreq = clkrate / (i + 1); 767 768 if (freq == afreq) 769 sub = 0; 770 else if (freq / afreq == 1) 771 sub = freq - afreq; 772 else if (afreq / freq == 1) 773 sub = afreq - freq; 774 else 775 continue; 776 777 /* Calculate the fraction */ 778 sub *= 100000; 779 do_div(sub, freq); 780 781 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 782 baudrate = tmprate; 783 savesub = sub; 784 pm = i; 785 } 786 787 /* We are lucky */ 788 if (savesub == 0) 789 break; 790 } 791 792 /* No proper pm found if it is still remaining the initial value */ 793 if (pm == 999) { 794 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 795 return -EINVAL; 796 } 797 798 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 799 (psr ? CCSR_SSI_SxCCR_PSR : 0); 800 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 801 CCSR_SSI_SxCCR_PSR; 802 803 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 804 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 805 else 806 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 807 808 if (!baudclk_is_used) { 809 ret = clk_set_rate(ssi_private->baudclk, baudrate); 810 if (ret) { 811 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 812 return -EINVAL; 813 } 814 } 815 816 return 0; 817 } 818 819 /** 820 * fsl_ssi_hw_params - program the sample size 821 * 822 * Most of the SSI registers have been programmed in the startup function, 823 * but the word length must be programmed here. Unfortunately, programming 824 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 825 * cause a problem with supporting simultaneous playback and capture. If 826 * the SSI is already playing a stream, then that stream may be temporarily 827 * stopped when you start capture. 828 * 829 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 830 * clock master. 831 */ 832 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 833 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 834 { 835 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 836 struct regmap *regs = ssi_private->regs; 837 unsigned int channels = params_channels(hw_params); 838 unsigned int sample_size = params_width(hw_params); 839 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 840 int ret; 841 u32 scr_val; 842 int enabled; 843 844 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 845 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 846 847 /* 848 * If we're in synchronous mode, and the SSI is already enabled, 849 * then STCCR is already set properly. 850 */ 851 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 852 return 0; 853 854 if (fsl_ssi_is_i2s_master(ssi_private)) { 855 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); 856 if (ret) 857 return ret; 858 859 /* Do not enable the clock if it is already enabled */ 860 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { 861 ret = clk_prepare_enable(ssi_private->baudclk); 862 if (ret) 863 return ret; 864 865 ssi_private->baudclk_streams |= BIT(substream->stream); 866 } 867 } 868 869 if (!fsl_ssi_is_ac97(ssi_private)) { 870 u8 i2smode; 871 /* 872 * Switch to normal net mode in order to have a frame sync 873 * signal every 32 bits instead of 16 bits 874 */ 875 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) 876 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 877 CCSR_SSI_SCR_NET; 878 else 879 i2smode = ssi_private->i2s_mode; 880 881 regmap_update_bits(regs, CCSR_SSI_SCR, 882 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 883 channels == 1 ? 0 : i2smode); 884 } 885 886 /* 887 * FIXME: The documentation says that SxCCR[WL] should not be 888 * modified while the SSI is enabled. The only time this can 889 * happen is if we're trying to do simultaneous playback and 890 * capture in asynchronous mode. Unfortunately, I have been enable 891 * to get that to work at all on the P1022DS. Therefore, we don't 892 * bother to disable/enable the SSI when setting SxCCR[WL], because 893 * the SSI will stop anyway. Maybe one day, this will get fixed. 894 */ 895 896 /* In synchronous mode, the SSI uses STCCR for capture */ 897 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 898 ssi_private->cpu_dai_drv.symmetric_rates) 899 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 900 wl); 901 else 902 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 903 wl); 904 905 return 0; 906 } 907 908 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 909 struct snd_soc_dai *cpu_dai) 910 { 911 struct snd_soc_pcm_runtime *rtd = substream->private_data; 912 struct fsl_ssi_private *ssi_private = 913 snd_soc_dai_get_drvdata(rtd->cpu_dai); 914 915 if (fsl_ssi_is_i2s_master(ssi_private) && 916 ssi_private->baudclk_streams & BIT(substream->stream)) { 917 clk_disable_unprepare(ssi_private->baudclk); 918 ssi_private->baudclk_streams &= ~BIT(substream->stream); 919 } 920 921 return 0; 922 } 923 924 static int _fsl_ssi_set_dai_fmt(struct device *dev, 925 struct fsl_ssi_private *ssi_private, 926 unsigned int fmt) 927 { 928 struct regmap *regs = ssi_private->regs; 929 u32 strcr = 0, stcr, srcr, scr, mask; 930 u8 wm; 931 932 ssi_private->dai_fmt = fmt; 933 934 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { 935 dev_err(dev, "baudclk is missing which is necessary for master mode\n"); 936 return -EINVAL; 937 } 938 939 fsl_ssi_setup_reg_vals(ssi_private); 940 941 regmap_read(regs, CCSR_SSI_SCR, &scr); 942 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 943 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 944 945 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 946 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 947 CCSR_SSI_STCR_TEFS; 948 regmap_read(regs, CCSR_SSI_STCR, &stcr); 949 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 950 stcr &= ~mask; 951 srcr &= ~mask; 952 953 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 954 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 955 case SND_SOC_DAIFMT_I2S: 956 regmap_update_bits(regs, CCSR_SSI_STCCR, 957 CCSR_SSI_SxCCR_DC_MASK, 958 CCSR_SSI_SxCCR_DC(2)); 959 regmap_update_bits(regs, CCSR_SSI_SRCCR, 960 CCSR_SSI_SxCCR_DC_MASK, 961 CCSR_SSI_SxCCR_DC(2)); 962 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 963 case SND_SOC_DAIFMT_CBM_CFS: 964 case SND_SOC_DAIFMT_CBS_CFS: 965 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 966 break; 967 case SND_SOC_DAIFMT_CBM_CFM: 968 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 969 break; 970 default: 971 return -EINVAL; 972 } 973 974 /* Data on rising edge of bclk, frame low, 1clk before data */ 975 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 976 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 977 break; 978 case SND_SOC_DAIFMT_LEFT_J: 979 /* Data on rising edge of bclk, frame high */ 980 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 981 break; 982 case SND_SOC_DAIFMT_DSP_A: 983 /* Data on rising edge of bclk, frame high, 1clk before data */ 984 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 985 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 986 break; 987 case SND_SOC_DAIFMT_DSP_B: 988 /* Data on rising edge of bclk, frame high */ 989 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 990 CCSR_SSI_STCR_TXBIT0; 991 break; 992 case SND_SOC_DAIFMT_AC97: 993 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 994 break; 995 default: 996 return -EINVAL; 997 } 998 scr |= ssi_private->i2s_mode; 999 1000 /* DAI clock inversion */ 1001 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1002 case SND_SOC_DAIFMT_NB_NF: 1003 /* Nothing to do for both normal cases */ 1004 break; 1005 case SND_SOC_DAIFMT_IB_NF: 1006 /* Invert bit clock */ 1007 strcr ^= CCSR_SSI_STCR_TSCKP; 1008 break; 1009 case SND_SOC_DAIFMT_NB_IF: 1010 /* Invert frame clock */ 1011 strcr ^= CCSR_SSI_STCR_TFSI; 1012 break; 1013 case SND_SOC_DAIFMT_IB_IF: 1014 /* Invert both clocks */ 1015 strcr ^= CCSR_SSI_STCR_TSCKP; 1016 strcr ^= CCSR_SSI_STCR_TFSI; 1017 break; 1018 default: 1019 return -EINVAL; 1020 } 1021 1022 /* DAI clock master masks */ 1023 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1024 case SND_SOC_DAIFMT_CBS_CFS: 1025 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 1026 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 1027 break; 1028 case SND_SOC_DAIFMT_CBM_CFM: 1029 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1030 break; 1031 case SND_SOC_DAIFMT_CBM_CFS: 1032 strcr &= ~CCSR_SSI_STCR_TXDIR; 1033 strcr |= CCSR_SSI_STCR_TFDIR; 1034 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1035 break; 1036 default: 1037 if (!fsl_ssi_is_ac97(ssi_private)) 1038 return -EINVAL; 1039 } 1040 1041 stcr |= strcr; 1042 srcr |= strcr; 1043 1044 if (ssi_private->cpu_dai_drv.symmetric_rates 1045 || fsl_ssi_is_ac97(ssi_private)) { 1046 /* Need to clear RXDIR when using SYNC or AC97 mode */ 1047 srcr &= ~CCSR_SSI_SRCR_RXDIR; 1048 scr |= CCSR_SSI_SCR_SYN; 1049 } 1050 1051 regmap_write(regs, CCSR_SSI_STCR, stcr); 1052 regmap_write(regs, CCSR_SSI_SRCR, srcr); 1053 regmap_write(regs, CCSR_SSI_SCR, scr); 1054 1055 wm = ssi_private->fifo_watermark; 1056 1057 regmap_write(regs, CCSR_SSI_SFCSR, 1058 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 1059 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 1060 1061 if (ssi_private->use_dual_fifo) { 1062 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 1063 CCSR_SSI_SRCR_RFEN1); 1064 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 1065 CCSR_SSI_STCR_TFEN1); 1066 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 1067 CCSR_SSI_SCR_TCH_EN); 1068 } 1069 1070 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1071 fsl_ssi_setup_ac97(ssi_private); 1072 1073 return 0; 1074 1075 } 1076 1077 /** 1078 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 1079 */ 1080 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 1081 { 1082 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1083 1084 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); 1085 } 1086 1087 /** 1088 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 1089 * 1090 * Note: This function can be only called when using SSI as DAI master 1091 */ 1092 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 1093 u32 rx_mask, int slots, int slot_width) 1094 { 1095 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1096 struct regmap *regs = ssi_private->regs; 1097 u32 val; 1098 1099 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ 1100 if (slot_width & 1 || slot_width < 8 || slot_width > 24) { 1101 dev_err(cpu_dai->dev, "invalid slot width: %d\n", slot_width); 1102 return -EINVAL; 1103 } 1104 1105 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1106 regmap_read(regs, CCSR_SSI_SCR, &val); 1107 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 1108 if (val && slots < 2) { 1109 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1110 return -EINVAL; 1111 } 1112 1113 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 1114 CCSR_SSI_SxCCR_DC(slots)); 1115 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 1116 CCSR_SSI_SxCCR_DC(slots)); 1117 1118 /* The register SxMSKs needs SSI to provide essential clock due to 1119 * hardware design. So we here temporarily enable SSI to set them. 1120 */ 1121 regmap_read(regs, CCSR_SSI_SCR, &val); 1122 val &= CCSR_SSI_SCR_SSIEN; 1123 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 1124 CCSR_SSI_SCR_SSIEN); 1125 1126 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1127 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1128 1129 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1130 1131 ssi_private->slot_width = slot_width; 1132 ssi_private->slots = slots; 1133 1134 return 0; 1135 } 1136 1137 /** 1138 * fsl_ssi_trigger: start and stop the DMA transfer. 1139 * 1140 * This function is called by ALSA to start, stop, pause, and resume the DMA 1141 * transfer of data. 1142 * 1143 * The DMA channel is in external master start and pause mode, which 1144 * means the SSI completely controls the flow of data. 1145 */ 1146 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1147 struct snd_soc_dai *dai) 1148 { 1149 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1150 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1151 struct regmap *regs = ssi_private->regs; 1152 1153 switch (cmd) { 1154 case SNDRV_PCM_TRIGGER_START: 1155 case SNDRV_PCM_TRIGGER_RESUME: 1156 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1157 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1158 fsl_ssi_tx_config(ssi_private, true); 1159 else 1160 fsl_ssi_rx_config(ssi_private, true); 1161 break; 1162 1163 case SNDRV_PCM_TRIGGER_STOP: 1164 case SNDRV_PCM_TRIGGER_SUSPEND: 1165 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1166 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1167 fsl_ssi_tx_config(ssi_private, false); 1168 else 1169 fsl_ssi_rx_config(ssi_private, false); 1170 break; 1171 1172 default: 1173 return -EINVAL; 1174 } 1175 1176 if (fsl_ssi_is_ac97(ssi_private)) { 1177 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1178 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1179 else 1180 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1187 { 1188 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 1189 1190 if (ssi_private->soc->imx && ssi_private->use_dma) { 1191 dai->playback_dma_data = &ssi_private->dma_params_tx; 1192 dai->capture_dma_data = &ssi_private->dma_params_rx; 1193 } 1194 1195 return 0; 1196 } 1197 1198 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1199 .startup = fsl_ssi_startup, 1200 .shutdown = fsl_ssi_shutdown, 1201 .hw_params = fsl_ssi_hw_params, 1202 .hw_free = fsl_ssi_hw_free, 1203 .set_fmt = fsl_ssi_set_dai_fmt, 1204 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1205 .trigger = fsl_ssi_trigger, 1206 }; 1207 1208 /* Template for the CPU dai driver structure */ 1209 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1210 .probe = fsl_ssi_dai_probe, 1211 .playback = { 1212 .stream_name = "CPU-Playback", 1213 .channels_min = 1, 1214 .channels_max = 32, 1215 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1216 .formats = FSLSSI_I2S_FORMATS, 1217 }, 1218 .capture = { 1219 .stream_name = "CPU-Capture", 1220 .channels_min = 1, 1221 .channels_max = 32, 1222 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1223 .formats = FSLSSI_I2S_FORMATS, 1224 }, 1225 .ops = &fsl_ssi_dai_ops, 1226 }; 1227 1228 static const struct snd_soc_component_driver fsl_ssi_component = { 1229 .name = "fsl-ssi", 1230 }; 1231 1232 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1233 .bus_control = true, 1234 .probe = fsl_ssi_dai_probe, 1235 .playback = { 1236 .stream_name = "AC97 Playback", 1237 .channels_min = 2, 1238 .channels_max = 2, 1239 .rates = SNDRV_PCM_RATE_8000_48000, 1240 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1241 }, 1242 .capture = { 1243 .stream_name = "AC97 Capture", 1244 .channels_min = 2, 1245 .channels_max = 2, 1246 .rates = SNDRV_PCM_RATE_48000, 1247 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1248 }, 1249 .ops = &fsl_ssi_dai_ops, 1250 }; 1251 1252 1253 static struct fsl_ssi_private *fsl_ac97_data; 1254 1255 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1256 unsigned short val) 1257 { 1258 struct regmap *regs = fsl_ac97_data->regs; 1259 unsigned int lreg; 1260 unsigned int lval; 1261 int ret; 1262 1263 if (reg > 0x7f) 1264 return; 1265 1266 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1267 1268 ret = clk_prepare_enable(fsl_ac97_data->clk); 1269 if (ret) { 1270 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1271 ret); 1272 goto ret_unlock; 1273 } 1274 1275 lreg = reg << 12; 1276 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1277 1278 lval = val << 4; 1279 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1280 1281 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1282 CCSR_SSI_SACNT_WR); 1283 udelay(100); 1284 1285 clk_disable_unprepare(fsl_ac97_data->clk); 1286 1287 ret_unlock: 1288 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1289 } 1290 1291 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1292 unsigned short reg) 1293 { 1294 struct regmap *regs = fsl_ac97_data->regs; 1295 1296 unsigned short val = 0; 1297 u32 reg_val; 1298 unsigned int lreg; 1299 int ret; 1300 1301 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1302 1303 ret = clk_prepare_enable(fsl_ac97_data->clk); 1304 if (ret) { 1305 pr_err("ac97 read clk_prepare_enable failed: %d\n", 1306 ret); 1307 goto ret_unlock; 1308 } 1309 1310 lreg = (reg & 0x7f) << 12; 1311 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1312 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1313 CCSR_SSI_SACNT_RD); 1314 1315 udelay(100); 1316 1317 regmap_read(regs, CCSR_SSI_SACDAT, ®_val); 1318 val = (reg_val >> 4) & 0xffff; 1319 1320 clk_disable_unprepare(fsl_ac97_data->clk); 1321 1322 ret_unlock: 1323 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1324 return val; 1325 } 1326 1327 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1328 .read = fsl_ssi_ac97_read, 1329 .write = fsl_ssi_ac97_write, 1330 }; 1331 1332 /** 1333 * Make every character in a string lower-case 1334 */ 1335 static void make_lowercase(char *s) 1336 { 1337 if (!s) 1338 return; 1339 for (; *s; s++) 1340 *s = tolower(*s); 1341 } 1342 1343 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1344 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1345 { 1346 struct device_node *np = pdev->dev.of_node; 1347 u32 dmas[4]; 1348 int ret; 1349 1350 if (ssi_private->has_ipg_clk_name) 1351 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); 1352 else 1353 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1354 if (IS_ERR(ssi_private->clk)) { 1355 ret = PTR_ERR(ssi_private->clk); 1356 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1357 return ret; 1358 } 1359 1360 if (!ssi_private->has_ipg_clk_name) { 1361 ret = clk_prepare_enable(ssi_private->clk); 1362 if (ret) { 1363 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1364 return ret; 1365 } 1366 } 1367 1368 /* For those SLAVE implementations, we ignore non-baudclk cases 1369 * and, instead, abandon MASTER mode that needs baud clock. 1370 */ 1371 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1372 if (IS_ERR(ssi_private->baudclk)) 1373 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1374 PTR_ERR(ssi_private->baudclk)); 1375 1376 ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst; 1377 ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst; 1378 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; 1379 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; 1380 1381 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1382 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1383 ssi_private->use_dual_fifo = true; 1384 /* When using dual fifo mode, we need to keep watermark 1385 * as even numbers due to dma script limitation. 1386 */ 1387 ssi_private->dma_params_tx.maxburst &= ~0x1; 1388 ssi_private->dma_params_rx.maxburst &= ~0x1; 1389 } 1390 1391 if (!ssi_private->use_dma) { 1392 1393 /* 1394 * Some boards use an incompatible codec. To get it 1395 * working, we are using imx-fiq-pcm-audio, that 1396 * can handle those codecs. DMA is not possible in this 1397 * situation. 1398 */ 1399 1400 ssi_private->fiq_params.irq = ssi_private->irq; 1401 ssi_private->fiq_params.base = iomem; 1402 ssi_private->fiq_params.dma_params_rx = 1403 &ssi_private->dma_params_rx; 1404 ssi_private->fiq_params.dma_params_tx = 1405 &ssi_private->dma_params_tx; 1406 1407 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1408 if (ret) 1409 goto error_pcm; 1410 } else { 1411 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1412 if (ret) 1413 goto error_pcm; 1414 } 1415 1416 return 0; 1417 1418 error_pcm: 1419 1420 if (!ssi_private->has_ipg_clk_name) 1421 clk_disable_unprepare(ssi_private->clk); 1422 return ret; 1423 } 1424 1425 static void fsl_ssi_imx_clean(struct platform_device *pdev, 1426 struct fsl_ssi_private *ssi_private) 1427 { 1428 if (!ssi_private->use_dma) 1429 imx_pcm_fiq_exit(pdev); 1430 if (!ssi_private->has_ipg_clk_name) 1431 clk_disable_unprepare(ssi_private->clk); 1432 } 1433 1434 static int fsl_ssi_probe(struct platform_device *pdev) 1435 { 1436 struct fsl_ssi_private *ssi_private; 1437 int ret = 0; 1438 struct device_node *np = pdev->dev.of_node; 1439 const struct of_device_id *of_id; 1440 const char *p, *sprop; 1441 const uint32_t *iprop; 1442 struct resource *res; 1443 void __iomem *iomem; 1444 char name[64]; 1445 struct regmap_config regconfig = fsl_ssi_regconfig; 1446 1447 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1448 if (!of_id || !of_id->data) 1449 return -EINVAL; 1450 1451 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1452 GFP_KERNEL); 1453 if (!ssi_private) 1454 return -ENOMEM; 1455 1456 ssi_private->soc = of_id->data; 1457 ssi_private->dev = &pdev->dev; 1458 1459 sprop = of_get_property(np, "fsl,mode", NULL); 1460 if (sprop) { 1461 if (!strcmp(sprop, "ac97-slave")) 1462 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; 1463 } 1464 1465 ssi_private->use_dma = !of_property_read_bool(np, 1466 "fsl,fiq-stream-filter"); 1467 1468 if (fsl_ssi_is_ac97(ssi_private)) { 1469 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1470 sizeof(fsl_ssi_ac97_dai)); 1471 1472 fsl_ac97_data = ssi_private; 1473 } else { 1474 /* Initialize this copy of the CPU DAI driver structure */ 1475 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1476 sizeof(fsl_ssi_dai_template)); 1477 } 1478 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1479 1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1481 iomem = devm_ioremap_resource(&pdev->dev, res); 1482 if (IS_ERR(iomem)) 1483 return PTR_ERR(iomem); 1484 ssi_private->ssi_phys = res->start; 1485 1486 if (ssi_private->soc->imx21regs) { 1487 /* 1488 * According to datasheet imx21-class SSI 1489 * don't have SACC{ST,EN,DIS} regs. 1490 */ 1491 regconfig.max_register = CCSR_SSI_SRMSK; 1492 regconfig.num_reg_defaults_raw = 1493 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1; 1494 } 1495 1496 ret = of_property_match_string(np, "clock-names", "ipg"); 1497 if (ret < 0) { 1498 ssi_private->has_ipg_clk_name = false; 1499 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1500 ®config); 1501 } else { 1502 ssi_private->has_ipg_clk_name = true; 1503 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1504 "ipg", iomem, ®config); 1505 } 1506 if (IS_ERR(ssi_private->regs)) { 1507 dev_err(&pdev->dev, "Failed to init register map\n"); 1508 return PTR_ERR(ssi_private->regs); 1509 } 1510 1511 ssi_private->irq = platform_get_irq(pdev, 0); 1512 if (ssi_private->irq < 0) { 1513 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1514 return ssi_private->irq; 1515 } 1516 1517 /* Are the RX and the TX clocks locked? */ 1518 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1519 if (!fsl_ssi_is_ac97(ssi_private)) 1520 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1521 1522 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1523 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1524 } 1525 1526 /* Determine the FIFO depth. */ 1527 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1528 if (iprop) 1529 ssi_private->fifo_depth = be32_to_cpup(iprop); 1530 else 1531 /* Older 8610 DTs didn't have the fifo-depth property */ 1532 ssi_private->fifo_depth = 8; 1533 1534 /* 1535 * Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't 1536 * use FIFO 1 but set the watermark appropriately nontheless. 1537 * We program the transmit water to signal a DMA transfer 1538 * if there are N elements left in the FIFO. For chips with 15-deep 1539 * FIFOs, set watermark to 8. This allows the SSI to operate at a 1540 * high data rate without channel slipping. Behavior is unchanged 1541 * for the older chips with a fifo depth of only 8. A value of 4 1542 * might be appropriate for the older chips, but is left at 1543 * fifo_depth-2 until sombody has a chance to test. 1544 * 1545 * We set the watermark on the same level as the DMA burstsize. For 1546 * fiq it is probably better to use the biggest possible watermark 1547 * size. 1548 */ 1549 switch (ssi_private->fifo_depth) { 1550 case 15: 1551 /* 1552 * 2 samples is not enough when running at high data 1553 * rates (like 48kHz @ 16 bits/channel, 16 channels) 1554 * 8 seems to split things evenly and leave enough time 1555 * for the DMA to fill the FIFO before it's over/under 1556 * run. 1557 */ 1558 ssi_private->fifo_watermark = 8; 1559 ssi_private->dma_maxburst = 8; 1560 break; 1561 case 8: 1562 default: 1563 /* 1564 * maintain old behavior for older chips. 1565 * Keeping it the same because I don't have an older 1566 * board to test with. 1567 * I suspect this could be changed to be something to 1568 * leave some more space in the fifo. 1569 */ 1570 ssi_private->fifo_watermark = ssi_private->fifo_depth - 2; 1571 ssi_private->dma_maxburst = ssi_private->fifo_depth - 2; 1572 break; 1573 } 1574 1575 dev_set_drvdata(&pdev->dev, ssi_private); 1576 1577 if (ssi_private->soc->imx) { 1578 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); 1579 if (ret) 1580 return ret; 1581 } 1582 1583 if (fsl_ssi_is_ac97(ssi_private)) { 1584 mutex_init(&ssi_private->ac97_reg_lock); 1585 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1586 if (ret) { 1587 dev_err(&pdev->dev, "could not set AC'97 ops\n"); 1588 goto error_ac97_ops; 1589 } 1590 } 1591 1592 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1593 &ssi_private->cpu_dai_drv, 1); 1594 if (ret) { 1595 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1596 goto error_asoc_register; 1597 } 1598 1599 if (ssi_private->use_dma) { 1600 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1601 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1602 ssi_private); 1603 if (ret < 0) { 1604 dev_err(&pdev->dev, "could not claim irq %u\n", 1605 ssi_private->irq); 1606 goto error_asoc_register; 1607 } 1608 } 1609 1610 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1611 if (ret) 1612 goto error_asoc_register; 1613 1614 /* 1615 * If codec-handle property is missing from SSI node, we assume 1616 * that the machine driver uses new binding which does not require 1617 * SSI driver to trigger machine driver's probe. 1618 */ 1619 if (!of_get_property(np, "codec-handle", NULL)) 1620 goto done; 1621 1622 /* Trigger the machine driver's probe function. The platform driver 1623 * name of the machine driver is taken from /compatible property of the 1624 * device tree. We also pass the address of the CPU DAI driver 1625 * structure. 1626 */ 1627 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1628 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1629 p = strrchr(sprop, ','); 1630 if (p) 1631 sprop = p + 1; 1632 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1633 make_lowercase(name); 1634 1635 ssi_private->pdev = 1636 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1637 if (IS_ERR(ssi_private->pdev)) { 1638 ret = PTR_ERR(ssi_private->pdev); 1639 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1640 goto error_sound_card; 1641 } 1642 1643 done: 1644 if (ssi_private->dai_fmt) 1645 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, 1646 ssi_private->dai_fmt); 1647 1648 if (fsl_ssi_is_ac97(ssi_private)) { 1649 u32 ssi_idx; 1650 1651 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1652 if (ret) { 1653 dev_err(&pdev->dev, "cannot get SSI index property\n"); 1654 goto error_sound_card; 1655 } 1656 1657 ssi_private->pdev = 1658 platform_device_register_data(NULL, 1659 "ac97-codec", ssi_idx, NULL, 0); 1660 if (IS_ERR(ssi_private->pdev)) { 1661 ret = PTR_ERR(ssi_private->pdev); 1662 dev_err(&pdev->dev, 1663 "failed to register AC97 codec platform: %d\n", 1664 ret); 1665 goto error_sound_card; 1666 } 1667 } 1668 1669 return 0; 1670 1671 error_sound_card: 1672 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1673 1674 error_asoc_register: 1675 if (fsl_ssi_is_ac97(ssi_private)) 1676 snd_soc_set_ac97_ops(NULL); 1677 1678 error_ac97_ops: 1679 if (fsl_ssi_is_ac97(ssi_private)) 1680 mutex_destroy(&ssi_private->ac97_reg_lock); 1681 1682 if (ssi_private->soc->imx) 1683 fsl_ssi_imx_clean(pdev, ssi_private); 1684 1685 return ret; 1686 } 1687 1688 static int fsl_ssi_remove(struct platform_device *pdev) 1689 { 1690 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1691 1692 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1693 1694 if (ssi_private->pdev) 1695 platform_device_unregister(ssi_private->pdev); 1696 1697 if (ssi_private->soc->imx) 1698 fsl_ssi_imx_clean(pdev, ssi_private); 1699 1700 if (fsl_ssi_is_ac97(ssi_private)) { 1701 snd_soc_set_ac97_ops(NULL); 1702 mutex_destroy(&ssi_private->ac97_reg_lock); 1703 } 1704 1705 return 0; 1706 } 1707 1708 #ifdef CONFIG_PM_SLEEP 1709 static int fsl_ssi_suspend(struct device *dev) 1710 { 1711 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1712 struct regmap *regs = ssi_private->regs; 1713 1714 regmap_read(regs, CCSR_SSI_SFCSR, 1715 &ssi_private->regcache_sfcsr); 1716 regmap_read(regs, CCSR_SSI_SACNT, 1717 &ssi_private->regcache_sacnt); 1718 1719 regcache_cache_only(regs, true); 1720 regcache_mark_dirty(regs); 1721 1722 return 0; 1723 } 1724 1725 static int fsl_ssi_resume(struct device *dev) 1726 { 1727 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1728 struct regmap *regs = ssi_private->regs; 1729 1730 regcache_cache_only(regs, false); 1731 1732 regmap_update_bits(regs, CCSR_SSI_SFCSR, 1733 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1734 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1735 ssi_private->regcache_sfcsr); 1736 regmap_write(regs, CCSR_SSI_SACNT, 1737 ssi_private->regcache_sacnt); 1738 1739 return regcache_sync(regs); 1740 } 1741 #endif /* CONFIG_PM_SLEEP */ 1742 1743 static const struct dev_pm_ops fsl_ssi_pm = { 1744 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1745 }; 1746 1747 static struct platform_driver fsl_ssi_driver = { 1748 .driver = { 1749 .name = "fsl-ssi-dai", 1750 .of_match_table = fsl_ssi_ids, 1751 .pm = &fsl_ssi_pm, 1752 }, 1753 .probe = fsl_ssi_probe, 1754 .remove = fsl_ssi_remove, 1755 }; 1756 1757 module_platform_driver(fsl_ssi_driver); 1758 1759 MODULE_ALIAS("platform:fsl-ssi-dai"); 1760 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1761 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1762 MODULE_LICENSE("GPL v2"); 1763