1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/ctype.h> 39 #include <linux/device.h> 40 #include <linux/delay.h> 41 #include <linux/slab.h> 42 #include <linux/spinlock.h> 43 #include <linux/of.h> 44 #include <linux/of_address.h> 45 #include <linux/of_irq.h> 46 #include <linux/of_platform.h> 47 48 #include <sound/core.h> 49 #include <sound/pcm.h> 50 #include <sound/pcm_params.h> 51 #include <sound/initval.h> 52 #include <sound/soc.h> 53 #include <sound/dmaengine_pcm.h> 54 55 #include "fsl_ssi.h" 56 #include "imx-pcm.h" 57 58 /** 59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 60 * 61 * The SSI has a limitation in that the samples must be in the same byte 62 * order as the host CPU. This is because when multiple bytes are written 63 * to the STX register, the bytes and bits must be written in the same 64 * order. The STX is a shift register, so all the bits need to be aligned 65 * (bit-endianness must match byte-endianness). Processors typically write 66 * the bits within a byte in the same order that the bytes of a word are 67 * written in. So if the host CPU is big-endian, then only big-endian 68 * samples will be written to STX properly. 69 */ 70 #ifdef __BIG_ENDIAN 71 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 72 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 73 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 74 #else 75 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 76 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 77 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 78 #endif 79 80 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 81 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 82 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 83 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 84 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 85 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 86 87 enum fsl_ssi_type { 88 FSL_SSI_MCP8610, 89 FSL_SSI_MX21, 90 FSL_SSI_MX35, 91 FSL_SSI_MX51, 92 }; 93 94 struct fsl_ssi_reg_val { 95 u32 sier; 96 u32 srcr; 97 u32 stcr; 98 u32 scr; 99 }; 100 101 struct fsl_ssi_rxtx_reg_val { 102 struct fsl_ssi_reg_val rx; 103 struct fsl_ssi_reg_val tx; 104 }; 105 106 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 107 { 108 switch (reg) { 109 case CCSR_SSI_SACCEN: 110 case CCSR_SSI_SACCDIS: 111 return false; 112 default: 113 return true; 114 } 115 } 116 117 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 118 { 119 switch (reg) { 120 case CCSR_SSI_STX0: 121 case CCSR_SSI_STX1: 122 case CCSR_SSI_SRX0: 123 case CCSR_SSI_SRX1: 124 case CCSR_SSI_SISR: 125 case CCSR_SSI_SFCSR: 126 case CCSR_SSI_SACNT: 127 case CCSR_SSI_SACADD: 128 case CCSR_SSI_SACDAT: 129 case CCSR_SSI_SATAG: 130 case CCSR_SSI_SACCST: 131 case CCSR_SSI_SOR: 132 return true; 133 default: 134 return false; 135 } 136 } 137 138 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 139 { 140 switch (reg) { 141 case CCSR_SSI_SRX0: 142 case CCSR_SSI_SRX1: 143 case CCSR_SSI_SISR: 144 case CCSR_SSI_SACADD: 145 case CCSR_SSI_SACDAT: 146 case CCSR_SSI_SATAG: 147 return true; 148 default: 149 return false; 150 } 151 } 152 153 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 154 { 155 switch (reg) { 156 case CCSR_SSI_SRX0: 157 case CCSR_SSI_SRX1: 158 case CCSR_SSI_SACCST: 159 return false; 160 default: 161 return true; 162 } 163 } 164 165 static const struct regmap_config fsl_ssi_regconfig = { 166 .max_register = CCSR_SSI_SACCDIS, 167 .reg_bits = 32, 168 .val_bits = 32, 169 .reg_stride = 4, 170 .val_format_endian = REGMAP_ENDIAN_NATIVE, 171 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1, 172 .readable_reg = fsl_ssi_readable_reg, 173 .volatile_reg = fsl_ssi_volatile_reg, 174 .precious_reg = fsl_ssi_precious_reg, 175 .writeable_reg = fsl_ssi_writeable_reg, 176 .cache_type = REGCACHE_FLAT, 177 }; 178 179 struct fsl_ssi_soc_data { 180 bool imx; 181 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 182 bool offline_config; 183 u32 sisr_write_mask; 184 }; 185 186 /** 187 * fsl_ssi_private: per-SSI private data 188 * 189 * @reg: Pointer to the regmap registers 190 * @irq: IRQ of this SSI 191 * @cpu_dai_drv: CPU DAI driver for this device 192 * 193 * @dai_fmt: DAI configuration this device is currently used with 194 * @i2s_mode: i2s and network mode configuration of the device. Is used to 195 * switch between normal and i2s/network mode 196 * mode depending on the number of channels 197 * @use_dma: DMA is used or FIQ with stream filter 198 * @use_dual_fifo: DMA with support for both FIFOs used 199 * @fifo_deph: Depth of the SSI FIFOs 200 * @slot_width: width of each DAI slot 201 * @slots: number of slots 202 * @rxtx_reg_val: Specific register settings for receive/transmit configuration 203 * 204 * @clk: SSI clock 205 * @baudclk: SSI baud clock for master mode 206 * @baudclk_streams: Active streams that are using baudclk 207 * 208 * @dma_params_tx: DMA transmit parameters 209 * @dma_params_rx: DMA receive parameters 210 * @ssi_phys: physical address of the SSI registers 211 * 212 * @fiq_params: FIQ stream filtering parameters 213 * 214 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card 215 * 216 * @dbg_stats: Debugging statistics 217 * 218 * @soc: SoC specific data 219 * 220 * @fifo_watermark: the FIFO watermark setting. Notifies DMA when 221 * there are @fifo_watermark or fewer words in TX fifo or 222 * @fifo_watermark or more empty words in RX fifo. 223 * @dma_maxburst: max number of words to transfer in one go. So far, 224 * this is always the same as fifo_watermark. 225 */ 226 struct fsl_ssi_private { 227 struct regmap *regs; 228 int irq; 229 struct snd_soc_dai_driver cpu_dai_drv; 230 231 unsigned int dai_fmt; 232 u8 i2s_mode; 233 bool use_dma; 234 bool use_dual_fifo; 235 bool has_ipg_clk_name; 236 unsigned int fifo_depth; 237 unsigned int slot_width; 238 unsigned int slots; 239 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 240 241 struct clk *clk; 242 struct clk *baudclk; 243 unsigned int baudclk_streams; 244 245 /* regcache for volatile regs */ 246 u32 regcache_sfcsr; 247 u32 regcache_sacnt; 248 249 /* DMA params */ 250 struct snd_dmaengine_dai_dma_data dma_params_tx; 251 struct snd_dmaengine_dai_dma_data dma_params_rx; 252 dma_addr_t ssi_phys; 253 254 /* params for non-dma FIQ stream filtered mode */ 255 struct imx_pcm_fiq_params fiq_params; 256 257 /* Used when using fsl-ssi as sound-card. This is only used by ppc and 258 * should be replaced with simple-sound-card. */ 259 struct platform_device *pdev; 260 261 struct fsl_ssi_dbg dbg_stats; 262 263 const struct fsl_ssi_soc_data *soc; 264 struct device *dev; 265 266 u32 fifo_watermark; 267 u32 dma_maxburst; 268 }; 269 270 /* 271 * imx51 and later SoCs have a slightly different IP that allows the 272 * SSI configuration while the SSI unit is running. 273 * 274 * More important, it is necessary on those SoCs to configure the 275 * sperate TX/RX DMA bits just before starting the stream 276 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 277 * sends any DMA requests to the SDMA unit, otherwise it is not defined 278 * how the SDMA unit handles the DMA request. 279 * 280 * SDMA units are present on devices starting at imx35 but the imx35 281 * reference manual states that the DMA bits should not be changed 282 * while the SSI unit is running (SSIEN). So we support the necessary 283 * online configuration of fsl-ssi starting at imx51. 284 */ 285 286 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 287 .imx = false, 288 .offline_config = true, 289 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 290 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 291 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 292 }; 293 294 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 295 .imx = true, 296 .imx21regs = true, 297 .offline_config = true, 298 .sisr_write_mask = 0, 299 }; 300 301 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 302 .imx = true, 303 .offline_config = true, 304 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 305 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 306 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 307 }; 308 309 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 310 .imx = true, 311 .offline_config = false, 312 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 313 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 314 }; 315 316 static const struct of_device_id fsl_ssi_ids[] = { 317 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 318 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 319 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 320 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 321 {} 322 }; 323 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 324 325 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 326 { 327 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 328 SND_SOC_DAIFMT_AC97; 329 } 330 331 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) 332 { 333 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 334 SND_SOC_DAIFMT_CBS_CFS; 335 } 336 337 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) 338 { 339 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 340 SND_SOC_DAIFMT_CBM_CFS; 341 } 342 /** 343 * fsl_ssi_isr: SSI interrupt handler 344 * 345 * Although it's possible to use the interrupt handler to send and receive 346 * data to/from the SSI, we use the DMA instead. Programming is more 347 * complicated, but the performance is much better. 348 * 349 * This interrupt handler is used only to gather statistics. 350 * 351 * @irq: IRQ of the SSI device 352 * @dev_id: pointer to the ssi_private structure for this SSI device 353 */ 354 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 355 { 356 struct fsl_ssi_private *ssi_private = dev_id; 357 struct regmap *regs = ssi_private->regs; 358 __be32 sisr; 359 __be32 sisr2; 360 361 /* We got an interrupt, so read the status register to see what we 362 were interrupted for. We mask it with the Interrupt Enable register 363 so that we only check for events that we're interested in. 364 */ 365 regmap_read(regs, CCSR_SSI_SISR, &sisr); 366 367 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 368 /* Clear the bits that we set */ 369 if (sisr2) 370 regmap_write(regs, CCSR_SSI_SISR, sisr2); 371 372 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 373 374 return IRQ_HANDLED; 375 } 376 377 /* 378 * Enable/Disable all rx/tx config flags at once. 379 */ 380 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 381 bool enable) 382 { 383 struct regmap *regs = ssi_private->regs; 384 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 385 386 if (enable) { 387 regmap_update_bits(regs, CCSR_SSI_SIER, 388 vals->rx.sier | vals->tx.sier, 389 vals->rx.sier | vals->tx.sier); 390 regmap_update_bits(regs, CCSR_SSI_SRCR, 391 vals->rx.srcr | vals->tx.srcr, 392 vals->rx.srcr | vals->tx.srcr); 393 regmap_update_bits(regs, CCSR_SSI_STCR, 394 vals->rx.stcr | vals->tx.stcr, 395 vals->rx.stcr | vals->tx.stcr); 396 } else { 397 regmap_update_bits(regs, CCSR_SSI_SRCR, 398 vals->rx.srcr | vals->tx.srcr, 0); 399 regmap_update_bits(regs, CCSR_SSI_STCR, 400 vals->rx.stcr | vals->tx.stcr, 0); 401 regmap_update_bits(regs, CCSR_SSI_SIER, 402 vals->rx.sier | vals->tx.sier, 0); 403 } 404 } 405 406 /* 407 * Clear RX or TX FIFO to remove samples from the previous 408 * stream session which may be still present in the FIFO and 409 * may introduce bad samples and/or channel slipping. 410 * 411 * Note: The SOR is not documented in recent IMX datasheet, but 412 * is described in IMX51 reference manual at section 56.3.3.15. 413 */ 414 static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private, 415 bool is_rx) 416 { 417 if (is_rx) { 418 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 419 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR); 420 } else { 421 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 422 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR); 423 } 424 } 425 426 /* 427 * Calculate the bits that have to be disabled for the current stream that is 428 * getting disabled. This keeps the bits enabled that are necessary for the 429 * second stream to work if 'stream_active' is true. 430 * 431 * Detailed calculation: 432 * These are the values that need to be active after disabling. For non-active 433 * second stream, this is 0: 434 * vals_stream * !!stream_active 435 * 436 * The following computes the overall differences between the setup for the 437 * to-disable stream and the active stream, a simple XOR: 438 * vals_disable ^ (vals_stream * !!(stream_active)) 439 * 440 * The full expression adds a mask on all values we care about 441 */ 442 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 443 ((vals_disable) & \ 444 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 445 446 /* 447 * Enable/Disable a ssi configuration. You have to pass either 448 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 449 */ 450 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 451 struct fsl_ssi_reg_val *vals) 452 { 453 struct regmap *regs = ssi_private->regs; 454 struct fsl_ssi_reg_val *avals; 455 int nr_active_streams; 456 u32 scr_val; 457 int keep_active; 458 459 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 460 461 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 462 !!(scr_val & CCSR_SSI_SCR_RE); 463 464 if (nr_active_streams - 1 > 0) 465 keep_active = 1; 466 else 467 keep_active = 0; 468 469 /* Find the other direction values rx or tx which we do not want to 470 * modify */ 471 if (&ssi_private->rxtx_reg_val.rx == vals) 472 avals = &ssi_private->rxtx_reg_val.tx; 473 else 474 avals = &ssi_private->rxtx_reg_val.rx; 475 476 /* If vals should be disabled, start with disabling the unit */ 477 if (!enable) { 478 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 479 keep_active); 480 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 481 } 482 483 /* 484 * We are running on a SoC which does not support online SSI 485 * reconfiguration, so we have to enable all necessary flags at once 486 * even if we do not use them later (capture and playback configuration) 487 */ 488 if (ssi_private->soc->offline_config) { 489 if ((enable && !nr_active_streams) || 490 (!enable && !keep_active)) 491 fsl_ssi_rxtx_config(ssi_private, enable); 492 493 goto config_done; 494 } 495 496 /* 497 * Configure single direction units while the SSI unit is running 498 * (online configuration) 499 */ 500 if (enable) { 501 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE); 502 503 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 504 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 505 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 506 } else { 507 u32 sier; 508 u32 srcr; 509 u32 stcr; 510 511 /* 512 * Disabling the necessary flags for one of rx/tx while the 513 * other stream is active is a little bit more difficult. We 514 * have to disable only those flags that differ between both 515 * streams (rx XOR tx) and that are set in the stream that is 516 * disabled now. Otherwise we could alter flags of the other 517 * stream 518 */ 519 520 /* These assignments are simply vals without bits set in avals*/ 521 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 522 keep_active); 523 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 524 keep_active); 525 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 526 keep_active); 527 528 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 529 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 530 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 531 } 532 533 config_done: 534 /* Enabling of subunits is done after configuration */ 535 if (enable) { 536 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { 537 /* 538 * Be sure the Tx FIFO is filled when TE is set. 539 * Otherwise, there are some chances to start the 540 * playback with some void samples inserted first, 541 * generating a channel slip. 542 * 543 * First, SSIEN must be set, to let the FIFO be filled. 544 * 545 * Notes: 546 * - Limit this fix to the DMA case until FIQ cases can 547 * be tested. 548 * - Limit the length of the busy loop to not lock the 549 * system too long, even if 1-2 loops are sufficient 550 * in general. 551 */ 552 int i; 553 int max_loop = 100; 554 regmap_update_bits(regs, CCSR_SSI_SCR, 555 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); 556 for (i = 0; i < max_loop; i++) { 557 u32 sfcsr; 558 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); 559 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) 560 break; 561 } 562 if (i == max_loop) { 563 dev_err(ssi_private->dev, 564 "Timeout waiting TX FIFO filling\n"); 565 } 566 } 567 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 568 } 569 } 570 571 572 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 573 { 574 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 575 } 576 577 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 578 { 579 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 580 } 581 582 /* 583 * Setup rx/tx register values used to enable/disable the streams. These will 584 * be used later in fsl_ssi_config to setup the streams without the need to 585 * check for all different SSI modes. 586 */ 587 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 588 { 589 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 590 591 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 592 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 593 reg->rx.scr = 0; 594 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 595 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 596 reg->tx.scr = 0; 597 598 if (!fsl_ssi_is_ac97(ssi_private)) { 599 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 600 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 601 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 602 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 603 } 604 605 if (ssi_private->use_dma) { 606 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 607 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 608 } else { 609 reg->rx.sier |= CCSR_SSI_SIER_RIE; 610 reg->tx.sier |= CCSR_SSI_SIER_TIE; 611 } 612 613 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 614 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 615 } 616 617 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 618 { 619 struct regmap *regs = ssi_private->regs; 620 621 /* 622 * Setup the clock control register 623 */ 624 regmap_write(regs, CCSR_SSI_STCCR, 625 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 626 regmap_write(regs, CCSR_SSI_SRCCR, 627 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 628 629 /* 630 * Enable AC97 mode and startup the SSI 631 */ 632 regmap_write(regs, CCSR_SSI_SACNT, 633 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 634 635 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 636 if (!ssi_private->soc->imx21regs) { 637 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 638 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 639 } 640 641 /* 642 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 643 * codec before a stream is started. 644 */ 645 regmap_update_bits(regs, CCSR_SSI_SCR, 646 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 647 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 648 649 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 650 } 651 652 /** 653 * fsl_ssi_startup: create a new substream 654 * 655 * This is the first function called when a stream is opened. 656 * 657 * If this is the first stream open, then grab the IRQ and program most of 658 * the SSI registers. 659 */ 660 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 661 struct snd_soc_dai *dai) 662 { 663 struct snd_soc_pcm_runtime *rtd = substream->private_data; 664 struct fsl_ssi_private *ssi_private = 665 snd_soc_dai_get_drvdata(rtd->cpu_dai); 666 int ret; 667 668 ret = clk_prepare_enable(ssi_private->clk); 669 if (ret) 670 return ret; 671 672 /* When using dual fifo mode, it is safer to ensure an even period 673 * size. If appearing to an odd number while DMA always starts its 674 * task from fifo0, fifo1 would be neglected at the end of each 675 * period. But SSI would still access fifo1 with an invalid data. 676 */ 677 if (ssi_private->use_dual_fifo) 678 snd_pcm_hw_constraint_step(substream->runtime, 0, 679 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 680 681 return 0; 682 } 683 684 /** 685 * fsl_ssi_shutdown: shutdown the SSI 686 * 687 */ 688 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 689 struct snd_soc_dai *dai) 690 { 691 struct snd_soc_pcm_runtime *rtd = substream->private_data; 692 struct fsl_ssi_private *ssi_private = 693 snd_soc_dai_get_drvdata(rtd->cpu_dai); 694 695 clk_disable_unprepare(ssi_private->clk); 696 697 } 698 699 /** 700 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock 701 * 702 * Note: This function can be only called when using SSI as DAI master 703 * 704 * Quick instruction for parameters: 705 * freq: Output BCLK frequency = samplerate * slots * slot_width 706 * (In 2-channel I2S Master mode, slot_width is fixed 32) 707 */ 708 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 709 struct snd_soc_dai *cpu_dai, 710 struct snd_pcm_hw_params *hw_params) 711 { 712 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 713 struct regmap *regs = ssi_private->regs; 714 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 715 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 716 unsigned long clkrate, baudrate, tmprate; 717 unsigned int slots = params_channels(hw_params); 718 unsigned int slot_width = 32; 719 u64 sub, savesub = 100000; 720 unsigned int freq; 721 bool baudclk_is_used; 722 723 /* Override slots and slot_width if being specifically set... */ 724 if (ssi_private->slots) 725 slots = ssi_private->slots; 726 /* ...but keep 32 bits if slots is 2 -- I2S Master mode */ 727 if (ssi_private->slot_width && slots != 2) 728 slot_width = ssi_private->slot_width; 729 730 /* Generate bit clock based on the slot number and slot width */ 731 freq = slots * slot_width * params_rate(hw_params); 732 733 /* Don't apply it to any non-baudclk circumstance */ 734 if (IS_ERR(ssi_private->baudclk)) 735 return -EINVAL; 736 737 /* 738 * Hardware limitation: The bclk rate must be 739 * never greater than 1/5 IPG clock rate 740 */ 741 if (freq * 5 > clk_get_rate(ssi_private->clk)) { 742 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n"); 743 return -EINVAL; 744 } 745 746 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); 747 748 /* It should be already enough to divide clock by setting pm alone */ 749 psr = 0; 750 div2 = 0; 751 752 factor = (div2 + 1) * (7 * psr + 1) * 2; 753 754 for (i = 0; i < 255; i++) { 755 tmprate = freq * factor * (i + 1); 756 757 if (baudclk_is_used) 758 clkrate = clk_get_rate(ssi_private->baudclk); 759 else 760 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 761 762 clkrate /= factor; 763 afreq = clkrate / (i + 1); 764 765 if (freq == afreq) 766 sub = 0; 767 else if (freq / afreq == 1) 768 sub = freq - afreq; 769 else if (afreq / freq == 1) 770 sub = afreq - freq; 771 else 772 continue; 773 774 /* Calculate the fraction */ 775 sub *= 100000; 776 do_div(sub, freq); 777 778 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 779 baudrate = tmprate; 780 savesub = sub; 781 pm = i; 782 } 783 784 /* We are lucky */ 785 if (savesub == 0) 786 break; 787 } 788 789 /* No proper pm found if it is still remaining the initial value */ 790 if (pm == 999) { 791 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 792 return -EINVAL; 793 } 794 795 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 796 (psr ? CCSR_SSI_SxCCR_PSR : 0); 797 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 798 CCSR_SSI_SxCCR_PSR; 799 800 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 801 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 802 else 803 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 804 805 if (!baudclk_is_used) { 806 ret = clk_set_rate(ssi_private->baudclk, baudrate); 807 if (ret) { 808 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 809 return -EINVAL; 810 } 811 } 812 813 return 0; 814 } 815 816 /** 817 * fsl_ssi_hw_params - program the sample size 818 * 819 * Most of the SSI registers have been programmed in the startup function, 820 * but the word length must be programmed here. Unfortunately, programming 821 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 822 * cause a problem with supporting simultaneous playback and capture. If 823 * the SSI is already playing a stream, then that stream may be temporarily 824 * stopped when you start capture. 825 * 826 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 827 * clock master. 828 */ 829 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 830 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 831 { 832 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 833 struct regmap *regs = ssi_private->regs; 834 unsigned int channels = params_channels(hw_params); 835 unsigned int sample_size = params_width(hw_params); 836 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 837 int ret; 838 u32 scr_val; 839 int enabled; 840 841 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 842 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 843 844 /* 845 * If we're in synchronous mode, and the SSI is already enabled, 846 * then STCCR is already set properly. 847 */ 848 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 849 return 0; 850 851 if (fsl_ssi_is_i2s_master(ssi_private)) { 852 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); 853 if (ret) 854 return ret; 855 856 /* Do not enable the clock if it is already enabled */ 857 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { 858 ret = clk_prepare_enable(ssi_private->baudclk); 859 if (ret) 860 return ret; 861 862 ssi_private->baudclk_streams |= BIT(substream->stream); 863 } 864 } 865 866 if (!fsl_ssi_is_ac97(ssi_private)) { 867 u8 i2smode; 868 /* 869 * Switch to normal net mode in order to have a frame sync 870 * signal every 32 bits instead of 16 bits 871 */ 872 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) 873 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 874 CCSR_SSI_SCR_NET; 875 else 876 i2smode = ssi_private->i2s_mode; 877 878 regmap_update_bits(regs, CCSR_SSI_SCR, 879 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 880 channels == 1 ? 0 : i2smode); 881 } 882 883 /* 884 * FIXME: The documentation says that SxCCR[WL] should not be 885 * modified while the SSI is enabled. The only time this can 886 * happen is if we're trying to do simultaneous playback and 887 * capture in asynchronous mode. Unfortunately, I have been enable 888 * to get that to work at all on the P1022DS. Therefore, we don't 889 * bother to disable/enable the SSI when setting SxCCR[WL], because 890 * the SSI will stop anyway. Maybe one day, this will get fixed. 891 */ 892 893 /* In synchronous mode, the SSI uses STCCR for capture */ 894 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 895 ssi_private->cpu_dai_drv.symmetric_rates) 896 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 897 wl); 898 else 899 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 900 wl); 901 902 return 0; 903 } 904 905 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 906 struct snd_soc_dai *cpu_dai) 907 { 908 struct snd_soc_pcm_runtime *rtd = substream->private_data; 909 struct fsl_ssi_private *ssi_private = 910 snd_soc_dai_get_drvdata(rtd->cpu_dai); 911 912 if (fsl_ssi_is_i2s_master(ssi_private) && 913 ssi_private->baudclk_streams & BIT(substream->stream)) { 914 clk_disable_unprepare(ssi_private->baudclk); 915 ssi_private->baudclk_streams &= ~BIT(substream->stream); 916 } 917 918 return 0; 919 } 920 921 static int _fsl_ssi_set_dai_fmt(struct device *dev, 922 struct fsl_ssi_private *ssi_private, 923 unsigned int fmt) 924 { 925 struct regmap *regs = ssi_private->regs; 926 u32 strcr = 0, stcr, srcr, scr, mask; 927 u8 wm; 928 929 ssi_private->dai_fmt = fmt; 930 931 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { 932 dev_err(dev, "baudclk is missing which is necessary for master mode\n"); 933 return -EINVAL; 934 } 935 936 fsl_ssi_setup_reg_vals(ssi_private); 937 938 regmap_read(regs, CCSR_SSI_SCR, &scr); 939 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 940 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 941 942 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 943 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 944 CCSR_SSI_STCR_TEFS; 945 regmap_read(regs, CCSR_SSI_STCR, &stcr); 946 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 947 stcr &= ~mask; 948 srcr &= ~mask; 949 950 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 951 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 952 case SND_SOC_DAIFMT_I2S: 953 regmap_update_bits(regs, CCSR_SSI_STCCR, 954 CCSR_SSI_SxCCR_DC_MASK, 955 CCSR_SSI_SxCCR_DC(2)); 956 regmap_update_bits(regs, CCSR_SSI_SRCCR, 957 CCSR_SSI_SxCCR_DC_MASK, 958 CCSR_SSI_SxCCR_DC(2)); 959 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 960 case SND_SOC_DAIFMT_CBM_CFS: 961 case SND_SOC_DAIFMT_CBS_CFS: 962 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 963 break; 964 case SND_SOC_DAIFMT_CBM_CFM: 965 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 966 break; 967 default: 968 return -EINVAL; 969 } 970 971 /* Data on rising edge of bclk, frame low, 1clk before data */ 972 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 973 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 974 break; 975 case SND_SOC_DAIFMT_LEFT_J: 976 /* Data on rising edge of bclk, frame high */ 977 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 978 break; 979 case SND_SOC_DAIFMT_DSP_A: 980 /* Data on rising edge of bclk, frame high, 1clk before data */ 981 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 982 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 983 break; 984 case SND_SOC_DAIFMT_DSP_B: 985 /* Data on rising edge of bclk, frame high */ 986 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 987 CCSR_SSI_STCR_TXBIT0; 988 break; 989 case SND_SOC_DAIFMT_AC97: 990 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 991 break; 992 default: 993 return -EINVAL; 994 } 995 scr |= ssi_private->i2s_mode; 996 997 /* DAI clock inversion */ 998 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 999 case SND_SOC_DAIFMT_NB_NF: 1000 /* Nothing to do for both normal cases */ 1001 break; 1002 case SND_SOC_DAIFMT_IB_NF: 1003 /* Invert bit clock */ 1004 strcr ^= CCSR_SSI_STCR_TSCKP; 1005 break; 1006 case SND_SOC_DAIFMT_NB_IF: 1007 /* Invert frame clock */ 1008 strcr ^= CCSR_SSI_STCR_TFSI; 1009 break; 1010 case SND_SOC_DAIFMT_IB_IF: 1011 /* Invert both clocks */ 1012 strcr ^= CCSR_SSI_STCR_TSCKP; 1013 strcr ^= CCSR_SSI_STCR_TFSI; 1014 break; 1015 default: 1016 return -EINVAL; 1017 } 1018 1019 /* DAI clock master masks */ 1020 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1021 case SND_SOC_DAIFMT_CBS_CFS: 1022 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 1023 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 1024 break; 1025 case SND_SOC_DAIFMT_CBM_CFM: 1026 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1027 break; 1028 case SND_SOC_DAIFMT_CBM_CFS: 1029 strcr &= ~CCSR_SSI_STCR_TXDIR; 1030 strcr |= CCSR_SSI_STCR_TFDIR; 1031 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1032 break; 1033 default: 1034 if (!fsl_ssi_is_ac97(ssi_private)) 1035 return -EINVAL; 1036 } 1037 1038 stcr |= strcr; 1039 srcr |= strcr; 1040 1041 if (ssi_private->cpu_dai_drv.symmetric_rates 1042 || fsl_ssi_is_ac97(ssi_private)) { 1043 /* Need to clear RXDIR when using SYNC or AC97 mode */ 1044 srcr &= ~CCSR_SSI_SRCR_RXDIR; 1045 scr |= CCSR_SSI_SCR_SYN; 1046 } 1047 1048 regmap_write(regs, CCSR_SSI_STCR, stcr); 1049 regmap_write(regs, CCSR_SSI_SRCR, srcr); 1050 regmap_write(regs, CCSR_SSI_SCR, scr); 1051 1052 wm = ssi_private->fifo_watermark; 1053 1054 regmap_write(regs, CCSR_SSI_SFCSR, 1055 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 1056 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 1057 1058 if (ssi_private->use_dual_fifo) { 1059 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 1060 CCSR_SSI_SRCR_RFEN1); 1061 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 1062 CCSR_SSI_STCR_TFEN1); 1063 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 1064 CCSR_SSI_SCR_TCH_EN); 1065 } 1066 1067 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1068 fsl_ssi_setup_ac97(ssi_private); 1069 1070 return 0; 1071 1072 } 1073 1074 /** 1075 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 1076 */ 1077 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 1078 { 1079 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1080 1081 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); 1082 } 1083 1084 /** 1085 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 1086 * 1087 * Note: This function can be only called when using SSI as DAI master 1088 */ 1089 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 1090 u32 rx_mask, int slots, int slot_width) 1091 { 1092 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1093 struct regmap *regs = ssi_private->regs; 1094 u32 val; 1095 1096 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ 1097 if (slot_width & 1 || slot_width < 8 || slot_width > 24) { 1098 dev_err(cpu_dai->dev, "invalid slot width: %d\n", slot_width); 1099 return -EINVAL; 1100 } 1101 1102 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1103 regmap_read(regs, CCSR_SSI_SCR, &val); 1104 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 1105 if (val && slots < 2) { 1106 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1107 return -EINVAL; 1108 } 1109 1110 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 1111 CCSR_SSI_SxCCR_DC(slots)); 1112 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 1113 CCSR_SSI_SxCCR_DC(slots)); 1114 1115 /* The register SxMSKs needs SSI to provide essential clock due to 1116 * hardware design. So we here temporarily enable SSI to set them. 1117 */ 1118 regmap_read(regs, CCSR_SSI_SCR, &val); 1119 val &= CCSR_SSI_SCR_SSIEN; 1120 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 1121 CCSR_SSI_SCR_SSIEN); 1122 1123 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1124 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1125 1126 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1127 1128 ssi_private->slot_width = slot_width; 1129 ssi_private->slots = slots; 1130 1131 return 0; 1132 } 1133 1134 /** 1135 * fsl_ssi_trigger: start and stop the DMA transfer. 1136 * 1137 * This function is called by ALSA to start, stop, pause, and resume the DMA 1138 * transfer of data. 1139 * 1140 * The DMA channel is in external master start and pause mode, which 1141 * means the SSI completely controls the flow of data. 1142 */ 1143 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1144 struct snd_soc_dai *dai) 1145 { 1146 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1147 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1148 struct regmap *regs = ssi_private->regs; 1149 1150 switch (cmd) { 1151 case SNDRV_PCM_TRIGGER_START: 1152 case SNDRV_PCM_TRIGGER_RESUME: 1153 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1154 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1155 fsl_ssi_tx_config(ssi_private, true); 1156 else 1157 fsl_ssi_rx_config(ssi_private, true); 1158 break; 1159 1160 case SNDRV_PCM_TRIGGER_STOP: 1161 case SNDRV_PCM_TRIGGER_SUSPEND: 1162 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1163 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1164 fsl_ssi_tx_config(ssi_private, false); 1165 else 1166 fsl_ssi_rx_config(ssi_private, false); 1167 break; 1168 1169 default: 1170 return -EINVAL; 1171 } 1172 1173 if (fsl_ssi_is_ac97(ssi_private)) { 1174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1175 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1176 else 1177 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1184 { 1185 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 1186 1187 if (ssi_private->soc->imx && ssi_private->use_dma) { 1188 dai->playback_dma_data = &ssi_private->dma_params_tx; 1189 dai->capture_dma_data = &ssi_private->dma_params_rx; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1196 .startup = fsl_ssi_startup, 1197 .shutdown = fsl_ssi_shutdown, 1198 .hw_params = fsl_ssi_hw_params, 1199 .hw_free = fsl_ssi_hw_free, 1200 .set_fmt = fsl_ssi_set_dai_fmt, 1201 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1202 .trigger = fsl_ssi_trigger, 1203 }; 1204 1205 /* Template for the CPU dai driver structure */ 1206 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1207 .probe = fsl_ssi_dai_probe, 1208 .playback = { 1209 .stream_name = "CPU-Playback", 1210 .channels_min = 1, 1211 .channels_max = 32, 1212 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1213 .formats = FSLSSI_I2S_FORMATS, 1214 }, 1215 .capture = { 1216 .stream_name = "CPU-Capture", 1217 .channels_min = 1, 1218 .channels_max = 32, 1219 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1220 .formats = FSLSSI_I2S_FORMATS, 1221 }, 1222 .ops = &fsl_ssi_dai_ops, 1223 }; 1224 1225 static const struct snd_soc_component_driver fsl_ssi_component = { 1226 .name = "fsl-ssi", 1227 }; 1228 1229 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1230 .bus_control = true, 1231 .probe = fsl_ssi_dai_probe, 1232 .playback = { 1233 .stream_name = "AC97 Playback", 1234 .channels_min = 2, 1235 .channels_max = 2, 1236 .rates = SNDRV_PCM_RATE_8000_48000, 1237 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1238 }, 1239 .capture = { 1240 .stream_name = "AC97 Capture", 1241 .channels_min = 2, 1242 .channels_max = 2, 1243 .rates = SNDRV_PCM_RATE_48000, 1244 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1245 }, 1246 .ops = &fsl_ssi_dai_ops, 1247 }; 1248 1249 1250 static struct fsl_ssi_private *fsl_ac97_data; 1251 1252 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1253 unsigned short val) 1254 { 1255 struct regmap *regs = fsl_ac97_data->regs; 1256 unsigned int lreg; 1257 unsigned int lval; 1258 int ret; 1259 1260 if (reg > 0x7f) 1261 return; 1262 1263 ret = clk_prepare_enable(fsl_ac97_data->clk); 1264 if (ret) { 1265 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1266 ret); 1267 return; 1268 } 1269 1270 lreg = reg << 12; 1271 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1272 1273 lval = val << 4; 1274 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1275 1276 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1277 CCSR_SSI_SACNT_WR); 1278 udelay(100); 1279 1280 clk_disable_unprepare(fsl_ac97_data->clk); 1281 } 1282 1283 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1284 unsigned short reg) 1285 { 1286 struct regmap *regs = fsl_ac97_data->regs; 1287 1288 unsigned short val = -1; 1289 u32 reg_val; 1290 unsigned int lreg; 1291 int ret; 1292 1293 ret = clk_prepare_enable(fsl_ac97_data->clk); 1294 if (ret) { 1295 pr_err("ac97 read clk_prepare_enable failed: %d\n", 1296 ret); 1297 return -1; 1298 } 1299 1300 lreg = (reg & 0x7f) << 12; 1301 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1302 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1303 CCSR_SSI_SACNT_RD); 1304 1305 udelay(100); 1306 1307 regmap_read(regs, CCSR_SSI_SACDAT, ®_val); 1308 val = (reg_val >> 4) & 0xffff; 1309 1310 clk_disable_unprepare(fsl_ac97_data->clk); 1311 1312 return val; 1313 } 1314 1315 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1316 .read = fsl_ssi_ac97_read, 1317 .write = fsl_ssi_ac97_write, 1318 }; 1319 1320 /** 1321 * Make every character in a string lower-case 1322 */ 1323 static void make_lowercase(char *s) 1324 { 1325 if (!s) 1326 return; 1327 for (; *s; s++) 1328 *s = tolower(*s); 1329 } 1330 1331 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1332 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1333 { 1334 struct device_node *np = pdev->dev.of_node; 1335 u32 dmas[4]; 1336 int ret; 1337 1338 if (ssi_private->has_ipg_clk_name) 1339 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); 1340 else 1341 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1342 if (IS_ERR(ssi_private->clk)) { 1343 ret = PTR_ERR(ssi_private->clk); 1344 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1345 return ret; 1346 } 1347 1348 if (!ssi_private->has_ipg_clk_name) { 1349 ret = clk_prepare_enable(ssi_private->clk); 1350 if (ret) { 1351 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1352 return ret; 1353 } 1354 } 1355 1356 /* For those SLAVE implementations, we ignore non-baudclk cases 1357 * and, instead, abandon MASTER mode that needs baud clock. 1358 */ 1359 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1360 if (IS_ERR(ssi_private->baudclk)) 1361 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1362 PTR_ERR(ssi_private->baudclk)); 1363 1364 ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst; 1365 ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst; 1366 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; 1367 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; 1368 1369 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1370 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1371 ssi_private->use_dual_fifo = true; 1372 /* When using dual fifo mode, we need to keep watermark 1373 * as even numbers due to dma script limitation. 1374 */ 1375 ssi_private->dma_params_tx.maxburst &= ~0x1; 1376 ssi_private->dma_params_rx.maxburst &= ~0x1; 1377 } 1378 1379 if (!ssi_private->use_dma) { 1380 1381 /* 1382 * Some boards use an incompatible codec. To get it 1383 * working, we are using imx-fiq-pcm-audio, that 1384 * can handle those codecs. DMA is not possible in this 1385 * situation. 1386 */ 1387 1388 ssi_private->fiq_params.irq = ssi_private->irq; 1389 ssi_private->fiq_params.base = iomem; 1390 ssi_private->fiq_params.dma_params_rx = 1391 &ssi_private->dma_params_rx; 1392 ssi_private->fiq_params.dma_params_tx = 1393 &ssi_private->dma_params_tx; 1394 1395 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1396 if (ret) 1397 goto error_pcm; 1398 } else { 1399 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1400 if (ret) 1401 goto error_pcm; 1402 } 1403 1404 return 0; 1405 1406 error_pcm: 1407 1408 if (!ssi_private->has_ipg_clk_name) 1409 clk_disable_unprepare(ssi_private->clk); 1410 return ret; 1411 } 1412 1413 static void fsl_ssi_imx_clean(struct platform_device *pdev, 1414 struct fsl_ssi_private *ssi_private) 1415 { 1416 if (!ssi_private->use_dma) 1417 imx_pcm_fiq_exit(pdev); 1418 if (!ssi_private->has_ipg_clk_name) 1419 clk_disable_unprepare(ssi_private->clk); 1420 } 1421 1422 static int fsl_ssi_probe(struct platform_device *pdev) 1423 { 1424 struct fsl_ssi_private *ssi_private; 1425 int ret = 0; 1426 struct device_node *np = pdev->dev.of_node; 1427 const struct of_device_id *of_id; 1428 const char *p, *sprop; 1429 const uint32_t *iprop; 1430 struct resource *res; 1431 void __iomem *iomem; 1432 char name[64]; 1433 struct regmap_config regconfig = fsl_ssi_regconfig; 1434 1435 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1436 if (!of_id || !of_id->data) 1437 return -EINVAL; 1438 1439 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1440 GFP_KERNEL); 1441 if (!ssi_private) 1442 return -ENOMEM; 1443 1444 ssi_private->soc = of_id->data; 1445 ssi_private->dev = &pdev->dev; 1446 1447 sprop = of_get_property(np, "fsl,mode", NULL); 1448 if (sprop) { 1449 if (!strcmp(sprop, "ac97-slave")) 1450 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; 1451 } 1452 1453 ssi_private->use_dma = !of_property_read_bool(np, 1454 "fsl,fiq-stream-filter"); 1455 1456 if (fsl_ssi_is_ac97(ssi_private)) { 1457 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1458 sizeof(fsl_ssi_ac97_dai)); 1459 1460 fsl_ac97_data = ssi_private; 1461 1462 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1463 if (ret) { 1464 dev_err(&pdev->dev, "could not set AC'97 ops\n"); 1465 return ret; 1466 } 1467 } else { 1468 /* Initialize this copy of the CPU DAI driver structure */ 1469 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1470 sizeof(fsl_ssi_dai_template)); 1471 } 1472 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1473 1474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1475 iomem = devm_ioremap_resource(&pdev->dev, res); 1476 if (IS_ERR(iomem)) 1477 return PTR_ERR(iomem); 1478 ssi_private->ssi_phys = res->start; 1479 1480 if (ssi_private->soc->imx21regs) { 1481 /* 1482 * According to datasheet imx21-class SSI 1483 * don't have SACC{ST,EN,DIS} regs. 1484 */ 1485 regconfig.max_register = CCSR_SSI_SRMSK; 1486 regconfig.num_reg_defaults_raw = 1487 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1; 1488 } 1489 1490 ret = of_property_match_string(np, "clock-names", "ipg"); 1491 if (ret < 0) { 1492 ssi_private->has_ipg_clk_name = false; 1493 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1494 ®config); 1495 } else { 1496 ssi_private->has_ipg_clk_name = true; 1497 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1498 "ipg", iomem, ®config); 1499 } 1500 if (IS_ERR(ssi_private->regs)) { 1501 dev_err(&pdev->dev, "Failed to init register map\n"); 1502 return PTR_ERR(ssi_private->regs); 1503 } 1504 1505 ssi_private->irq = platform_get_irq(pdev, 0); 1506 if (ssi_private->irq < 0) { 1507 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1508 return ssi_private->irq; 1509 } 1510 1511 /* Are the RX and the TX clocks locked? */ 1512 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1513 if (!fsl_ssi_is_ac97(ssi_private)) 1514 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1515 1516 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1517 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1518 } 1519 1520 /* Determine the FIFO depth. */ 1521 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1522 if (iprop) 1523 ssi_private->fifo_depth = be32_to_cpup(iprop); 1524 else 1525 /* Older 8610 DTs didn't have the fifo-depth property */ 1526 ssi_private->fifo_depth = 8; 1527 1528 /* 1529 * Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't 1530 * use FIFO 1 but set the watermark appropriately nontheless. 1531 * We program the transmit water to signal a DMA transfer 1532 * if there are N elements left in the FIFO. For chips with 15-deep 1533 * FIFOs, set watermark to 8. This allows the SSI to operate at a 1534 * high data rate without channel slipping. Behavior is unchanged 1535 * for the older chips with a fifo depth of only 8. A value of 4 1536 * might be appropriate for the older chips, but is left at 1537 * fifo_depth-2 until sombody has a chance to test. 1538 * 1539 * We set the watermark on the same level as the DMA burstsize. For 1540 * fiq it is probably better to use the biggest possible watermark 1541 * size. 1542 */ 1543 switch (ssi_private->fifo_depth) { 1544 case 15: 1545 /* 1546 * 2 samples is not enough when running at high data 1547 * rates (like 48kHz @ 16 bits/channel, 16 channels) 1548 * 8 seems to split things evenly and leave enough time 1549 * for the DMA to fill the FIFO before it's over/under 1550 * run. 1551 */ 1552 ssi_private->fifo_watermark = 8; 1553 ssi_private->dma_maxburst = 8; 1554 break; 1555 case 8: 1556 default: 1557 /* 1558 * maintain old behavior for older chips. 1559 * Keeping it the same because I don't have an older 1560 * board to test with. 1561 * I suspect this could be changed to be something to 1562 * leave some more space in the fifo. 1563 */ 1564 ssi_private->fifo_watermark = ssi_private->fifo_depth - 2; 1565 ssi_private->dma_maxburst = ssi_private->fifo_depth - 2; 1566 break; 1567 } 1568 1569 dev_set_drvdata(&pdev->dev, ssi_private); 1570 1571 if (ssi_private->soc->imx) { 1572 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); 1573 if (ret) 1574 return ret; 1575 } 1576 1577 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1578 &ssi_private->cpu_dai_drv, 1); 1579 if (ret) { 1580 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1581 goto error_asoc_register; 1582 } 1583 1584 if (ssi_private->use_dma) { 1585 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1586 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1587 ssi_private); 1588 if (ret < 0) { 1589 dev_err(&pdev->dev, "could not claim irq %u\n", 1590 ssi_private->irq); 1591 goto error_asoc_register; 1592 } 1593 } 1594 1595 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1596 if (ret) 1597 goto error_asoc_register; 1598 1599 /* 1600 * If codec-handle property is missing from SSI node, we assume 1601 * that the machine driver uses new binding which does not require 1602 * SSI driver to trigger machine driver's probe. 1603 */ 1604 if (!of_get_property(np, "codec-handle", NULL)) 1605 goto done; 1606 1607 /* Trigger the machine driver's probe function. The platform driver 1608 * name of the machine driver is taken from /compatible property of the 1609 * device tree. We also pass the address of the CPU DAI driver 1610 * structure. 1611 */ 1612 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1613 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1614 p = strrchr(sprop, ','); 1615 if (p) 1616 sprop = p + 1; 1617 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1618 make_lowercase(name); 1619 1620 ssi_private->pdev = 1621 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1622 if (IS_ERR(ssi_private->pdev)) { 1623 ret = PTR_ERR(ssi_private->pdev); 1624 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1625 goto error_sound_card; 1626 } 1627 1628 done: 1629 if (ssi_private->dai_fmt) 1630 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, 1631 ssi_private->dai_fmt); 1632 1633 if (fsl_ssi_is_ac97(ssi_private)) { 1634 u32 ssi_idx; 1635 1636 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1637 if (ret) { 1638 dev_err(&pdev->dev, "cannot get SSI index property\n"); 1639 goto error_sound_card; 1640 } 1641 1642 ssi_private->pdev = 1643 platform_device_register_data(NULL, 1644 "ac97-codec", ssi_idx, NULL, 0); 1645 if (IS_ERR(ssi_private->pdev)) { 1646 ret = PTR_ERR(ssi_private->pdev); 1647 dev_err(&pdev->dev, 1648 "failed to register AC97 codec platform: %d\n", 1649 ret); 1650 goto error_sound_card; 1651 } 1652 } 1653 1654 return 0; 1655 1656 error_sound_card: 1657 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1658 1659 error_asoc_register: 1660 if (ssi_private->soc->imx) 1661 fsl_ssi_imx_clean(pdev, ssi_private); 1662 1663 return ret; 1664 } 1665 1666 static int fsl_ssi_remove(struct platform_device *pdev) 1667 { 1668 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1669 1670 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1671 1672 if (ssi_private->pdev) 1673 platform_device_unregister(ssi_private->pdev); 1674 1675 if (ssi_private->soc->imx) 1676 fsl_ssi_imx_clean(pdev, ssi_private); 1677 1678 if (fsl_ssi_is_ac97(ssi_private)) 1679 snd_soc_set_ac97_ops(NULL); 1680 1681 return 0; 1682 } 1683 1684 #ifdef CONFIG_PM_SLEEP 1685 static int fsl_ssi_suspend(struct device *dev) 1686 { 1687 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1688 struct regmap *regs = ssi_private->regs; 1689 1690 regmap_read(regs, CCSR_SSI_SFCSR, 1691 &ssi_private->regcache_sfcsr); 1692 regmap_read(regs, CCSR_SSI_SACNT, 1693 &ssi_private->regcache_sacnt); 1694 1695 regcache_cache_only(regs, true); 1696 regcache_mark_dirty(regs); 1697 1698 return 0; 1699 } 1700 1701 static int fsl_ssi_resume(struct device *dev) 1702 { 1703 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1704 struct regmap *regs = ssi_private->regs; 1705 1706 regcache_cache_only(regs, false); 1707 1708 regmap_update_bits(regs, CCSR_SSI_SFCSR, 1709 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1710 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1711 ssi_private->regcache_sfcsr); 1712 regmap_write(regs, CCSR_SSI_SACNT, 1713 ssi_private->regcache_sacnt); 1714 1715 return regcache_sync(regs); 1716 } 1717 #endif /* CONFIG_PM_SLEEP */ 1718 1719 static const struct dev_pm_ops fsl_ssi_pm = { 1720 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1721 }; 1722 1723 static struct platform_driver fsl_ssi_driver = { 1724 .driver = { 1725 .name = "fsl-ssi-dai", 1726 .of_match_table = fsl_ssi_ids, 1727 .pm = &fsl_ssi_pm, 1728 }, 1729 .probe = fsl_ssi_probe, 1730 .remove = fsl_ssi_remove, 1731 }; 1732 1733 module_platform_driver(fsl_ssi_driver); 1734 1735 MODULE_ALIAS("platform:fsl-ssi-dai"); 1736 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1737 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1738 MODULE_LICENSE("GPL v2"); 1739