1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/device.h> 39 #include <linux/delay.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/of.h> 43 #include <linux/of_address.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_platform.h> 46 47 #include <sound/core.h> 48 #include <sound/pcm.h> 49 #include <sound/pcm_params.h> 50 #include <sound/initval.h> 51 #include <sound/soc.h> 52 #include <sound/dmaengine_pcm.h> 53 54 #include "fsl_ssi.h" 55 #include "imx-pcm.h" 56 57 /** 58 * FSLSSI_I2S_RATES: sample rates supported by the I2S 59 * 60 * This driver currently only supports the SSI running in I2S slave mode, 61 * which means the codec determines the sample rate. Therefore, we tell 62 * ALSA that we support all rates and let the codec driver decide what rates 63 * are really supported. 64 */ 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS 66 67 /** 68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 69 * 70 * The SSI has a limitation in that the samples must be in the same byte 71 * order as the host CPU. This is because when multiple bytes are written 72 * to the STX register, the bytes and bits must be written in the same 73 * order. The STX is a shift register, so all the bits need to be aligned 74 * (bit-endianness must match byte-endianness). Processors typically write 75 * the bits within a byte in the same order that the bytes of a word are 76 * written in. So if the host CPU is big-endian, then only big-endian 77 * samples will be written to STX properly. 78 */ 79 #ifdef __BIG_ENDIAN 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 83 #else 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 87 #endif 88 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 95 96 enum fsl_ssi_type { 97 FSL_SSI_MCP8610, 98 FSL_SSI_MX21, 99 FSL_SSI_MX35, 100 FSL_SSI_MX51, 101 }; 102 103 struct fsl_ssi_reg_val { 104 u32 sier; 105 u32 srcr; 106 u32 stcr; 107 u32 scr; 108 }; 109 110 struct fsl_ssi_rxtx_reg_val { 111 struct fsl_ssi_reg_val rx; 112 struct fsl_ssi_reg_val tx; 113 }; 114 static const struct regmap_config fsl_ssi_regconfig = { 115 .max_register = CCSR_SSI_SACCDIS, 116 .reg_bits = 32, 117 .val_bits = 32, 118 .reg_stride = 4, 119 .val_format_endian = REGMAP_ENDIAN_NATIVE, 120 }; 121 122 struct fsl_ssi_soc_data { 123 bool imx; 124 bool offline_config; 125 u32 sisr_write_mask; 126 }; 127 128 /** 129 * fsl_ssi_private: per-SSI private data 130 * 131 * @reg: Pointer to the regmap registers 132 * @irq: IRQ of this SSI 133 * @cpu_dai_drv: CPU DAI driver for this device 134 * 135 * @dai_fmt: DAI configuration this device is currently used with 136 * @i2s_mode: i2s and network mode configuration of the device. Is used to 137 * switch between normal and i2s/network mode 138 * mode depending on the number of channels 139 * @use_dma: DMA is used or FIQ with stream filter 140 * @use_dual_fifo: DMA with support for both FIFOs used 141 * @fifo_deph: Depth of the SSI FIFOs 142 * @rxtx_reg_val: Specific register settings for receive/transmit configuration 143 * 144 * @clk: SSI clock 145 * @baudclk: SSI baud clock for master mode 146 * @baudclk_streams: Active streams that are using baudclk 147 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk 148 * 149 * @dma_params_tx: DMA transmit parameters 150 * @dma_params_rx: DMA receive parameters 151 * @ssi_phys: physical address of the SSI registers 152 * 153 * @fiq_params: FIQ stream filtering parameters 154 * 155 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card 156 * 157 * @dbg_stats: Debugging statistics 158 * 159 * @soc: SoC specific data 160 */ 161 struct fsl_ssi_private { 162 struct regmap *regs; 163 int irq; 164 struct snd_soc_dai_driver cpu_dai_drv; 165 166 unsigned int dai_fmt; 167 u8 i2s_mode; 168 bool use_dma; 169 bool use_dual_fifo; 170 bool has_ipg_clk_name; 171 unsigned int fifo_depth; 172 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 173 174 struct clk *clk; 175 struct clk *baudclk; 176 unsigned int baudclk_streams; 177 unsigned int bitclk_freq; 178 179 /* DMA params */ 180 struct snd_dmaengine_dai_dma_data dma_params_tx; 181 struct snd_dmaengine_dai_dma_data dma_params_rx; 182 dma_addr_t ssi_phys; 183 184 /* params for non-dma FIQ stream filtered mode */ 185 struct imx_pcm_fiq_params fiq_params; 186 187 /* Used when using fsl-ssi as sound-card. This is only used by ppc and 188 * should be replaced with simple-sound-card. */ 189 struct platform_device *pdev; 190 191 struct fsl_ssi_dbg dbg_stats; 192 193 const struct fsl_ssi_soc_data *soc; 194 }; 195 196 /* 197 * imx51 and later SoCs have a slightly different IP that allows the 198 * SSI configuration while the SSI unit is running. 199 * 200 * More important, it is necessary on those SoCs to configure the 201 * sperate TX/RX DMA bits just before starting the stream 202 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 203 * sends any DMA requests to the SDMA unit, otherwise it is not defined 204 * how the SDMA unit handles the DMA request. 205 * 206 * SDMA units are present on devices starting at imx35 but the imx35 207 * reference manual states that the DMA bits should not be changed 208 * while the SSI unit is running (SSIEN). So we support the necessary 209 * online configuration of fsl-ssi starting at imx51. 210 */ 211 212 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 213 .imx = false, 214 .offline_config = true, 215 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 216 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 217 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 218 }; 219 220 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 221 .imx = true, 222 .offline_config = true, 223 .sisr_write_mask = 0, 224 }; 225 226 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 227 .imx = true, 228 .offline_config = true, 229 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 230 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 231 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 232 }; 233 234 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 235 .imx = true, 236 .offline_config = false, 237 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 238 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 239 }; 240 241 static const struct of_device_id fsl_ssi_ids[] = { 242 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 243 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 244 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 245 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 246 {} 247 }; 248 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 249 250 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 251 { 252 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 253 SND_SOC_DAIFMT_AC97; 254 } 255 256 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) 257 { 258 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 259 SND_SOC_DAIFMT_CBS_CFS; 260 } 261 262 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) 263 { 264 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 265 SND_SOC_DAIFMT_CBM_CFS; 266 } 267 /** 268 * fsl_ssi_isr: SSI interrupt handler 269 * 270 * Although it's possible to use the interrupt handler to send and receive 271 * data to/from the SSI, we use the DMA instead. Programming is more 272 * complicated, but the performance is much better. 273 * 274 * This interrupt handler is used only to gather statistics. 275 * 276 * @irq: IRQ of the SSI device 277 * @dev_id: pointer to the ssi_private structure for this SSI device 278 */ 279 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 280 { 281 struct fsl_ssi_private *ssi_private = dev_id; 282 struct regmap *regs = ssi_private->regs; 283 __be32 sisr; 284 __be32 sisr2; 285 286 /* We got an interrupt, so read the status register to see what we 287 were interrupted for. We mask it with the Interrupt Enable register 288 so that we only check for events that we're interested in. 289 */ 290 regmap_read(regs, CCSR_SSI_SISR, &sisr); 291 292 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 293 /* Clear the bits that we set */ 294 if (sisr2) 295 regmap_write(regs, CCSR_SSI_SISR, sisr2); 296 297 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 298 299 return IRQ_HANDLED; 300 } 301 302 /* 303 * Enable/Disable all rx/tx config flags at once. 304 */ 305 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 306 bool enable) 307 { 308 struct regmap *regs = ssi_private->regs; 309 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 310 311 if (enable) { 312 regmap_update_bits(regs, CCSR_SSI_SIER, 313 vals->rx.sier | vals->tx.sier, 314 vals->rx.sier | vals->tx.sier); 315 regmap_update_bits(regs, CCSR_SSI_SRCR, 316 vals->rx.srcr | vals->tx.srcr, 317 vals->rx.srcr | vals->tx.srcr); 318 regmap_update_bits(regs, CCSR_SSI_STCR, 319 vals->rx.stcr | vals->tx.stcr, 320 vals->rx.stcr | vals->tx.stcr); 321 } else { 322 regmap_update_bits(regs, CCSR_SSI_SRCR, 323 vals->rx.srcr | vals->tx.srcr, 0); 324 regmap_update_bits(regs, CCSR_SSI_STCR, 325 vals->rx.stcr | vals->tx.stcr, 0); 326 regmap_update_bits(regs, CCSR_SSI_SIER, 327 vals->rx.sier | vals->tx.sier, 0); 328 } 329 } 330 331 /* 332 * Calculate the bits that have to be disabled for the current stream that is 333 * getting disabled. This keeps the bits enabled that are necessary for the 334 * second stream to work if 'stream_active' is true. 335 * 336 * Detailed calculation: 337 * These are the values that need to be active after disabling. For non-active 338 * second stream, this is 0: 339 * vals_stream * !!stream_active 340 * 341 * The following computes the overall differences between the setup for the 342 * to-disable stream and the active stream, a simple XOR: 343 * vals_disable ^ (vals_stream * !!(stream_active)) 344 * 345 * The full expression adds a mask on all values we care about 346 */ 347 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 348 ((vals_disable) & \ 349 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 350 351 /* 352 * Enable/Disable a ssi configuration. You have to pass either 353 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 354 */ 355 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 356 struct fsl_ssi_reg_val *vals) 357 { 358 struct regmap *regs = ssi_private->regs; 359 struct fsl_ssi_reg_val *avals; 360 int nr_active_streams; 361 u32 scr_val; 362 int keep_active; 363 364 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 365 366 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 367 !!(scr_val & CCSR_SSI_SCR_RE); 368 369 if (nr_active_streams - 1 > 0) 370 keep_active = 1; 371 else 372 keep_active = 0; 373 374 /* Find the other direction values rx or tx which we do not want to 375 * modify */ 376 if (&ssi_private->rxtx_reg_val.rx == vals) 377 avals = &ssi_private->rxtx_reg_val.tx; 378 else 379 avals = &ssi_private->rxtx_reg_val.rx; 380 381 /* If vals should be disabled, start with disabling the unit */ 382 if (!enable) { 383 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 384 keep_active); 385 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 386 } 387 388 /* 389 * We are running on a SoC which does not support online SSI 390 * reconfiguration, so we have to enable all necessary flags at once 391 * even if we do not use them later (capture and playback configuration) 392 */ 393 if (ssi_private->soc->offline_config) { 394 if ((enable && !nr_active_streams) || 395 (!enable && !keep_active)) 396 fsl_ssi_rxtx_config(ssi_private, enable); 397 398 goto config_done; 399 } 400 401 /* 402 * Configure single direction units while the SSI unit is running 403 * (online configuration) 404 */ 405 if (enable) { 406 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 407 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 408 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 409 } else { 410 u32 sier; 411 u32 srcr; 412 u32 stcr; 413 414 /* 415 * Disabling the necessary flags for one of rx/tx while the 416 * other stream is active is a little bit more difficult. We 417 * have to disable only those flags that differ between both 418 * streams (rx XOR tx) and that are set in the stream that is 419 * disabled now. Otherwise we could alter flags of the other 420 * stream 421 */ 422 423 /* These assignments are simply vals without bits set in avals*/ 424 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 425 keep_active); 426 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 427 keep_active); 428 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 429 keep_active); 430 431 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 432 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 433 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 434 } 435 436 config_done: 437 /* Enabling of subunits is done after configuration */ 438 if (enable) 439 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 440 } 441 442 443 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 444 { 445 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 446 } 447 448 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 449 { 450 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 451 } 452 453 /* 454 * Setup rx/tx register values used to enable/disable the streams. These will 455 * be used later in fsl_ssi_config to setup the streams without the need to 456 * check for all different SSI modes. 457 */ 458 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 459 { 460 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 461 462 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 463 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 464 reg->rx.scr = 0; 465 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 466 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 467 reg->tx.scr = 0; 468 469 if (!fsl_ssi_is_ac97(ssi_private)) { 470 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 471 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 472 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 473 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 474 } 475 476 if (ssi_private->use_dma) { 477 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 478 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 479 } else { 480 reg->rx.sier |= CCSR_SSI_SIER_RIE; 481 reg->tx.sier |= CCSR_SSI_SIER_TIE; 482 } 483 484 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 485 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 486 } 487 488 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 489 { 490 struct regmap *regs = ssi_private->regs; 491 492 /* 493 * Setup the clock control register 494 */ 495 regmap_write(regs, CCSR_SSI_STCCR, 496 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 497 regmap_write(regs, CCSR_SSI_SRCCR, 498 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 499 500 /* 501 * Enable AC97 mode and startup the SSI 502 */ 503 regmap_write(regs, CCSR_SSI_SACNT, 504 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 505 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 506 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 507 508 /* 509 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 510 * codec before a stream is started. 511 */ 512 regmap_update_bits(regs, CCSR_SSI_SCR, 513 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 514 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 515 516 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 517 } 518 519 /** 520 * fsl_ssi_startup: create a new substream 521 * 522 * This is the first function called when a stream is opened. 523 * 524 * If this is the first stream open, then grab the IRQ and program most of 525 * the SSI registers. 526 */ 527 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 528 struct snd_soc_dai *dai) 529 { 530 struct snd_soc_pcm_runtime *rtd = substream->private_data; 531 struct fsl_ssi_private *ssi_private = 532 snd_soc_dai_get_drvdata(rtd->cpu_dai); 533 int ret; 534 535 ret = clk_prepare_enable(ssi_private->clk); 536 if (ret) 537 return ret; 538 539 /* When using dual fifo mode, it is safer to ensure an even period 540 * size. If appearing to an odd number while DMA always starts its 541 * task from fifo0, fifo1 would be neglected at the end of each 542 * period. But SSI would still access fifo1 with an invalid data. 543 */ 544 if (ssi_private->use_dual_fifo) 545 snd_pcm_hw_constraint_step(substream->runtime, 0, 546 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 547 548 return 0; 549 } 550 551 /** 552 * fsl_ssi_shutdown: shutdown the SSI 553 * 554 */ 555 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 556 struct snd_soc_dai *dai) 557 { 558 struct snd_soc_pcm_runtime *rtd = substream->private_data; 559 struct fsl_ssi_private *ssi_private = 560 snd_soc_dai_get_drvdata(rtd->cpu_dai); 561 562 clk_disable_unprepare(ssi_private->clk); 563 564 } 565 566 /** 567 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock 568 * 569 * Note: This function can be only called when using SSI as DAI master 570 * 571 * Quick instruction for parameters: 572 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels 573 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. 574 */ 575 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 576 struct snd_soc_dai *cpu_dai, 577 struct snd_pcm_hw_params *hw_params) 578 { 579 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 580 struct regmap *regs = ssi_private->regs; 581 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 582 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 583 unsigned long clkrate, baudrate, tmprate; 584 u64 sub, savesub = 100000; 585 unsigned int freq; 586 bool baudclk_is_used; 587 588 /* Prefer the explicitly set bitclock frequency */ 589 if (ssi_private->bitclk_freq) 590 freq = ssi_private->bitclk_freq; 591 else 592 freq = params_channels(hw_params) * 32 * params_rate(hw_params); 593 594 /* Don't apply it to any non-baudclk circumstance */ 595 if (IS_ERR(ssi_private->baudclk)) 596 return -EINVAL; 597 598 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); 599 600 /* It should be already enough to divide clock by setting pm alone */ 601 psr = 0; 602 div2 = 0; 603 604 factor = (div2 + 1) * (7 * psr + 1) * 2; 605 606 for (i = 0; i < 255; i++) { 607 tmprate = freq * factor * (i + 1); 608 609 if (baudclk_is_used) 610 clkrate = clk_get_rate(ssi_private->baudclk); 611 else 612 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 613 614 /* 615 * Hardware limitation: The bclk rate must be 616 * never greater than 1/5 IPG clock rate 617 */ 618 if (clkrate * 5 > clk_get_rate(ssi_private->clk)) 619 continue; 620 621 clkrate /= factor; 622 afreq = clkrate / (i + 1); 623 624 if (freq == afreq) 625 sub = 0; 626 else if (freq / afreq == 1) 627 sub = freq - afreq; 628 else if (afreq / freq == 1) 629 sub = afreq - freq; 630 else 631 continue; 632 633 /* Calculate the fraction */ 634 sub *= 100000; 635 do_div(sub, freq); 636 637 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 638 baudrate = tmprate; 639 savesub = sub; 640 pm = i; 641 } 642 643 /* We are lucky */ 644 if (savesub == 0) 645 break; 646 } 647 648 /* No proper pm found if it is still remaining the initial value */ 649 if (pm == 999) { 650 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 651 return -EINVAL; 652 } 653 654 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 655 (psr ? CCSR_SSI_SxCCR_PSR : 0); 656 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 657 CCSR_SSI_SxCCR_PSR; 658 659 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 660 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 661 else 662 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 663 664 if (!baudclk_is_used) { 665 ret = clk_set_rate(ssi_private->baudclk, baudrate); 666 if (ret) { 667 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 668 return -EINVAL; 669 } 670 } 671 672 return 0; 673 } 674 675 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 676 int clk_id, unsigned int freq, int dir) 677 { 678 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 679 680 ssi_private->bitclk_freq = freq; 681 682 return 0; 683 } 684 685 /** 686 * fsl_ssi_hw_params - program the sample size 687 * 688 * Most of the SSI registers have been programmed in the startup function, 689 * but the word length must be programmed here. Unfortunately, programming 690 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 691 * cause a problem with supporting simultaneous playback and capture. If 692 * the SSI is already playing a stream, then that stream may be temporarily 693 * stopped when you start capture. 694 * 695 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 696 * clock master. 697 */ 698 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 699 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 700 { 701 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 702 struct regmap *regs = ssi_private->regs; 703 unsigned int channels = params_channels(hw_params); 704 unsigned int sample_size = 705 snd_pcm_format_width(params_format(hw_params)); 706 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 707 int ret; 708 u32 scr_val; 709 int enabled; 710 711 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 712 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 713 714 /* 715 * If we're in synchronous mode, and the SSI is already enabled, 716 * then STCCR is already set properly. 717 */ 718 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 719 return 0; 720 721 if (fsl_ssi_is_i2s_master(ssi_private)) { 722 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); 723 if (ret) 724 return ret; 725 726 /* Do not enable the clock if it is already enabled */ 727 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { 728 ret = clk_prepare_enable(ssi_private->baudclk); 729 if (ret) 730 return ret; 731 732 ssi_private->baudclk_streams |= BIT(substream->stream); 733 } 734 } 735 736 if (!fsl_ssi_is_ac97(ssi_private)) { 737 u8 i2smode; 738 /* 739 * Switch to normal net mode in order to have a frame sync 740 * signal every 32 bits instead of 16 bits 741 */ 742 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) 743 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 744 CCSR_SSI_SCR_NET; 745 else 746 i2smode = ssi_private->i2s_mode; 747 748 regmap_update_bits(regs, CCSR_SSI_SCR, 749 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 750 channels == 1 ? 0 : i2smode); 751 } 752 753 /* 754 * FIXME: The documentation says that SxCCR[WL] should not be 755 * modified while the SSI is enabled. The only time this can 756 * happen is if we're trying to do simultaneous playback and 757 * capture in asynchronous mode. Unfortunately, I have been enable 758 * to get that to work at all on the P1022DS. Therefore, we don't 759 * bother to disable/enable the SSI when setting SxCCR[WL], because 760 * the SSI will stop anyway. Maybe one day, this will get fixed. 761 */ 762 763 /* In synchronous mode, the SSI uses STCCR for capture */ 764 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 765 ssi_private->cpu_dai_drv.symmetric_rates) 766 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 767 wl); 768 else 769 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 770 wl); 771 772 return 0; 773 } 774 775 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 776 struct snd_soc_dai *cpu_dai) 777 { 778 struct snd_soc_pcm_runtime *rtd = substream->private_data; 779 struct fsl_ssi_private *ssi_private = 780 snd_soc_dai_get_drvdata(rtd->cpu_dai); 781 782 if (fsl_ssi_is_i2s_master(ssi_private) && 783 ssi_private->baudclk_streams & BIT(substream->stream)) { 784 clk_disable_unprepare(ssi_private->baudclk); 785 ssi_private->baudclk_streams &= ~BIT(substream->stream); 786 } 787 788 return 0; 789 } 790 791 static int _fsl_ssi_set_dai_fmt(struct device *dev, 792 struct fsl_ssi_private *ssi_private, 793 unsigned int fmt) 794 { 795 struct regmap *regs = ssi_private->regs; 796 u32 strcr = 0, stcr, srcr, scr, mask; 797 u8 wm; 798 799 ssi_private->dai_fmt = fmt; 800 801 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { 802 dev_err(dev, "baudclk is missing which is necessary for master mode\n"); 803 return -EINVAL; 804 } 805 806 fsl_ssi_setup_reg_vals(ssi_private); 807 808 regmap_read(regs, CCSR_SSI_SCR, &scr); 809 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 810 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 811 812 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 813 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 814 CCSR_SSI_STCR_TEFS; 815 regmap_read(regs, CCSR_SSI_STCR, &stcr); 816 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 817 stcr &= ~mask; 818 srcr &= ~mask; 819 820 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 821 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 822 case SND_SOC_DAIFMT_I2S: 823 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 824 case SND_SOC_DAIFMT_CBM_CFS: 825 case SND_SOC_DAIFMT_CBS_CFS: 826 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 827 regmap_update_bits(regs, CCSR_SSI_STCCR, 828 CCSR_SSI_SxCCR_DC_MASK, 829 CCSR_SSI_SxCCR_DC(2)); 830 regmap_update_bits(regs, CCSR_SSI_SRCCR, 831 CCSR_SSI_SxCCR_DC_MASK, 832 CCSR_SSI_SxCCR_DC(2)); 833 break; 834 case SND_SOC_DAIFMT_CBM_CFM: 835 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 836 break; 837 default: 838 return -EINVAL; 839 } 840 841 /* Data on rising edge of bclk, frame low, 1clk before data */ 842 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 843 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 844 break; 845 case SND_SOC_DAIFMT_LEFT_J: 846 /* Data on rising edge of bclk, frame high */ 847 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 848 break; 849 case SND_SOC_DAIFMT_DSP_A: 850 /* Data on rising edge of bclk, frame high, 1clk before data */ 851 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 852 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 853 break; 854 case SND_SOC_DAIFMT_DSP_B: 855 /* Data on rising edge of bclk, frame high */ 856 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 857 CCSR_SSI_STCR_TXBIT0; 858 break; 859 case SND_SOC_DAIFMT_AC97: 860 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 861 break; 862 default: 863 return -EINVAL; 864 } 865 scr |= ssi_private->i2s_mode; 866 867 /* DAI clock inversion */ 868 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 869 case SND_SOC_DAIFMT_NB_NF: 870 /* Nothing to do for both normal cases */ 871 break; 872 case SND_SOC_DAIFMT_IB_NF: 873 /* Invert bit clock */ 874 strcr ^= CCSR_SSI_STCR_TSCKP; 875 break; 876 case SND_SOC_DAIFMT_NB_IF: 877 /* Invert frame clock */ 878 strcr ^= CCSR_SSI_STCR_TFSI; 879 break; 880 case SND_SOC_DAIFMT_IB_IF: 881 /* Invert both clocks */ 882 strcr ^= CCSR_SSI_STCR_TSCKP; 883 strcr ^= CCSR_SSI_STCR_TFSI; 884 break; 885 default: 886 return -EINVAL; 887 } 888 889 /* DAI clock master masks */ 890 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 891 case SND_SOC_DAIFMT_CBS_CFS: 892 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 893 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 894 break; 895 case SND_SOC_DAIFMT_CBM_CFM: 896 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 897 break; 898 case SND_SOC_DAIFMT_CBM_CFS: 899 strcr &= ~CCSR_SSI_STCR_TXDIR; 900 strcr |= CCSR_SSI_STCR_TFDIR; 901 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 902 break; 903 default: 904 if (!fsl_ssi_is_ac97(ssi_private)) 905 return -EINVAL; 906 } 907 908 stcr |= strcr; 909 srcr |= strcr; 910 911 if (ssi_private->cpu_dai_drv.symmetric_rates 912 || fsl_ssi_is_ac97(ssi_private)) { 913 /* Need to clear RXDIR when using SYNC or AC97 mode */ 914 srcr &= ~CCSR_SSI_SRCR_RXDIR; 915 scr |= CCSR_SSI_SCR_SYN; 916 } 917 918 regmap_write(regs, CCSR_SSI_STCR, stcr); 919 regmap_write(regs, CCSR_SSI_SRCR, srcr); 920 regmap_write(regs, CCSR_SSI_SCR, scr); 921 922 /* 923 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't 924 * use FIFO 1. We program the transmit water to signal a DMA transfer 925 * if there are only two (or fewer) elements left in the FIFO. Two 926 * elements equals one frame (left channel, right channel). This value, 927 * however, depends on the depth of the transmit buffer. 928 * 929 * We set the watermark on the same level as the DMA burstsize. For 930 * fiq it is probably better to use the biggest possible watermark 931 * size. 932 */ 933 if (ssi_private->use_dma) 934 wm = ssi_private->fifo_depth - 2; 935 else 936 wm = ssi_private->fifo_depth; 937 938 regmap_write(regs, CCSR_SSI_SFCSR, 939 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 940 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 941 942 if (ssi_private->use_dual_fifo) { 943 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 944 CCSR_SSI_SRCR_RFEN1); 945 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 946 CCSR_SSI_STCR_TFEN1); 947 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 948 CCSR_SSI_SCR_TCH_EN); 949 } 950 951 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 952 fsl_ssi_setup_ac97(ssi_private); 953 954 return 0; 955 956 } 957 958 /** 959 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 960 */ 961 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 962 { 963 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 964 965 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); 966 } 967 968 /** 969 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 970 * 971 * Note: This function can be only called when using SSI as DAI master 972 */ 973 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 974 u32 rx_mask, int slots, int slot_width) 975 { 976 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 977 struct regmap *regs = ssi_private->regs; 978 u32 val; 979 980 /* The slot number should be >= 2 if using Network mode or I2S mode */ 981 regmap_read(regs, CCSR_SSI_SCR, &val); 982 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 983 if (val && slots < 2) { 984 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 985 return -EINVAL; 986 } 987 988 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 989 CCSR_SSI_SxCCR_DC(slots)); 990 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 991 CCSR_SSI_SxCCR_DC(slots)); 992 993 /* The register SxMSKs needs SSI to provide essential clock due to 994 * hardware design. So we here temporarily enable SSI to set them. 995 */ 996 regmap_read(regs, CCSR_SSI_SCR, &val); 997 val &= CCSR_SSI_SCR_SSIEN; 998 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 999 CCSR_SSI_SCR_SSIEN); 1000 1001 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1002 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1003 1004 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1005 1006 return 0; 1007 } 1008 1009 /** 1010 * fsl_ssi_trigger: start and stop the DMA transfer. 1011 * 1012 * This function is called by ALSA to start, stop, pause, and resume the DMA 1013 * transfer of data. 1014 * 1015 * The DMA channel is in external master start and pause mode, which 1016 * means the SSI completely controls the flow of data. 1017 */ 1018 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1019 struct snd_soc_dai *dai) 1020 { 1021 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1022 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1023 struct regmap *regs = ssi_private->regs; 1024 1025 switch (cmd) { 1026 case SNDRV_PCM_TRIGGER_START: 1027 case SNDRV_PCM_TRIGGER_RESUME: 1028 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1029 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1030 fsl_ssi_tx_config(ssi_private, true); 1031 else 1032 fsl_ssi_rx_config(ssi_private, true); 1033 break; 1034 1035 case SNDRV_PCM_TRIGGER_STOP: 1036 case SNDRV_PCM_TRIGGER_SUSPEND: 1037 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1038 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1039 fsl_ssi_tx_config(ssi_private, false); 1040 else 1041 fsl_ssi_rx_config(ssi_private, false); 1042 break; 1043 1044 default: 1045 return -EINVAL; 1046 } 1047 1048 if (fsl_ssi_is_ac97(ssi_private)) { 1049 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1050 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1051 else 1052 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1059 { 1060 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 1061 1062 if (ssi_private->soc->imx && ssi_private->use_dma) { 1063 dai->playback_dma_data = &ssi_private->dma_params_tx; 1064 dai->capture_dma_data = &ssi_private->dma_params_rx; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1071 .startup = fsl_ssi_startup, 1072 .shutdown = fsl_ssi_shutdown, 1073 .hw_params = fsl_ssi_hw_params, 1074 .hw_free = fsl_ssi_hw_free, 1075 .set_fmt = fsl_ssi_set_dai_fmt, 1076 .set_sysclk = fsl_ssi_set_dai_sysclk, 1077 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1078 .trigger = fsl_ssi_trigger, 1079 }; 1080 1081 /* Template for the CPU dai driver structure */ 1082 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1083 .probe = fsl_ssi_dai_probe, 1084 .playback = { 1085 .stream_name = "CPU-Playback", 1086 .channels_min = 1, 1087 .channels_max = 2, 1088 .rates = FSLSSI_I2S_RATES, 1089 .formats = FSLSSI_I2S_FORMATS, 1090 }, 1091 .capture = { 1092 .stream_name = "CPU-Capture", 1093 .channels_min = 1, 1094 .channels_max = 2, 1095 .rates = FSLSSI_I2S_RATES, 1096 .formats = FSLSSI_I2S_FORMATS, 1097 }, 1098 .ops = &fsl_ssi_dai_ops, 1099 }; 1100 1101 static const struct snd_soc_component_driver fsl_ssi_component = { 1102 .name = "fsl-ssi", 1103 }; 1104 1105 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1106 .bus_control = true, 1107 .probe = fsl_ssi_dai_probe, 1108 .playback = { 1109 .stream_name = "AC97 Playback", 1110 .channels_min = 2, 1111 .channels_max = 2, 1112 .rates = SNDRV_PCM_RATE_8000_48000, 1113 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1114 }, 1115 .capture = { 1116 .stream_name = "AC97 Capture", 1117 .channels_min = 2, 1118 .channels_max = 2, 1119 .rates = SNDRV_PCM_RATE_48000, 1120 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1121 }, 1122 .ops = &fsl_ssi_dai_ops, 1123 }; 1124 1125 1126 static struct fsl_ssi_private *fsl_ac97_data; 1127 1128 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1129 unsigned short val) 1130 { 1131 struct regmap *regs = fsl_ac97_data->regs; 1132 unsigned int lreg; 1133 unsigned int lval; 1134 int ret; 1135 1136 if (reg > 0x7f) 1137 return; 1138 1139 ret = clk_prepare_enable(fsl_ac97_data->clk); 1140 if (ret) { 1141 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1142 ret); 1143 return; 1144 } 1145 1146 lreg = reg << 12; 1147 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1148 1149 lval = val << 4; 1150 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1151 1152 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1153 CCSR_SSI_SACNT_WR); 1154 udelay(100); 1155 1156 clk_disable_unprepare(fsl_ac97_data->clk); 1157 } 1158 1159 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1160 unsigned short reg) 1161 { 1162 struct regmap *regs = fsl_ac97_data->regs; 1163 1164 unsigned short val = -1; 1165 u32 reg_val; 1166 unsigned int lreg; 1167 int ret; 1168 1169 ret = clk_prepare_enable(fsl_ac97_data->clk); 1170 if (ret) { 1171 pr_err("ac97 read clk_prepare_enable failed: %d\n", 1172 ret); 1173 return -1; 1174 } 1175 1176 lreg = (reg & 0x7f) << 12; 1177 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1178 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1179 CCSR_SSI_SACNT_RD); 1180 1181 udelay(100); 1182 1183 regmap_read(regs, CCSR_SSI_SACDAT, ®_val); 1184 val = (reg_val >> 4) & 0xffff; 1185 1186 clk_disable_unprepare(fsl_ac97_data->clk); 1187 1188 return val; 1189 } 1190 1191 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1192 .read = fsl_ssi_ac97_read, 1193 .write = fsl_ssi_ac97_write, 1194 }; 1195 1196 /** 1197 * Make every character in a string lower-case 1198 */ 1199 static void make_lowercase(char *s) 1200 { 1201 char *p = s; 1202 char c; 1203 1204 while ((c = *p)) { 1205 if ((c >= 'A') && (c <= 'Z')) 1206 *p = c + ('a' - 'A'); 1207 p++; 1208 } 1209 } 1210 1211 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1212 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1213 { 1214 struct device_node *np = pdev->dev.of_node; 1215 u32 dmas[4]; 1216 int ret; 1217 1218 if (ssi_private->has_ipg_clk_name) 1219 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); 1220 else 1221 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1222 if (IS_ERR(ssi_private->clk)) { 1223 ret = PTR_ERR(ssi_private->clk); 1224 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1225 return ret; 1226 } 1227 1228 if (!ssi_private->has_ipg_clk_name) { 1229 ret = clk_prepare_enable(ssi_private->clk); 1230 if (ret) { 1231 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1232 return ret; 1233 } 1234 } 1235 1236 /* For those SLAVE implementations, we ignore non-baudclk cases 1237 * and, instead, abandon MASTER mode that needs baud clock. 1238 */ 1239 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1240 if (IS_ERR(ssi_private->baudclk)) 1241 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1242 PTR_ERR(ssi_private->baudclk)); 1243 1244 /* 1245 * We have burstsize be "fifo_depth - 2" to match the SSI 1246 * watermark setting in fsl_ssi_startup(). 1247 */ 1248 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; 1249 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; 1250 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; 1251 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; 1252 1253 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1254 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1255 ssi_private->use_dual_fifo = true; 1256 /* When using dual fifo mode, we need to keep watermark 1257 * as even numbers due to dma script limitation. 1258 */ 1259 ssi_private->dma_params_tx.maxburst &= ~0x1; 1260 ssi_private->dma_params_rx.maxburst &= ~0x1; 1261 } 1262 1263 if (!ssi_private->use_dma) { 1264 1265 /* 1266 * Some boards use an incompatible codec. To get it 1267 * working, we are using imx-fiq-pcm-audio, that 1268 * can handle those codecs. DMA is not possible in this 1269 * situation. 1270 */ 1271 1272 ssi_private->fiq_params.irq = ssi_private->irq; 1273 ssi_private->fiq_params.base = iomem; 1274 ssi_private->fiq_params.dma_params_rx = 1275 &ssi_private->dma_params_rx; 1276 ssi_private->fiq_params.dma_params_tx = 1277 &ssi_private->dma_params_tx; 1278 1279 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1280 if (ret) 1281 goto error_pcm; 1282 } else { 1283 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1284 if (ret) 1285 goto error_pcm; 1286 } 1287 1288 return 0; 1289 1290 error_pcm: 1291 1292 if (!ssi_private->has_ipg_clk_name) 1293 clk_disable_unprepare(ssi_private->clk); 1294 return ret; 1295 } 1296 1297 static void fsl_ssi_imx_clean(struct platform_device *pdev, 1298 struct fsl_ssi_private *ssi_private) 1299 { 1300 if (!ssi_private->use_dma) 1301 imx_pcm_fiq_exit(pdev); 1302 if (!ssi_private->has_ipg_clk_name) 1303 clk_disable_unprepare(ssi_private->clk); 1304 } 1305 1306 static int fsl_ssi_probe(struct platform_device *pdev) 1307 { 1308 struct fsl_ssi_private *ssi_private; 1309 int ret = 0; 1310 struct device_node *np = pdev->dev.of_node; 1311 const struct of_device_id *of_id; 1312 const char *p, *sprop; 1313 const uint32_t *iprop; 1314 struct resource *res; 1315 void __iomem *iomem; 1316 char name[64]; 1317 1318 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1319 if (!of_id || !of_id->data) 1320 return -EINVAL; 1321 1322 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1323 GFP_KERNEL); 1324 if (!ssi_private) { 1325 dev_err(&pdev->dev, "could not allocate DAI object\n"); 1326 return -ENOMEM; 1327 } 1328 1329 ssi_private->soc = of_id->data; 1330 1331 sprop = of_get_property(np, "fsl,mode", NULL); 1332 if (sprop) { 1333 if (!strcmp(sprop, "ac97-slave")) 1334 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; 1335 } 1336 1337 ssi_private->use_dma = !of_property_read_bool(np, 1338 "fsl,fiq-stream-filter"); 1339 1340 if (fsl_ssi_is_ac97(ssi_private)) { 1341 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1342 sizeof(fsl_ssi_ac97_dai)); 1343 1344 fsl_ac97_data = ssi_private; 1345 1346 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1347 if (ret) { 1348 dev_err(&pdev->dev, "could not set AC'97 ops\n"); 1349 return ret; 1350 } 1351 } else { 1352 /* Initialize this copy of the CPU DAI driver structure */ 1353 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1354 sizeof(fsl_ssi_dai_template)); 1355 } 1356 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1357 1358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1359 iomem = devm_ioremap_resource(&pdev->dev, res); 1360 if (IS_ERR(iomem)) 1361 return PTR_ERR(iomem); 1362 ssi_private->ssi_phys = res->start; 1363 1364 ret = of_property_match_string(np, "clock-names", "ipg"); 1365 if (ret < 0) { 1366 ssi_private->has_ipg_clk_name = false; 1367 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1368 &fsl_ssi_regconfig); 1369 } else { 1370 ssi_private->has_ipg_clk_name = true; 1371 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1372 "ipg", iomem, &fsl_ssi_regconfig); 1373 } 1374 if (IS_ERR(ssi_private->regs)) { 1375 dev_err(&pdev->dev, "Failed to init register map\n"); 1376 return PTR_ERR(ssi_private->regs); 1377 } 1378 1379 ssi_private->irq = platform_get_irq(pdev, 0); 1380 if (ssi_private->irq < 0) { 1381 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1382 return ssi_private->irq; 1383 } 1384 1385 /* Are the RX and the TX clocks locked? */ 1386 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1387 if (!fsl_ssi_is_ac97(ssi_private)) 1388 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1389 1390 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1391 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1392 } 1393 1394 /* Determine the FIFO depth. */ 1395 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1396 if (iprop) 1397 ssi_private->fifo_depth = be32_to_cpup(iprop); 1398 else 1399 /* Older 8610 DTs didn't have the fifo-depth property */ 1400 ssi_private->fifo_depth = 8; 1401 1402 dev_set_drvdata(&pdev->dev, ssi_private); 1403 1404 if (ssi_private->soc->imx) { 1405 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); 1406 if (ret) 1407 return ret; 1408 } 1409 1410 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1411 &ssi_private->cpu_dai_drv, 1); 1412 if (ret) { 1413 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1414 goto error_asoc_register; 1415 } 1416 1417 if (ssi_private->use_dma) { 1418 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1419 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1420 ssi_private); 1421 if (ret < 0) { 1422 dev_err(&pdev->dev, "could not claim irq %u\n", 1423 ssi_private->irq); 1424 goto error_asoc_register; 1425 } 1426 } 1427 1428 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1429 if (ret) 1430 goto error_asoc_register; 1431 1432 /* 1433 * If codec-handle property is missing from SSI node, we assume 1434 * that the machine driver uses new binding which does not require 1435 * SSI driver to trigger machine driver's probe. 1436 */ 1437 if (!of_get_property(np, "codec-handle", NULL)) 1438 goto done; 1439 1440 /* Trigger the machine driver's probe function. The platform driver 1441 * name of the machine driver is taken from /compatible property of the 1442 * device tree. We also pass the address of the CPU DAI driver 1443 * structure. 1444 */ 1445 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1446 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1447 p = strrchr(sprop, ','); 1448 if (p) 1449 sprop = p + 1; 1450 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1451 make_lowercase(name); 1452 1453 ssi_private->pdev = 1454 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1455 if (IS_ERR(ssi_private->pdev)) { 1456 ret = PTR_ERR(ssi_private->pdev); 1457 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1458 goto error_sound_card; 1459 } 1460 1461 done: 1462 if (ssi_private->dai_fmt) 1463 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, 1464 ssi_private->dai_fmt); 1465 1466 if (fsl_ssi_is_ac97(ssi_private)) { 1467 u32 ssi_idx; 1468 1469 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1470 if (ret) { 1471 dev_err(&pdev->dev, "cannot get SSI index property\n"); 1472 goto error_sound_card; 1473 } 1474 1475 ssi_private->pdev = 1476 platform_device_register_data(NULL, 1477 "ac97-codec", ssi_idx, NULL, 0); 1478 if (IS_ERR(ssi_private->pdev)) { 1479 ret = PTR_ERR(ssi_private->pdev); 1480 dev_err(&pdev->dev, 1481 "failed to register AC97 codec platform: %d\n", 1482 ret); 1483 goto error_sound_card; 1484 } 1485 } 1486 1487 return 0; 1488 1489 error_sound_card: 1490 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1491 1492 error_asoc_register: 1493 if (ssi_private->soc->imx) 1494 fsl_ssi_imx_clean(pdev, ssi_private); 1495 1496 return ret; 1497 } 1498 1499 static int fsl_ssi_remove(struct platform_device *pdev) 1500 { 1501 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1502 1503 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1504 1505 if (ssi_private->pdev) 1506 platform_device_unregister(ssi_private->pdev); 1507 1508 if (ssi_private->soc->imx) 1509 fsl_ssi_imx_clean(pdev, ssi_private); 1510 1511 if (fsl_ssi_is_ac97(ssi_private)) 1512 snd_soc_set_ac97_ops(NULL); 1513 1514 return 0; 1515 } 1516 1517 static struct platform_driver fsl_ssi_driver = { 1518 .driver = { 1519 .name = "fsl-ssi-dai", 1520 .of_match_table = fsl_ssi_ids, 1521 }, 1522 .probe = fsl_ssi_probe, 1523 .remove = fsl_ssi_remove, 1524 }; 1525 1526 module_platform_driver(fsl_ssi_driver); 1527 1528 MODULE_ALIAS("platform:fsl-ssi-dai"); 1529 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1530 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1531 MODULE_LICENSE("GPL v2"); 1532