1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed 7 * under the terms of the GNU General Public License version 2. This 8 * program is licensed "as is" without any warranty of any kind, whether 9 * express or implied. 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/device.h> 16 #include <linux/delay.h> 17 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/initval.h> 22 #include <sound/soc.h> 23 24 #include <asm/immap_86xx.h> 25 26 #include "fsl_ssi.h" 27 28 /** 29 * FSLSSI_I2S_RATES: sample rates supported by the I2S 30 * 31 * This driver currently only supports the SSI running in I2S slave mode, 32 * which means the codec determines the sample rate. Therefore, we tell 33 * ALSA that we support all rates and let the codec driver decide what rates 34 * are really supported. 35 */ 36 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \ 37 SNDRV_PCM_RATE_CONTINUOUS) 38 39 /** 40 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 41 * 42 * This driver currently only supports the SSI running in I2S slave mode. 43 * 44 * The SSI has a limitation in that the samples must be in the same byte 45 * order as the host CPU. This is because when multiple bytes are written 46 * to the STX register, the bytes and bits must be written in the same 47 * order. The STX is a shift register, so all the bits need to be aligned 48 * (bit-endianness must match byte-endianness). Processors typically write 49 * the bits within a byte in the same order that the bytes of a word are 50 * written in. So if the host CPU is big-endian, then only big-endian 51 * samples will be written to STX properly. 52 */ 53 #ifdef __BIG_ENDIAN 54 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 55 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 56 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 57 #else 58 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 59 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 60 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 61 #endif 62 63 /* SIER bitflag of interrupts to enable */ 64 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \ 65 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \ 66 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \ 67 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \ 68 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN) 69 70 /** 71 * fsl_ssi_private: per-SSI private data 72 * 73 * @name: short name for this device ("SSI0", "SSI1", etc) 74 * @ssi: pointer to the SSI's registers 75 * @ssi_phys: physical address of the SSI registers 76 * @irq: IRQ of this SSI 77 * @first_stream: pointer to the stream that was opened first 78 * @second_stream: pointer to second stream 79 * @dev: struct device pointer 80 * @playback: the number of playback streams opened 81 * @capture: the number of capture streams opened 82 * @asynchronous: 0=synchronous mode, 1=asynchronous mode 83 * @cpu_dai: the CPU DAI for this device 84 * @dev_attr: the sysfs device attribute structure 85 * @stats: SSI statistics 86 */ 87 struct fsl_ssi_private { 88 char name[8]; 89 struct ccsr_ssi __iomem *ssi; 90 dma_addr_t ssi_phys; 91 unsigned int irq; 92 struct snd_pcm_substream *first_stream; 93 struct snd_pcm_substream *second_stream; 94 struct device *dev; 95 unsigned int playback; 96 unsigned int capture; 97 int asynchronous; 98 struct snd_soc_dai cpu_dai; 99 struct device_attribute dev_attr; 100 101 struct { 102 unsigned int rfrc; 103 unsigned int tfrc; 104 unsigned int cmdau; 105 unsigned int cmddu; 106 unsigned int rxt; 107 unsigned int rdr1; 108 unsigned int rdr0; 109 unsigned int tde1; 110 unsigned int tde0; 111 unsigned int roe1; 112 unsigned int roe0; 113 unsigned int tue1; 114 unsigned int tue0; 115 unsigned int tfs; 116 unsigned int rfs; 117 unsigned int tls; 118 unsigned int rls; 119 unsigned int rff1; 120 unsigned int rff0; 121 unsigned int tfe1; 122 unsigned int tfe0; 123 } stats; 124 }; 125 126 /** 127 * fsl_ssi_isr: SSI interrupt handler 128 * 129 * Although it's possible to use the interrupt handler to send and receive 130 * data to/from the SSI, we use the DMA instead. Programming is more 131 * complicated, but the performance is much better. 132 * 133 * This interrupt handler is used only to gather statistics. 134 * 135 * @irq: IRQ of the SSI device 136 * @dev_id: pointer to the ssi_private structure for this SSI device 137 */ 138 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 139 { 140 struct fsl_ssi_private *ssi_private = dev_id; 141 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 142 irqreturn_t ret = IRQ_NONE; 143 __be32 sisr; 144 __be32 sisr2 = 0; 145 146 /* We got an interrupt, so read the status register to see what we 147 were interrupted for. We mask it with the Interrupt Enable register 148 so that we only check for events that we're interested in. 149 */ 150 sisr = in_be32(&ssi->sisr) & SIER_FLAGS; 151 152 if (sisr & CCSR_SSI_SISR_RFRC) { 153 ssi_private->stats.rfrc++; 154 sisr2 |= CCSR_SSI_SISR_RFRC; 155 ret = IRQ_HANDLED; 156 } 157 158 if (sisr & CCSR_SSI_SISR_TFRC) { 159 ssi_private->stats.tfrc++; 160 sisr2 |= CCSR_SSI_SISR_TFRC; 161 ret = IRQ_HANDLED; 162 } 163 164 if (sisr & CCSR_SSI_SISR_CMDAU) { 165 ssi_private->stats.cmdau++; 166 ret = IRQ_HANDLED; 167 } 168 169 if (sisr & CCSR_SSI_SISR_CMDDU) { 170 ssi_private->stats.cmddu++; 171 ret = IRQ_HANDLED; 172 } 173 174 if (sisr & CCSR_SSI_SISR_RXT) { 175 ssi_private->stats.rxt++; 176 ret = IRQ_HANDLED; 177 } 178 179 if (sisr & CCSR_SSI_SISR_RDR1) { 180 ssi_private->stats.rdr1++; 181 ret = IRQ_HANDLED; 182 } 183 184 if (sisr & CCSR_SSI_SISR_RDR0) { 185 ssi_private->stats.rdr0++; 186 ret = IRQ_HANDLED; 187 } 188 189 if (sisr & CCSR_SSI_SISR_TDE1) { 190 ssi_private->stats.tde1++; 191 ret = IRQ_HANDLED; 192 } 193 194 if (sisr & CCSR_SSI_SISR_TDE0) { 195 ssi_private->stats.tde0++; 196 ret = IRQ_HANDLED; 197 } 198 199 if (sisr & CCSR_SSI_SISR_ROE1) { 200 ssi_private->stats.roe1++; 201 sisr2 |= CCSR_SSI_SISR_ROE1; 202 ret = IRQ_HANDLED; 203 } 204 205 if (sisr & CCSR_SSI_SISR_ROE0) { 206 ssi_private->stats.roe0++; 207 sisr2 |= CCSR_SSI_SISR_ROE0; 208 ret = IRQ_HANDLED; 209 } 210 211 if (sisr & CCSR_SSI_SISR_TUE1) { 212 ssi_private->stats.tue1++; 213 sisr2 |= CCSR_SSI_SISR_TUE1; 214 ret = IRQ_HANDLED; 215 } 216 217 if (sisr & CCSR_SSI_SISR_TUE0) { 218 ssi_private->stats.tue0++; 219 sisr2 |= CCSR_SSI_SISR_TUE0; 220 ret = IRQ_HANDLED; 221 } 222 223 if (sisr & CCSR_SSI_SISR_TFS) { 224 ssi_private->stats.tfs++; 225 ret = IRQ_HANDLED; 226 } 227 228 if (sisr & CCSR_SSI_SISR_RFS) { 229 ssi_private->stats.rfs++; 230 ret = IRQ_HANDLED; 231 } 232 233 if (sisr & CCSR_SSI_SISR_TLS) { 234 ssi_private->stats.tls++; 235 ret = IRQ_HANDLED; 236 } 237 238 if (sisr & CCSR_SSI_SISR_RLS) { 239 ssi_private->stats.rls++; 240 ret = IRQ_HANDLED; 241 } 242 243 if (sisr & CCSR_SSI_SISR_RFF1) { 244 ssi_private->stats.rff1++; 245 ret = IRQ_HANDLED; 246 } 247 248 if (sisr & CCSR_SSI_SISR_RFF0) { 249 ssi_private->stats.rff0++; 250 ret = IRQ_HANDLED; 251 } 252 253 if (sisr & CCSR_SSI_SISR_TFE1) { 254 ssi_private->stats.tfe1++; 255 ret = IRQ_HANDLED; 256 } 257 258 if (sisr & CCSR_SSI_SISR_TFE0) { 259 ssi_private->stats.tfe0++; 260 ret = IRQ_HANDLED; 261 } 262 263 /* Clear the bits that we set */ 264 if (sisr2) 265 out_be32(&ssi->sisr, sisr2); 266 267 return ret; 268 } 269 270 /** 271 * fsl_ssi_startup: create a new substream 272 * 273 * This is the first function called when a stream is opened. 274 * 275 * If this is the first stream open, then grab the IRQ and program most of 276 * the SSI registers. 277 */ 278 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 279 struct snd_soc_dai *dai) 280 { 281 struct snd_soc_pcm_runtime *rtd = substream->private_data; 282 struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data; 283 284 /* 285 * If this is the first stream opened, then request the IRQ 286 * and initialize the SSI registers. 287 */ 288 if (!ssi_private->playback && !ssi_private->capture) { 289 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 290 int ret; 291 292 ret = request_irq(ssi_private->irq, fsl_ssi_isr, 0, 293 ssi_private->name, ssi_private); 294 if (ret < 0) { 295 dev_err(substream->pcm->card->dev, 296 "could not claim irq %u\n", ssi_private->irq); 297 return ret; 298 } 299 300 /* 301 * Section 16.5 of the MPC8610 reference manual says that the 302 * SSI needs to be disabled before updating the registers we set 303 * here. 304 */ 305 clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); 306 307 /* 308 * Program the SSI into I2S Slave Non-Network Synchronous mode. 309 * Also enable the transmit and receive FIFO. 310 * 311 * FIXME: Little-endian samples require a different shift dir 312 */ 313 clrsetbits_be32(&ssi->scr, 314 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN, 315 CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE 316 | (ssi_private->asynchronous ? 0 : CCSR_SSI_SCR_SYN)); 317 318 out_be32(&ssi->stcr, 319 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 | 320 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS | 321 CCSR_SSI_STCR_TSCKP); 322 323 out_be32(&ssi->srcr, 324 CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 | 325 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS | 326 CCSR_SSI_SRCR_RSCKP); 327 328 /* 329 * The DC and PM bits are only used if the SSI is the clock 330 * master. 331 */ 332 333 /* 4. Enable the interrupts and DMA requests */ 334 out_be32(&ssi->sier, SIER_FLAGS); 335 336 /* 337 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We 338 * don't use FIFO 1. Since the SSI only supports stereo, the 339 * watermark should never be an odd number. 340 */ 341 out_be32(&ssi->sfcsr, 342 CCSR_SSI_SFCSR_TFWM0(6) | CCSR_SSI_SFCSR_RFWM0(2)); 343 344 /* 345 * We keep the SSI disabled because if we enable it, then the 346 * DMA controller will start. It's not supposed to start until 347 * the SCR.TE (or SCR.RE) bit is set, but it does anyway. The 348 * DMA controller will transfer one "BWC" of data (i.e. the 349 * amount of data that the MR.BWC bits are set to). The reason 350 * this is bad is because at this point, the PCM driver has not 351 * finished initializing the DMA controller. 352 */ 353 } 354 355 if (!ssi_private->first_stream) 356 ssi_private->first_stream = substream; 357 else { 358 /* This is the second stream open, so we need to impose sample 359 * rate and maybe sample size constraints. Note that this can 360 * cause a race condition if the second stream is opened before 361 * the first stream is fully initialized. 362 * 363 * We provide some protection by checking to make sure the first 364 * stream is initialized, but it's not perfect. ALSA sometimes 365 * re-initializes the driver with a different sample rate or 366 * size. If the second stream is opened before the first stream 367 * has received its final parameters, then the second stream may 368 * be constrained to the wrong sample rate or size. 369 * 370 * FIXME: This code does not handle opening and closing streams 371 * repeatedly. If you open two streams and then close the first 372 * one, you may not be able to open another stream until you 373 * close the second one as well. 374 */ 375 struct snd_pcm_runtime *first_runtime = 376 ssi_private->first_stream->runtime; 377 378 if (!first_runtime->rate || !first_runtime->sample_bits) { 379 dev_err(substream->pcm->card->dev, 380 "set sample rate and size in %s stream first\n", 381 substream->stream == SNDRV_PCM_STREAM_PLAYBACK 382 ? "capture" : "playback"); 383 return -EAGAIN; 384 } 385 386 snd_pcm_hw_constraint_minmax(substream->runtime, 387 SNDRV_PCM_HW_PARAM_RATE, 388 first_runtime->rate, first_runtime->rate); 389 390 /* If we're in synchronous mode, then we need to constrain 391 * the sample size as well. We don't support independent sample 392 * rates in asynchronous mode. 393 */ 394 if (!ssi_private->asynchronous) 395 snd_pcm_hw_constraint_minmax(substream->runtime, 396 SNDRV_PCM_HW_PARAM_SAMPLE_BITS, 397 first_runtime->sample_bits, 398 first_runtime->sample_bits); 399 400 ssi_private->second_stream = substream; 401 } 402 403 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 404 ssi_private->playback++; 405 406 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 407 ssi_private->capture++; 408 409 return 0; 410 } 411 412 /** 413 * fsl_ssi_hw_params - program the sample size 414 * 415 * Most of the SSI registers have been programmed in the startup function, 416 * but the word length must be programmed here. Unfortunately, programming 417 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 418 * cause a problem with supporting simultaneous playback and capture. If 419 * the SSI is already playing a stream, then that stream may be temporarily 420 * stopped when you start capture. 421 * 422 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 423 * clock master. 424 */ 425 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 426 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 427 { 428 struct fsl_ssi_private *ssi_private = cpu_dai->private_data; 429 430 if (substream == ssi_private->first_stream) { 431 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 432 unsigned int sample_size = 433 snd_pcm_format_width(params_format(hw_params)); 434 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 435 436 /* The SSI should always be disabled at this points (SSIEN=0) */ 437 438 /* In synchronous mode, the SSI uses STCCR for capture */ 439 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 440 !ssi_private->asynchronous) 441 clrsetbits_be32(&ssi->stccr, 442 CCSR_SSI_SxCCR_WL_MASK, wl); 443 else 444 clrsetbits_be32(&ssi->srccr, 445 CCSR_SSI_SxCCR_WL_MASK, wl); 446 } 447 448 return 0; 449 } 450 451 /** 452 * fsl_ssi_trigger: start and stop the DMA transfer. 453 * 454 * This function is called by ALSA to start, stop, pause, and resume the DMA 455 * transfer of data. 456 * 457 * The DMA channel is in external master start and pause mode, which 458 * means the SSI completely controls the flow of data. 459 */ 460 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 461 struct snd_soc_dai *dai) 462 { 463 struct snd_soc_pcm_runtime *rtd = substream->private_data; 464 struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data; 465 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 466 467 switch (cmd) { 468 case SNDRV_PCM_TRIGGER_START: 469 clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); 470 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 471 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 472 setbits32(&ssi->scr, 473 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE); 474 else 475 setbits32(&ssi->scr, 476 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE); 477 break; 478 479 case SNDRV_PCM_TRIGGER_STOP: 480 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 481 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 482 clrbits32(&ssi->scr, CCSR_SSI_SCR_TE); 483 else 484 clrbits32(&ssi->scr, CCSR_SSI_SCR_RE); 485 break; 486 487 default: 488 return -EINVAL; 489 } 490 491 return 0; 492 } 493 494 /** 495 * fsl_ssi_shutdown: shutdown the SSI 496 * 497 * Shutdown the SSI if there are no other substreams open. 498 */ 499 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 500 struct snd_soc_dai *dai) 501 { 502 struct snd_soc_pcm_runtime *rtd = substream->private_data; 503 struct fsl_ssi_private *ssi_private = rtd->dai->cpu_dai->private_data; 504 505 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 506 ssi_private->playback--; 507 508 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 509 ssi_private->capture--; 510 511 if (ssi_private->first_stream == substream) 512 ssi_private->first_stream = ssi_private->second_stream; 513 514 ssi_private->second_stream = NULL; 515 516 /* 517 * If this is the last active substream, disable the SSI and release 518 * the IRQ. 519 */ 520 if (!ssi_private->playback && !ssi_private->capture) { 521 struct ccsr_ssi __iomem *ssi = ssi_private->ssi; 522 523 clrbits32(&ssi->scr, CCSR_SSI_SCR_SSIEN); 524 525 free_irq(ssi_private->irq, ssi_private); 526 } 527 } 528 529 /** 530 * fsl_ssi_set_sysclk: set the clock frequency and direction 531 * 532 * This function is called by the machine driver to tell us what the clock 533 * frequency and direction are. 534 * 535 * Currently, we only support operating as a clock slave (SND_SOC_CLOCK_IN), 536 * and we don't care about the frequency. Return an error if the direction 537 * is not SND_SOC_CLOCK_IN. 538 * 539 * @clk_id: reserved, should be zero 540 * @freq: the frequency of the given clock ID, currently ignored 541 * @dir: SND_SOC_CLOCK_IN (clock slave) or SND_SOC_CLOCK_OUT (clock master) 542 */ 543 static int fsl_ssi_set_sysclk(struct snd_soc_dai *cpu_dai, 544 int clk_id, unsigned int freq, int dir) 545 { 546 547 return (dir == SND_SOC_CLOCK_IN) ? 0 : -EINVAL; 548 } 549 550 /** 551 * fsl_ssi_set_fmt: set the serial format. 552 * 553 * This function is called by the machine driver to tell us what serial 554 * format to use. 555 * 556 * Currently, we only support I2S mode. Return an error if the format is 557 * not SND_SOC_DAIFMT_I2S. 558 * 559 * @format: one of SND_SOC_DAIFMT_xxx 560 */ 561 static int fsl_ssi_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int format) 562 { 563 return (format == SND_SOC_DAIFMT_I2S) ? 0 : -EINVAL; 564 } 565 566 /** 567 * fsl_ssi_dai_template: template CPU DAI for the SSI 568 */ 569 static struct snd_soc_dai_ops fsl_ssi_dai_ops = { 570 .startup = fsl_ssi_startup, 571 .hw_params = fsl_ssi_hw_params, 572 .shutdown = fsl_ssi_shutdown, 573 .trigger = fsl_ssi_trigger, 574 .set_sysclk = fsl_ssi_set_sysclk, 575 .set_fmt = fsl_ssi_set_fmt, 576 }; 577 578 static struct snd_soc_dai fsl_ssi_dai_template = { 579 .playback = { 580 /* The SSI does not support monaural audio. */ 581 .channels_min = 2, 582 .channels_max = 2, 583 .rates = FSLSSI_I2S_RATES, 584 .formats = FSLSSI_I2S_FORMATS, 585 }, 586 .capture = { 587 .channels_min = 2, 588 .channels_max = 2, 589 .rates = FSLSSI_I2S_RATES, 590 .formats = FSLSSI_I2S_FORMATS, 591 }, 592 .ops = &fsl_ssi_dai_ops, 593 }; 594 595 /* Show the statistics of a flag only if its interrupt is enabled. The 596 * compiler will optimze this code to a no-op if the interrupt is not 597 * enabled. 598 */ 599 #define SIER_SHOW(flag, name) \ 600 do { \ 601 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \ 602 length += sprintf(buf + length, #name "=%u\n", \ 603 ssi_private->stats.name); \ 604 } while (0) 605 606 607 /** 608 * fsl_sysfs_ssi_show: display SSI statistics 609 * 610 * Display the statistics for the current SSI device. To avoid confusion, 611 * we only show those counts that are enabled. 612 */ 613 static ssize_t fsl_sysfs_ssi_show(struct device *dev, 614 struct device_attribute *attr, char *buf) 615 { 616 struct fsl_ssi_private *ssi_private = 617 container_of(attr, struct fsl_ssi_private, dev_attr); 618 ssize_t length = 0; 619 620 SIER_SHOW(RFRC_EN, rfrc); 621 SIER_SHOW(TFRC_EN, tfrc); 622 SIER_SHOW(CMDAU_EN, cmdau); 623 SIER_SHOW(CMDDU_EN, cmddu); 624 SIER_SHOW(RXT_EN, rxt); 625 SIER_SHOW(RDR1_EN, rdr1); 626 SIER_SHOW(RDR0_EN, rdr0); 627 SIER_SHOW(TDE1_EN, tde1); 628 SIER_SHOW(TDE0_EN, tde0); 629 SIER_SHOW(ROE1_EN, roe1); 630 SIER_SHOW(ROE0_EN, roe0); 631 SIER_SHOW(TUE1_EN, tue1); 632 SIER_SHOW(TUE0_EN, tue0); 633 SIER_SHOW(TFS_EN, tfs); 634 SIER_SHOW(RFS_EN, rfs); 635 SIER_SHOW(TLS_EN, tls); 636 SIER_SHOW(RLS_EN, rls); 637 SIER_SHOW(RFF1_EN, rff1); 638 SIER_SHOW(RFF0_EN, rff0); 639 SIER_SHOW(TFE1_EN, tfe1); 640 SIER_SHOW(TFE0_EN, tfe0); 641 642 return length; 643 } 644 645 /** 646 * fsl_ssi_create_dai: create a snd_soc_dai structure 647 * 648 * This function is called by the machine driver to create a snd_soc_dai 649 * structure. The function creates an ssi_private object, which contains 650 * the snd_soc_dai. It also creates the sysfs statistics device. 651 */ 652 struct snd_soc_dai *fsl_ssi_create_dai(struct fsl_ssi_info *ssi_info) 653 { 654 struct snd_soc_dai *fsl_ssi_dai; 655 struct fsl_ssi_private *ssi_private; 656 int ret = 0; 657 struct device_attribute *dev_attr; 658 659 ssi_private = kzalloc(sizeof(struct fsl_ssi_private), GFP_KERNEL); 660 if (!ssi_private) { 661 dev_err(ssi_info->dev, "could not allocate DAI object\n"); 662 return NULL; 663 } 664 memcpy(&ssi_private->cpu_dai, &fsl_ssi_dai_template, 665 sizeof(struct snd_soc_dai)); 666 667 fsl_ssi_dai = &ssi_private->cpu_dai; 668 dev_attr = &ssi_private->dev_attr; 669 670 sprintf(ssi_private->name, "ssi%u", (u8) ssi_info->id); 671 ssi_private->ssi = ssi_info->ssi; 672 ssi_private->ssi_phys = ssi_info->ssi_phys; 673 ssi_private->irq = ssi_info->irq; 674 ssi_private->dev = ssi_info->dev; 675 ssi_private->asynchronous = ssi_info->asynchronous; 676 677 ssi_private->dev->driver_data = fsl_ssi_dai; 678 679 /* Initialize the the device_attribute structure */ 680 dev_attr->attr.name = "ssi-stats"; 681 dev_attr->attr.mode = S_IRUGO; 682 dev_attr->show = fsl_sysfs_ssi_show; 683 684 ret = device_create_file(ssi_private->dev, dev_attr); 685 if (ret) { 686 dev_err(ssi_info->dev, "could not create sysfs %s file\n", 687 ssi_private->dev_attr.attr.name); 688 kfree(fsl_ssi_dai); 689 return NULL; 690 } 691 692 fsl_ssi_dai->private_data = ssi_private; 693 fsl_ssi_dai->name = ssi_private->name; 694 fsl_ssi_dai->id = ssi_info->id; 695 fsl_ssi_dai->dev = ssi_info->dev; 696 697 ret = snd_soc_register_dai(fsl_ssi_dai); 698 if (ret != 0) { 699 dev_err(ssi_info->dev, "failed to register DAI: %d\n", ret); 700 kfree(fsl_ssi_dai); 701 return NULL; 702 } 703 704 return fsl_ssi_dai; 705 } 706 EXPORT_SYMBOL_GPL(fsl_ssi_create_dai); 707 708 /** 709 * fsl_ssi_destroy_dai: destroy the snd_soc_dai object 710 * 711 * This function undoes the operations of fsl_ssi_create_dai() 712 */ 713 void fsl_ssi_destroy_dai(struct snd_soc_dai *fsl_ssi_dai) 714 { 715 struct fsl_ssi_private *ssi_private = 716 container_of(fsl_ssi_dai, struct fsl_ssi_private, cpu_dai); 717 718 device_remove_file(ssi_private->dev, &ssi_private->dev_attr); 719 720 snd_soc_unregister_dai(&ssi_private->cpu_dai); 721 722 kfree(ssi_private); 723 } 724 EXPORT_SYMBOL_GPL(fsl_ssi_destroy_dai); 725 726 static int __init fsl_ssi_init(void) 727 { 728 printk(KERN_INFO "Freescale Synchronous Serial Interface (SSI) ASoC Driver\n"); 729 730 return 0; 731 } 732 module_init(fsl_ssi_init); 733 734 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 735 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 736 MODULE_LICENSE("GPL"); 737