1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards: 10 // 11 // The i.MX SSI core has some nasty limitations in AC97 mode. While most 12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only 13 // one FIFO which combines all valid receive slots. We cannot even select 14 // which slots we want to receive. The WM9712 with which this driver 15 // was developed with always sends GPIO status data in slot 12 which 16 // we receive in our (PCM-) data stream. The only chance we have is to 17 // manually skip this data in the FIQ handler. With sampling rates different 18 // from 48000Hz not every frame has valid receive data, so the ratio 19 // between pcm data and GPIO status data changes. Our FIQ handler is not 20 // able to handle this, hence this driver only works with 48000Hz sampling 21 // rate. 22 // Reading and writing AC97 registers is another challenge. The core 23 // provides us status bits when the read register is updated with *another* 24 // value. When we read the same register two times (and the register still 25 // contains the same value) these status bits are not set. We work 26 // around this by not polling these bits but only wait a fixed delay. 27 28 #include <linux/init.h> 29 #include <linux/io.h> 30 #include <linux/module.h> 31 #include <linux/interrupt.h> 32 #include <linux/clk.h> 33 #include <linux/ctype.h> 34 #include <linux/device.h> 35 #include <linux/delay.h> 36 #include <linux/mutex.h> 37 #include <linux/slab.h> 38 #include <linux/spinlock.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/of_platform.h> 43 44 #include <sound/core.h> 45 #include <sound/pcm.h> 46 #include <sound/pcm_params.h> 47 #include <sound/initval.h> 48 #include <sound/soc.h> 49 #include <sound/dmaengine_pcm.h> 50 51 #include "fsl_ssi.h" 52 #include "imx-pcm.h" 53 54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ 55 #define RX 0 56 #define TX 1 57 58 /** 59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 60 * 61 * The SSI has a limitation in that the samples must be in the same byte 62 * order as the host CPU. This is because when multiple bytes are written 63 * to the STX register, the bytes and bits must be written in the same 64 * order. The STX is a shift register, so all the bits need to be aligned 65 * (bit-endianness must match byte-endianness). Processors typically write 66 * the bits within a byte in the same order that the bytes of a word are 67 * written in. So if the host CPU is big-endian, then only big-endian 68 * samples will be written to STX properly. 69 */ 70 #ifdef __BIG_ENDIAN 71 #define FSLSSI_I2S_FORMATS \ 72 (SNDRV_PCM_FMTBIT_S8 | \ 73 SNDRV_PCM_FMTBIT_S16_BE | \ 74 SNDRV_PCM_FMTBIT_S18_3BE | \ 75 SNDRV_PCM_FMTBIT_S20_3BE | \ 76 SNDRV_PCM_FMTBIT_S24_3BE | \ 77 SNDRV_PCM_FMTBIT_S24_BE) 78 #else 79 #define FSLSSI_I2S_FORMATS \ 80 (SNDRV_PCM_FMTBIT_S8 | \ 81 SNDRV_PCM_FMTBIT_S16_LE | \ 82 SNDRV_PCM_FMTBIT_S18_3LE | \ 83 SNDRV_PCM_FMTBIT_S20_3LE | \ 84 SNDRV_PCM_FMTBIT_S24_3LE | \ 85 SNDRV_PCM_FMTBIT_S24_LE) 86 #endif 87 88 /* 89 * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: 90 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS 91 * - Also have NB_NF to mark these two clocks will not be inverted 92 */ 93 #define FSLSSI_AC97_DAIFMT \ 94 (SND_SOC_DAIFMT_AC97 | \ 95 SND_SOC_DAIFMT_CBM_CFS | \ 96 SND_SOC_DAIFMT_NB_NF) 97 98 #define FSLSSI_SIER_DBG_RX_FLAGS \ 99 (SSI_SIER_RFF0_EN | \ 100 SSI_SIER_RLS_EN | \ 101 SSI_SIER_RFS_EN | \ 102 SSI_SIER_ROE0_EN | \ 103 SSI_SIER_RFRC_EN) 104 #define FSLSSI_SIER_DBG_TX_FLAGS \ 105 (SSI_SIER_TFE0_EN | \ 106 SSI_SIER_TLS_EN | \ 107 SSI_SIER_TFS_EN | \ 108 SSI_SIER_TUE0_EN | \ 109 SSI_SIER_TFRC_EN) 110 111 enum fsl_ssi_type { 112 FSL_SSI_MCP8610, 113 FSL_SSI_MX21, 114 FSL_SSI_MX35, 115 FSL_SSI_MX51, 116 }; 117 118 struct fsl_ssi_regvals { 119 u32 sier; 120 u32 srcr; 121 u32 stcr; 122 u32 scr; 123 }; 124 125 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 126 { 127 switch (reg) { 128 case REG_SSI_SACCEN: 129 case REG_SSI_SACCDIS: 130 return false; 131 default: 132 return true; 133 } 134 } 135 136 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 137 { 138 switch (reg) { 139 case REG_SSI_STX0: 140 case REG_SSI_STX1: 141 case REG_SSI_SRX0: 142 case REG_SSI_SRX1: 143 case REG_SSI_SISR: 144 case REG_SSI_SFCSR: 145 case REG_SSI_SACNT: 146 case REG_SSI_SACADD: 147 case REG_SSI_SACDAT: 148 case REG_SSI_SATAG: 149 case REG_SSI_SACCST: 150 case REG_SSI_SOR: 151 return true; 152 default: 153 return false; 154 } 155 } 156 157 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 158 { 159 switch (reg) { 160 case REG_SSI_SRX0: 161 case REG_SSI_SRX1: 162 case REG_SSI_SISR: 163 case REG_SSI_SACADD: 164 case REG_SSI_SACDAT: 165 case REG_SSI_SATAG: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 173 { 174 switch (reg) { 175 case REG_SSI_SRX0: 176 case REG_SSI_SRX1: 177 case REG_SSI_SACCST: 178 return false; 179 default: 180 return true; 181 } 182 } 183 184 static const struct regmap_config fsl_ssi_regconfig = { 185 .max_register = REG_SSI_SACCDIS, 186 .reg_bits = 32, 187 .val_bits = 32, 188 .reg_stride = 4, 189 .val_format_endian = REGMAP_ENDIAN_NATIVE, 190 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, 191 .readable_reg = fsl_ssi_readable_reg, 192 .volatile_reg = fsl_ssi_volatile_reg, 193 .precious_reg = fsl_ssi_precious_reg, 194 .writeable_reg = fsl_ssi_writeable_reg, 195 .cache_type = REGCACHE_FLAT, 196 }; 197 198 struct fsl_ssi_soc_data { 199 bool imx; 200 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 201 bool offline_config; 202 u32 sisr_write_mask; 203 }; 204 205 /** 206 * fsl_ssi: per-SSI private data 207 * 208 * @regs: Pointer to the regmap registers 209 * @irq: IRQ of this SSI 210 * @cpu_dai_drv: CPU DAI driver for this device 211 * 212 * @dai_fmt: DAI configuration this device is currently used with 213 * @streams: Mask of current active streams: BIT(TX) and BIT(RX) 214 * @i2s_net: I2S and Network mode configurations of SCR register 215 * (this is the initial settings based on the DAI format) 216 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK 217 * @use_dma: DMA is used or FIQ with stream filter 218 * @use_dual_fifo: DMA with support for dual FIFO mode 219 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree 220 * @fifo_depth: Depth of the SSI FIFOs 221 * @slot_width: Width of each DAI slot 222 * @slots: Number of slots 223 * @regvals: Specific RX/TX register settings 224 * 225 * @clk: Clock source to access register 226 * @baudclk: Clock source to generate bit and frame-sync clocks 227 * @baudclk_streams: Active streams that are using baudclk 228 * 229 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume 230 * @regcache_sacnt: Cache sacnt register value during suspend and resume 231 * 232 * @dma_params_tx: DMA transmit parameters 233 * @dma_params_rx: DMA receive parameters 234 * @ssi_phys: physical address of the SSI registers 235 * 236 * @fiq_params: FIQ stream filtering parameters 237 * 238 * @card_pdev: Platform_device pointer to register a sound card for PowerPC or 239 * to register a CODEC platform device for AC97 240 * @card_name: Platform_device name to register a sound card for PowerPC or 241 * to register a CODEC platform device for AC97 242 * @card_idx: The index of SSI to register a sound card for PowerPC or 243 * to register a CODEC platform device for AC97 244 * 245 * @dbg_stats: Debugging statistics 246 * 247 * @soc: SoC specific data 248 * @dev: Pointer to &pdev->dev 249 * 250 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are 251 * @fifo_watermark or fewer words in TX fifo or 252 * @fifo_watermark or more empty words in RX fifo. 253 * @dma_maxburst: Max number of words to transfer in one go. So far, 254 * this is always the same as fifo_watermark. 255 * 256 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations 257 */ 258 struct fsl_ssi { 259 struct regmap *regs; 260 int irq; 261 struct snd_soc_dai_driver cpu_dai_drv; 262 263 unsigned int dai_fmt; 264 u8 streams; 265 u8 i2s_net; 266 bool synchronous; 267 bool use_dma; 268 bool use_dual_fifo; 269 bool has_ipg_clk_name; 270 unsigned int fifo_depth; 271 unsigned int slot_width; 272 unsigned int slots; 273 struct fsl_ssi_regvals regvals[2]; 274 275 struct clk *clk; 276 struct clk *baudclk; 277 unsigned int baudclk_streams; 278 279 u32 regcache_sfcsr; 280 u32 regcache_sacnt; 281 282 struct snd_dmaengine_dai_dma_data dma_params_tx; 283 struct snd_dmaengine_dai_dma_data dma_params_rx; 284 dma_addr_t ssi_phys; 285 286 struct imx_pcm_fiq_params fiq_params; 287 288 struct platform_device *card_pdev; 289 char card_name[32]; 290 u32 card_idx; 291 292 struct fsl_ssi_dbg dbg_stats; 293 294 const struct fsl_ssi_soc_data *soc; 295 struct device *dev; 296 297 u32 fifo_watermark; 298 u32 dma_maxburst; 299 300 struct mutex ac97_reg_lock; 301 }; 302 303 /* 304 * SoC specific data 305 * 306 * Notes: 307 * 1) SSI in earlier SoCS has critical bits in control registers that 308 * cannot be changed after SSI starts running -- a software reset 309 * (set SSIEN to 0) is required to change their values. So adding 310 * an offline_config flag for these SoCs. 311 * 2) SDMA is available since imx35. However, imx35 does not support 312 * DMA bits changing when SSI is running, so set offline_config. 313 * 3) imx51 and later versions support register configurations when 314 * SSI is running (SSIEN); For these versions, DMA needs to be 315 * configured before SSI sends DMA request to avoid an undefined 316 * DMA request on the SDMA side. 317 */ 318 319 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 320 .imx = false, 321 .offline_config = true, 322 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 323 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 324 SSI_SISR_TUE0 | SSI_SISR_TUE1, 325 }; 326 327 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 328 .imx = true, 329 .imx21regs = true, 330 .offline_config = true, 331 .sisr_write_mask = 0, 332 }; 333 334 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 335 .imx = true, 336 .offline_config = true, 337 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 338 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 339 SSI_SISR_TUE0 | SSI_SISR_TUE1, 340 }; 341 342 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 343 .imx = true, 344 .offline_config = false, 345 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | 346 SSI_SISR_TUE0 | SSI_SISR_TUE1, 347 }; 348 349 static const struct of_device_id fsl_ssi_ids[] = { 350 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 351 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 352 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 353 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 354 {} 355 }; 356 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 357 358 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) 359 { 360 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 361 SND_SOC_DAIFMT_AC97; 362 } 363 364 static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi) 365 { 366 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 367 SND_SOC_DAIFMT_CBS_CFS; 368 } 369 370 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi) 371 { 372 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 373 SND_SOC_DAIFMT_CBM_CFS; 374 } 375 376 /** 377 * Interrupt handler to gather states 378 */ 379 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 380 { 381 struct fsl_ssi *ssi = dev_id; 382 struct regmap *regs = ssi->regs; 383 u32 sisr, sisr2; 384 385 regmap_read(regs, REG_SSI_SISR, &sisr); 386 387 sisr2 = sisr & ssi->soc->sisr_write_mask; 388 /* Clear the bits that we set */ 389 if (sisr2) 390 regmap_write(regs, REG_SSI_SISR, sisr2); 391 392 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); 393 394 return IRQ_HANDLED; 395 } 396 397 /** 398 * Set SCR, SIER, STCR and SRCR registers with cached values in regvals 399 * 400 * Notes: 401 * 1) For offline_config SoCs, enable all necessary bits of both streams 402 * when 1st stream starts, even if the opposite stream will not start 403 * 2) It also clears FIFO before setting regvals; SOR is safe to set online 404 */ 405 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) 406 { 407 struct fsl_ssi_regvals *vals = ssi->regvals; 408 int dir = tx ? TX : RX; 409 u32 sier, srcr, stcr; 410 411 /* Clear dirty data in the FIFO; It also prevents channel slipping */ 412 regmap_update_bits(ssi->regs, REG_SSI_SOR, 413 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); 414 415 /* 416 * On offline_config SoCs, SxCR and SIER are already configured when 417 * the previous stream started. So skip all SxCR and SIER settings 418 * to prevent online reconfigurations, then jump to set SCR directly 419 */ 420 if (ssi->soc->offline_config && ssi->streams) 421 goto enable_scr; 422 423 if (ssi->soc->offline_config) { 424 /* 425 * Online reconfiguration not supported, so enable all bits for 426 * both streams at once to avoid necessity of reconfigurations 427 */ 428 srcr = vals[RX].srcr | vals[TX].srcr; 429 stcr = vals[RX].stcr | vals[TX].stcr; 430 sier = vals[RX].sier | vals[TX].sier; 431 } else { 432 /* Otherwise, only set bits for the current stream */ 433 srcr = vals[dir].srcr; 434 stcr = vals[dir].stcr; 435 sier = vals[dir].sier; 436 } 437 438 /* Configure SRCR, STCR and SIER at once */ 439 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr); 440 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr); 441 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier); 442 443 enable_scr: 444 /* 445 * Start DMA before setting TE to avoid FIFO underrun 446 * which may cause a channel slip or a channel swap 447 * 448 * TODO: FIQ cases might also need this upon testing 449 */ 450 if (ssi->use_dma && tx) { 451 int try = 100; 452 u32 sfcsr; 453 454 /* Enable SSI first to send TX DMA request */ 455 regmap_update_bits(ssi->regs, REG_SSI_SCR, 456 SSI_SCR_SSIEN, SSI_SCR_SSIEN); 457 458 /* Busy wait until TX FIFO not empty -- DMA working */ 459 do { 460 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr); 461 if (SSI_SFCSR_TFCNT0(sfcsr)) 462 break; 463 } while (--try); 464 465 /* FIFO still empty -- something might be wrong */ 466 if (!SSI_SFCSR_TFCNT0(sfcsr)) 467 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n"); 468 } 469 /* Enable all remaining bits in SCR */ 470 regmap_update_bits(ssi->regs, REG_SSI_SCR, 471 vals[dir].scr, vals[dir].scr); 472 473 /* Log the enabled stream to the mask */ 474 ssi->streams |= BIT(dir); 475 } 476 477 /** 478 * Exclude bits that are used by the opposite stream 479 * 480 * When both streams are active, disabling some bits for the current stream 481 * might break the other stream if these bits are used by it. 482 * 483 * @vals : regvals of the current stream 484 * @avals: regvals of the opposite stream 485 * @aactive: active state of the opposite stream 486 * 487 * 1) XOR vals and avals to get the differences if the other stream is active; 488 * Otherwise, return current vals if the other stream is not active 489 * 2) AND the result of 1) with the current vals 490 */ 491 #define _ssi_xor_shared_bits(vals, avals, aactive) \ 492 ((vals) ^ ((avals) * (aactive))) 493 494 #define ssi_excl_shared_bits(vals, avals, aactive) \ 495 ((vals) & _ssi_xor_shared_bits(vals, avals, aactive)) 496 497 /** 498 * Unset SCR, SIER, STCR and SRCR registers with cached values in regvals 499 * 500 * Notes: 501 * 1) For offline_config SoCs, to avoid online reconfigurations, disable all 502 * bits of both streams at once when the last stream is abort to end 503 * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online 504 */ 505 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) 506 { 507 struct fsl_ssi_regvals *vals, *avals; 508 u32 sier, srcr, stcr, scr; 509 int adir = tx ? RX : TX; 510 int dir = tx ? TX : RX; 511 bool aactive; 512 513 /* Check if the opposite stream is active */ 514 aactive = ssi->streams & BIT(adir); 515 516 vals = &ssi->regvals[dir]; 517 518 /* Get regvals of the opposite stream to keep opposite stream safe */ 519 avals = &ssi->regvals[adir]; 520 521 /* 522 * To keep the other stream safe, exclude shared bits between 523 * both streams, and get safe bits to disable current stream 524 */ 525 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); 526 527 /* Disable safe bits of SCR register for the current stream */ 528 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0); 529 530 /* Log the disabled stream to the mask */ 531 ssi->streams &= ~BIT(dir); 532 533 /* 534 * On offline_config SoCs, if the other stream is active, skip 535 * SxCR and SIER settings to prevent online reconfigurations 536 */ 537 if (ssi->soc->offline_config && aactive) 538 goto fifo_clear; 539 540 if (ssi->soc->offline_config) { 541 /* Now there is only current stream active, disable all bits */ 542 srcr = vals->srcr | avals->srcr; 543 stcr = vals->stcr | avals->stcr; 544 sier = vals->sier | avals->sier; 545 } else { 546 /* 547 * To keep the other stream safe, exclude shared bits between 548 * both streams, and get safe bits to disable current stream 549 */ 550 sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive); 551 srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive); 552 stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive); 553 } 554 555 /* Clear configurations of SRCR, STCR and SIER at once */ 556 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0); 557 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0); 558 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0); 559 560 fifo_clear: 561 /* Clear remaining data in the FIFO */ 562 regmap_update_bits(ssi->regs, REG_SSI_SOR, 563 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); 564 } 565 566 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) 567 { 568 struct regmap *regs = ssi->regs; 569 570 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 571 if (!ssi->soc->imx21regs) { 572 /* Disable all channel slots */ 573 regmap_write(regs, REG_SSI_SACCDIS, 0xff); 574 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ 575 regmap_write(regs, REG_SSI_SACCEN, 0x300); 576 } 577 } 578 579 /** 580 * Cache critical bits of SIER, SRCR, STCR and SCR to later set them safely 581 */ 582 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) 583 { 584 struct fsl_ssi_regvals *vals = ssi->regvals; 585 586 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS; 587 vals[RX].srcr = SSI_SRCR_RFEN0; 588 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; 589 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; 590 vals[TX].stcr = SSI_STCR_TFEN0; 591 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; 592 593 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ 594 if (fsl_ssi_is_ac97(ssi)) 595 vals[RX].scr = vals[TX].scr = 0; 596 597 if (ssi->use_dual_fifo) { 598 vals[RX].srcr |= SSI_SRCR_RFEN1; 599 vals[TX].stcr |= SSI_STCR_TFEN1; 600 } 601 602 if (ssi->use_dma) { 603 vals[RX].sier |= SSI_SIER_RDMAE; 604 vals[TX].sier |= SSI_SIER_TDMAE; 605 } else { 606 vals[RX].sier |= SSI_SIER_RIE; 607 vals[TX].sier |= SSI_SIER_TIE; 608 } 609 } 610 611 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) 612 { 613 struct regmap *regs = ssi->regs; 614 615 /* Setup the clock control register */ 616 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 617 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 618 619 /* Enable AC97 mode and startup the SSI */ 620 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); 621 622 /* AC97 has to communicate with codec before starting a stream */ 623 regmap_update_bits(regs, REG_SSI_SCR, 624 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, 625 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); 626 627 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); 628 } 629 630 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 631 struct snd_soc_dai *dai) 632 { 633 struct snd_soc_pcm_runtime *rtd = substream->private_data; 634 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 635 int ret; 636 637 ret = clk_prepare_enable(ssi->clk); 638 if (ret) 639 return ret; 640 641 /* 642 * When using dual fifo mode, it is safer to ensure an even period 643 * size. If appearing to an odd number while DMA always starts its 644 * task from fifo0, fifo1 would be neglected at the end of each 645 * period. But SSI would still access fifo1 with an invalid data. 646 */ 647 if (ssi->use_dual_fifo) 648 snd_pcm_hw_constraint_step(substream->runtime, 0, 649 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 650 651 return 0; 652 } 653 654 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 655 struct snd_soc_dai *dai) 656 { 657 struct snd_soc_pcm_runtime *rtd = substream->private_data; 658 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 659 660 clk_disable_unprepare(ssi->clk); 661 } 662 663 /** 664 * Configure Digital Audio Interface bit clock 665 * 666 * Note: This function can be only called when using SSI as DAI master 667 * 668 * Quick instruction for parameters: 669 * freq: Output BCLK frequency = samplerate * slots * slot_width 670 * (In 2-channel I2S Master mode, slot_width is fixed 32) 671 */ 672 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 673 struct snd_soc_dai *dai, 674 struct snd_pcm_hw_params *hw_params) 675 { 676 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 677 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 678 struct regmap *regs = ssi->regs; 679 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 680 unsigned long clkrate, baudrate, tmprate; 681 unsigned int channels = params_channels(hw_params); 682 unsigned int slot_width = params_width(hw_params); 683 unsigned int slots = 2; 684 u64 sub, savesub = 100000; 685 unsigned int freq; 686 bool baudclk_is_used; 687 int ret; 688 689 /* Override slots and slot_width if being specifically set... */ 690 if (ssi->slots) 691 slots = ssi->slots; 692 if (ssi->slot_width) 693 slot_width = ssi->slot_width; 694 695 /* ...but force 32 bits for stereo audio using I2S Master Mode */ 696 if (channels == 2 && 697 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER) 698 slot_width = 32; 699 700 /* Generate bit clock based on the slot number and slot width */ 701 freq = slots * slot_width * params_rate(hw_params); 702 703 /* Don't apply it to any non-baudclk circumstance */ 704 if (IS_ERR(ssi->baudclk)) 705 return -EINVAL; 706 707 /* 708 * Hardware limitation: The bclk rate must be 709 * never greater than 1/5 IPG clock rate 710 */ 711 if (freq * 5 > clk_get_rate(ssi->clk)) { 712 dev_err(dai->dev, "bitclk > ipgclk / 5\n"); 713 return -EINVAL; 714 } 715 716 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); 717 718 /* It should be already enough to divide clock by setting pm alone */ 719 psr = 0; 720 div2 = 0; 721 722 factor = (div2 + 1) * (7 * psr + 1) * 2; 723 724 for (i = 0; i < 255; i++) { 725 tmprate = freq * factor * (i + 1); 726 727 if (baudclk_is_used) 728 clkrate = clk_get_rate(ssi->baudclk); 729 else 730 clkrate = clk_round_rate(ssi->baudclk, tmprate); 731 732 clkrate /= factor; 733 afreq = clkrate / (i + 1); 734 735 if (freq == afreq) 736 sub = 0; 737 else if (freq / afreq == 1) 738 sub = freq - afreq; 739 else if (afreq / freq == 1) 740 sub = afreq - freq; 741 else 742 continue; 743 744 /* Calculate the fraction */ 745 sub *= 100000; 746 do_div(sub, freq); 747 748 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 749 baudrate = tmprate; 750 savesub = sub; 751 pm = i; 752 } 753 754 /* We are lucky */ 755 if (savesub == 0) 756 break; 757 } 758 759 /* No proper pm found if it is still remaining the initial value */ 760 if (pm == 999) { 761 dev_err(dai->dev, "failed to handle the required sysclk\n"); 762 return -EINVAL; 763 } 764 765 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | 766 (psr ? SSI_SxCCR_PSR : 0); 767 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; 768 769 /* STCCR is used for RX in synchronous mode */ 770 tx2 = tx || ssi->synchronous; 771 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); 772 773 if (!baudclk_is_used) { 774 ret = clk_set_rate(ssi->baudclk, baudrate); 775 if (ret) { 776 dev_err(dai->dev, "failed to set baudclk rate\n"); 777 return -EINVAL; 778 } 779 } 780 781 return 0; 782 } 783 784 /** 785 * Configure SSI based on PCM hardware parameters 786 * 787 * Notes: 788 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily 789 * disabled on offline_config SoCs. Even for online configurable SoCs 790 * running in synchronous mode (both TX and RX use STCCR), it is not 791 * safe to re-configure them when both two streams start running. 792 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the 793 * fsl_ssi_set_bclk() if SSI is the DAI clock master. 794 */ 795 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 796 struct snd_pcm_hw_params *hw_params, 797 struct snd_soc_dai *dai) 798 { 799 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 800 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 801 struct regmap *regs = ssi->regs; 802 unsigned int channels = params_channels(hw_params); 803 unsigned int sample_size = params_width(hw_params); 804 u32 wl = SSI_SxCCR_WL(sample_size); 805 int ret; 806 807 if (fsl_ssi_is_i2s_master(ssi)) { 808 ret = fsl_ssi_set_bclk(substream, dai, hw_params); 809 if (ret) 810 return ret; 811 812 /* Do not enable the clock if it is already enabled */ 813 if (!(ssi->baudclk_streams & BIT(substream->stream))) { 814 ret = clk_prepare_enable(ssi->baudclk); 815 if (ret) 816 return ret; 817 818 ssi->baudclk_streams |= BIT(substream->stream); 819 } 820 } 821 822 /* 823 * SSI is properly configured if it is enabled and running in 824 * the synchronous mode; Note that AC97 mode is an exception 825 * that should set separate configurations for STCCR and SRCCR 826 * despite running in the synchronous mode. 827 */ 828 if (ssi->streams && ssi->synchronous) 829 return 0; 830 831 if (!fsl_ssi_is_ac97(ssi)) { 832 /* 833 * Keep the ssi->i2s_net intact while having a local variable 834 * to override settings for special use cases. Otherwise, the 835 * ssi->i2s_net will lose the settings for regular use cases. 836 */ 837 u8 i2s_net = ssi->i2s_net; 838 839 /* Normal + Network mode to send 16-bit data in 32-bit frames */ 840 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) 841 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; 842 843 /* Use Normal mode to send mono data at 1st slot of 2 slots */ 844 if (channels == 1) 845 i2s_net = SSI_SCR_I2S_MODE_NORMAL; 846 847 regmap_update_bits(regs, REG_SSI_SCR, 848 SSI_SCR_I2S_NET_MASK, i2s_net); 849 } 850 851 /* In synchronous mode, the SSI uses STCCR for capture */ 852 tx2 = tx || ssi->synchronous; 853 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); 854 855 return 0; 856 } 857 858 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 859 struct snd_soc_dai *dai) 860 { 861 struct snd_soc_pcm_runtime *rtd = substream->private_data; 862 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 863 864 if (fsl_ssi_is_i2s_master(ssi) && 865 ssi->baudclk_streams & BIT(substream->stream)) { 866 clk_disable_unprepare(ssi->baudclk); 867 ssi->baudclk_streams &= ~BIT(substream->stream); 868 } 869 870 return 0; 871 } 872 873 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) 874 { 875 u32 strcr = 0, scr = 0, stcr, srcr, mask; 876 877 ssi->dai_fmt = fmt; 878 879 /* Synchronize frame sync clock for TE to avoid data slipping */ 880 scr |= SSI_SCR_SYNC_TX_FS; 881 882 /* Set to default shifting settings: LSB_ALIGNED */ 883 strcr |= SSI_STCR_TXBIT0; 884 885 /* Use Network mode as default */ 886 ssi->i2s_net = SSI_SCR_NET; 887 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 888 case SND_SOC_DAIFMT_I2S: 889 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 890 case SND_SOC_DAIFMT_CBS_CFS: 891 if (IS_ERR(ssi->baudclk)) { 892 dev_err(ssi->dev, 893 "missing baudclk for master mode\n"); 894 return -EINVAL; 895 } 896 /* fall through */ 897 case SND_SOC_DAIFMT_CBM_CFS: 898 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; 899 break; 900 case SND_SOC_DAIFMT_CBM_CFM: 901 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 regmap_update_bits(ssi->regs, REG_SSI_STCCR, 908 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 909 regmap_update_bits(ssi->regs, REG_SSI_SRCCR, 910 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 911 912 /* Data on rising edge of bclk, frame low, 1clk before data */ 913 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS; 914 break; 915 case SND_SOC_DAIFMT_LEFT_J: 916 /* Data on rising edge of bclk, frame high */ 917 strcr |= SSI_STCR_TSCKP; 918 break; 919 case SND_SOC_DAIFMT_DSP_A: 920 /* Data on rising edge of bclk, frame high, 1clk before data */ 921 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS; 922 break; 923 case SND_SOC_DAIFMT_DSP_B: 924 /* Data on rising edge of bclk, frame high */ 925 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP; 926 break; 927 case SND_SOC_DAIFMT_AC97: 928 /* Data on falling edge of bclk, frame high, 1clk before data */ 929 strcr |= SSI_STCR_TEFS; 930 break; 931 default: 932 return -EINVAL; 933 } 934 935 scr |= ssi->i2s_net; 936 937 /* DAI clock inversion */ 938 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 939 case SND_SOC_DAIFMT_NB_NF: 940 /* Nothing to do for both normal cases */ 941 break; 942 case SND_SOC_DAIFMT_IB_NF: 943 /* Invert bit clock */ 944 strcr ^= SSI_STCR_TSCKP; 945 break; 946 case SND_SOC_DAIFMT_NB_IF: 947 /* Invert frame clock */ 948 strcr ^= SSI_STCR_TFSI; 949 break; 950 case SND_SOC_DAIFMT_IB_IF: 951 /* Invert both clocks */ 952 strcr ^= SSI_STCR_TSCKP; 953 strcr ^= SSI_STCR_TFSI; 954 break; 955 default: 956 return -EINVAL; 957 } 958 959 /* DAI clock master masks */ 960 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 961 case SND_SOC_DAIFMT_CBS_CFS: 962 /* Output bit and frame sync clocks */ 963 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; 964 scr |= SSI_SCR_SYS_CLK_EN; 965 break; 966 case SND_SOC_DAIFMT_CBM_CFM: 967 /* Input bit or frame sync clocks */ 968 break; 969 case SND_SOC_DAIFMT_CBM_CFS: 970 /* Input bit clock but output frame sync clock */ 971 strcr |= SSI_STCR_TFDIR; 972 break; 973 default: 974 return -EINVAL; 975 } 976 977 stcr = strcr; 978 srcr = strcr; 979 980 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ 981 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { 982 srcr &= ~SSI_SRCR_RXDIR; 983 scr |= SSI_SCR_SYN; 984 } 985 986 mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | 987 SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; 988 989 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); 990 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); 991 992 mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | 993 SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN; 994 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); 995 996 return 0; 997 } 998 999 /** 1000 * Configure Digital Audio Interface (DAI) Format 1001 */ 1002 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1003 { 1004 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1005 1006 /* AC97 configured DAIFMT earlier in the probe() */ 1007 if (fsl_ssi_is_ac97(ssi)) 1008 return 0; 1009 1010 return _fsl_ssi_set_dai_fmt(ssi, fmt); 1011 } 1012 1013 /** 1014 * Set TDM slot number and slot width 1015 */ 1016 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 1017 u32 rx_mask, int slots, int slot_width) 1018 { 1019 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1020 struct regmap *regs = ssi->regs; 1021 u32 val; 1022 1023 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ 1024 if (slot_width & 1 || slot_width < 8 || slot_width > 24) { 1025 dev_err(dai->dev, "invalid slot width: %d\n", slot_width); 1026 return -EINVAL; 1027 } 1028 1029 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1030 if (ssi->i2s_net && slots < 2) { 1031 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1032 return -EINVAL; 1033 } 1034 1035 regmap_update_bits(regs, REG_SSI_STCCR, 1036 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1037 regmap_update_bits(regs, REG_SSI_SRCCR, 1038 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1039 1040 /* Save the SCR register value */ 1041 regmap_read(regs, REG_SSI_SCR, &val); 1042 /* Temporarily enable SSI to allow SxMSKs to be configurable */ 1043 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); 1044 1045 regmap_write(regs, REG_SSI_STMSK, ~tx_mask); 1046 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); 1047 1048 /* Restore the value of SSIEN bit */ 1049 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); 1050 1051 ssi->slot_width = slot_width; 1052 ssi->slots = slots; 1053 1054 return 0; 1055 } 1056 1057 /** 1058 * Start or stop SSI and corresponding DMA transaction. 1059 * 1060 * The DMA channel is in external master start and pause mode, which 1061 * means the SSI completely controls the flow of data. 1062 */ 1063 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1064 struct snd_soc_dai *dai) 1065 { 1066 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1067 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 1068 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 1069 1070 switch (cmd) { 1071 case SNDRV_PCM_TRIGGER_START: 1072 case SNDRV_PCM_TRIGGER_RESUME: 1073 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1074 /* 1075 * SACCST might be modified via AC Link by a CODEC if it sends 1076 * extra bits in their SLOTREQ requests, which'll accidentally 1077 * send valid data to slots other than normal playback slots. 1078 * 1079 * To be safe, configure SACCST right before TX starts. 1080 */ 1081 if (tx && fsl_ssi_is_ac97(ssi)) 1082 fsl_ssi_tx_ac97_saccst_setup(ssi); 1083 fsl_ssi_config_enable(ssi, tx); 1084 break; 1085 1086 case SNDRV_PCM_TRIGGER_STOP: 1087 case SNDRV_PCM_TRIGGER_SUSPEND: 1088 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1089 fsl_ssi_config_disable(ssi, tx); 1090 break; 1091 1092 default: 1093 return -EINVAL; 1094 } 1095 1096 return 0; 1097 } 1098 1099 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1100 { 1101 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1102 1103 if (ssi->soc->imx && ssi->use_dma) 1104 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx, 1105 &ssi->dma_params_rx); 1106 1107 return 0; 1108 } 1109 1110 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1111 .startup = fsl_ssi_startup, 1112 .shutdown = fsl_ssi_shutdown, 1113 .hw_params = fsl_ssi_hw_params, 1114 .hw_free = fsl_ssi_hw_free, 1115 .set_fmt = fsl_ssi_set_dai_fmt, 1116 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1117 .trigger = fsl_ssi_trigger, 1118 }; 1119 1120 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1121 .probe = fsl_ssi_dai_probe, 1122 .playback = { 1123 .stream_name = "CPU-Playback", 1124 .channels_min = 1, 1125 .channels_max = 32, 1126 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1127 .formats = FSLSSI_I2S_FORMATS, 1128 }, 1129 .capture = { 1130 .stream_name = "CPU-Capture", 1131 .channels_min = 1, 1132 .channels_max = 32, 1133 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1134 .formats = FSLSSI_I2S_FORMATS, 1135 }, 1136 .ops = &fsl_ssi_dai_ops, 1137 }; 1138 1139 static const struct snd_soc_component_driver fsl_ssi_component = { 1140 .name = "fsl-ssi", 1141 }; 1142 1143 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1144 .symmetric_channels = 1, 1145 .probe = fsl_ssi_dai_probe, 1146 .playback = { 1147 .stream_name = "AC97 Playback", 1148 .channels_min = 2, 1149 .channels_max = 2, 1150 .rates = SNDRV_PCM_RATE_8000_48000, 1151 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, 1152 }, 1153 .capture = { 1154 .stream_name = "AC97 Capture", 1155 .channels_min = 2, 1156 .channels_max = 2, 1157 .rates = SNDRV_PCM_RATE_48000, 1158 /* 16-bit capture is broken (errata ERR003778) */ 1159 .formats = SNDRV_PCM_FMTBIT_S20, 1160 }, 1161 .ops = &fsl_ssi_dai_ops, 1162 }; 1163 1164 static struct fsl_ssi *fsl_ac97_data; 1165 1166 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1167 unsigned short val) 1168 { 1169 struct regmap *regs = fsl_ac97_data->regs; 1170 unsigned int lreg; 1171 unsigned int lval; 1172 int ret; 1173 1174 if (reg > 0x7f) 1175 return; 1176 1177 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1178 1179 ret = clk_prepare_enable(fsl_ac97_data->clk); 1180 if (ret) { 1181 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1182 ret); 1183 goto ret_unlock; 1184 } 1185 1186 lreg = reg << 12; 1187 regmap_write(regs, REG_SSI_SACADD, lreg); 1188 1189 lval = val << 4; 1190 regmap_write(regs, REG_SSI_SACDAT, lval); 1191 1192 regmap_update_bits(regs, REG_SSI_SACNT, 1193 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); 1194 udelay(100); 1195 1196 clk_disable_unprepare(fsl_ac97_data->clk); 1197 1198 ret_unlock: 1199 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1200 } 1201 1202 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1203 unsigned short reg) 1204 { 1205 struct regmap *regs = fsl_ac97_data->regs; 1206 unsigned short val = 0; 1207 u32 reg_val; 1208 unsigned int lreg; 1209 int ret; 1210 1211 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1212 1213 ret = clk_prepare_enable(fsl_ac97_data->clk); 1214 if (ret) { 1215 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); 1216 goto ret_unlock; 1217 } 1218 1219 lreg = (reg & 0x7f) << 12; 1220 regmap_write(regs, REG_SSI_SACADD, lreg); 1221 regmap_update_bits(regs, REG_SSI_SACNT, 1222 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); 1223 1224 udelay(100); 1225 1226 regmap_read(regs, REG_SSI_SACDAT, ®_val); 1227 val = (reg_val >> 4) & 0xffff; 1228 1229 clk_disable_unprepare(fsl_ac97_data->clk); 1230 1231 ret_unlock: 1232 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1233 return val; 1234 } 1235 1236 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1237 .read = fsl_ssi_ac97_read, 1238 .write = fsl_ssi_ac97_write, 1239 }; 1240 1241 /** 1242 * Initialize SSI registers 1243 */ 1244 static int fsl_ssi_hw_init(struct fsl_ssi *ssi) 1245 { 1246 u32 wm = ssi->fifo_watermark; 1247 1248 /* Initialize regvals */ 1249 fsl_ssi_setup_regvals(ssi); 1250 1251 /* Set watermarks */ 1252 regmap_write(ssi->regs, REG_SSI_SFCSR, 1253 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | 1254 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); 1255 1256 /* Enable Dual FIFO mode */ 1257 if (ssi->use_dual_fifo) 1258 regmap_update_bits(ssi->regs, REG_SSI_SCR, 1259 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); 1260 1261 /* AC97 should start earlier to communicate with CODECs */ 1262 if (fsl_ssi_is_ac97(ssi)) { 1263 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt); 1264 fsl_ssi_setup_ac97(ssi); 1265 } 1266 1267 return 0; 1268 } 1269 1270 /** 1271 * Clear SSI registers 1272 */ 1273 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) 1274 { 1275 /* Disable registers for AC97 */ 1276 if (fsl_ssi_is_ac97(ssi)) { 1277 /* Disable TE and RE bits first */ 1278 regmap_update_bits(ssi->regs, REG_SSI_SCR, 1279 SSI_SCR_TE | SSI_SCR_RE, 0); 1280 /* Disable AC97 mode */ 1281 regmap_write(ssi->regs, REG_SSI_SACNT, 0); 1282 /* Unset WAIT bits */ 1283 regmap_write(ssi->regs, REG_SSI_SOR, 0); 1284 /* Disable SSI -- software reset */ 1285 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0); 1286 } 1287 } 1288 /** 1289 * Make every character in a string lower-case 1290 */ 1291 static void make_lowercase(char *s) 1292 { 1293 if (!s) 1294 return; 1295 for (; *s; s++) 1296 *s = tolower(*s); 1297 } 1298 1299 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1300 struct fsl_ssi *ssi, void __iomem *iomem) 1301 { 1302 struct device *dev = &pdev->dev; 1303 int ret; 1304 1305 /* Backward compatible for a DT without ipg clock name assigned */ 1306 if (ssi->has_ipg_clk_name) 1307 ssi->clk = devm_clk_get(dev, "ipg"); 1308 else 1309 ssi->clk = devm_clk_get(dev, NULL); 1310 if (IS_ERR(ssi->clk)) { 1311 ret = PTR_ERR(ssi->clk); 1312 dev_err(dev, "failed to get clock: %d\n", ret); 1313 return ret; 1314 } 1315 1316 /* Enable the clock since regmap will not handle it in this case */ 1317 if (!ssi->has_ipg_clk_name) { 1318 ret = clk_prepare_enable(ssi->clk); 1319 if (ret) { 1320 dev_err(dev, "clk_prepare_enable failed: %d\n", ret); 1321 return ret; 1322 } 1323 } 1324 1325 /* Do not error out for slave cases that live without a baud clock */ 1326 ssi->baudclk = devm_clk_get(dev, "baud"); 1327 if (IS_ERR(ssi->baudclk)) 1328 dev_dbg(dev, "failed to get baud clock: %ld\n", 1329 PTR_ERR(ssi->baudclk)); 1330 1331 ssi->dma_params_tx.maxburst = ssi->dma_maxburst; 1332 ssi->dma_params_rx.maxburst = ssi->dma_maxburst; 1333 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; 1334 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; 1335 1336 /* Use even numbers to avoid channel swap due to SDMA script design */ 1337 if (ssi->use_dual_fifo) { 1338 ssi->dma_params_tx.maxburst &= ~0x1; 1339 ssi->dma_params_rx.maxburst &= ~0x1; 1340 } 1341 1342 if (!ssi->use_dma) { 1343 /* 1344 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio 1345 * to get it working, as DMA is not possible in this situation. 1346 */ 1347 ssi->fiq_params.irq = ssi->irq; 1348 ssi->fiq_params.base = iomem; 1349 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; 1350 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; 1351 1352 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); 1353 if (ret) 1354 goto error_pcm; 1355 } else { 1356 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1357 if (ret) 1358 goto error_pcm; 1359 } 1360 1361 return 0; 1362 1363 error_pcm: 1364 if (!ssi->has_ipg_clk_name) 1365 clk_disable_unprepare(ssi->clk); 1366 1367 return ret; 1368 } 1369 1370 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) 1371 { 1372 if (!ssi->use_dma) 1373 imx_pcm_fiq_exit(pdev); 1374 if (!ssi->has_ipg_clk_name) 1375 clk_disable_unprepare(ssi->clk); 1376 } 1377 1378 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) 1379 { 1380 struct device *dev = ssi->dev; 1381 struct device_node *np = dev->of_node; 1382 const struct of_device_id *of_id; 1383 const char *p, *sprop; 1384 const __be32 *iprop; 1385 u32 dmas[4]; 1386 int ret; 1387 1388 of_id = of_match_device(fsl_ssi_ids, dev); 1389 if (!of_id || !of_id->data) 1390 return -EINVAL; 1391 1392 ssi->soc = of_id->data; 1393 1394 ret = of_property_match_string(np, "clock-names", "ipg"); 1395 /* Get error code if not found */ 1396 ssi->has_ipg_clk_name = ret >= 0; 1397 1398 /* Check if being used in AC97 mode */ 1399 sprop = of_get_property(np, "fsl,mode", NULL); 1400 if (sprop && !strcmp(sprop, "ac97-slave")) { 1401 ssi->dai_fmt = FSLSSI_AC97_DAIFMT; 1402 1403 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx); 1404 if (ret) { 1405 dev_err(dev, "failed to get SSI index property\n"); 1406 return -EINVAL; 1407 } 1408 strcpy(ssi->card_name, "ac97-codec"); 1409 } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1410 /* 1411 * In synchronous mode, STCK and STFS ports are used by RX 1412 * as well. So the software should limit the sample rates, 1413 * sample bits and channels to be symmetric. 1414 * 1415 * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs 1416 * in the SSI synchronous mode however it does not have to 1417 * limit symmetric sample rates and sample bits. 1418 */ 1419 ssi->synchronous = true; 1420 } 1421 1422 /* Select DMA or FIQ */ 1423 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); 1424 1425 /* Fetch FIFO depth; Set to 8 for older DT without this property */ 1426 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1427 if (iprop) 1428 ssi->fifo_depth = be32_to_cpup(iprop); 1429 else 1430 ssi->fifo_depth = 8; 1431 1432 /* Use dual FIFO mode depending on the support from SDMA script */ 1433 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1434 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) 1435 ssi->use_dual_fifo = true; 1436 1437 /* 1438 * Backward compatible for older bindings by manually triggering the 1439 * machine driver's probe(). Use /compatible property, including the 1440 * address of CPU DAI driver structure, as the name of machine driver 1441 * 1442 * If card_name is set by AC97 earlier, bypass here since it uses a 1443 * different name to register the device. 1444 */ 1445 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) { 1446 struct device_node *root = of_find_node_by_path("/"); 1447 1448 sprop = of_get_property(root, "compatible", NULL); 1449 of_node_put(root); 1450 /* Strip "fsl," in the compatible name if applicable */ 1451 p = strrchr(sprop, ','); 1452 if (p) 1453 sprop = p + 1; 1454 snprintf(ssi->card_name, sizeof(ssi->card_name), 1455 "snd-soc-%s", sprop); 1456 make_lowercase(ssi->card_name); 1457 ssi->card_idx = 0; 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int fsl_ssi_probe(struct platform_device *pdev) 1464 { 1465 struct regmap_config regconfig = fsl_ssi_regconfig; 1466 struct device *dev = &pdev->dev; 1467 struct fsl_ssi *ssi; 1468 struct resource *res; 1469 void __iomem *iomem; 1470 int ret = 0; 1471 1472 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1473 if (!ssi) 1474 return -ENOMEM; 1475 1476 ssi->dev = dev; 1477 1478 /* Probe from DT */ 1479 ret = fsl_ssi_probe_from_dt(ssi); 1480 if (ret) 1481 return ret; 1482 1483 if (fsl_ssi_is_ac97(ssi)) { 1484 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, 1485 sizeof(fsl_ssi_ac97_dai)); 1486 fsl_ac97_data = ssi; 1487 } else { 1488 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, 1489 sizeof(fsl_ssi_dai_template)); 1490 } 1491 ssi->cpu_dai_drv.name = dev_name(dev); 1492 1493 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1494 iomem = devm_ioremap_resource(dev, res); 1495 if (IS_ERR(iomem)) 1496 return PTR_ERR(iomem); 1497 ssi->ssi_phys = res->start; 1498 1499 if (ssi->soc->imx21regs) { 1500 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ 1501 regconfig.max_register = REG_SSI_SRMSK; 1502 regconfig.num_reg_defaults_raw = 1503 REG_SSI_SRMSK / sizeof(uint32_t) + 1; 1504 } 1505 1506 if (ssi->has_ipg_clk_name) 1507 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, 1508 ®config); 1509 else 1510 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); 1511 if (IS_ERR(ssi->regs)) { 1512 dev_err(dev, "failed to init register map\n"); 1513 return PTR_ERR(ssi->regs); 1514 } 1515 1516 ssi->irq = platform_get_irq(pdev, 0); 1517 if (ssi->irq < 0) 1518 return ssi->irq; 1519 1520 /* Set software limitations for synchronous mode except AC97 */ 1521 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) { 1522 ssi->cpu_dai_drv.symmetric_rates = 1; 1523 ssi->cpu_dai_drv.symmetric_channels = 1; 1524 ssi->cpu_dai_drv.symmetric_samplebits = 1; 1525 } 1526 1527 /* 1528 * Configure TX and RX DMA watermarks -- when to send a DMA request 1529 * 1530 * Values should be tested to avoid FIFO under/over run. Set maxburst 1531 * to fifo_watermark to maxiumize DMA transaction to reduce overhead. 1532 */ 1533 switch (ssi->fifo_depth) { 1534 case 15: 1535 /* 1536 * Set to 8 as a balanced configuration -- When TX FIFO has 8 1537 * empty slots, send a DMA request to fill these 8 slots. The 1538 * remaining 7 slots should be able to allow DMA to finish the 1539 * transaction before TX FIFO underruns; Same applies to RX. 1540 * 1541 * Tested with cases running at 48kHz @ 16 bits x 16 channels 1542 */ 1543 ssi->fifo_watermark = 8; 1544 ssi->dma_maxburst = 8; 1545 break; 1546 case 8: 1547 default: 1548 /* Safely use old watermark configurations for older chips */ 1549 ssi->fifo_watermark = ssi->fifo_depth - 2; 1550 ssi->dma_maxburst = ssi->fifo_depth - 2; 1551 break; 1552 } 1553 1554 dev_set_drvdata(dev, ssi); 1555 1556 if (ssi->soc->imx) { 1557 ret = fsl_ssi_imx_probe(pdev, ssi, iomem); 1558 if (ret) 1559 return ret; 1560 } 1561 1562 if (fsl_ssi_is_ac97(ssi)) { 1563 mutex_init(&ssi->ac97_reg_lock); 1564 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1565 if (ret) { 1566 dev_err(dev, "failed to set AC'97 ops\n"); 1567 goto error_ac97_ops; 1568 } 1569 } 1570 1571 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, 1572 &ssi->cpu_dai_drv, 1); 1573 if (ret) { 1574 dev_err(dev, "failed to register DAI: %d\n", ret); 1575 goto error_asoc_register; 1576 } 1577 1578 if (ssi->use_dma) { 1579 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, 1580 dev_name(dev), ssi); 1581 if (ret < 0) { 1582 dev_err(dev, "failed to claim irq %u\n", ssi->irq); 1583 goto error_asoc_register; 1584 } 1585 } 1586 1587 fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); 1588 1589 /* Initially configures SSI registers */ 1590 fsl_ssi_hw_init(ssi); 1591 1592 /* Register a platform device for older bindings or AC97 */ 1593 if (ssi->card_name[0]) { 1594 struct device *parent = dev; 1595 /* 1596 * Do not set SSI dev as the parent of AC97 CODEC device since 1597 * it does not have a DT node. Otherwise ASoC core will assume 1598 * CODEC has the same DT node as the SSI, so it may bypass the 1599 * dai_probe() of SSI and then cause NULL DMA data pointers. 1600 */ 1601 if (fsl_ssi_is_ac97(ssi)) 1602 parent = NULL; 1603 1604 ssi->card_pdev = platform_device_register_data(parent, 1605 ssi->card_name, ssi->card_idx, NULL, 0); 1606 if (IS_ERR(ssi->card_pdev)) { 1607 ret = PTR_ERR(ssi->card_pdev); 1608 dev_err(dev, "failed to register %s: %d\n", 1609 ssi->card_name, ret); 1610 goto error_sound_card; 1611 } 1612 } 1613 1614 return 0; 1615 1616 error_sound_card: 1617 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1618 error_asoc_register: 1619 if (fsl_ssi_is_ac97(ssi)) 1620 snd_soc_set_ac97_ops(NULL); 1621 error_ac97_ops: 1622 if (fsl_ssi_is_ac97(ssi)) 1623 mutex_destroy(&ssi->ac97_reg_lock); 1624 1625 if (ssi->soc->imx) 1626 fsl_ssi_imx_clean(pdev, ssi); 1627 1628 return ret; 1629 } 1630 1631 static int fsl_ssi_remove(struct platform_device *pdev) 1632 { 1633 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); 1634 1635 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1636 1637 if (ssi->card_pdev) 1638 platform_device_unregister(ssi->card_pdev); 1639 1640 /* Clean up SSI registers */ 1641 fsl_ssi_hw_clean(ssi); 1642 1643 if (ssi->soc->imx) 1644 fsl_ssi_imx_clean(pdev, ssi); 1645 1646 if (fsl_ssi_is_ac97(ssi)) { 1647 snd_soc_set_ac97_ops(NULL); 1648 mutex_destroy(&ssi->ac97_reg_lock); 1649 } 1650 1651 return 0; 1652 } 1653 1654 #ifdef CONFIG_PM_SLEEP 1655 static int fsl_ssi_suspend(struct device *dev) 1656 { 1657 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1658 struct regmap *regs = ssi->regs; 1659 1660 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); 1661 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); 1662 1663 regcache_cache_only(regs, true); 1664 regcache_mark_dirty(regs); 1665 1666 return 0; 1667 } 1668 1669 static int fsl_ssi_resume(struct device *dev) 1670 { 1671 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1672 struct regmap *regs = ssi->regs; 1673 1674 regcache_cache_only(regs, false); 1675 1676 regmap_update_bits(regs, REG_SSI_SFCSR, 1677 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | 1678 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, 1679 ssi->regcache_sfcsr); 1680 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); 1681 1682 return regcache_sync(regs); 1683 } 1684 #endif /* CONFIG_PM_SLEEP */ 1685 1686 static const struct dev_pm_ops fsl_ssi_pm = { 1687 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1688 }; 1689 1690 static struct platform_driver fsl_ssi_driver = { 1691 .driver = { 1692 .name = "fsl-ssi-dai", 1693 .of_match_table = fsl_ssi_ids, 1694 .pm = &fsl_ssi_pm, 1695 }, 1696 .probe = fsl_ssi_probe, 1697 .remove = fsl_ssi_remove, 1698 }; 1699 1700 module_platform_driver(fsl_ssi_driver); 1701 1702 MODULE_ALIAS("platform:fsl-ssi-dai"); 1703 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1704 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1705 MODULE_LICENSE("GPL v2"); 1706