1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/device.h> 39 #include <linux/delay.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/of.h> 43 #include <linux/of_address.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_platform.h> 46 47 #include <sound/core.h> 48 #include <sound/pcm.h> 49 #include <sound/pcm_params.h> 50 #include <sound/initval.h> 51 #include <sound/soc.h> 52 #include <sound/dmaengine_pcm.h> 53 54 #include "fsl_ssi.h" 55 #include "imx-pcm.h" 56 57 /** 58 * FSLSSI_I2S_RATES: sample rates supported by the I2S 59 * 60 * This driver currently only supports the SSI running in I2S slave mode, 61 * which means the codec determines the sample rate. Therefore, we tell 62 * ALSA that we support all rates and let the codec driver decide what rates 63 * are really supported. 64 */ 65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS 66 67 /** 68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 69 * 70 * The SSI has a limitation in that the samples must be in the same byte 71 * order as the host CPU. This is because when multiple bytes are written 72 * to the STX register, the bytes and bits must be written in the same 73 * order. The STX is a shift register, so all the bits need to be aligned 74 * (bit-endianness must match byte-endianness). Processors typically write 75 * the bits within a byte in the same order that the bytes of a word are 76 * written in. So if the host CPU is big-endian, then only big-endian 77 * samples will be written to STX properly. 78 */ 79 #ifdef __BIG_ENDIAN 80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ 81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ 82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) 83 #else 84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ 85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) 87 #endif 88 89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ 90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ 91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) 92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ 93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ 94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) 95 96 enum fsl_ssi_type { 97 FSL_SSI_MCP8610, 98 FSL_SSI_MX21, 99 FSL_SSI_MX35, 100 FSL_SSI_MX51, 101 }; 102 103 struct fsl_ssi_reg_val { 104 u32 sier; 105 u32 srcr; 106 u32 stcr; 107 u32 scr; 108 }; 109 110 struct fsl_ssi_rxtx_reg_val { 111 struct fsl_ssi_reg_val rx; 112 struct fsl_ssi_reg_val tx; 113 }; 114 115 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 116 { 117 switch (reg) { 118 case CCSR_SSI_SACCEN: 119 case CCSR_SSI_SACCDIS: 120 return false; 121 default: 122 return true; 123 } 124 } 125 126 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 127 { 128 switch (reg) { 129 case CCSR_SSI_STX0: 130 case CCSR_SSI_STX1: 131 case CCSR_SSI_SRX0: 132 case CCSR_SSI_SRX1: 133 case CCSR_SSI_SISR: 134 case CCSR_SSI_SFCSR: 135 case CCSR_SSI_SACNT: 136 case CCSR_SSI_SACADD: 137 case CCSR_SSI_SACDAT: 138 case CCSR_SSI_SATAG: 139 case CCSR_SSI_SACCST: 140 case CCSR_SSI_SOR: 141 return true; 142 default: 143 return false; 144 } 145 } 146 147 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case CCSR_SSI_SRX0: 151 case CCSR_SSI_SRX1: 152 case CCSR_SSI_SISR: 153 case CCSR_SSI_SACADD: 154 case CCSR_SSI_SACDAT: 155 case CCSR_SSI_SATAG: 156 return true; 157 default: 158 return false; 159 } 160 } 161 162 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 163 { 164 switch (reg) { 165 case CCSR_SSI_SRX0: 166 case CCSR_SSI_SRX1: 167 case CCSR_SSI_SACCST: 168 return false; 169 default: 170 return true; 171 } 172 } 173 174 static const struct regmap_config fsl_ssi_regconfig = { 175 .max_register = CCSR_SSI_SACCDIS, 176 .reg_bits = 32, 177 .val_bits = 32, 178 .reg_stride = 4, 179 .val_format_endian = REGMAP_ENDIAN_NATIVE, 180 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1, 181 .readable_reg = fsl_ssi_readable_reg, 182 .volatile_reg = fsl_ssi_volatile_reg, 183 .precious_reg = fsl_ssi_precious_reg, 184 .writeable_reg = fsl_ssi_writeable_reg, 185 .cache_type = REGCACHE_FLAT, 186 }; 187 188 struct fsl_ssi_soc_data { 189 bool imx; 190 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 191 bool offline_config; 192 u32 sisr_write_mask; 193 }; 194 195 /** 196 * fsl_ssi_private: per-SSI private data 197 * 198 * @reg: Pointer to the regmap registers 199 * @irq: IRQ of this SSI 200 * @cpu_dai_drv: CPU DAI driver for this device 201 * 202 * @dai_fmt: DAI configuration this device is currently used with 203 * @i2s_mode: i2s and network mode configuration of the device. Is used to 204 * switch between normal and i2s/network mode 205 * mode depending on the number of channels 206 * @use_dma: DMA is used or FIQ with stream filter 207 * @use_dual_fifo: DMA with support for both FIFOs used 208 * @fifo_deph: Depth of the SSI FIFOs 209 * @rxtx_reg_val: Specific register settings for receive/transmit configuration 210 * 211 * @clk: SSI clock 212 * @baudclk: SSI baud clock for master mode 213 * @baudclk_streams: Active streams that are using baudclk 214 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk 215 * 216 * @dma_params_tx: DMA transmit parameters 217 * @dma_params_rx: DMA receive parameters 218 * @ssi_phys: physical address of the SSI registers 219 * 220 * @fiq_params: FIQ stream filtering parameters 221 * 222 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card 223 * 224 * @dbg_stats: Debugging statistics 225 * 226 * @soc: SoC specific data 227 * 228 * @fifo_watermark: the FIFO watermark setting. Notifies DMA when 229 * there are @fifo_watermark or fewer words in TX fifo or 230 * @fifo_watermark or more empty words in RX fifo. 231 * @dma_maxburst: max number of words to transfer in one go. So far, 232 * this is always the same as fifo_watermark. 233 */ 234 struct fsl_ssi_private { 235 struct regmap *regs; 236 int irq; 237 struct snd_soc_dai_driver cpu_dai_drv; 238 239 unsigned int dai_fmt; 240 u8 i2s_mode; 241 bool use_dma; 242 bool use_dual_fifo; 243 bool has_ipg_clk_name; 244 unsigned int fifo_depth; 245 struct fsl_ssi_rxtx_reg_val rxtx_reg_val; 246 247 struct clk *clk; 248 struct clk *baudclk; 249 unsigned int baudclk_streams; 250 unsigned int bitclk_freq; 251 252 /* regcache for volatile regs */ 253 u32 regcache_sfcsr; 254 u32 regcache_sacnt; 255 256 /* DMA params */ 257 struct snd_dmaengine_dai_dma_data dma_params_tx; 258 struct snd_dmaengine_dai_dma_data dma_params_rx; 259 dma_addr_t ssi_phys; 260 261 /* params for non-dma FIQ stream filtered mode */ 262 struct imx_pcm_fiq_params fiq_params; 263 264 /* Used when using fsl-ssi as sound-card. This is only used by ppc and 265 * should be replaced with simple-sound-card. */ 266 struct platform_device *pdev; 267 268 struct fsl_ssi_dbg dbg_stats; 269 270 const struct fsl_ssi_soc_data *soc; 271 struct device *dev; 272 273 u32 fifo_watermark; 274 u32 dma_maxburst; 275 }; 276 277 /* 278 * imx51 and later SoCs have a slightly different IP that allows the 279 * SSI configuration while the SSI unit is running. 280 * 281 * More important, it is necessary on those SoCs to configure the 282 * sperate TX/RX DMA bits just before starting the stream 283 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi 284 * sends any DMA requests to the SDMA unit, otherwise it is not defined 285 * how the SDMA unit handles the DMA request. 286 * 287 * SDMA units are present on devices starting at imx35 but the imx35 288 * reference manual states that the DMA bits should not be changed 289 * while the SSI unit is running (SSIEN). So we support the necessary 290 * online configuration of fsl-ssi starting at imx51. 291 */ 292 293 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 294 .imx = false, 295 .offline_config = true, 296 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 297 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 298 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 299 }; 300 301 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 302 .imx = true, 303 .imx21regs = true, 304 .offline_config = true, 305 .sisr_write_mask = 0, 306 }; 307 308 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 309 .imx = true, 310 .offline_config = true, 311 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | 312 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 313 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 314 }; 315 316 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 317 .imx = true, 318 .offline_config = false, 319 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | 320 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, 321 }; 322 323 static const struct of_device_id fsl_ssi_ids[] = { 324 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 325 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 326 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 327 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 328 {} 329 }; 330 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 331 332 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) 333 { 334 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 335 SND_SOC_DAIFMT_AC97; 336 } 337 338 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) 339 { 340 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 341 SND_SOC_DAIFMT_CBS_CFS; 342 } 343 344 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) 345 { 346 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 347 SND_SOC_DAIFMT_CBM_CFS; 348 } 349 /** 350 * fsl_ssi_isr: SSI interrupt handler 351 * 352 * Although it's possible to use the interrupt handler to send and receive 353 * data to/from the SSI, we use the DMA instead. Programming is more 354 * complicated, but the performance is much better. 355 * 356 * This interrupt handler is used only to gather statistics. 357 * 358 * @irq: IRQ of the SSI device 359 * @dev_id: pointer to the ssi_private structure for this SSI device 360 */ 361 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 362 { 363 struct fsl_ssi_private *ssi_private = dev_id; 364 struct regmap *regs = ssi_private->regs; 365 __be32 sisr; 366 __be32 sisr2; 367 368 /* We got an interrupt, so read the status register to see what we 369 were interrupted for. We mask it with the Interrupt Enable register 370 so that we only check for events that we're interested in. 371 */ 372 regmap_read(regs, CCSR_SSI_SISR, &sisr); 373 374 sisr2 = sisr & ssi_private->soc->sisr_write_mask; 375 /* Clear the bits that we set */ 376 if (sisr2) 377 regmap_write(regs, CCSR_SSI_SISR, sisr2); 378 379 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); 380 381 return IRQ_HANDLED; 382 } 383 384 /* 385 * Enable/Disable all rx/tx config flags at once. 386 */ 387 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, 388 bool enable) 389 { 390 struct regmap *regs = ssi_private->regs; 391 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; 392 393 if (enable) { 394 regmap_update_bits(regs, CCSR_SSI_SIER, 395 vals->rx.sier | vals->tx.sier, 396 vals->rx.sier | vals->tx.sier); 397 regmap_update_bits(regs, CCSR_SSI_SRCR, 398 vals->rx.srcr | vals->tx.srcr, 399 vals->rx.srcr | vals->tx.srcr); 400 regmap_update_bits(regs, CCSR_SSI_STCR, 401 vals->rx.stcr | vals->tx.stcr, 402 vals->rx.stcr | vals->tx.stcr); 403 } else { 404 regmap_update_bits(regs, CCSR_SSI_SRCR, 405 vals->rx.srcr | vals->tx.srcr, 0); 406 regmap_update_bits(regs, CCSR_SSI_STCR, 407 vals->rx.stcr | vals->tx.stcr, 0); 408 regmap_update_bits(regs, CCSR_SSI_SIER, 409 vals->rx.sier | vals->tx.sier, 0); 410 } 411 } 412 413 /* 414 * Clear RX or TX FIFO to remove samples from the previous 415 * stream session which may be still present in the FIFO and 416 * may introduce bad samples and/or channel slipping. 417 * 418 * Note: The SOR is not documented in recent IMX datasheet, but 419 * is described in IMX51 reference manual at section 56.3.3.15. 420 */ 421 static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private, 422 bool is_rx) 423 { 424 if (is_rx) { 425 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 426 CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR); 427 } else { 428 regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, 429 CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR); 430 } 431 } 432 433 /* 434 * Calculate the bits that have to be disabled for the current stream that is 435 * getting disabled. This keeps the bits enabled that are necessary for the 436 * second stream to work if 'stream_active' is true. 437 * 438 * Detailed calculation: 439 * These are the values that need to be active after disabling. For non-active 440 * second stream, this is 0: 441 * vals_stream * !!stream_active 442 * 443 * The following computes the overall differences between the setup for the 444 * to-disable stream and the active stream, a simple XOR: 445 * vals_disable ^ (vals_stream * !!(stream_active)) 446 * 447 * The full expression adds a mask on all values we care about 448 */ 449 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 450 ((vals_disable) & \ 451 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 452 453 /* 454 * Enable/Disable a ssi configuration. You have to pass either 455 * ssi_private->rxtx_reg_val.rx or tx as vals parameter. 456 */ 457 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, 458 struct fsl_ssi_reg_val *vals) 459 { 460 struct regmap *regs = ssi_private->regs; 461 struct fsl_ssi_reg_val *avals; 462 int nr_active_streams; 463 u32 scr_val; 464 int keep_active; 465 466 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 467 468 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + 469 !!(scr_val & CCSR_SSI_SCR_RE); 470 471 if (nr_active_streams - 1 > 0) 472 keep_active = 1; 473 else 474 keep_active = 0; 475 476 /* Find the other direction values rx or tx which we do not want to 477 * modify */ 478 if (&ssi_private->rxtx_reg_val.rx == vals) 479 avals = &ssi_private->rxtx_reg_val.tx; 480 else 481 avals = &ssi_private->rxtx_reg_val.rx; 482 483 /* If vals should be disabled, start with disabling the unit */ 484 if (!enable) { 485 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 486 keep_active); 487 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); 488 } 489 490 /* 491 * We are running on a SoC which does not support online SSI 492 * reconfiguration, so we have to enable all necessary flags at once 493 * even if we do not use them later (capture and playback configuration) 494 */ 495 if (ssi_private->soc->offline_config) { 496 if ((enable && !nr_active_streams) || 497 (!enable && !keep_active)) 498 fsl_ssi_rxtx_config(ssi_private, enable); 499 500 goto config_done; 501 } 502 503 /* 504 * Configure single direction units while the SSI unit is running 505 * (online configuration) 506 */ 507 if (enable) { 508 fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE); 509 510 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); 511 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); 512 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); 513 } else { 514 u32 sier; 515 u32 srcr; 516 u32 stcr; 517 518 /* 519 * Disabling the necessary flags for one of rx/tx while the 520 * other stream is active is a little bit more difficult. We 521 * have to disable only those flags that differ between both 522 * streams (rx XOR tx) and that are set in the stream that is 523 * disabled now. Otherwise we could alter flags of the other 524 * stream 525 */ 526 527 /* These assignments are simply vals without bits set in avals*/ 528 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 529 keep_active); 530 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 531 keep_active); 532 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 533 keep_active); 534 535 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); 536 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); 537 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); 538 } 539 540 config_done: 541 /* Enabling of subunits is done after configuration */ 542 if (enable) { 543 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { 544 /* 545 * Be sure the Tx FIFO is filled when TE is set. 546 * Otherwise, there are some chances to start the 547 * playback with some void samples inserted first, 548 * generating a channel slip. 549 * 550 * First, SSIEN must be set, to let the FIFO be filled. 551 * 552 * Notes: 553 * - Limit this fix to the DMA case until FIQ cases can 554 * be tested. 555 * - Limit the length of the busy loop to not lock the 556 * system too long, even if 1-2 loops are sufficient 557 * in general. 558 */ 559 int i; 560 int max_loop = 100; 561 regmap_update_bits(regs, CCSR_SSI_SCR, 562 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); 563 for (i = 0; i < max_loop; i++) { 564 u32 sfcsr; 565 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); 566 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) 567 break; 568 } 569 if (i == max_loop) { 570 dev_err(ssi_private->dev, 571 "Timeout waiting TX FIFO filling\n"); 572 } 573 } 574 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); 575 } 576 } 577 578 579 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) 580 { 581 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); 582 } 583 584 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) 585 { 586 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); 587 } 588 589 /* 590 * Setup rx/tx register values used to enable/disable the streams. These will 591 * be used later in fsl_ssi_config to setup the streams without the need to 592 * check for all different SSI modes. 593 */ 594 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) 595 { 596 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; 597 598 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; 599 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; 600 reg->rx.scr = 0; 601 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; 602 reg->tx.stcr = CCSR_SSI_STCR_TFEN0; 603 reg->tx.scr = 0; 604 605 if (!fsl_ssi_is_ac97(ssi_private)) { 606 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; 607 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; 608 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; 609 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; 610 } 611 612 if (ssi_private->use_dma) { 613 reg->rx.sier |= CCSR_SSI_SIER_RDMAE; 614 reg->tx.sier |= CCSR_SSI_SIER_TDMAE; 615 } else { 616 reg->rx.sier |= CCSR_SSI_SIER_RIE; 617 reg->tx.sier |= CCSR_SSI_SIER_TIE; 618 } 619 620 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; 621 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; 622 } 623 624 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) 625 { 626 struct regmap *regs = ssi_private->regs; 627 628 /* 629 * Setup the clock control register 630 */ 631 regmap_write(regs, CCSR_SSI_STCCR, 632 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 633 regmap_write(regs, CCSR_SSI_SRCCR, 634 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); 635 636 /* 637 * Enable AC97 mode and startup the SSI 638 */ 639 regmap_write(regs, CCSR_SSI_SACNT, 640 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); 641 642 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 643 if (!ssi_private->soc->imx21regs) { 644 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); 645 regmap_write(regs, CCSR_SSI_SACCEN, 0x300); 646 } 647 648 /* 649 * Enable SSI, Transmit and Receive. AC97 has to communicate with the 650 * codec before a stream is started. 651 */ 652 regmap_update_bits(regs, CCSR_SSI_SCR, 653 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, 654 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); 655 656 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); 657 } 658 659 /** 660 * fsl_ssi_startup: create a new substream 661 * 662 * This is the first function called when a stream is opened. 663 * 664 * If this is the first stream open, then grab the IRQ and program most of 665 * the SSI registers. 666 */ 667 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 668 struct snd_soc_dai *dai) 669 { 670 struct snd_soc_pcm_runtime *rtd = substream->private_data; 671 struct fsl_ssi_private *ssi_private = 672 snd_soc_dai_get_drvdata(rtd->cpu_dai); 673 int ret; 674 675 ret = clk_prepare_enable(ssi_private->clk); 676 if (ret) 677 return ret; 678 679 /* When using dual fifo mode, it is safer to ensure an even period 680 * size. If appearing to an odd number while DMA always starts its 681 * task from fifo0, fifo1 would be neglected at the end of each 682 * period. But SSI would still access fifo1 with an invalid data. 683 */ 684 if (ssi_private->use_dual_fifo) 685 snd_pcm_hw_constraint_step(substream->runtime, 0, 686 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 687 688 return 0; 689 } 690 691 /** 692 * fsl_ssi_shutdown: shutdown the SSI 693 * 694 */ 695 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 696 struct snd_soc_dai *dai) 697 { 698 struct snd_soc_pcm_runtime *rtd = substream->private_data; 699 struct fsl_ssi_private *ssi_private = 700 snd_soc_dai_get_drvdata(rtd->cpu_dai); 701 702 clk_disable_unprepare(ssi_private->clk); 703 704 } 705 706 /** 707 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock 708 * 709 * Note: This function can be only called when using SSI as DAI master 710 * 711 * Quick instruction for parameters: 712 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels 713 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. 714 */ 715 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 716 struct snd_soc_dai *cpu_dai, 717 struct snd_pcm_hw_params *hw_params) 718 { 719 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 720 struct regmap *regs = ssi_private->regs; 721 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; 722 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 723 unsigned long clkrate, baudrate, tmprate; 724 u64 sub, savesub = 100000; 725 unsigned int freq; 726 bool baudclk_is_used; 727 728 /* Prefer the explicitly set bitclock frequency */ 729 if (ssi_private->bitclk_freq) 730 freq = ssi_private->bitclk_freq; 731 else 732 freq = params_channels(hw_params) * 32 * params_rate(hw_params); 733 734 /* Don't apply it to any non-baudclk circumstance */ 735 if (IS_ERR(ssi_private->baudclk)) 736 return -EINVAL; 737 738 /* 739 * Hardware limitation: The bclk rate must be 740 * never greater than 1/5 IPG clock rate 741 */ 742 if (freq * 5 > clk_get_rate(ssi_private->clk)) { 743 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n"); 744 return -EINVAL; 745 } 746 747 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); 748 749 /* It should be already enough to divide clock by setting pm alone */ 750 psr = 0; 751 div2 = 0; 752 753 factor = (div2 + 1) * (7 * psr + 1) * 2; 754 755 for (i = 0; i < 255; i++) { 756 tmprate = freq * factor * (i + 1); 757 758 if (baudclk_is_used) 759 clkrate = clk_get_rate(ssi_private->baudclk); 760 else 761 clkrate = clk_round_rate(ssi_private->baudclk, tmprate); 762 763 clkrate /= factor; 764 afreq = clkrate / (i + 1); 765 766 if (freq == afreq) 767 sub = 0; 768 else if (freq / afreq == 1) 769 sub = freq - afreq; 770 else if (afreq / freq == 1) 771 sub = afreq - freq; 772 else 773 continue; 774 775 /* Calculate the fraction */ 776 sub *= 100000; 777 do_div(sub, freq); 778 779 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 780 baudrate = tmprate; 781 savesub = sub; 782 pm = i; 783 } 784 785 /* We are lucky */ 786 if (savesub == 0) 787 break; 788 } 789 790 /* No proper pm found if it is still remaining the initial value */ 791 if (pm == 999) { 792 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); 793 return -EINVAL; 794 } 795 796 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | 797 (psr ? CCSR_SSI_SxCCR_PSR : 0); 798 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | 799 CCSR_SSI_SxCCR_PSR; 800 801 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) 802 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); 803 else 804 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); 805 806 if (!baudclk_is_used) { 807 ret = clk_set_rate(ssi_private->baudclk, baudrate); 808 if (ret) { 809 dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); 810 return -EINVAL; 811 } 812 } 813 814 return 0; 815 } 816 817 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 818 int clk_id, unsigned int freq, int dir) 819 { 820 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 821 822 ssi_private->bitclk_freq = freq; 823 824 return 0; 825 } 826 827 /** 828 * fsl_ssi_hw_params - program the sample size 829 * 830 * Most of the SSI registers have been programmed in the startup function, 831 * but the word length must be programmed here. Unfortunately, programming 832 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can 833 * cause a problem with supporting simultaneous playback and capture. If 834 * the SSI is already playing a stream, then that stream may be temporarily 835 * stopped when you start capture. 836 * 837 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the 838 * clock master. 839 */ 840 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 841 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) 842 { 843 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 844 struct regmap *regs = ssi_private->regs; 845 unsigned int channels = params_channels(hw_params); 846 unsigned int sample_size = params_width(hw_params); 847 u32 wl = CCSR_SSI_SxCCR_WL(sample_size); 848 int ret; 849 u32 scr_val; 850 int enabled; 851 852 regmap_read(regs, CCSR_SSI_SCR, &scr_val); 853 enabled = scr_val & CCSR_SSI_SCR_SSIEN; 854 855 /* 856 * If we're in synchronous mode, and the SSI is already enabled, 857 * then STCCR is already set properly. 858 */ 859 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) 860 return 0; 861 862 if (fsl_ssi_is_i2s_master(ssi_private)) { 863 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); 864 if (ret) 865 return ret; 866 867 /* Do not enable the clock if it is already enabled */ 868 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { 869 ret = clk_prepare_enable(ssi_private->baudclk); 870 if (ret) 871 return ret; 872 873 ssi_private->baudclk_streams |= BIT(substream->stream); 874 } 875 } 876 877 if (!fsl_ssi_is_ac97(ssi_private)) { 878 u8 i2smode; 879 /* 880 * Switch to normal net mode in order to have a frame sync 881 * signal every 32 bits instead of 16 bits 882 */ 883 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) 884 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | 885 CCSR_SSI_SCR_NET; 886 else 887 i2smode = ssi_private->i2s_mode; 888 889 regmap_update_bits(regs, CCSR_SSI_SCR, 890 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, 891 channels == 1 ? 0 : i2smode); 892 } 893 894 /* 895 * FIXME: The documentation says that SxCCR[WL] should not be 896 * modified while the SSI is enabled. The only time this can 897 * happen is if we're trying to do simultaneous playback and 898 * capture in asynchronous mode. Unfortunately, I have been enable 899 * to get that to work at all on the P1022DS. Therefore, we don't 900 * bother to disable/enable the SSI when setting SxCCR[WL], because 901 * the SSI will stop anyway. Maybe one day, this will get fixed. 902 */ 903 904 /* In synchronous mode, the SSI uses STCCR for capture */ 905 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || 906 ssi_private->cpu_dai_drv.symmetric_rates) 907 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, 908 wl); 909 else 910 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, 911 wl); 912 913 return 0; 914 } 915 916 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 917 struct snd_soc_dai *cpu_dai) 918 { 919 struct snd_soc_pcm_runtime *rtd = substream->private_data; 920 struct fsl_ssi_private *ssi_private = 921 snd_soc_dai_get_drvdata(rtd->cpu_dai); 922 923 if (fsl_ssi_is_i2s_master(ssi_private) && 924 ssi_private->baudclk_streams & BIT(substream->stream)) { 925 clk_disable_unprepare(ssi_private->baudclk); 926 ssi_private->baudclk_streams &= ~BIT(substream->stream); 927 } 928 929 return 0; 930 } 931 932 static int _fsl_ssi_set_dai_fmt(struct device *dev, 933 struct fsl_ssi_private *ssi_private, 934 unsigned int fmt) 935 { 936 struct regmap *regs = ssi_private->regs; 937 u32 strcr = 0, stcr, srcr, scr, mask; 938 u8 wm; 939 940 ssi_private->dai_fmt = fmt; 941 942 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { 943 dev_err(dev, "baudclk is missing which is necessary for master mode\n"); 944 return -EINVAL; 945 } 946 947 fsl_ssi_setup_reg_vals(ssi_private); 948 949 regmap_read(regs, CCSR_SSI_SCR, &scr); 950 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); 951 scr |= CCSR_SSI_SCR_SYNC_TX_FS; 952 953 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | 954 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | 955 CCSR_SSI_STCR_TEFS; 956 regmap_read(regs, CCSR_SSI_STCR, &stcr); 957 regmap_read(regs, CCSR_SSI_SRCR, &srcr); 958 stcr &= ~mask; 959 srcr &= ~mask; 960 961 ssi_private->i2s_mode = CCSR_SSI_SCR_NET; 962 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 963 case SND_SOC_DAIFMT_I2S: 964 regmap_update_bits(regs, CCSR_SSI_STCCR, 965 CCSR_SSI_SxCCR_DC_MASK, 966 CCSR_SSI_SxCCR_DC(2)); 967 regmap_update_bits(regs, CCSR_SSI_SRCCR, 968 CCSR_SSI_SxCCR_DC_MASK, 969 CCSR_SSI_SxCCR_DC(2)); 970 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 971 case SND_SOC_DAIFMT_CBM_CFS: 972 case SND_SOC_DAIFMT_CBS_CFS: 973 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; 974 break; 975 case SND_SOC_DAIFMT_CBM_CFM: 976 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; 977 break; 978 default: 979 return -EINVAL; 980 } 981 982 /* Data on rising edge of bclk, frame low, 1clk before data */ 983 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | 984 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 985 break; 986 case SND_SOC_DAIFMT_LEFT_J: 987 /* Data on rising edge of bclk, frame high */ 988 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; 989 break; 990 case SND_SOC_DAIFMT_DSP_A: 991 /* Data on rising edge of bclk, frame high, 1clk before data */ 992 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 993 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; 994 break; 995 case SND_SOC_DAIFMT_DSP_B: 996 /* Data on rising edge of bclk, frame high */ 997 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | 998 CCSR_SSI_STCR_TXBIT0; 999 break; 1000 case SND_SOC_DAIFMT_AC97: 1001 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; 1002 break; 1003 default: 1004 return -EINVAL; 1005 } 1006 scr |= ssi_private->i2s_mode; 1007 1008 /* DAI clock inversion */ 1009 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1010 case SND_SOC_DAIFMT_NB_NF: 1011 /* Nothing to do for both normal cases */ 1012 break; 1013 case SND_SOC_DAIFMT_IB_NF: 1014 /* Invert bit clock */ 1015 strcr ^= CCSR_SSI_STCR_TSCKP; 1016 break; 1017 case SND_SOC_DAIFMT_NB_IF: 1018 /* Invert frame clock */ 1019 strcr ^= CCSR_SSI_STCR_TFSI; 1020 break; 1021 case SND_SOC_DAIFMT_IB_IF: 1022 /* Invert both clocks */ 1023 strcr ^= CCSR_SSI_STCR_TSCKP; 1024 strcr ^= CCSR_SSI_STCR_TFSI; 1025 break; 1026 default: 1027 return -EINVAL; 1028 } 1029 1030 /* DAI clock master masks */ 1031 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1032 case SND_SOC_DAIFMT_CBS_CFS: 1033 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; 1034 scr |= CCSR_SSI_SCR_SYS_CLK_EN; 1035 break; 1036 case SND_SOC_DAIFMT_CBM_CFM: 1037 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1038 break; 1039 case SND_SOC_DAIFMT_CBM_CFS: 1040 strcr &= ~CCSR_SSI_STCR_TXDIR; 1041 strcr |= CCSR_SSI_STCR_TFDIR; 1042 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; 1043 break; 1044 default: 1045 if (!fsl_ssi_is_ac97(ssi_private)) 1046 return -EINVAL; 1047 } 1048 1049 stcr |= strcr; 1050 srcr |= strcr; 1051 1052 if (ssi_private->cpu_dai_drv.symmetric_rates 1053 || fsl_ssi_is_ac97(ssi_private)) { 1054 /* Need to clear RXDIR when using SYNC or AC97 mode */ 1055 srcr &= ~CCSR_SSI_SRCR_RXDIR; 1056 scr |= CCSR_SSI_SCR_SYN; 1057 } 1058 1059 regmap_write(regs, CCSR_SSI_STCR, stcr); 1060 regmap_write(regs, CCSR_SSI_SRCR, srcr); 1061 regmap_write(regs, CCSR_SSI_SCR, scr); 1062 1063 wm = ssi_private->fifo_watermark; 1064 1065 regmap_write(regs, CCSR_SSI_SFCSR, 1066 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | 1067 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); 1068 1069 if (ssi_private->use_dual_fifo) { 1070 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, 1071 CCSR_SSI_SRCR_RFEN1); 1072 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, 1073 CCSR_SSI_STCR_TFEN1); 1074 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, 1075 CCSR_SSI_SCR_TCH_EN); 1076 } 1077 1078 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1079 fsl_ssi_setup_ac97(ssi_private); 1080 1081 return 0; 1082 1083 } 1084 1085 /** 1086 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. 1087 */ 1088 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 1089 { 1090 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1091 1092 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); 1093 } 1094 1095 /** 1096 * fsl_ssi_set_dai_tdm_slot - set TDM slot number 1097 * 1098 * Note: This function can be only called when using SSI as DAI master 1099 */ 1100 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 1101 u32 rx_mask, int slots, int slot_width) 1102 { 1103 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); 1104 struct regmap *regs = ssi_private->regs; 1105 u32 val; 1106 1107 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1108 regmap_read(regs, CCSR_SSI_SCR, &val); 1109 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; 1110 if (val && slots < 2) { 1111 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1112 return -EINVAL; 1113 } 1114 1115 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, 1116 CCSR_SSI_SxCCR_DC(slots)); 1117 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, 1118 CCSR_SSI_SxCCR_DC(slots)); 1119 1120 /* The register SxMSKs needs SSI to provide essential clock due to 1121 * hardware design. So we here temporarily enable SSI to set them. 1122 */ 1123 regmap_read(regs, CCSR_SSI_SCR, &val); 1124 val &= CCSR_SSI_SCR_SSIEN; 1125 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, 1126 CCSR_SSI_SCR_SSIEN); 1127 1128 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); 1129 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); 1130 1131 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); 1132 1133 return 0; 1134 } 1135 1136 /** 1137 * fsl_ssi_trigger: start and stop the DMA transfer. 1138 * 1139 * This function is called by ALSA to start, stop, pause, and resume the DMA 1140 * transfer of data. 1141 * 1142 * The DMA channel is in external master start and pause mode, which 1143 * means the SSI completely controls the flow of data. 1144 */ 1145 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1146 struct snd_soc_dai *dai) 1147 { 1148 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1149 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1150 struct regmap *regs = ssi_private->regs; 1151 1152 switch (cmd) { 1153 case SNDRV_PCM_TRIGGER_START: 1154 case SNDRV_PCM_TRIGGER_RESUME: 1155 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1156 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1157 fsl_ssi_tx_config(ssi_private, true); 1158 else 1159 fsl_ssi_rx_config(ssi_private, true); 1160 break; 1161 1162 case SNDRV_PCM_TRIGGER_STOP: 1163 case SNDRV_PCM_TRIGGER_SUSPEND: 1164 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1165 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1166 fsl_ssi_tx_config(ssi_private, false); 1167 else 1168 fsl_ssi_rx_config(ssi_private, false); 1169 break; 1170 1171 default: 1172 return -EINVAL; 1173 } 1174 1175 if (fsl_ssi_is_ac97(ssi_private)) { 1176 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1177 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); 1178 else 1179 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1186 { 1187 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); 1188 1189 if (ssi_private->soc->imx && ssi_private->use_dma) { 1190 dai->playback_dma_data = &ssi_private->dma_params_tx; 1191 dai->capture_dma_data = &ssi_private->dma_params_rx; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1198 .startup = fsl_ssi_startup, 1199 .shutdown = fsl_ssi_shutdown, 1200 .hw_params = fsl_ssi_hw_params, 1201 .hw_free = fsl_ssi_hw_free, 1202 .set_fmt = fsl_ssi_set_dai_fmt, 1203 .set_sysclk = fsl_ssi_set_dai_sysclk, 1204 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1205 .trigger = fsl_ssi_trigger, 1206 }; 1207 1208 /* Template for the CPU dai driver structure */ 1209 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1210 .probe = fsl_ssi_dai_probe, 1211 .playback = { 1212 .stream_name = "CPU-Playback", 1213 .channels_min = 1, 1214 .channels_max = 32, 1215 .rates = FSLSSI_I2S_RATES, 1216 .formats = FSLSSI_I2S_FORMATS, 1217 }, 1218 .capture = { 1219 .stream_name = "CPU-Capture", 1220 .channels_min = 1, 1221 .channels_max = 32, 1222 .rates = FSLSSI_I2S_RATES, 1223 .formats = FSLSSI_I2S_FORMATS, 1224 }, 1225 .ops = &fsl_ssi_dai_ops, 1226 }; 1227 1228 static const struct snd_soc_component_driver fsl_ssi_component = { 1229 .name = "fsl-ssi", 1230 }; 1231 1232 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1233 .bus_control = true, 1234 .probe = fsl_ssi_dai_probe, 1235 .playback = { 1236 .stream_name = "AC97 Playback", 1237 .channels_min = 2, 1238 .channels_max = 2, 1239 .rates = SNDRV_PCM_RATE_8000_48000, 1240 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1241 }, 1242 .capture = { 1243 .stream_name = "AC97 Capture", 1244 .channels_min = 2, 1245 .channels_max = 2, 1246 .rates = SNDRV_PCM_RATE_48000, 1247 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1248 }, 1249 .ops = &fsl_ssi_dai_ops, 1250 }; 1251 1252 1253 static struct fsl_ssi_private *fsl_ac97_data; 1254 1255 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1256 unsigned short val) 1257 { 1258 struct regmap *regs = fsl_ac97_data->regs; 1259 unsigned int lreg; 1260 unsigned int lval; 1261 int ret; 1262 1263 if (reg > 0x7f) 1264 return; 1265 1266 ret = clk_prepare_enable(fsl_ac97_data->clk); 1267 if (ret) { 1268 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1269 ret); 1270 return; 1271 } 1272 1273 lreg = reg << 12; 1274 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1275 1276 lval = val << 4; 1277 regmap_write(regs, CCSR_SSI_SACDAT, lval); 1278 1279 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1280 CCSR_SSI_SACNT_WR); 1281 udelay(100); 1282 1283 clk_disable_unprepare(fsl_ac97_data->clk); 1284 } 1285 1286 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1287 unsigned short reg) 1288 { 1289 struct regmap *regs = fsl_ac97_data->regs; 1290 1291 unsigned short val = -1; 1292 u32 reg_val; 1293 unsigned int lreg; 1294 int ret; 1295 1296 ret = clk_prepare_enable(fsl_ac97_data->clk); 1297 if (ret) { 1298 pr_err("ac97 read clk_prepare_enable failed: %d\n", 1299 ret); 1300 return -1; 1301 } 1302 1303 lreg = (reg & 0x7f) << 12; 1304 regmap_write(regs, CCSR_SSI_SACADD, lreg); 1305 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, 1306 CCSR_SSI_SACNT_RD); 1307 1308 udelay(100); 1309 1310 regmap_read(regs, CCSR_SSI_SACDAT, ®_val); 1311 val = (reg_val >> 4) & 0xffff; 1312 1313 clk_disable_unprepare(fsl_ac97_data->clk); 1314 1315 return val; 1316 } 1317 1318 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1319 .read = fsl_ssi_ac97_read, 1320 .write = fsl_ssi_ac97_write, 1321 }; 1322 1323 /** 1324 * Make every character in a string lower-case 1325 */ 1326 static void make_lowercase(char *s) 1327 { 1328 char *p = s; 1329 char c; 1330 1331 while ((c = *p)) { 1332 if ((c >= 'A') && (c <= 'Z')) 1333 *p = c + ('a' - 'A'); 1334 p++; 1335 } 1336 } 1337 1338 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1339 struct fsl_ssi_private *ssi_private, void __iomem *iomem) 1340 { 1341 struct device_node *np = pdev->dev.of_node; 1342 u32 dmas[4]; 1343 int ret; 1344 1345 if (ssi_private->has_ipg_clk_name) 1346 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); 1347 else 1348 ssi_private->clk = devm_clk_get(&pdev->dev, NULL); 1349 if (IS_ERR(ssi_private->clk)) { 1350 ret = PTR_ERR(ssi_private->clk); 1351 dev_err(&pdev->dev, "could not get clock: %d\n", ret); 1352 return ret; 1353 } 1354 1355 if (!ssi_private->has_ipg_clk_name) { 1356 ret = clk_prepare_enable(ssi_private->clk); 1357 if (ret) { 1358 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); 1359 return ret; 1360 } 1361 } 1362 1363 /* For those SLAVE implementations, we ignore non-baudclk cases 1364 * and, instead, abandon MASTER mode that needs baud clock. 1365 */ 1366 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); 1367 if (IS_ERR(ssi_private->baudclk)) 1368 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", 1369 PTR_ERR(ssi_private->baudclk)); 1370 1371 ssi_private->dma_params_tx.maxburst = ssi_private->dma_maxburst; 1372 ssi_private->dma_params_rx.maxburst = ssi_private->dma_maxburst; 1373 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; 1374 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; 1375 1376 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1377 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1378 ssi_private->use_dual_fifo = true; 1379 /* When using dual fifo mode, we need to keep watermark 1380 * as even numbers due to dma script limitation. 1381 */ 1382 ssi_private->dma_params_tx.maxburst &= ~0x1; 1383 ssi_private->dma_params_rx.maxburst &= ~0x1; 1384 } 1385 1386 if (!ssi_private->use_dma) { 1387 1388 /* 1389 * Some boards use an incompatible codec. To get it 1390 * working, we are using imx-fiq-pcm-audio, that 1391 * can handle those codecs. DMA is not possible in this 1392 * situation. 1393 */ 1394 1395 ssi_private->fiq_params.irq = ssi_private->irq; 1396 ssi_private->fiq_params.base = iomem; 1397 ssi_private->fiq_params.dma_params_rx = 1398 &ssi_private->dma_params_rx; 1399 ssi_private->fiq_params.dma_params_tx = 1400 &ssi_private->dma_params_tx; 1401 1402 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); 1403 if (ret) 1404 goto error_pcm; 1405 } else { 1406 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1407 if (ret) 1408 goto error_pcm; 1409 } 1410 1411 return 0; 1412 1413 error_pcm: 1414 1415 if (!ssi_private->has_ipg_clk_name) 1416 clk_disable_unprepare(ssi_private->clk); 1417 return ret; 1418 } 1419 1420 static void fsl_ssi_imx_clean(struct platform_device *pdev, 1421 struct fsl_ssi_private *ssi_private) 1422 { 1423 if (!ssi_private->use_dma) 1424 imx_pcm_fiq_exit(pdev); 1425 if (!ssi_private->has_ipg_clk_name) 1426 clk_disable_unprepare(ssi_private->clk); 1427 } 1428 1429 static int fsl_ssi_probe(struct platform_device *pdev) 1430 { 1431 struct fsl_ssi_private *ssi_private; 1432 int ret = 0; 1433 struct device_node *np = pdev->dev.of_node; 1434 const struct of_device_id *of_id; 1435 const char *p, *sprop; 1436 const uint32_t *iprop; 1437 struct resource *res; 1438 void __iomem *iomem; 1439 char name[64]; 1440 struct regmap_config regconfig = fsl_ssi_regconfig; 1441 1442 of_id = of_match_device(fsl_ssi_ids, &pdev->dev); 1443 if (!of_id || !of_id->data) 1444 return -EINVAL; 1445 1446 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), 1447 GFP_KERNEL); 1448 if (!ssi_private) { 1449 dev_err(&pdev->dev, "could not allocate DAI object\n"); 1450 return -ENOMEM; 1451 } 1452 1453 ssi_private->soc = of_id->data; 1454 ssi_private->dev = &pdev->dev; 1455 1456 sprop = of_get_property(np, "fsl,mode", NULL); 1457 if (sprop) { 1458 if (!strcmp(sprop, "ac97-slave")) 1459 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; 1460 } 1461 1462 ssi_private->use_dma = !of_property_read_bool(np, 1463 "fsl,fiq-stream-filter"); 1464 1465 if (fsl_ssi_is_ac97(ssi_private)) { 1466 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, 1467 sizeof(fsl_ssi_ac97_dai)); 1468 1469 fsl_ac97_data = ssi_private; 1470 1471 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1472 if (ret) { 1473 dev_err(&pdev->dev, "could not set AC'97 ops\n"); 1474 return ret; 1475 } 1476 } else { 1477 /* Initialize this copy of the CPU DAI driver structure */ 1478 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, 1479 sizeof(fsl_ssi_dai_template)); 1480 } 1481 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); 1482 1483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1484 iomem = devm_ioremap_resource(&pdev->dev, res); 1485 if (IS_ERR(iomem)) 1486 return PTR_ERR(iomem); 1487 ssi_private->ssi_phys = res->start; 1488 1489 if (ssi_private->soc->imx21regs) { 1490 /* 1491 * According to datasheet imx21-class SSI 1492 * don't have SACC{ST,EN,DIS} regs. 1493 */ 1494 regconfig.max_register = CCSR_SSI_SRMSK; 1495 regconfig.num_reg_defaults_raw = 1496 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1; 1497 } 1498 1499 ret = of_property_match_string(np, "clock-names", "ipg"); 1500 if (ret < 0) { 1501 ssi_private->has_ipg_clk_name = false; 1502 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, 1503 ®config); 1504 } else { 1505 ssi_private->has_ipg_clk_name = true; 1506 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, 1507 "ipg", iomem, ®config); 1508 } 1509 if (IS_ERR(ssi_private->regs)) { 1510 dev_err(&pdev->dev, "Failed to init register map\n"); 1511 return PTR_ERR(ssi_private->regs); 1512 } 1513 1514 ssi_private->irq = platform_get_irq(pdev, 0); 1515 if (ssi_private->irq < 0) { 1516 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1517 return ssi_private->irq; 1518 } 1519 1520 /* Are the RX and the TX clocks locked? */ 1521 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1522 if (!fsl_ssi_is_ac97(ssi_private)) 1523 ssi_private->cpu_dai_drv.symmetric_rates = 1; 1524 1525 ssi_private->cpu_dai_drv.symmetric_channels = 1; 1526 ssi_private->cpu_dai_drv.symmetric_samplebits = 1; 1527 } 1528 1529 /* Determine the FIFO depth. */ 1530 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1531 if (iprop) 1532 ssi_private->fifo_depth = be32_to_cpup(iprop); 1533 else 1534 /* Older 8610 DTs didn't have the fifo-depth property */ 1535 ssi_private->fifo_depth = 8; 1536 1537 /* 1538 * Set the watermark for transmit FIFO 0 and receive FIFO 0. We don't 1539 * use FIFO 1 but set the watermark appropriately nontheless. 1540 * We program the transmit water to signal a DMA transfer 1541 * if there are N elements left in the FIFO. For chips with 15-deep 1542 * FIFOs, set watermark to 8. This allows the SSI to operate at a 1543 * high data rate without channel slipping. Behavior is unchanged 1544 * for the older chips with a fifo depth of only 8. A value of 4 1545 * might be appropriate for the older chips, but is left at 1546 * fifo_depth-2 until sombody has a chance to test. 1547 * 1548 * We set the watermark on the same level as the DMA burstsize. For 1549 * fiq it is probably better to use the biggest possible watermark 1550 * size. 1551 */ 1552 switch (ssi_private->fifo_depth) { 1553 case 15: 1554 /* 1555 * 2 samples is not enough when running at high data 1556 * rates (like 48kHz @ 16 bits/channel, 16 channels) 1557 * 8 seems to split things evenly and leave enough time 1558 * for the DMA to fill the FIFO before it's over/under 1559 * run. 1560 */ 1561 ssi_private->fifo_watermark = 8; 1562 ssi_private->dma_maxburst = 8; 1563 break; 1564 case 8: 1565 default: 1566 /* 1567 * maintain old behavior for older chips. 1568 * Keeping it the same because I don't have an older 1569 * board to test with. 1570 * I suspect this could be changed to be something to 1571 * leave some more space in the fifo. 1572 */ 1573 ssi_private->fifo_watermark = ssi_private->fifo_depth - 2; 1574 ssi_private->dma_maxburst = ssi_private->fifo_depth - 2; 1575 break; 1576 } 1577 1578 dev_set_drvdata(&pdev->dev, ssi_private); 1579 1580 if (ssi_private->soc->imx) { 1581 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); 1582 if (ret) 1583 return ret; 1584 } 1585 1586 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, 1587 &ssi_private->cpu_dai_drv, 1); 1588 if (ret) { 1589 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1590 goto error_asoc_register; 1591 } 1592 1593 if (ssi_private->use_dma) { 1594 ret = devm_request_irq(&pdev->dev, ssi_private->irq, 1595 fsl_ssi_isr, 0, dev_name(&pdev->dev), 1596 ssi_private); 1597 if (ret < 0) { 1598 dev_err(&pdev->dev, "could not claim irq %u\n", 1599 ssi_private->irq); 1600 goto error_asoc_register; 1601 } 1602 } 1603 1604 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); 1605 if (ret) 1606 goto error_asoc_register; 1607 1608 /* 1609 * If codec-handle property is missing from SSI node, we assume 1610 * that the machine driver uses new binding which does not require 1611 * SSI driver to trigger machine driver's probe. 1612 */ 1613 if (!of_get_property(np, "codec-handle", NULL)) 1614 goto done; 1615 1616 /* Trigger the machine driver's probe function. The platform driver 1617 * name of the machine driver is taken from /compatible property of the 1618 * device tree. We also pass the address of the CPU DAI driver 1619 * structure. 1620 */ 1621 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1622 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1623 p = strrchr(sprop, ','); 1624 if (p) 1625 sprop = p + 1; 1626 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1627 make_lowercase(name); 1628 1629 ssi_private->pdev = 1630 platform_device_register_data(&pdev->dev, name, 0, NULL, 0); 1631 if (IS_ERR(ssi_private->pdev)) { 1632 ret = PTR_ERR(ssi_private->pdev); 1633 dev_err(&pdev->dev, "failed to register platform: %d\n", ret); 1634 goto error_sound_card; 1635 } 1636 1637 done: 1638 if (ssi_private->dai_fmt) 1639 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, 1640 ssi_private->dai_fmt); 1641 1642 if (fsl_ssi_is_ac97(ssi_private)) { 1643 u32 ssi_idx; 1644 1645 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1646 if (ret) { 1647 dev_err(&pdev->dev, "cannot get SSI index property\n"); 1648 goto error_sound_card; 1649 } 1650 1651 ssi_private->pdev = 1652 platform_device_register_data(NULL, 1653 "ac97-codec", ssi_idx, NULL, 0); 1654 if (IS_ERR(ssi_private->pdev)) { 1655 ret = PTR_ERR(ssi_private->pdev); 1656 dev_err(&pdev->dev, 1657 "failed to register AC97 codec platform: %d\n", 1658 ret); 1659 goto error_sound_card; 1660 } 1661 } 1662 1663 return 0; 1664 1665 error_sound_card: 1666 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1667 1668 error_asoc_register: 1669 if (ssi_private->soc->imx) 1670 fsl_ssi_imx_clean(pdev, ssi_private); 1671 1672 return ret; 1673 } 1674 1675 static int fsl_ssi_remove(struct platform_device *pdev) 1676 { 1677 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); 1678 1679 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); 1680 1681 if (ssi_private->pdev) 1682 platform_device_unregister(ssi_private->pdev); 1683 1684 if (ssi_private->soc->imx) 1685 fsl_ssi_imx_clean(pdev, ssi_private); 1686 1687 if (fsl_ssi_is_ac97(ssi_private)) 1688 snd_soc_set_ac97_ops(NULL); 1689 1690 return 0; 1691 } 1692 1693 #ifdef CONFIG_PM_SLEEP 1694 static int fsl_ssi_suspend(struct device *dev) 1695 { 1696 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1697 struct regmap *regs = ssi_private->regs; 1698 1699 regmap_read(regs, CCSR_SSI_SFCSR, 1700 &ssi_private->regcache_sfcsr); 1701 regmap_read(regs, CCSR_SSI_SACNT, 1702 &ssi_private->regcache_sacnt); 1703 1704 regcache_cache_only(regs, true); 1705 regcache_mark_dirty(regs); 1706 1707 return 0; 1708 } 1709 1710 static int fsl_ssi_resume(struct device *dev) 1711 { 1712 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); 1713 struct regmap *regs = ssi_private->regs; 1714 1715 regcache_cache_only(regs, false); 1716 1717 regmap_update_bits(regs, CCSR_SSI_SFCSR, 1718 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | 1719 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, 1720 ssi_private->regcache_sfcsr); 1721 regmap_write(regs, CCSR_SSI_SACNT, 1722 ssi_private->regcache_sacnt); 1723 1724 return regcache_sync(regs); 1725 } 1726 #endif /* CONFIG_PM_SLEEP */ 1727 1728 static const struct dev_pm_ops fsl_ssi_pm = { 1729 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1730 }; 1731 1732 static struct platform_driver fsl_ssi_driver = { 1733 .driver = { 1734 .name = "fsl-ssi-dai", 1735 .of_match_table = fsl_ssi_ids, 1736 .pm = &fsl_ssi_pm, 1737 }, 1738 .probe = fsl_ssi_probe, 1739 .remove = fsl_ssi_remove, 1740 }; 1741 1742 module_platform_driver(fsl_ssi_driver); 1743 1744 MODULE_ALIAS("platform:fsl-ssi-dai"); 1745 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1746 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1747 MODULE_LICENSE("GPL v2"); 1748