1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Author: Timur Tabi <timur@freescale.com> 6 // 7 // Copyright 2007-2010 Freescale Semiconductor, Inc. 8 // 9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards: 10 // 11 // The i.MX SSI core has some nasty limitations in AC97 mode. While most 12 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only 13 // one FIFO which combines all valid receive slots. We cannot even select 14 // which slots we want to receive. The WM9712 with which this driver 15 // was developed with always sends GPIO status data in slot 12 which 16 // we receive in our (PCM-) data stream. The only chance we have is to 17 // manually skip this data in the FIQ handler. With sampling rates different 18 // from 48000Hz not every frame has valid receive data, so the ratio 19 // between pcm data and GPIO status data changes. Our FIQ handler is not 20 // able to handle this, hence this driver only works with 48000Hz sampling 21 // rate. 22 // Reading and writing AC97 registers is another challenge. The core 23 // provides us status bits when the read register is updated with *another* 24 // value. When we read the same register two times (and the register still 25 // contains the same value) these status bits are not set. We work 26 // around this by not polling these bits but only wait a fixed delay. 27 28 #include <linux/init.h> 29 #include <linux/io.h> 30 #include <linux/module.h> 31 #include <linux/interrupt.h> 32 #include <linux/clk.h> 33 #include <linux/ctype.h> 34 #include <linux/device.h> 35 #include <linux/delay.h> 36 #include <linux/mutex.h> 37 #include <linux/slab.h> 38 #include <linux/spinlock.h> 39 #include <linux/of.h> 40 #include <linux/of_address.h> 41 #include <linux/of_irq.h> 42 #include <linux/of_platform.h> 43 44 #include <sound/core.h> 45 #include <sound/pcm.h> 46 #include <sound/pcm_params.h> 47 #include <sound/initval.h> 48 #include <sound/soc.h> 49 #include <sound/dmaengine_pcm.h> 50 51 #include "fsl_ssi.h" 52 #include "imx-pcm.h" 53 54 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ 55 #define RX 0 56 #define TX 1 57 58 /** 59 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 60 * 61 * The SSI has a limitation in that the samples must be in the same byte 62 * order as the host CPU. This is because when multiple bytes are written 63 * to the STX register, the bytes and bits must be written in the same 64 * order. The STX is a shift register, so all the bits need to be aligned 65 * (bit-endianness must match byte-endianness). Processors typically write 66 * the bits within a byte in the same order that the bytes of a word are 67 * written in. So if the host CPU is big-endian, then only big-endian 68 * samples will be written to STX properly. 69 */ 70 #ifdef __BIG_ENDIAN 71 #define FSLSSI_I2S_FORMATS \ 72 (SNDRV_PCM_FMTBIT_S8 | \ 73 SNDRV_PCM_FMTBIT_S16_BE | \ 74 SNDRV_PCM_FMTBIT_S18_3BE | \ 75 SNDRV_PCM_FMTBIT_S20_3BE | \ 76 SNDRV_PCM_FMTBIT_S24_3BE | \ 77 SNDRV_PCM_FMTBIT_S24_BE) 78 #else 79 #define FSLSSI_I2S_FORMATS \ 80 (SNDRV_PCM_FMTBIT_S8 | \ 81 SNDRV_PCM_FMTBIT_S16_LE | \ 82 SNDRV_PCM_FMTBIT_S18_3LE | \ 83 SNDRV_PCM_FMTBIT_S20_3LE | \ 84 SNDRV_PCM_FMTBIT_S24_3LE | \ 85 SNDRV_PCM_FMTBIT_S24_LE) 86 #endif 87 88 /* 89 * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: 90 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS 91 * - Also have NB_NF to mark these two clocks will not be inverted 92 */ 93 #define FSLSSI_AC97_DAIFMT \ 94 (SND_SOC_DAIFMT_AC97 | \ 95 SND_SOC_DAIFMT_CBM_CFS | \ 96 SND_SOC_DAIFMT_NB_NF) 97 98 #define FSLSSI_SIER_DBG_RX_FLAGS \ 99 (SSI_SIER_RFF0_EN | \ 100 SSI_SIER_RLS_EN | \ 101 SSI_SIER_RFS_EN | \ 102 SSI_SIER_ROE0_EN | \ 103 SSI_SIER_RFRC_EN) 104 #define FSLSSI_SIER_DBG_TX_FLAGS \ 105 (SSI_SIER_TFE0_EN | \ 106 SSI_SIER_TLS_EN | \ 107 SSI_SIER_TFS_EN | \ 108 SSI_SIER_TUE0_EN | \ 109 SSI_SIER_TFRC_EN) 110 111 enum fsl_ssi_type { 112 FSL_SSI_MCP8610, 113 FSL_SSI_MX21, 114 FSL_SSI_MX35, 115 FSL_SSI_MX51, 116 }; 117 118 struct fsl_ssi_regvals { 119 u32 sier; 120 u32 srcr; 121 u32 stcr; 122 u32 scr; 123 }; 124 125 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 126 { 127 switch (reg) { 128 case REG_SSI_SACCEN: 129 case REG_SSI_SACCDIS: 130 return false; 131 default: 132 return true; 133 } 134 } 135 136 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 137 { 138 switch (reg) { 139 case REG_SSI_STX0: 140 case REG_SSI_STX1: 141 case REG_SSI_SRX0: 142 case REG_SSI_SRX1: 143 case REG_SSI_SISR: 144 case REG_SSI_SFCSR: 145 case REG_SSI_SACNT: 146 case REG_SSI_SACADD: 147 case REG_SSI_SACDAT: 148 case REG_SSI_SATAG: 149 case REG_SSI_SACCST: 150 case REG_SSI_SOR: 151 return true; 152 default: 153 return false; 154 } 155 } 156 157 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 158 { 159 switch (reg) { 160 case REG_SSI_SRX0: 161 case REG_SSI_SRX1: 162 case REG_SSI_SISR: 163 case REG_SSI_SACADD: 164 case REG_SSI_SACDAT: 165 case REG_SSI_SATAG: 166 return true; 167 default: 168 return false; 169 } 170 } 171 172 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 173 { 174 switch (reg) { 175 case REG_SSI_SRX0: 176 case REG_SSI_SRX1: 177 case REG_SSI_SACCST: 178 return false; 179 default: 180 return true; 181 } 182 } 183 184 static const struct regmap_config fsl_ssi_regconfig = { 185 .max_register = REG_SSI_SACCDIS, 186 .reg_bits = 32, 187 .val_bits = 32, 188 .reg_stride = 4, 189 .val_format_endian = REGMAP_ENDIAN_NATIVE, 190 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, 191 .readable_reg = fsl_ssi_readable_reg, 192 .volatile_reg = fsl_ssi_volatile_reg, 193 .precious_reg = fsl_ssi_precious_reg, 194 .writeable_reg = fsl_ssi_writeable_reg, 195 .cache_type = REGCACHE_FLAT, 196 }; 197 198 struct fsl_ssi_soc_data { 199 bool imx; 200 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 201 bool offline_config; 202 u32 sisr_write_mask; 203 }; 204 205 /** 206 * struct fsl_ssi - per-SSI private data 207 * @regs: Pointer to the regmap registers 208 * @irq: IRQ of this SSI 209 * @cpu_dai_drv: CPU DAI driver for this device 210 * @dai_fmt: DAI configuration this device is currently used with 211 * @streams: Mask of current active streams: BIT(TX) and BIT(RX) 212 * @i2s_net: I2S and Network mode configurations of SCR register 213 * (this is the initial settings based on the DAI format) 214 * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK 215 * @use_dma: DMA is used or FIQ with stream filter 216 * @use_dual_fifo: DMA with support for dual FIFO mode 217 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree 218 * @fifo_depth: Depth of the SSI FIFOs 219 * @slot_width: Width of each DAI slot 220 * @slots: Number of slots 221 * @regvals: Specific RX/TX register settings 222 * @clk: Clock source to access register 223 * @baudclk: Clock source to generate bit and frame-sync clocks 224 * @baudclk_streams: Active streams that are using baudclk 225 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume 226 * @regcache_sacnt: Cache sacnt register value during suspend and resume 227 * @dma_params_tx: DMA transmit parameters 228 * @dma_params_rx: DMA receive parameters 229 * @ssi_phys: physical address of the SSI registers 230 * @fiq_params: FIQ stream filtering parameters 231 * @card_pdev: Platform_device pointer to register a sound card for PowerPC or 232 * to register a CODEC platform device for AC97 233 * @card_name: Platform_device name to register a sound card for PowerPC or 234 * to register a CODEC platform device for AC97 235 * @card_idx: The index of SSI to register a sound card for PowerPC or 236 * to register a CODEC platform device for AC97 237 * @dbg_stats: Debugging statistics 238 * @soc: SoC specific data 239 * @dev: Pointer to &pdev->dev 240 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are 241 * @fifo_watermark or fewer words in TX fifo or 242 * @fifo_watermark or more empty words in RX fifo. 243 * @dma_maxburst: Max number of words to transfer in one go. So far, 244 * this is always the same as fifo_watermark. 245 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations 246 */ 247 struct fsl_ssi { 248 struct regmap *regs; 249 int irq; 250 struct snd_soc_dai_driver cpu_dai_drv; 251 252 unsigned int dai_fmt; 253 u8 streams; 254 u8 i2s_net; 255 bool synchronous; 256 bool use_dma; 257 bool use_dual_fifo; 258 bool has_ipg_clk_name; 259 unsigned int fifo_depth; 260 unsigned int slot_width; 261 unsigned int slots; 262 struct fsl_ssi_regvals regvals[2]; 263 264 struct clk *clk; 265 struct clk *baudclk; 266 unsigned int baudclk_streams; 267 268 u32 regcache_sfcsr; 269 u32 regcache_sacnt; 270 271 struct snd_dmaengine_dai_dma_data dma_params_tx; 272 struct snd_dmaengine_dai_dma_data dma_params_rx; 273 dma_addr_t ssi_phys; 274 275 struct imx_pcm_fiq_params fiq_params; 276 277 struct platform_device *card_pdev; 278 char card_name[32]; 279 u32 card_idx; 280 281 struct fsl_ssi_dbg dbg_stats; 282 283 const struct fsl_ssi_soc_data *soc; 284 struct device *dev; 285 286 u32 fifo_watermark; 287 u32 dma_maxburst; 288 289 struct mutex ac97_reg_lock; 290 }; 291 292 /* 293 * SoC specific data 294 * 295 * Notes: 296 * 1) SSI in earlier SoCS has critical bits in control registers that 297 * cannot be changed after SSI starts running -- a software reset 298 * (set SSIEN to 0) is required to change their values. So adding 299 * an offline_config flag for these SoCs. 300 * 2) SDMA is available since imx35. However, imx35 does not support 301 * DMA bits changing when SSI is running, so set offline_config. 302 * 3) imx51 and later versions support register configurations when 303 * SSI is running (SSIEN); For these versions, DMA needs to be 304 * configured before SSI sends DMA request to avoid an undefined 305 * DMA request on the SDMA side. 306 */ 307 308 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 309 .imx = false, 310 .offline_config = true, 311 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 312 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 313 SSI_SISR_TUE0 | SSI_SISR_TUE1, 314 }; 315 316 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 317 .imx = true, 318 .imx21regs = true, 319 .offline_config = true, 320 .sisr_write_mask = 0, 321 }; 322 323 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 324 .imx = true, 325 .offline_config = true, 326 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 327 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 328 SSI_SISR_TUE0 | SSI_SISR_TUE1, 329 }; 330 331 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 332 .imx = true, 333 .offline_config = false, 334 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | 335 SSI_SISR_TUE0 | SSI_SISR_TUE1, 336 }; 337 338 static const struct of_device_id fsl_ssi_ids[] = { 339 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 340 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 341 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 342 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 343 {} 344 }; 345 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 346 347 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) 348 { 349 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 350 SND_SOC_DAIFMT_AC97; 351 } 352 353 static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi) 354 { 355 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 356 SND_SOC_DAIFMT_CBS_CFS; 357 } 358 359 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi) 360 { 361 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 362 SND_SOC_DAIFMT_CBM_CFS; 363 } 364 365 /** 366 * fsl_ssi_irq - Interrupt handler to gather states 367 * @irq: irq number 368 * @dev_id: context 369 */ 370 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 371 { 372 struct fsl_ssi *ssi = dev_id; 373 struct regmap *regs = ssi->regs; 374 u32 sisr, sisr2; 375 376 regmap_read(regs, REG_SSI_SISR, &sisr); 377 378 sisr2 = sisr & ssi->soc->sisr_write_mask; 379 /* Clear the bits that we set */ 380 if (sisr2) 381 regmap_write(regs, REG_SSI_SISR, sisr2); 382 383 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); 384 385 return IRQ_HANDLED; 386 } 387 388 /** 389 * fsl_ssi_config_enable - Set SCR, SIER, STCR and SRCR registers with 390 * cached values in regvals 391 * @ssi: SSI context 392 * @tx: direction 393 * 394 * Notes: 395 * 1) For offline_config SoCs, enable all necessary bits of both streams 396 * when 1st stream starts, even if the opposite stream will not start 397 * 2) It also clears FIFO before setting regvals; SOR is safe to set online 398 */ 399 static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) 400 { 401 struct fsl_ssi_regvals *vals = ssi->regvals; 402 int dir = tx ? TX : RX; 403 u32 sier, srcr, stcr; 404 405 /* Clear dirty data in the FIFO; It also prevents channel slipping */ 406 regmap_update_bits(ssi->regs, REG_SSI_SOR, 407 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); 408 409 /* 410 * On offline_config SoCs, SxCR and SIER are already configured when 411 * the previous stream started. So skip all SxCR and SIER settings 412 * to prevent online reconfigurations, then jump to set SCR directly 413 */ 414 if (ssi->soc->offline_config && ssi->streams) 415 goto enable_scr; 416 417 if (ssi->soc->offline_config) { 418 /* 419 * Online reconfiguration not supported, so enable all bits for 420 * both streams at once to avoid necessity of reconfigurations 421 */ 422 srcr = vals[RX].srcr | vals[TX].srcr; 423 stcr = vals[RX].stcr | vals[TX].stcr; 424 sier = vals[RX].sier | vals[TX].sier; 425 } else { 426 /* Otherwise, only set bits for the current stream */ 427 srcr = vals[dir].srcr; 428 stcr = vals[dir].stcr; 429 sier = vals[dir].sier; 430 } 431 432 /* Configure SRCR, STCR and SIER at once */ 433 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr); 434 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr); 435 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier); 436 437 enable_scr: 438 /* 439 * Start DMA before setting TE to avoid FIFO underrun 440 * which may cause a channel slip or a channel swap 441 * 442 * TODO: FIQ cases might also need this upon testing 443 */ 444 if (ssi->use_dma && tx) { 445 int try = 100; 446 u32 sfcsr; 447 448 /* Enable SSI first to send TX DMA request */ 449 regmap_update_bits(ssi->regs, REG_SSI_SCR, 450 SSI_SCR_SSIEN, SSI_SCR_SSIEN); 451 452 /* Busy wait until TX FIFO not empty -- DMA working */ 453 do { 454 regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr); 455 if (SSI_SFCSR_TFCNT0(sfcsr)) 456 break; 457 } while (--try); 458 459 /* FIFO still empty -- something might be wrong */ 460 if (!SSI_SFCSR_TFCNT0(sfcsr)) 461 dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n"); 462 } 463 /* Enable all remaining bits in SCR */ 464 regmap_update_bits(ssi->regs, REG_SSI_SCR, 465 vals[dir].scr, vals[dir].scr); 466 467 /* Log the enabled stream to the mask */ 468 ssi->streams |= BIT(dir); 469 } 470 471 /* 472 * Exclude bits that are used by the opposite stream 473 * 474 * When both streams are active, disabling some bits for the current stream 475 * might break the other stream if these bits are used by it. 476 * 477 * @vals : regvals of the current stream 478 * @avals: regvals of the opposite stream 479 * @aactive: active state of the opposite stream 480 * 481 * 1) XOR vals and avals to get the differences if the other stream is active; 482 * Otherwise, return current vals if the other stream is not active 483 * 2) AND the result of 1) with the current vals 484 */ 485 #define _ssi_xor_shared_bits(vals, avals, aactive) \ 486 ((vals) ^ ((avals) * (aactive))) 487 488 #define ssi_excl_shared_bits(vals, avals, aactive) \ 489 ((vals) & _ssi_xor_shared_bits(vals, avals, aactive)) 490 491 /** 492 * fsl_ssi_config_disable - Unset SCR, SIER, STCR and SRCR registers 493 * with cached values in regvals 494 * @ssi: SSI context 495 * @tx: direction 496 * 497 * Notes: 498 * 1) For offline_config SoCs, to avoid online reconfigurations, disable all 499 * bits of both streams at once when the last stream is abort to end 500 * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online 501 */ 502 static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) 503 { 504 struct fsl_ssi_regvals *vals, *avals; 505 u32 sier, srcr, stcr, scr; 506 int adir = tx ? RX : TX; 507 int dir = tx ? TX : RX; 508 bool aactive; 509 510 /* Check if the opposite stream is active */ 511 aactive = ssi->streams & BIT(adir); 512 513 vals = &ssi->regvals[dir]; 514 515 /* Get regvals of the opposite stream to keep opposite stream safe */ 516 avals = &ssi->regvals[adir]; 517 518 /* 519 * To keep the other stream safe, exclude shared bits between 520 * both streams, and get safe bits to disable current stream 521 */ 522 scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); 523 524 /* Disable safe bits of SCR register for the current stream */ 525 regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0); 526 527 /* Log the disabled stream to the mask */ 528 ssi->streams &= ~BIT(dir); 529 530 /* 531 * On offline_config SoCs, if the other stream is active, skip 532 * SxCR and SIER settings to prevent online reconfigurations 533 */ 534 if (ssi->soc->offline_config && aactive) 535 goto fifo_clear; 536 537 if (ssi->soc->offline_config) { 538 /* Now there is only current stream active, disable all bits */ 539 srcr = vals->srcr | avals->srcr; 540 stcr = vals->stcr | avals->stcr; 541 sier = vals->sier | avals->sier; 542 } else { 543 /* 544 * To keep the other stream safe, exclude shared bits between 545 * both streams, and get safe bits to disable current stream 546 */ 547 sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive); 548 srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive); 549 stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive); 550 } 551 552 /* Clear configurations of SRCR, STCR and SIER at once */ 553 regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0); 554 regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0); 555 regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0); 556 557 fifo_clear: 558 /* Clear remaining data in the FIFO */ 559 regmap_update_bits(ssi->regs, REG_SSI_SOR, 560 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); 561 } 562 563 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) 564 { 565 struct regmap *regs = ssi->regs; 566 567 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 568 if (!ssi->soc->imx21regs) { 569 /* Disable all channel slots */ 570 regmap_write(regs, REG_SSI_SACCDIS, 0xff); 571 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ 572 regmap_write(regs, REG_SSI_SACCEN, 0x300); 573 } 574 } 575 576 /** 577 * fsl_ssi_setup_regvals - Cache critical bits of SIER, SRCR, STCR and 578 * SCR to later set them safely 579 * @ssi: SSI context 580 */ 581 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) 582 { 583 struct fsl_ssi_regvals *vals = ssi->regvals; 584 585 vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS; 586 vals[RX].srcr = SSI_SRCR_RFEN0; 587 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; 588 vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; 589 vals[TX].stcr = SSI_STCR_TFEN0; 590 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; 591 592 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ 593 if (fsl_ssi_is_ac97(ssi)) 594 vals[RX].scr = vals[TX].scr = 0; 595 596 if (ssi->use_dual_fifo) { 597 vals[RX].srcr |= SSI_SRCR_RFEN1; 598 vals[TX].stcr |= SSI_STCR_TFEN1; 599 } 600 601 if (ssi->use_dma) { 602 vals[RX].sier |= SSI_SIER_RDMAE; 603 vals[TX].sier |= SSI_SIER_TDMAE; 604 } else { 605 vals[RX].sier |= SSI_SIER_RIE; 606 vals[TX].sier |= SSI_SIER_TIE; 607 } 608 } 609 610 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) 611 { 612 struct regmap *regs = ssi->regs; 613 614 /* Setup the clock control register */ 615 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 616 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 617 618 /* Enable AC97 mode and startup the SSI */ 619 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); 620 621 /* AC97 has to communicate with codec before starting a stream */ 622 regmap_update_bits(regs, REG_SSI_SCR, 623 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, 624 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); 625 626 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); 627 } 628 629 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 630 struct snd_soc_dai *dai) 631 { 632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 633 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 634 int ret; 635 636 ret = clk_prepare_enable(ssi->clk); 637 if (ret) 638 return ret; 639 640 /* 641 * When using dual fifo mode, it is safer to ensure an even period 642 * size. If appearing to an odd number while DMA always starts its 643 * task from fifo0, fifo1 would be neglected at the end of each 644 * period. But SSI would still access fifo1 with an invalid data. 645 */ 646 if (ssi->use_dual_fifo) 647 snd_pcm_hw_constraint_step(substream->runtime, 0, 648 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 649 650 return 0; 651 } 652 653 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 654 struct snd_soc_dai *dai) 655 { 656 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 657 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 658 659 clk_disable_unprepare(ssi->clk); 660 } 661 662 /** 663 * fsl_ssi_set_bclk - Configure Digital Audio Interface bit clock 664 * @substream: ASoC substream 665 * @dai: pointer to DAI 666 * @hw_params: pointers to hw_params 667 * 668 * Notes: This function can be only called when using SSI as DAI master 669 * 670 * Quick instruction for parameters: 671 * freq: Output BCLK frequency = samplerate * slots * slot_width 672 * (In 2-channel I2S Master mode, slot_width is fixed 32) 673 */ 674 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 675 struct snd_soc_dai *dai, 676 struct snd_pcm_hw_params *hw_params) 677 { 678 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 679 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 680 struct regmap *regs = ssi->regs; 681 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 682 unsigned long clkrate, baudrate, tmprate; 683 unsigned int channels = params_channels(hw_params); 684 unsigned int slot_width = params_width(hw_params); 685 unsigned int slots = 2; 686 u64 sub, savesub = 100000; 687 unsigned int freq; 688 bool baudclk_is_used; 689 int ret; 690 691 /* Override slots and slot_width if being specifically set... */ 692 if (ssi->slots) 693 slots = ssi->slots; 694 if (ssi->slot_width) 695 slot_width = ssi->slot_width; 696 697 /* ...but force 32 bits for stereo audio using I2S Master Mode */ 698 if (channels == 2 && 699 (ssi->i2s_net & SSI_SCR_I2S_MODE_MASK) == SSI_SCR_I2S_MODE_MASTER) 700 slot_width = 32; 701 702 /* Generate bit clock based on the slot number and slot width */ 703 freq = slots * slot_width * params_rate(hw_params); 704 705 /* Don't apply it to any non-baudclk circumstance */ 706 if (IS_ERR(ssi->baudclk)) 707 return -EINVAL; 708 709 /* 710 * Hardware limitation: The bclk rate must be 711 * never greater than 1/5 IPG clock rate 712 */ 713 if (freq * 5 > clk_get_rate(ssi->clk)) { 714 dev_err(dai->dev, "bitclk > ipgclk / 5\n"); 715 return -EINVAL; 716 } 717 718 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); 719 720 /* It should be already enough to divide clock by setting pm alone */ 721 psr = 0; 722 div2 = 0; 723 724 factor = (div2 + 1) * (7 * psr + 1) * 2; 725 726 for (i = 0; i < 255; i++) { 727 tmprate = freq * factor * (i + 1); 728 729 if (baudclk_is_used) 730 clkrate = clk_get_rate(ssi->baudclk); 731 else 732 clkrate = clk_round_rate(ssi->baudclk, tmprate); 733 734 clkrate /= factor; 735 afreq = clkrate / (i + 1); 736 737 if (freq == afreq) 738 sub = 0; 739 else if (freq / afreq == 1) 740 sub = freq - afreq; 741 else if (afreq / freq == 1) 742 sub = afreq - freq; 743 else 744 continue; 745 746 /* Calculate the fraction */ 747 sub *= 100000; 748 do_div(sub, freq); 749 750 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 751 baudrate = tmprate; 752 savesub = sub; 753 pm = i; 754 } 755 756 /* We are lucky */ 757 if (savesub == 0) 758 break; 759 } 760 761 /* No proper pm found if it is still remaining the initial value */ 762 if (pm == 999) { 763 dev_err(dai->dev, "failed to handle the required sysclk\n"); 764 return -EINVAL; 765 } 766 767 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | 768 (psr ? SSI_SxCCR_PSR : 0); 769 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; 770 771 /* STCCR is used for RX in synchronous mode */ 772 tx2 = tx || ssi->synchronous; 773 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); 774 775 if (!baudclk_is_used) { 776 ret = clk_set_rate(ssi->baudclk, baudrate); 777 if (ret) { 778 dev_err(dai->dev, "failed to set baudclk rate\n"); 779 return -EINVAL; 780 } 781 } 782 783 return 0; 784 } 785 786 /** 787 * fsl_ssi_hw_params - Configure SSI based on PCM hardware parameters 788 * @substream: ASoC substream 789 * @hw_params: pointers to hw_params 790 * @dai: pointer to DAI 791 * 792 * Notes: 793 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily 794 * disabled on offline_config SoCs. Even for online configurable SoCs 795 * running in synchronous mode (both TX and RX use STCCR), it is not 796 * safe to re-configure them when both two streams start running. 797 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the 798 * fsl_ssi_set_bclk() if SSI is the DAI clock master. 799 */ 800 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 801 struct snd_pcm_hw_params *hw_params, 802 struct snd_soc_dai *dai) 803 { 804 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 805 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 806 struct regmap *regs = ssi->regs; 807 unsigned int channels = params_channels(hw_params); 808 unsigned int sample_size = params_width(hw_params); 809 u32 wl = SSI_SxCCR_WL(sample_size); 810 int ret; 811 812 if (fsl_ssi_is_i2s_master(ssi)) { 813 ret = fsl_ssi_set_bclk(substream, dai, hw_params); 814 if (ret) 815 return ret; 816 817 /* Do not enable the clock if it is already enabled */ 818 if (!(ssi->baudclk_streams & BIT(substream->stream))) { 819 ret = clk_prepare_enable(ssi->baudclk); 820 if (ret) 821 return ret; 822 823 ssi->baudclk_streams |= BIT(substream->stream); 824 } 825 } 826 827 /* 828 * SSI is properly configured if it is enabled and running in 829 * the synchronous mode; Note that AC97 mode is an exception 830 * that should set separate configurations for STCCR and SRCCR 831 * despite running in the synchronous mode. 832 */ 833 if (ssi->streams && ssi->synchronous) 834 return 0; 835 836 if (!fsl_ssi_is_ac97(ssi)) { 837 /* 838 * Keep the ssi->i2s_net intact while having a local variable 839 * to override settings for special use cases. Otherwise, the 840 * ssi->i2s_net will lose the settings for regular use cases. 841 */ 842 u8 i2s_net = ssi->i2s_net; 843 844 /* Normal + Network mode to send 16-bit data in 32-bit frames */ 845 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) 846 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; 847 848 /* Use Normal mode to send mono data at 1st slot of 2 slots */ 849 if (channels == 1) 850 i2s_net = SSI_SCR_I2S_MODE_NORMAL; 851 852 regmap_update_bits(regs, REG_SSI_SCR, 853 SSI_SCR_I2S_NET_MASK, i2s_net); 854 } 855 856 /* In synchronous mode, the SSI uses STCCR for capture */ 857 tx2 = tx || ssi->synchronous; 858 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); 859 860 return 0; 861 } 862 863 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 864 struct snd_soc_dai *dai) 865 { 866 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 867 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 868 869 if (fsl_ssi_is_i2s_master(ssi) && 870 ssi->baudclk_streams & BIT(substream->stream)) { 871 clk_disable_unprepare(ssi->baudclk); 872 ssi->baudclk_streams &= ~BIT(substream->stream); 873 } 874 875 return 0; 876 } 877 878 static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) 879 { 880 u32 strcr = 0, scr = 0, stcr, srcr, mask; 881 882 ssi->dai_fmt = fmt; 883 884 /* Synchronize frame sync clock for TE to avoid data slipping */ 885 scr |= SSI_SCR_SYNC_TX_FS; 886 887 /* Set to default shifting settings: LSB_ALIGNED */ 888 strcr |= SSI_STCR_TXBIT0; 889 890 /* Use Network mode as default */ 891 ssi->i2s_net = SSI_SCR_NET; 892 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 893 case SND_SOC_DAIFMT_I2S: 894 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 895 case SND_SOC_DAIFMT_CBS_CFS: 896 if (IS_ERR(ssi->baudclk)) { 897 dev_err(ssi->dev, 898 "missing baudclk for master mode\n"); 899 return -EINVAL; 900 } 901 fallthrough; 902 case SND_SOC_DAIFMT_CBM_CFS: 903 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; 904 break; 905 case SND_SOC_DAIFMT_CBM_CFM: 906 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; 907 break; 908 default: 909 return -EINVAL; 910 } 911 912 regmap_update_bits(ssi->regs, REG_SSI_STCCR, 913 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 914 regmap_update_bits(ssi->regs, REG_SSI_SRCCR, 915 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 916 917 /* Data on rising edge of bclk, frame low, 1clk before data */ 918 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS; 919 break; 920 case SND_SOC_DAIFMT_LEFT_J: 921 /* Data on rising edge of bclk, frame high */ 922 strcr |= SSI_STCR_TSCKP; 923 break; 924 case SND_SOC_DAIFMT_DSP_A: 925 /* Data on rising edge of bclk, frame high, 1clk before data */ 926 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS; 927 break; 928 case SND_SOC_DAIFMT_DSP_B: 929 /* Data on rising edge of bclk, frame high */ 930 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP; 931 break; 932 case SND_SOC_DAIFMT_AC97: 933 /* Data on falling edge of bclk, frame high, 1clk before data */ 934 strcr |= SSI_STCR_TEFS; 935 break; 936 default: 937 return -EINVAL; 938 } 939 940 scr |= ssi->i2s_net; 941 942 /* DAI clock inversion */ 943 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 944 case SND_SOC_DAIFMT_NB_NF: 945 /* Nothing to do for both normal cases */ 946 break; 947 case SND_SOC_DAIFMT_IB_NF: 948 /* Invert bit clock */ 949 strcr ^= SSI_STCR_TSCKP; 950 break; 951 case SND_SOC_DAIFMT_NB_IF: 952 /* Invert frame clock */ 953 strcr ^= SSI_STCR_TFSI; 954 break; 955 case SND_SOC_DAIFMT_IB_IF: 956 /* Invert both clocks */ 957 strcr ^= SSI_STCR_TSCKP; 958 strcr ^= SSI_STCR_TFSI; 959 break; 960 default: 961 return -EINVAL; 962 } 963 964 /* DAI clock master masks */ 965 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 966 case SND_SOC_DAIFMT_CBS_CFS: 967 /* Output bit and frame sync clocks */ 968 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; 969 scr |= SSI_SCR_SYS_CLK_EN; 970 break; 971 case SND_SOC_DAIFMT_CBM_CFM: 972 /* Input bit or frame sync clocks */ 973 break; 974 case SND_SOC_DAIFMT_CBM_CFS: 975 /* Input bit clock but output frame sync clock */ 976 strcr |= SSI_STCR_TFDIR; 977 break; 978 default: 979 return -EINVAL; 980 } 981 982 stcr = strcr; 983 srcr = strcr; 984 985 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ 986 if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { 987 srcr &= ~SSI_SRCR_RXDIR; 988 scr |= SSI_SCR_SYN; 989 } 990 991 mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | 992 SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; 993 994 regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); 995 regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); 996 997 mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | 998 SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN; 999 regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); 1000 1001 return 0; 1002 } 1003 1004 /** 1005 * fsl_ssi_set_dai_fmt - Configure Digital Audio Interface (DAI) Format 1006 * @dai: pointer to DAI 1007 * @fmt: format mask 1008 */ 1009 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1010 { 1011 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1012 1013 /* AC97 configured DAIFMT earlier in the probe() */ 1014 if (fsl_ssi_is_ac97(ssi)) 1015 return 0; 1016 1017 return _fsl_ssi_set_dai_fmt(ssi, fmt); 1018 } 1019 1020 /** 1021 * fsl_ssi_set_dai_tdm_slot - Set TDM slot number and slot width 1022 * @dai: pointer to DAI 1023 * @tx_mask: mask for TX 1024 * @rx_mask: mask for RX 1025 * @slots: number of slots 1026 * @slot_width: number of bits per slot 1027 */ 1028 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 1029 u32 rx_mask, int slots, int slot_width) 1030 { 1031 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1032 struct regmap *regs = ssi->regs; 1033 u32 val; 1034 1035 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ 1036 if (slot_width & 1 || slot_width < 8 || slot_width > 24) { 1037 dev_err(dai->dev, "invalid slot width: %d\n", slot_width); 1038 return -EINVAL; 1039 } 1040 1041 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1042 if (ssi->i2s_net && slots < 2) { 1043 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1044 return -EINVAL; 1045 } 1046 1047 regmap_update_bits(regs, REG_SSI_STCCR, 1048 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1049 regmap_update_bits(regs, REG_SSI_SRCCR, 1050 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1051 1052 /* Save the SCR register value */ 1053 regmap_read(regs, REG_SSI_SCR, &val); 1054 /* Temporarily enable SSI to allow SxMSKs to be configurable */ 1055 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); 1056 1057 regmap_write(regs, REG_SSI_STMSK, ~tx_mask); 1058 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); 1059 1060 /* Restore the value of SSIEN bit */ 1061 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); 1062 1063 ssi->slot_width = slot_width; 1064 ssi->slots = slots; 1065 1066 return 0; 1067 } 1068 1069 /** 1070 * fsl_ssi_trigger - Start or stop SSI and corresponding DMA transaction. 1071 * @substream: ASoC substream 1072 * @cmd: trigger command 1073 * @dai: pointer to DAI 1074 * 1075 * The DMA channel is in external master start and pause mode, which 1076 * means the SSI completely controls the flow of data. 1077 */ 1078 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1079 struct snd_soc_dai *dai) 1080 { 1081 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 1082 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 1083 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 1084 1085 switch (cmd) { 1086 case SNDRV_PCM_TRIGGER_START: 1087 case SNDRV_PCM_TRIGGER_RESUME: 1088 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1089 /* 1090 * SACCST might be modified via AC Link by a CODEC if it sends 1091 * extra bits in their SLOTREQ requests, which'll accidentally 1092 * send valid data to slots other than normal playback slots. 1093 * 1094 * To be safe, configure SACCST right before TX starts. 1095 */ 1096 if (tx && fsl_ssi_is_ac97(ssi)) 1097 fsl_ssi_tx_ac97_saccst_setup(ssi); 1098 fsl_ssi_config_enable(ssi, tx); 1099 break; 1100 1101 case SNDRV_PCM_TRIGGER_STOP: 1102 case SNDRV_PCM_TRIGGER_SUSPEND: 1103 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1104 fsl_ssi_config_disable(ssi, tx); 1105 break; 1106 1107 default: 1108 return -EINVAL; 1109 } 1110 1111 return 0; 1112 } 1113 1114 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1115 { 1116 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1117 1118 if (ssi->soc->imx && ssi->use_dma) 1119 snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx, 1120 &ssi->dma_params_rx); 1121 1122 return 0; 1123 } 1124 1125 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1126 .startup = fsl_ssi_startup, 1127 .shutdown = fsl_ssi_shutdown, 1128 .hw_params = fsl_ssi_hw_params, 1129 .hw_free = fsl_ssi_hw_free, 1130 .set_fmt = fsl_ssi_set_dai_fmt, 1131 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1132 .trigger = fsl_ssi_trigger, 1133 }; 1134 1135 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1136 .probe = fsl_ssi_dai_probe, 1137 .playback = { 1138 .stream_name = "CPU-Playback", 1139 .channels_min = 1, 1140 .channels_max = 32, 1141 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1142 .formats = FSLSSI_I2S_FORMATS, 1143 }, 1144 .capture = { 1145 .stream_name = "CPU-Capture", 1146 .channels_min = 1, 1147 .channels_max = 32, 1148 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1149 .formats = FSLSSI_I2S_FORMATS, 1150 }, 1151 .ops = &fsl_ssi_dai_ops, 1152 }; 1153 1154 static const struct snd_soc_component_driver fsl_ssi_component = { 1155 .name = "fsl-ssi", 1156 }; 1157 1158 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1159 .symmetric_channels = 1, 1160 .probe = fsl_ssi_dai_probe, 1161 .playback = { 1162 .stream_name = "AC97 Playback", 1163 .channels_min = 2, 1164 .channels_max = 2, 1165 .rates = SNDRV_PCM_RATE_8000_48000, 1166 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, 1167 }, 1168 .capture = { 1169 .stream_name = "AC97 Capture", 1170 .channels_min = 2, 1171 .channels_max = 2, 1172 .rates = SNDRV_PCM_RATE_48000, 1173 /* 16-bit capture is broken (errata ERR003778) */ 1174 .formats = SNDRV_PCM_FMTBIT_S20, 1175 }, 1176 .ops = &fsl_ssi_dai_ops, 1177 }; 1178 1179 static struct fsl_ssi *fsl_ac97_data; 1180 1181 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1182 unsigned short val) 1183 { 1184 struct regmap *regs = fsl_ac97_data->regs; 1185 unsigned int lreg; 1186 unsigned int lval; 1187 int ret; 1188 1189 if (reg > 0x7f) 1190 return; 1191 1192 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1193 1194 ret = clk_prepare_enable(fsl_ac97_data->clk); 1195 if (ret) { 1196 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1197 ret); 1198 goto ret_unlock; 1199 } 1200 1201 lreg = reg << 12; 1202 regmap_write(regs, REG_SSI_SACADD, lreg); 1203 1204 lval = val << 4; 1205 regmap_write(regs, REG_SSI_SACDAT, lval); 1206 1207 regmap_update_bits(regs, REG_SSI_SACNT, 1208 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); 1209 udelay(100); 1210 1211 clk_disable_unprepare(fsl_ac97_data->clk); 1212 1213 ret_unlock: 1214 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1215 } 1216 1217 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1218 unsigned short reg) 1219 { 1220 struct regmap *regs = fsl_ac97_data->regs; 1221 unsigned short val = 0; 1222 u32 reg_val; 1223 unsigned int lreg; 1224 int ret; 1225 1226 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1227 1228 ret = clk_prepare_enable(fsl_ac97_data->clk); 1229 if (ret) { 1230 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); 1231 goto ret_unlock; 1232 } 1233 1234 lreg = (reg & 0x7f) << 12; 1235 regmap_write(regs, REG_SSI_SACADD, lreg); 1236 regmap_update_bits(regs, REG_SSI_SACNT, 1237 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); 1238 1239 udelay(100); 1240 1241 regmap_read(regs, REG_SSI_SACDAT, ®_val); 1242 val = (reg_val >> 4) & 0xffff; 1243 1244 clk_disable_unprepare(fsl_ac97_data->clk); 1245 1246 ret_unlock: 1247 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1248 return val; 1249 } 1250 1251 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1252 .read = fsl_ssi_ac97_read, 1253 .write = fsl_ssi_ac97_write, 1254 }; 1255 1256 /** 1257 * fsl_ssi_hw_init - Initialize SSI registers 1258 * @ssi: SSI context 1259 */ 1260 static int fsl_ssi_hw_init(struct fsl_ssi *ssi) 1261 { 1262 u32 wm = ssi->fifo_watermark; 1263 1264 /* Initialize regvals */ 1265 fsl_ssi_setup_regvals(ssi); 1266 1267 /* Set watermarks */ 1268 regmap_write(ssi->regs, REG_SSI_SFCSR, 1269 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | 1270 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); 1271 1272 /* Enable Dual FIFO mode */ 1273 if (ssi->use_dual_fifo) 1274 regmap_update_bits(ssi->regs, REG_SSI_SCR, 1275 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); 1276 1277 /* AC97 should start earlier to communicate with CODECs */ 1278 if (fsl_ssi_is_ac97(ssi)) { 1279 _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt); 1280 fsl_ssi_setup_ac97(ssi); 1281 } 1282 1283 return 0; 1284 } 1285 1286 /** 1287 * fsl_ssi_hw_clean - Clear SSI registers 1288 * @ssi: SSI context 1289 */ 1290 static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) 1291 { 1292 /* Disable registers for AC97 */ 1293 if (fsl_ssi_is_ac97(ssi)) { 1294 /* Disable TE and RE bits first */ 1295 regmap_update_bits(ssi->regs, REG_SSI_SCR, 1296 SSI_SCR_TE | SSI_SCR_RE, 0); 1297 /* Disable AC97 mode */ 1298 regmap_write(ssi->regs, REG_SSI_SACNT, 0); 1299 /* Unset WAIT bits */ 1300 regmap_write(ssi->regs, REG_SSI_SOR, 0); 1301 /* Disable SSI -- software reset */ 1302 regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0); 1303 } 1304 } 1305 1306 /* 1307 * Make every character in a string lower-case 1308 */ 1309 static void make_lowercase(char *s) 1310 { 1311 if (!s) 1312 return; 1313 for (; *s; s++) 1314 *s = tolower(*s); 1315 } 1316 1317 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1318 struct fsl_ssi *ssi, void __iomem *iomem) 1319 { 1320 struct device *dev = &pdev->dev; 1321 int ret; 1322 1323 /* Backward compatible for a DT without ipg clock name assigned */ 1324 if (ssi->has_ipg_clk_name) 1325 ssi->clk = devm_clk_get(dev, "ipg"); 1326 else 1327 ssi->clk = devm_clk_get(dev, NULL); 1328 if (IS_ERR(ssi->clk)) { 1329 ret = PTR_ERR(ssi->clk); 1330 dev_err(dev, "failed to get clock: %d\n", ret); 1331 return ret; 1332 } 1333 1334 /* Enable the clock since regmap will not handle it in this case */ 1335 if (!ssi->has_ipg_clk_name) { 1336 ret = clk_prepare_enable(ssi->clk); 1337 if (ret) { 1338 dev_err(dev, "clk_prepare_enable failed: %d\n", ret); 1339 return ret; 1340 } 1341 } 1342 1343 /* Do not error out for slave cases that live without a baud clock */ 1344 ssi->baudclk = devm_clk_get(dev, "baud"); 1345 if (IS_ERR(ssi->baudclk)) 1346 dev_dbg(dev, "failed to get baud clock: %ld\n", 1347 PTR_ERR(ssi->baudclk)); 1348 1349 ssi->dma_params_tx.maxburst = ssi->dma_maxburst; 1350 ssi->dma_params_rx.maxburst = ssi->dma_maxburst; 1351 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; 1352 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; 1353 1354 /* Use even numbers to avoid channel swap due to SDMA script design */ 1355 if (ssi->use_dual_fifo) { 1356 ssi->dma_params_tx.maxburst &= ~0x1; 1357 ssi->dma_params_rx.maxburst &= ~0x1; 1358 } 1359 1360 if (!ssi->use_dma) { 1361 /* 1362 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio 1363 * to get it working, as DMA is not possible in this situation. 1364 */ 1365 ssi->fiq_params.irq = ssi->irq; 1366 ssi->fiq_params.base = iomem; 1367 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; 1368 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; 1369 1370 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); 1371 if (ret) 1372 goto error_pcm; 1373 } else { 1374 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1375 if (ret) 1376 goto error_pcm; 1377 } 1378 1379 return 0; 1380 1381 error_pcm: 1382 if (!ssi->has_ipg_clk_name) 1383 clk_disable_unprepare(ssi->clk); 1384 1385 return ret; 1386 } 1387 1388 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) 1389 { 1390 if (!ssi->use_dma) 1391 imx_pcm_fiq_exit(pdev); 1392 if (!ssi->has_ipg_clk_name) 1393 clk_disable_unprepare(ssi->clk); 1394 } 1395 1396 static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) 1397 { 1398 struct device *dev = ssi->dev; 1399 struct device_node *np = dev->of_node; 1400 const char *p, *sprop; 1401 const __be32 *iprop; 1402 u32 dmas[4]; 1403 int ret; 1404 1405 ret = of_property_match_string(np, "clock-names", "ipg"); 1406 /* Get error code if not found */ 1407 ssi->has_ipg_clk_name = ret >= 0; 1408 1409 /* Check if being used in AC97 mode */ 1410 sprop = of_get_property(np, "fsl,mode", NULL); 1411 if (sprop && !strcmp(sprop, "ac97-slave")) { 1412 ssi->dai_fmt = FSLSSI_AC97_DAIFMT; 1413 1414 ret = of_property_read_u32(np, "cell-index", &ssi->card_idx); 1415 if (ret) { 1416 dev_err(dev, "failed to get SSI index property\n"); 1417 return -EINVAL; 1418 } 1419 strcpy(ssi->card_name, "ac97-codec"); 1420 } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1421 /* 1422 * In synchronous mode, STCK and STFS ports are used by RX 1423 * as well. So the software should limit the sample rates, 1424 * sample bits and channels to be symmetric. 1425 * 1426 * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs 1427 * in the SSI synchronous mode however it does not have to 1428 * limit symmetric sample rates and sample bits. 1429 */ 1430 ssi->synchronous = true; 1431 } 1432 1433 /* Select DMA or FIQ */ 1434 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); 1435 1436 /* Fetch FIFO depth; Set to 8 for older DT without this property */ 1437 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1438 if (iprop) 1439 ssi->fifo_depth = be32_to_cpup(iprop); 1440 else 1441 ssi->fifo_depth = 8; 1442 1443 /* Use dual FIFO mode depending on the support from SDMA script */ 1444 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1445 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) 1446 ssi->use_dual_fifo = true; 1447 1448 /* 1449 * Backward compatible for older bindings by manually triggering the 1450 * machine driver's probe(). Use /compatible property, including the 1451 * address of CPU DAI driver structure, as the name of machine driver 1452 * 1453 * If card_name is set by AC97 earlier, bypass here since it uses a 1454 * different name to register the device. 1455 */ 1456 if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) { 1457 struct device_node *root = of_find_node_by_path("/"); 1458 1459 sprop = of_get_property(root, "compatible", NULL); 1460 of_node_put(root); 1461 /* Strip "fsl," in the compatible name if applicable */ 1462 p = strrchr(sprop, ','); 1463 if (p) 1464 sprop = p + 1; 1465 snprintf(ssi->card_name, sizeof(ssi->card_name), 1466 "snd-soc-%s", sprop); 1467 make_lowercase(ssi->card_name); 1468 ssi->card_idx = 0; 1469 } 1470 1471 return 0; 1472 } 1473 1474 static int fsl_ssi_probe(struct platform_device *pdev) 1475 { 1476 struct regmap_config regconfig = fsl_ssi_regconfig; 1477 struct device *dev = &pdev->dev; 1478 struct fsl_ssi *ssi; 1479 struct resource *res; 1480 void __iomem *iomem; 1481 int ret = 0; 1482 1483 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1484 if (!ssi) 1485 return -ENOMEM; 1486 1487 ssi->dev = dev; 1488 ssi->soc = of_device_get_match_data(&pdev->dev); 1489 1490 /* Probe from DT */ 1491 ret = fsl_ssi_probe_from_dt(ssi); 1492 if (ret) 1493 return ret; 1494 1495 if (fsl_ssi_is_ac97(ssi)) { 1496 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, 1497 sizeof(fsl_ssi_ac97_dai)); 1498 fsl_ac97_data = ssi; 1499 } else { 1500 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, 1501 sizeof(fsl_ssi_dai_template)); 1502 } 1503 ssi->cpu_dai_drv.name = dev_name(dev); 1504 1505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1506 iomem = devm_ioremap_resource(dev, res); 1507 if (IS_ERR(iomem)) 1508 return PTR_ERR(iomem); 1509 ssi->ssi_phys = res->start; 1510 1511 if (ssi->soc->imx21regs) { 1512 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ 1513 regconfig.max_register = REG_SSI_SRMSK; 1514 regconfig.num_reg_defaults_raw = 1515 REG_SSI_SRMSK / sizeof(uint32_t) + 1; 1516 } 1517 1518 if (ssi->has_ipg_clk_name) 1519 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, 1520 ®config); 1521 else 1522 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); 1523 if (IS_ERR(ssi->regs)) { 1524 dev_err(dev, "failed to init register map\n"); 1525 return PTR_ERR(ssi->regs); 1526 } 1527 1528 ssi->irq = platform_get_irq(pdev, 0); 1529 if (ssi->irq < 0) 1530 return ssi->irq; 1531 1532 /* Set software limitations for synchronous mode except AC97 */ 1533 if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) { 1534 ssi->cpu_dai_drv.symmetric_rate = 1; 1535 ssi->cpu_dai_drv.symmetric_channels = 1; 1536 ssi->cpu_dai_drv.symmetric_sample_bits = 1; 1537 } 1538 1539 /* 1540 * Configure TX and RX DMA watermarks -- when to send a DMA request 1541 * 1542 * Values should be tested to avoid FIFO under/over run. Set maxburst 1543 * to fifo_watermark to maxiumize DMA transaction to reduce overhead. 1544 */ 1545 switch (ssi->fifo_depth) { 1546 case 15: 1547 /* 1548 * Set to 8 as a balanced configuration -- When TX FIFO has 8 1549 * empty slots, send a DMA request to fill these 8 slots. The 1550 * remaining 7 slots should be able to allow DMA to finish the 1551 * transaction before TX FIFO underruns; Same applies to RX. 1552 * 1553 * Tested with cases running at 48kHz @ 16 bits x 16 channels 1554 */ 1555 ssi->fifo_watermark = 8; 1556 ssi->dma_maxburst = 8; 1557 break; 1558 case 8: 1559 default: 1560 /* Safely use old watermark configurations for older chips */ 1561 ssi->fifo_watermark = ssi->fifo_depth - 2; 1562 ssi->dma_maxburst = ssi->fifo_depth - 2; 1563 break; 1564 } 1565 1566 dev_set_drvdata(dev, ssi); 1567 1568 if (ssi->soc->imx) { 1569 ret = fsl_ssi_imx_probe(pdev, ssi, iomem); 1570 if (ret) 1571 return ret; 1572 } 1573 1574 if (fsl_ssi_is_ac97(ssi)) { 1575 mutex_init(&ssi->ac97_reg_lock); 1576 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1577 if (ret) { 1578 dev_err(dev, "failed to set AC'97 ops\n"); 1579 goto error_ac97_ops; 1580 } 1581 } 1582 1583 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, 1584 &ssi->cpu_dai_drv, 1); 1585 if (ret) { 1586 dev_err(dev, "failed to register DAI: %d\n", ret); 1587 goto error_asoc_register; 1588 } 1589 1590 if (ssi->use_dma) { 1591 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, 1592 dev_name(dev), ssi); 1593 if (ret < 0) { 1594 dev_err(dev, "failed to claim irq %u\n", ssi->irq); 1595 goto error_asoc_register; 1596 } 1597 } 1598 1599 fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); 1600 1601 /* Initially configures SSI registers */ 1602 fsl_ssi_hw_init(ssi); 1603 1604 /* Register a platform device for older bindings or AC97 */ 1605 if (ssi->card_name[0]) { 1606 struct device *parent = dev; 1607 /* 1608 * Do not set SSI dev as the parent of AC97 CODEC device since 1609 * it does not have a DT node. Otherwise ASoC core will assume 1610 * CODEC has the same DT node as the SSI, so it may bypass the 1611 * dai_probe() of SSI and then cause NULL DMA data pointers. 1612 */ 1613 if (fsl_ssi_is_ac97(ssi)) 1614 parent = NULL; 1615 1616 ssi->card_pdev = platform_device_register_data(parent, 1617 ssi->card_name, ssi->card_idx, NULL, 0); 1618 if (IS_ERR(ssi->card_pdev)) { 1619 ret = PTR_ERR(ssi->card_pdev); 1620 dev_err(dev, "failed to register %s: %d\n", 1621 ssi->card_name, ret); 1622 goto error_sound_card; 1623 } 1624 } 1625 1626 return 0; 1627 1628 error_sound_card: 1629 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1630 error_asoc_register: 1631 if (fsl_ssi_is_ac97(ssi)) 1632 snd_soc_set_ac97_ops(NULL); 1633 error_ac97_ops: 1634 if (fsl_ssi_is_ac97(ssi)) 1635 mutex_destroy(&ssi->ac97_reg_lock); 1636 1637 if (ssi->soc->imx) 1638 fsl_ssi_imx_clean(pdev, ssi); 1639 1640 return ret; 1641 } 1642 1643 static int fsl_ssi_remove(struct platform_device *pdev) 1644 { 1645 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); 1646 1647 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1648 1649 if (ssi->card_pdev) 1650 platform_device_unregister(ssi->card_pdev); 1651 1652 /* Clean up SSI registers */ 1653 fsl_ssi_hw_clean(ssi); 1654 1655 if (ssi->soc->imx) 1656 fsl_ssi_imx_clean(pdev, ssi); 1657 1658 if (fsl_ssi_is_ac97(ssi)) { 1659 snd_soc_set_ac97_ops(NULL); 1660 mutex_destroy(&ssi->ac97_reg_lock); 1661 } 1662 1663 return 0; 1664 } 1665 1666 #ifdef CONFIG_PM_SLEEP 1667 static int fsl_ssi_suspend(struct device *dev) 1668 { 1669 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1670 struct regmap *regs = ssi->regs; 1671 1672 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); 1673 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); 1674 1675 regcache_cache_only(regs, true); 1676 regcache_mark_dirty(regs); 1677 1678 return 0; 1679 } 1680 1681 static int fsl_ssi_resume(struct device *dev) 1682 { 1683 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1684 struct regmap *regs = ssi->regs; 1685 1686 regcache_cache_only(regs, false); 1687 1688 regmap_update_bits(regs, REG_SSI_SFCSR, 1689 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | 1690 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, 1691 ssi->regcache_sfcsr); 1692 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); 1693 1694 return regcache_sync(regs); 1695 } 1696 #endif /* CONFIG_PM_SLEEP */ 1697 1698 static const struct dev_pm_ops fsl_ssi_pm = { 1699 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1700 }; 1701 1702 static struct platform_driver fsl_ssi_driver = { 1703 .driver = { 1704 .name = "fsl-ssi-dai", 1705 .of_match_table = fsl_ssi_ids, 1706 .pm = &fsl_ssi_pm, 1707 }, 1708 .probe = fsl_ssi_probe, 1709 .remove = fsl_ssi_remove, 1710 }; 1711 1712 module_platform_driver(fsl_ssi_driver); 1713 1714 MODULE_ALIAS("platform:fsl-ssi-dai"); 1715 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1716 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1717 MODULE_LICENSE("GPL v2"); 1718