1 /* 2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Author: Timur Tabi <timur@freescale.com> 5 * 6 * Copyright 2007-2010 Freescale Semiconductor, Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 * 12 * 13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards: 14 * 15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most 16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only 17 * one FIFO which combines all valid receive slots. We cannot even select 18 * which slots we want to receive. The WM9712 with which this driver 19 * was developed with always sends GPIO status data in slot 12 which 20 * we receive in our (PCM-) data stream. The only chance we have is to 21 * manually skip this data in the FIQ handler. With sampling rates different 22 * from 48000Hz not every frame has valid receive data, so the ratio 23 * between pcm data and GPIO status data changes. Our FIQ handler is not 24 * able to handle this, hence this driver only works with 48000Hz sampling 25 * rate. 26 * Reading and writing AC97 registers is another challenge. The core 27 * provides us status bits when the read register is updated with *another* 28 * value. When we read the same register two times (and the register still 29 * contains the same value) these status bits are not set. We work 30 * around this by not polling these bits but only wait a fixed delay. 31 */ 32 33 #include <linux/init.h> 34 #include <linux/io.h> 35 #include <linux/module.h> 36 #include <linux/interrupt.h> 37 #include <linux/clk.h> 38 #include <linux/ctype.h> 39 #include <linux/device.h> 40 #include <linux/delay.h> 41 #include <linux/mutex.h> 42 #include <linux/slab.h> 43 #include <linux/spinlock.h> 44 #include <linux/of.h> 45 #include <linux/of_address.h> 46 #include <linux/of_irq.h> 47 #include <linux/of_platform.h> 48 49 #include <sound/core.h> 50 #include <sound/pcm.h> 51 #include <sound/pcm_params.h> 52 #include <sound/initval.h> 53 #include <sound/soc.h> 54 #include <sound/dmaengine_pcm.h> 55 56 #include "fsl_ssi.h" 57 #include "imx-pcm.h" 58 59 /** 60 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI 61 * 62 * The SSI has a limitation in that the samples must be in the same byte 63 * order as the host CPU. This is because when multiple bytes are written 64 * to the STX register, the bytes and bits must be written in the same 65 * order. The STX is a shift register, so all the bits need to be aligned 66 * (bit-endianness must match byte-endianness). Processors typically write 67 * the bits within a byte in the same order that the bytes of a word are 68 * written in. So if the host CPU is big-endian, then only big-endian 69 * samples will be written to STX properly. 70 */ 71 #ifdef __BIG_ENDIAN 72 #define FSLSSI_I2S_FORMATS \ 73 (SNDRV_PCM_FMTBIT_S8 | \ 74 SNDRV_PCM_FMTBIT_S16_BE | \ 75 SNDRV_PCM_FMTBIT_S18_3BE | \ 76 SNDRV_PCM_FMTBIT_S20_3BE | \ 77 SNDRV_PCM_FMTBIT_S24_3BE | \ 78 SNDRV_PCM_FMTBIT_S24_BE) 79 #else 80 #define FSLSSI_I2S_FORMATS \ 81 (SNDRV_PCM_FMTBIT_S8 | \ 82 SNDRV_PCM_FMTBIT_S16_LE | \ 83 SNDRV_PCM_FMTBIT_S18_3LE | \ 84 SNDRV_PCM_FMTBIT_S20_3LE | \ 85 SNDRV_PCM_FMTBIT_S24_3LE | \ 86 SNDRV_PCM_FMTBIT_S24_LE) 87 #endif 88 89 #define FSLSSI_SIER_DBG_RX_FLAGS \ 90 (SSI_SIER_RFF0_EN | \ 91 SSI_SIER_RLS_EN | \ 92 SSI_SIER_RFS_EN | \ 93 SSI_SIER_ROE0_EN | \ 94 SSI_SIER_RFRC_EN) 95 #define FSLSSI_SIER_DBG_TX_FLAGS \ 96 (SSI_SIER_TFE0_EN | \ 97 SSI_SIER_TLS_EN | \ 98 SSI_SIER_TFS_EN | \ 99 SSI_SIER_TUE0_EN | \ 100 SSI_SIER_TFRC_EN) 101 102 enum fsl_ssi_type { 103 FSL_SSI_MCP8610, 104 FSL_SSI_MX21, 105 FSL_SSI_MX35, 106 FSL_SSI_MX51, 107 }; 108 109 struct fsl_ssi_regvals { 110 u32 sier; 111 u32 srcr; 112 u32 stcr; 113 u32 scr; 114 }; 115 116 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) 117 { 118 switch (reg) { 119 case REG_SSI_SACCEN: 120 case REG_SSI_SACCDIS: 121 return false; 122 default: 123 return true; 124 } 125 } 126 127 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) 128 { 129 switch (reg) { 130 case REG_SSI_STX0: 131 case REG_SSI_STX1: 132 case REG_SSI_SRX0: 133 case REG_SSI_SRX1: 134 case REG_SSI_SISR: 135 case REG_SSI_SFCSR: 136 case REG_SSI_SACNT: 137 case REG_SSI_SACADD: 138 case REG_SSI_SACDAT: 139 case REG_SSI_SATAG: 140 case REG_SSI_SACCST: 141 case REG_SSI_SOR: 142 return true; 143 default: 144 return false; 145 } 146 } 147 148 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) 149 { 150 switch (reg) { 151 case REG_SSI_SRX0: 152 case REG_SSI_SRX1: 153 case REG_SSI_SISR: 154 case REG_SSI_SACADD: 155 case REG_SSI_SACDAT: 156 case REG_SSI_SATAG: 157 return true; 158 default: 159 return false; 160 } 161 } 162 163 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) 164 { 165 switch (reg) { 166 case REG_SSI_SRX0: 167 case REG_SSI_SRX1: 168 case REG_SSI_SACCST: 169 return false; 170 default: 171 return true; 172 } 173 } 174 175 static const struct regmap_config fsl_ssi_regconfig = { 176 .max_register = REG_SSI_SACCDIS, 177 .reg_bits = 32, 178 .val_bits = 32, 179 .reg_stride = 4, 180 .val_format_endian = REGMAP_ENDIAN_NATIVE, 181 .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, 182 .readable_reg = fsl_ssi_readable_reg, 183 .volatile_reg = fsl_ssi_volatile_reg, 184 .precious_reg = fsl_ssi_precious_reg, 185 .writeable_reg = fsl_ssi_writeable_reg, 186 .cache_type = REGCACHE_FLAT, 187 }; 188 189 struct fsl_ssi_soc_data { 190 bool imx; 191 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ 192 bool offline_config; 193 u32 sisr_write_mask; 194 }; 195 196 /** 197 * fsl_ssi: per-SSI private data 198 * 199 * @regs: Pointer to the regmap registers 200 * @irq: IRQ of this SSI 201 * @cpu_dai_drv: CPU DAI driver for this device 202 * 203 * @dai_fmt: DAI configuration this device is currently used with 204 * @i2s_net: I2S and Network mode configurations of SCR register 205 * @use_dma: DMA is used or FIQ with stream filter 206 * @use_dual_fifo: DMA with support for dual FIFO mode 207 * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree 208 * @fifo_depth: Depth of the SSI FIFOs 209 * @slot_width: Width of each DAI slot 210 * @slots: Number of slots 211 * @regvals: Specific RX/TX register settings 212 * 213 * @clk: Clock source to access register 214 * @baudclk: Clock source to generate bit and frame-sync clocks 215 * @baudclk_streams: Active streams that are using baudclk 216 * 217 * @regcache_sfcsr: Cache sfcsr register value during suspend and resume 218 * @regcache_sacnt: Cache sacnt register value during suspend and resume 219 * 220 * @dma_params_tx: DMA transmit parameters 221 * @dma_params_rx: DMA receive parameters 222 * @ssi_phys: physical address of the SSI registers 223 * 224 * @fiq_params: FIQ stream filtering parameters 225 * 226 * @pdev: Pointer to pdev when using fsl-ssi as sound card (ppc only) 227 * TODO: Should be replaced with simple-sound-card 228 * 229 * @dbg_stats: Debugging statistics 230 * 231 * @soc: SoC specific data 232 * @dev: Pointer to &pdev->dev 233 * 234 * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are 235 * @fifo_watermark or fewer words in TX fifo or 236 * @fifo_watermark or more empty words in RX fifo. 237 * @dma_maxburst: Max number of words to transfer in one go. So far, 238 * this is always the same as fifo_watermark. 239 * 240 * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations 241 */ 242 struct fsl_ssi { 243 struct regmap *regs; 244 int irq; 245 struct snd_soc_dai_driver cpu_dai_drv; 246 247 unsigned int dai_fmt; 248 u8 i2s_net; 249 bool use_dma; 250 bool use_dual_fifo; 251 bool has_ipg_clk_name; 252 unsigned int fifo_depth; 253 unsigned int slot_width; 254 unsigned int slots; 255 struct fsl_ssi_regvals regvals[2]; 256 257 struct clk *clk; 258 struct clk *baudclk; 259 unsigned int baudclk_streams; 260 261 u32 regcache_sfcsr; 262 u32 regcache_sacnt; 263 264 struct snd_dmaengine_dai_dma_data dma_params_tx; 265 struct snd_dmaengine_dai_dma_data dma_params_rx; 266 dma_addr_t ssi_phys; 267 268 struct imx_pcm_fiq_params fiq_params; 269 270 struct platform_device *pdev; 271 272 struct fsl_ssi_dbg dbg_stats; 273 274 const struct fsl_ssi_soc_data *soc; 275 struct device *dev; 276 277 u32 fifo_watermark; 278 u32 dma_maxburst; 279 280 struct mutex ac97_reg_lock; 281 }; 282 283 /* 284 * SoC specific data 285 * 286 * Notes: 287 * 1) SSI in earlier SoCS has critical bits in control registers that 288 * cannot be changed after SSI starts running -- a software reset 289 * (set SSIEN to 0) is required to change their values. So adding 290 * an offline_config flag for these SoCs. 291 * 2) SDMA is available since imx35. However, imx35 does not support 292 * DMA bits changing when SSI is running, so set offline_config. 293 * 3) imx51 and later versions support register configurations when 294 * SSI is running (SSIEN); For these versions, DMA needs to be 295 * configured before SSI sends DMA request to avoid an undefined 296 * DMA request on the SDMA side. 297 */ 298 299 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { 300 .imx = false, 301 .offline_config = true, 302 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 303 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 304 SSI_SISR_TUE0 | SSI_SISR_TUE1, 305 }; 306 307 static struct fsl_ssi_soc_data fsl_ssi_imx21 = { 308 .imx = true, 309 .imx21regs = true, 310 .offline_config = true, 311 .sisr_write_mask = 0, 312 }; 313 314 static struct fsl_ssi_soc_data fsl_ssi_imx35 = { 315 .imx = true, 316 .offline_config = true, 317 .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | 318 SSI_SISR_ROE0 | SSI_SISR_ROE1 | 319 SSI_SISR_TUE0 | SSI_SISR_TUE1, 320 }; 321 322 static struct fsl_ssi_soc_data fsl_ssi_imx51 = { 323 .imx = true, 324 .offline_config = false, 325 .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | 326 SSI_SISR_TUE0 | SSI_SISR_TUE1, 327 }; 328 329 static const struct of_device_id fsl_ssi_ids[] = { 330 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, 331 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, 332 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, 333 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, 334 {} 335 }; 336 MODULE_DEVICE_TABLE(of, fsl_ssi_ids); 337 338 static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) 339 { 340 return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 341 SND_SOC_DAIFMT_AC97; 342 } 343 344 static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi) 345 { 346 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 347 SND_SOC_DAIFMT_CBS_CFS; 348 } 349 350 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi) 351 { 352 return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == 353 SND_SOC_DAIFMT_CBM_CFS; 354 } 355 356 /** 357 * Interrupt handler to gather states 358 */ 359 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) 360 { 361 struct fsl_ssi *ssi = dev_id; 362 struct regmap *regs = ssi->regs; 363 __be32 sisr; 364 __be32 sisr2; 365 366 regmap_read(regs, REG_SSI_SISR, &sisr); 367 368 sisr2 = sisr & ssi->soc->sisr_write_mask; 369 /* Clear the bits that we set */ 370 if (sisr2) 371 regmap_write(regs, REG_SSI_SISR, sisr2); 372 373 fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); 374 375 return IRQ_HANDLED; 376 } 377 378 /** 379 * Enable or disable all rx/tx config flags at once 380 */ 381 static void fsl_ssi_rxtx_config(struct fsl_ssi *ssi, bool enable) 382 { 383 struct regmap *regs = ssi->regs; 384 struct fsl_ssi_regvals *vals = ssi->regvals; 385 386 if (enable) { 387 regmap_update_bits(regs, REG_SSI_SIER, 388 vals[RX].sier | vals[TX].sier, 389 vals[RX].sier | vals[TX].sier); 390 regmap_update_bits(regs, REG_SSI_SRCR, 391 vals[RX].srcr | vals[TX].srcr, 392 vals[RX].srcr | vals[TX].srcr); 393 regmap_update_bits(regs, REG_SSI_STCR, 394 vals[RX].stcr | vals[TX].stcr, 395 vals[RX].stcr | vals[TX].stcr); 396 } else { 397 regmap_update_bits(regs, REG_SSI_SRCR, 398 vals[RX].srcr | vals[TX].srcr, 0); 399 regmap_update_bits(regs, REG_SSI_STCR, 400 vals[RX].stcr | vals[TX].stcr, 0); 401 regmap_update_bits(regs, REG_SSI_SIER, 402 vals[RX].sier | vals[TX].sier, 0); 403 } 404 } 405 406 /** 407 * Clear remaining data in the FIFO to avoid dirty data or channel slipping 408 */ 409 static void fsl_ssi_fifo_clear(struct fsl_ssi *ssi, bool is_rx) 410 { 411 bool tx = !is_rx; 412 413 regmap_update_bits(ssi->regs, REG_SSI_SOR, 414 SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); 415 } 416 417 /** 418 * Calculate the bits that have to be disabled for the current stream that is 419 * getting disabled. This keeps the bits enabled that are necessary for the 420 * second stream to work if 'stream_active' is true. 421 * 422 * Detailed calculation: 423 * These are the values that need to be active after disabling. For non-active 424 * second stream, this is 0: 425 * vals_stream * !!stream_active 426 * 427 * The following computes the overall differences between the setup for the 428 * to-disable stream and the active stream, a simple XOR: 429 * vals_disable ^ (vals_stream * !!(stream_active)) 430 * 431 * The full expression adds a mask on all values we care about 432 */ 433 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ 434 ((vals_disable) & \ 435 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) 436 437 /** 438 * Enable or disable SSI configuration. 439 */ 440 static void fsl_ssi_config(struct fsl_ssi *ssi, bool enable, 441 struct fsl_ssi_regvals *vals) 442 { 443 struct regmap *regs = ssi->regs; 444 struct fsl_ssi_regvals *avals; 445 int nr_active_streams; 446 u32 scr; 447 int keep_active; 448 449 regmap_read(regs, REG_SSI_SCR, &scr); 450 451 nr_active_streams = !!(scr & SSI_SCR_TE) + !!(scr & SSI_SCR_RE); 452 453 if (nr_active_streams - 1 > 0) 454 keep_active = 1; 455 else 456 keep_active = 0; 457 458 /* Get the opposite direction to keep its values untouched */ 459 if (&ssi->regvals[RX] == vals) 460 avals = &ssi->regvals[TX]; 461 else 462 avals = &ssi->regvals[RX]; 463 464 if (!enable) { 465 /* 466 * To keep the other stream safe, exclude shared bits between 467 * both streams, and get safe bits to disable current stream 468 */ 469 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, 470 keep_active); 471 /* Safely disable SCR register for the stream */ 472 regmap_update_bits(regs, REG_SSI_SCR, scr, 0); 473 } 474 475 /* 476 * For cases where online configuration is not supported, 477 * 1) Enable all necessary bits of both streams when 1st stream starts 478 * even if the opposite stream will not start 479 * 2) Disable all remaining bits of both streams when last stream ends 480 */ 481 if (ssi->soc->offline_config) { 482 if ((enable && !nr_active_streams) || (!enable && !keep_active)) 483 fsl_ssi_rxtx_config(ssi, enable); 484 485 goto config_done; 486 } 487 488 /* Online configure single direction while SSI is running */ 489 if (enable) { 490 fsl_ssi_fifo_clear(ssi, vals->scr & SSI_SCR_RE); 491 492 regmap_update_bits(regs, REG_SSI_SRCR, vals->srcr, vals->srcr); 493 regmap_update_bits(regs, REG_SSI_STCR, vals->stcr, vals->stcr); 494 regmap_update_bits(regs, REG_SSI_SIER, vals->sier, vals->sier); 495 } else { 496 u32 sier; 497 u32 srcr; 498 u32 stcr; 499 500 /* 501 * To keep the other stream safe, exclude shared bits between 502 * both streams, and get safe bits to disable current stream 503 */ 504 sier = fsl_ssi_disable_val(vals->sier, avals->sier, 505 keep_active); 506 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, 507 keep_active); 508 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, 509 keep_active); 510 511 /* Safely disable other control registers for the stream */ 512 regmap_update_bits(regs, REG_SSI_SRCR, srcr, 0); 513 regmap_update_bits(regs, REG_SSI_STCR, stcr, 0); 514 regmap_update_bits(regs, REG_SSI_SIER, sier, 0); 515 } 516 517 config_done: 518 /* Enabling of subunits is done after configuration */ 519 if (enable) { 520 /* 521 * Start DMA before setting TE to avoid FIFO underrun 522 * which may cause a channel slip or a channel swap 523 * 524 * TODO: FIQ cases might also need this upon testing 525 */ 526 if (ssi->use_dma && (vals->scr & SSI_SCR_TE)) { 527 int i; 528 int max_loop = 100; 529 530 /* Enable SSI first to send TX DMA request */ 531 regmap_update_bits(regs, REG_SSI_SCR, 532 SSI_SCR_SSIEN, SSI_SCR_SSIEN); 533 534 /* Busy wait until TX FIFO not empty -- DMA working */ 535 for (i = 0; i < max_loop; i++) { 536 u32 sfcsr; 537 regmap_read(regs, REG_SSI_SFCSR, &sfcsr); 538 if (SSI_SFCSR_TFCNT0(sfcsr)) 539 break; 540 } 541 if (i == max_loop) { 542 dev_err(ssi->dev, 543 "Timeout waiting TX FIFO filling\n"); 544 } 545 } 546 /* Enable all remaining bits */ 547 regmap_update_bits(regs, REG_SSI_SCR, vals->scr, vals->scr); 548 } 549 } 550 551 static void fsl_ssi_rx_config(struct fsl_ssi *ssi, bool enable) 552 { 553 fsl_ssi_config(ssi, enable, &ssi->regvals[RX]); 554 } 555 556 static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) 557 { 558 struct regmap *regs = ssi->regs; 559 560 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ 561 if (!ssi->soc->imx21regs) { 562 /* Disable all channel slots */ 563 regmap_write(regs, REG_SSI_SACCDIS, 0xff); 564 /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ 565 regmap_write(regs, REG_SSI_SACCEN, 0x300); 566 } 567 } 568 569 static void fsl_ssi_tx_config(struct fsl_ssi *ssi, bool enable) 570 { 571 /* 572 * SACCST might be modified via AC Link by a CODEC if it sends 573 * extra bits in their SLOTREQ requests, which'll accidentally 574 * send valid data to slots other than normal playback slots. 575 * 576 * To be safe, configure SACCST right before TX starts. 577 */ 578 if (enable && fsl_ssi_is_ac97(ssi)) 579 fsl_ssi_tx_ac97_saccst_setup(ssi); 580 581 fsl_ssi_config(ssi, enable, &ssi->regvals[TX]); 582 } 583 584 /** 585 * Cache critical bits of SIER, SRCR, STCR and SCR to later set them safely 586 */ 587 static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) 588 { 589 struct fsl_ssi_regvals *vals = ssi->regvals; 590 591 vals[RX].sier = SSI_SIER_RFF0_EN; 592 vals[RX].srcr = SSI_SRCR_RFEN0; 593 vals[RX].scr = 0; 594 vals[TX].sier = SSI_SIER_TFE0_EN; 595 vals[TX].stcr = SSI_STCR_TFEN0; 596 vals[TX].scr = 0; 597 598 /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ 599 if (!fsl_ssi_is_ac97(ssi)) { 600 vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; 601 vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; 602 } 603 604 if (ssi->use_dma) { 605 vals[RX].sier |= SSI_SIER_RDMAE; 606 vals[TX].sier |= SSI_SIER_TDMAE; 607 } else { 608 vals[RX].sier |= SSI_SIER_RIE; 609 vals[TX].sier |= SSI_SIER_TIE; 610 } 611 612 vals[RX].sier |= FSLSSI_SIER_DBG_RX_FLAGS; 613 vals[TX].sier |= FSLSSI_SIER_DBG_TX_FLAGS; 614 } 615 616 static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) 617 { 618 struct regmap *regs = ssi->regs; 619 620 /* Setup the clock control register */ 621 regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 622 regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); 623 624 /* Enable AC97 mode and startup the SSI */ 625 regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); 626 627 /* AC97 has to communicate with codec before starting a stream */ 628 regmap_update_bits(regs, REG_SSI_SCR, 629 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, 630 SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); 631 632 regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); 633 } 634 635 static int fsl_ssi_startup(struct snd_pcm_substream *substream, 636 struct snd_soc_dai *dai) 637 { 638 struct snd_soc_pcm_runtime *rtd = substream->private_data; 639 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); 640 int ret; 641 642 ret = clk_prepare_enable(ssi->clk); 643 if (ret) 644 return ret; 645 646 /* 647 * When using dual fifo mode, it is safer to ensure an even period 648 * size. If appearing to an odd number while DMA always starts its 649 * task from fifo0, fifo1 would be neglected at the end of each 650 * period. But SSI would still access fifo1 with an invalid data. 651 */ 652 if (ssi->use_dual_fifo) 653 snd_pcm_hw_constraint_step(substream->runtime, 0, 654 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); 655 656 return 0; 657 } 658 659 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, 660 struct snd_soc_dai *dai) 661 { 662 struct snd_soc_pcm_runtime *rtd = substream->private_data; 663 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); 664 665 clk_disable_unprepare(ssi->clk); 666 } 667 668 /** 669 * Configure Digital Audio Interface bit clock 670 * 671 * Note: This function can be only called when using SSI as DAI master 672 * 673 * Quick instruction for parameters: 674 * freq: Output BCLK frequency = samplerate * slots * slot_width 675 * (In 2-channel I2S Master mode, slot_width is fixed 32) 676 */ 677 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, 678 struct snd_soc_dai *dai, 679 struct snd_pcm_hw_params *hw_params) 680 { 681 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 682 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 683 struct regmap *regs = ssi->regs; 684 int synchronous = ssi->cpu_dai_drv.symmetric_rates, ret; 685 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; 686 unsigned long clkrate, baudrate, tmprate; 687 unsigned int slots = params_channels(hw_params); 688 unsigned int slot_width = 32; 689 u64 sub, savesub = 100000; 690 unsigned int freq; 691 bool baudclk_is_used; 692 693 /* Override slots and slot_width if being specifically set... */ 694 if (ssi->slots) 695 slots = ssi->slots; 696 /* ...but keep 32 bits if slots is 2 -- I2S Master mode */ 697 if (ssi->slot_width && slots != 2) 698 slot_width = ssi->slot_width; 699 700 /* Generate bit clock based on the slot number and slot width */ 701 freq = slots * slot_width * params_rate(hw_params); 702 703 /* Don't apply it to any non-baudclk circumstance */ 704 if (IS_ERR(ssi->baudclk)) 705 return -EINVAL; 706 707 /* 708 * Hardware limitation: The bclk rate must be 709 * never greater than 1/5 IPG clock rate 710 */ 711 if (freq * 5 > clk_get_rate(ssi->clk)) { 712 dev_err(dai->dev, "bitclk > ipgclk / 5\n"); 713 return -EINVAL; 714 } 715 716 baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); 717 718 /* It should be already enough to divide clock by setting pm alone */ 719 psr = 0; 720 div2 = 0; 721 722 factor = (div2 + 1) * (7 * psr + 1) * 2; 723 724 for (i = 0; i < 255; i++) { 725 tmprate = freq * factor * (i + 1); 726 727 if (baudclk_is_used) 728 clkrate = clk_get_rate(ssi->baudclk); 729 else 730 clkrate = clk_round_rate(ssi->baudclk, tmprate); 731 732 clkrate /= factor; 733 afreq = clkrate / (i + 1); 734 735 if (freq == afreq) 736 sub = 0; 737 else if (freq / afreq == 1) 738 sub = freq - afreq; 739 else if (afreq / freq == 1) 740 sub = afreq - freq; 741 else 742 continue; 743 744 /* Calculate the fraction */ 745 sub *= 100000; 746 do_div(sub, freq); 747 748 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { 749 baudrate = tmprate; 750 savesub = sub; 751 pm = i; 752 } 753 754 /* We are lucky */ 755 if (savesub == 0) 756 break; 757 } 758 759 /* No proper pm found if it is still remaining the initial value */ 760 if (pm == 999) { 761 dev_err(dai->dev, "failed to handle the required sysclk\n"); 762 return -EINVAL; 763 } 764 765 stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | 766 (psr ? SSI_SxCCR_PSR : 0); 767 mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; 768 769 /* STCCR is used for RX in synchronous mode */ 770 tx2 = tx || synchronous; 771 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); 772 773 if (!baudclk_is_used) { 774 ret = clk_set_rate(ssi->baudclk, baudrate); 775 if (ret) { 776 dev_err(dai->dev, "failed to set baudclk rate\n"); 777 return -EINVAL; 778 } 779 } 780 781 return 0; 782 } 783 784 /** 785 * Configure SSI based on PCM hardware parameters 786 * 787 * Notes: 788 * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily 789 * disabled on offline_config SoCs. Even for online configurable SoCs 790 * running in synchronous mode (both TX and RX use STCCR), it is not 791 * safe to re-configure them when both two streams start running. 792 * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the 793 * fsl_ssi_set_bclk() if SSI is the DAI clock master. 794 */ 795 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, 796 struct snd_pcm_hw_params *hw_params, 797 struct snd_soc_dai *dai) 798 { 799 bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 800 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 801 struct regmap *regs = ssi->regs; 802 unsigned int channels = params_channels(hw_params); 803 unsigned int sample_size = params_width(hw_params); 804 u32 wl = SSI_SxCCR_WL(sample_size); 805 int ret; 806 u32 scr; 807 int enabled; 808 809 regmap_read(regs, REG_SSI_SCR, &scr); 810 enabled = scr & SSI_SCR_SSIEN; 811 812 /* 813 * SSI is properly configured if it is enabled and running in 814 * the synchronous mode; Note that AC97 mode is an exception 815 * that should set separate configurations for STCCR and SRCCR 816 * despite running in the synchronous mode. 817 */ 818 if (enabled && ssi->cpu_dai_drv.symmetric_rates) 819 return 0; 820 821 if (fsl_ssi_is_i2s_master(ssi)) { 822 ret = fsl_ssi_set_bclk(substream, dai, hw_params); 823 if (ret) 824 return ret; 825 826 /* Do not enable the clock if it is already enabled */ 827 if (!(ssi->baudclk_streams & BIT(substream->stream))) { 828 ret = clk_prepare_enable(ssi->baudclk); 829 if (ret) 830 return ret; 831 832 ssi->baudclk_streams |= BIT(substream->stream); 833 } 834 } 835 836 if (!fsl_ssi_is_ac97(ssi)) { 837 u8 i2s_net; 838 /* Normal + Network mode to send 16-bit data in 32-bit frames */ 839 if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) 840 i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; 841 else 842 i2s_net = ssi->i2s_net; 843 844 regmap_update_bits(regs, REG_SSI_SCR, 845 SSI_SCR_I2S_NET_MASK, 846 channels == 1 ? 0 : i2s_net); 847 } 848 849 /* In synchronous mode, the SSI uses STCCR for capture */ 850 tx2 = tx || ssi->cpu_dai_drv.symmetric_rates; 851 regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); 852 853 return 0; 854 } 855 856 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, 857 struct snd_soc_dai *dai) 858 { 859 struct snd_soc_pcm_runtime *rtd = substream->private_data; 860 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); 861 862 if (fsl_ssi_is_i2s_master(ssi) && 863 ssi->baudclk_streams & BIT(substream->stream)) { 864 clk_disable_unprepare(ssi->baudclk); 865 ssi->baudclk_streams &= ~BIT(substream->stream); 866 } 867 868 return 0; 869 } 870 871 static int _fsl_ssi_set_dai_fmt(struct device *dev, 872 struct fsl_ssi *ssi, unsigned int fmt) 873 { 874 struct regmap *regs = ssi->regs; 875 u32 strcr = 0, stcr, srcr, scr, mask; 876 u8 wm; 877 878 ssi->dai_fmt = fmt; 879 880 if (fsl_ssi_is_i2s_master(ssi) && IS_ERR(ssi->baudclk)) { 881 dev_err(dev, "missing baudclk for master mode\n"); 882 return -EINVAL; 883 } 884 885 fsl_ssi_setup_regvals(ssi); 886 887 regmap_read(regs, REG_SSI_SCR, &scr); 888 scr &= ~(SSI_SCR_SYN | SSI_SCR_I2S_MODE_MASK); 889 /* Synchronize frame sync clock for TE to avoid data slipping */ 890 scr |= SSI_SCR_SYNC_TX_FS; 891 892 mask = SSI_STCR_TXBIT0 | SSI_STCR_TFDIR | SSI_STCR_TXDIR | 893 SSI_STCR_TSCKP | SSI_STCR_TFSI | SSI_STCR_TFSL | SSI_STCR_TEFS; 894 regmap_read(regs, REG_SSI_STCR, &stcr); 895 regmap_read(regs, REG_SSI_SRCR, &srcr); 896 stcr &= ~mask; 897 srcr &= ~mask; 898 899 /* Use Network mode as default */ 900 ssi->i2s_net = SSI_SCR_NET; 901 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 902 case SND_SOC_DAIFMT_I2S: 903 regmap_update_bits(regs, REG_SSI_STCCR, 904 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 905 regmap_update_bits(regs, REG_SSI_SRCCR, 906 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); 907 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 908 case SND_SOC_DAIFMT_CBM_CFS: 909 case SND_SOC_DAIFMT_CBS_CFS: 910 ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; 911 break; 912 case SND_SOC_DAIFMT_CBM_CFM: 913 ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; 914 break; 915 default: 916 return -EINVAL; 917 } 918 919 /* Data on rising edge of bclk, frame low, 1clk before data */ 920 strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | 921 SSI_STCR_TXBIT0 | SSI_STCR_TEFS; 922 break; 923 case SND_SOC_DAIFMT_LEFT_J: 924 /* Data on rising edge of bclk, frame high */ 925 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP; 926 break; 927 case SND_SOC_DAIFMT_DSP_A: 928 /* Data on rising edge of bclk, frame high, 1clk before data */ 929 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | 930 SSI_STCR_TXBIT0 | SSI_STCR_TEFS; 931 break; 932 case SND_SOC_DAIFMT_DSP_B: 933 /* Data on rising edge of bclk, frame high */ 934 strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TXBIT0; 935 break; 936 case SND_SOC_DAIFMT_AC97: 937 /* Data on falling edge of bclk, frame high, 1clk before data */ 938 ssi->i2s_net |= SSI_SCR_I2S_MODE_NORMAL; 939 break; 940 default: 941 return -EINVAL; 942 } 943 scr |= ssi->i2s_net; 944 945 /* DAI clock inversion */ 946 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 947 case SND_SOC_DAIFMT_NB_NF: 948 /* Nothing to do for both normal cases */ 949 break; 950 case SND_SOC_DAIFMT_IB_NF: 951 /* Invert bit clock */ 952 strcr ^= SSI_STCR_TSCKP; 953 break; 954 case SND_SOC_DAIFMT_NB_IF: 955 /* Invert frame clock */ 956 strcr ^= SSI_STCR_TFSI; 957 break; 958 case SND_SOC_DAIFMT_IB_IF: 959 /* Invert both clocks */ 960 strcr ^= SSI_STCR_TSCKP; 961 strcr ^= SSI_STCR_TFSI; 962 break; 963 default: 964 return -EINVAL; 965 } 966 967 /* DAI clock master masks */ 968 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 969 case SND_SOC_DAIFMT_CBS_CFS: 970 /* Output bit and frame sync clocks */ 971 strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; 972 scr |= SSI_SCR_SYS_CLK_EN; 973 break; 974 case SND_SOC_DAIFMT_CBM_CFM: 975 /* Input bit or frame sync clocks */ 976 scr &= ~SSI_SCR_SYS_CLK_EN; 977 break; 978 case SND_SOC_DAIFMT_CBM_CFS: 979 /* Input bit clock but output frame sync clock */ 980 strcr &= ~SSI_STCR_TXDIR; 981 strcr |= SSI_STCR_TFDIR; 982 scr &= ~SSI_SCR_SYS_CLK_EN; 983 break; 984 default: 985 if (!fsl_ssi_is_ac97(ssi)) 986 return -EINVAL; 987 } 988 989 stcr |= strcr; 990 srcr |= strcr; 991 992 /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ 993 if (ssi->cpu_dai_drv.symmetric_rates || fsl_ssi_is_ac97(ssi)) { 994 srcr &= ~SSI_SRCR_RXDIR; 995 scr |= SSI_SCR_SYN; 996 } 997 998 regmap_write(regs, REG_SSI_STCR, stcr); 999 regmap_write(regs, REG_SSI_SRCR, srcr); 1000 regmap_write(regs, REG_SSI_SCR, scr); 1001 1002 wm = ssi->fifo_watermark; 1003 1004 regmap_write(regs, REG_SSI_SFCSR, 1005 SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | 1006 SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); 1007 1008 if (ssi->use_dual_fifo) { 1009 regmap_update_bits(regs, REG_SSI_SRCR, 1010 SSI_SRCR_RFEN1, SSI_SRCR_RFEN1); 1011 regmap_update_bits(regs, REG_SSI_STCR, 1012 SSI_STCR_TFEN1, SSI_STCR_TFEN1); 1013 regmap_update_bits(regs, REG_SSI_SCR, 1014 SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); 1015 } 1016 1017 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) 1018 fsl_ssi_setup_ac97(ssi); 1019 1020 return 0; 1021 } 1022 1023 /** 1024 * Configure Digital Audio Interface (DAI) Format 1025 */ 1026 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1027 { 1028 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1029 1030 /* AC97 configured DAIFMT earlier in the probe() */ 1031 if (fsl_ssi_is_ac97(ssi)) 1032 return 0; 1033 1034 return _fsl_ssi_set_dai_fmt(dai->dev, ssi, fmt); 1035 } 1036 1037 /** 1038 * Set TDM slot number and slot width 1039 */ 1040 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 1041 u32 rx_mask, int slots, int slot_width) 1042 { 1043 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1044 struct regmap *regs = ssi->regs; 1045 u32 val; 1046 1047 /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ 1048 if (slot_width & 1 || slot_width < 8 || slot_width > 24) { 1049 dev_err(dai->dev, "invalid slot width: %d\n", slot_width); 1050 return -EINVAL; 1051 } 1052 1053 /* The slot number should be >= 2 if using Network mode or I2S mode */ 1054 regmap_read(regs, REG_SSI_SCR, &val); 1055 val &= SSI_SCR_I2S_MODE_MASK | SSI_SCR_NET; 1056 if (val && slots < 2) { 1057 dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); 1058 return -EINVAL; 1059 } 1060 1061 regmap_update_bits(regs, REG_SSI_STCCR, 1062 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1063 regmap_update_bits(regs, REG_SSI_SRCCR, 1064 SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); 1065 1066 /* Save SSIEN bit of the SCR register */ 1067 regmap_read(regs, REG_SSI_SCR, &val); 1068 val &= SSI_SCR_SSIEN; 1069 /* Temporarily enable SSI to allow SxMSKs to be configurable */ 1070 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); 1071 1072 regmap_write(regs, REG_SSI_STMSK, ~tx_mask); 1073 regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); 1074 1075 /* Restore the value of SSIEN bit */ 1076 regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); 1077 1078 ssi->slot_width = slot_width; 1079 ssi->slots = slots; 1080 1081 return 0; 1082 } 1083 1084 /** 1085 * Start or stop SSI and corresponding DMA transaction. 1086 * 1087 * The DMA channel is in external master start and pause mode, which 1088 * means the SSI completely controls the flow of data. 1089 */ 1090 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, 1091 struct snd_soc_dai *dai) 1092 { 1093 struct snd_soc_pcm_runtime *rtd = substream->private_data; 1094 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); 1095 struct regmap *regs = ssi->regs; 1096 1097 switch (cmd) { 1098 case SNDRV_PCM_TRIGGER_START: 1099 case SNDRV_PCM_TRIGGER_RESUME: 1100 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1101 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1102 fsl_ssi_tx_config(ssi, true); 1103 else 1104 fsl_ssi_rx_config(ssi, true); 1105 break; 1106 1107 case SNDRV_PCM_TRIGGER_STOP: 1108 case SNDRV_PCM_TRIGGER_SUSPEND: 1109 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1110 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1111 fsl_ssi_tx_config(ssi, false); 1112 else 1113 fsl_ssi_rx_config(ssi, false); 1114 break; 1115 1116 default: 1117 return -EINVAL; 1118 } 1119 1120 /* Clear corresponding FIFO */ 1121 if (fsl_ssi_is_ac97(ssi)) { 1122 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1123 regmap_write(regs, REG_SSI_SOR, SSI_SOR_TX_CLR); 1124 else 1125 regmap_write(regs, REG_SSI_SOR, SSI_SOR_RX_CLR); 1126 } 1127 1128 return 0; 1129 } 1130 1131 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) 1132 { 1133 struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); 1134 1135 if (ssi->soc->imx && ssi->use_dma) { 1136 dai->playback_dma_data = &ssi->dma_params_tx; 1137 dai->capture_dma_data = &ssi->dma_params_rx; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { 1144 .startup = fsl_ssi_startup, 1145 .shutdown = fsl_ssi_shutdown, 1146 .hw_params = fsl_ssi_hw_params, 1147 .hw_free = fsl_ssi_hw_free, 1148 .set_fmt = fsl_ssi_set_dai_fmt, 1149 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, 1150 .trigger = fsl_ssi_trigger, 1151 }; 1152 1153 static struct snd_soc_dai_driver fsl_ssi_dai_template = { 1154 .probe = fsl_ssi_dai_probe, 1155 .playback = { 1156 .stream_name = "CPU-Playback", 1157 .channels_min = 1, 1158 .channels_max = 32, 1159 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1160 .formats = FSLSSI_I2S_FORMATS, 1161 }, 1162 .capture = { 1163 .stream_name = "CPU-Capture", 1164 .channels_min = 1, 1165 .channels_max = 32, 1166 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1167 .formats = FSLSSI_I2S_FORMATS, 1168 }, 1169 .ops = &fsl_ssi_dai_ops, 1170 }; 1171 1172 static const struct snd_soc_component_driver fsl_ssi_component = { 1173 .name = "fsl-ssi", 1174 }; 1175 1176 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { 1177 .bus_control = true, 1178 .probe = fsl_ssi_dai_probe, 1179 .playback = { 1180 .stream_name = "AC97 Playback", 1181 .channels_min = 2, 1182 .channels_max = 2, 1183 .rates = SNDRV_PCM_RATE_8000_48000, 1184 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, 1185 }, 1186 .capture = { 1187 .stream_name = "AC97 Capture", 1188 .channels_min = 2, 1189 .channels_max = 2, 1190 .rates = SNDRV_PCM_RATE_48000, 1191 /* 16-bit capture is broken (errata ERR003778) */ 1192 .formats = SNDRV_PCM_FMTBIT_S20, 1193 }, 1194 .ops = &fsl_ssi_dai_ops, 1195 }; 1196 1197 static struct fsl_ssi *fsl_ac97_data; 1198 1199 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, 1200 unsigned short val) 1201 { 1202 struct regmap *regs = fsl_ac97_data->regs; 1203 unsigned int lreg; 1204 unsigned int lval; 1205 int ret; 1206 1207 if (reg > 0x7f) 1208 return; 1209 1210 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1211 1212 ret = clk_prepare_enable(fsl_ac97_data->clk); 1213 if (ret) { 1214 pr_err("ac97 write clk_prepare_enable failed: %d\n", 1215 ret); 1216 goto ret_unlock; 1217 } 1218 1219 lreg = reg << 12; 1220 regmap_write(regs, REG_SSI_SACADD, lreg); 1221 1222 lval = val << 4; 1223 regmap_write(regs, REG_SSI_SACDAT, lval); 1224 1225 regmap_update_bits(regs, REG_SSI_SACNT, 1226 SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); 1227 udelay(100); 1228 1229 clk_disable_unprepare(fsl_ac97_data->clk); 1230 1231 ret_unlock: 1232 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1233 } 1234 1235 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, 1236 unsigned short reg) 1237 { 1238 struct regmap *regs = fsl_ac97_data->regs; 1239 unsigned short val = 0; 1240 u32 reg_val; 1241 unsigned int lreg; 1242 int ret; 1243 1244 mutex_lock(&fsl_ac97_data->ac97_reg_lock); 1245 1246 ret = clk_prepare_enable(fsl_ac97_data->clk); 1247 if (ret) { 1248 pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); 1249 goto ret_unlock; 1250 } 1251 1252 lreg = (reg & 0x7f) << 12; 1253 regmap_write(regs, REG_SSI_SACADD, lreg); 1254 regmap_update_bits(regs, REG_SSI_SACNT, 1255 SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); 1256 1257 udelay(100); 1258 1259 regmap_read(regs, REG_SSI_SACDAT, ®_val); 1260 val = (reg_val >> 4) & 0xffff; 1261 1262 clk_disable_unprepare(fsl_ac97_data->clk); 1263 1264 ret_unlock: 1265 mutex_unlock(&fsl_ac97_data->ac97_reg_lock); 1266 return val; 1267 } 1268 1269 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { 1270 .read = fsl_ssi_ac97_read, 1271 .write = fsl_ssi_ac97_write, 1272 }; 1273 1274 /** 1275 * Make every character in a string lower-case 1276 */ 1277 static void make_lowercase(char *s) 1278 { 1279 if (!s) 1280 return; 1281 for (; *s; s++) 1282 *s = tolower(*s); 1283 } 1284 1285 static int fsl_ssi_imx_probe(struct platform_device *pdev, 1286 struct fsl_ssi *ssi, void __iomem *iomem) 1287 { 1288 struct device_node *np = pdev->dev.of_node; 1289 struct device *dev = &pdev->dev; 1290 u32 dmas[4]; 1291 int ret; 1292 1293 /* Backward compatible for a DT without ipg clock name assigned */ 1294 if (ssi->has_ipg_clk_name) 1295 ssi->clk = devm_clk_get(dev, "ipg"); 1296 else 1297 ssi->clk = devm_clk_get(dev, NULL); 1298 if (IS_ERR(ssi->clk)) { 1299 ret = PTR_ERR(ssi->clk); 1300 dev_err(dev, "failed to get clock: %d\n", ret); 1301 return ret; 1302 } 1303 1304 /* Enable the clock since regmap will not handle it in this case */ 1305 if (!ssi->has_ipg_clk_name) { 1306 ret = clk_prepare_enable(ssi->clk); 1307 if (ret) { 1308 dev_err(dev, "clk_prepare_enable failed: %d\n", ret); 1309 return ret; 1310 } 1311 } 1312 1313 /* Do not error out for slave cases that live without a baud clock */ 1314 ssi->baudclk = devm_clk_get(dev, "baud"); 1315 if (IS_ERR(ssi->baudclk)) 1316 dev_dbg(dev, "failed to get baud clock: %ld\n", 1317 PTR_ERR(ssi->baudclk)); 1318 1319 ssi->dma_params_tx.maxburst = ssi->dma_maxburst; 1320 ssi->dma_params_rx.maxburst = ssi->dma_maxburst; 1321 ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; 1322 ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; 1323 1324 /* Set to dual FIFO mode according to the SDMA sciprt */ 1325 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1326 if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { 1327 ssi->use_dual_fifo = true; 1328 /* 1329 * Use even numbers to avoid channel swap due to SDMA 1330 * script design 1331 */ 1332 ssi->dma_params_tx.maxburst &= ~0x1; 1333 ssi->dma_params_rx.maxburst &= ~0x1; 1334 } 1335 1336 if (!ssi->use_dma) { 1337 /* 1338 * Some boards use an incompatible codec. Use imx-fiq-pcm-audio 1339 * to get it working, as DMA is not possible in this situation. 1340 */ 1341 ssi->fiq_params.irq = ssi->irq; 1342 ssi->fiq_params.base = iomem; 1343 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; 1344 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; 1345 1346 ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); 1347 if (ret) 1348 goto error_pcm; 1349 } else { 1350 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); 1351 if (ret) 1352 goto error_pcm; 1353 } 1354 1355 return 0; 1356 1357 error_pcm: 1358 if (!ssi->has_ipg_clk_name) 1359 clk_disable_unprepare(ssi->clk); 1360 1361 return ret; 1362 } 1363 1364 static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) 1365 { 1366 if (!ssi->use_dma) 1367 imx_pcm_fiq_exit(pdev); 1368 if (!ssi->has_ipg_clk_name) 1369 clk_disable_unprepare(ssi->clk); 1370 } 1371 1372 static int fsl_ssi_probe(struct platform_device *pdev) 1373 { 1374 struct fsl_ssi *ssi; 1375 int ret = 0; 1376 struct device_node *np = pdev->dev.of_node; 1377 struct device *dev = &pdev->dev; 1378 const struct of_device_id *of_id; 1379 const char *p, *sprop; 1380 const uint32_t *iprop; 1381 struct resource *res; 1382 void __iomem *iomem; 1383 char name[64]; 1384 struct regmap_config regconfig = fsl_ssi_regconfig; 1385 1386 of_id = of_match_device(fsl_ssi_ids, dev); 1387 if (!of_id || !of_id->data) 1388 return -EINVAL; 1389 1390 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1391 if (!ssi) 1392 return -ENOMEM; 1393 1394 ssi->soc = of_id->data; 1395 ssi->dev = dev; 1396 1397 /* Check if being used in AC97 mode */ 1398 sprop = of_get_property(np, "fsl,mode", NULL); 1399 if (sprop) { 1400 if (!strcmp(sprop, "ac97-slave")) 1401 ssi->dai_fmt = SND_SOC_DAIFMT_AC97; 1402 } 1403 1404 /* Select DMA or FIQ */ 1405 ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); 1406 1407 if (fsl_ssi_is_ac97(ssi)) { 1408 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, 1409 sizeof(fsl_ssi_ac97_dai)); 1410 fsl_ac97_data = ssi; 1411 } else { 1412 memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, 1413 sizeof(fsl_ssi_dai_template)); 1414 } 1415 ssi->cpu_dai_drv.name = dev_name(dev); 1416 1417 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1418 iomem = devm_ioremap_resource(dev, res); 1419 if (IS_ERR(iomem)) 1420 return PTR_ERR(iomem); 1421 ssi->ssi_phys = res->start; 1422 1423 if (ssi->soc->imx21regs) { 1424 /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ 1425 regconfig.max_register = REG_SSI_SRMSK; 1426 regconfig.num_reg_defaults_raw = 1427 REG_SSI_SRMSK / sizeof(uint32_t) + 1; 1428 } 1429 1430 ret = of_property_match_string(np, "clock-names", "ipg"); 1431 if (ret < 0) { 1432 ssi->has_ipg_clk_name = false; 1433 ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); 1434 } else { 1435 ssi->has_ipg_clk_name = true; 1436 ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, 1437 ®config); 1438 } 1439 if (IS_ERR(ssi->regs)) { 1440 dev_err(dev, "failed to init register map\n"); 1441 return PTR_ERR(ssi->regs); 1442 } 1443 1444 ssi->irq = platform_get_irq(pdev, 0); 1445 if (ssi->irq < 0) { 1446 dev_err(dev, "no irq for node %s\n", pdev->name); 1447 return ssi->irq; 1448 } 1449 1450 /* Set software limitations for synchronous mode */ 1451 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { 1452 if (!fsl_ssi_is_ac97(ssi)) { 1453 ssi->cpu_dai_drv.symmetric_rates = 1; 1454 ssi->cpu_dai_drv.symmetric_samplebits = 1; 1455 } 1456 1457 ssi->cpu_dai_drv.symmetric_channels = 1; 1458 } 1459 1460 /* Fetch FIFO depth; Set to 8 for older DT without this property */ 1461 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1462 if (iprop) 1463 ssi->fifo_depth = be32_to_cpup(iprop); 1464 else 1465 ssi->fifo_depth = 8; 1466 1467 /* 1468 * Configure TX and RX DMA watermarks -- when to send a DMA request 1469 * 1470 * Values should be tested to avoid FIFO under/over run. Set maxburst 1471 * to fifo_watermark to maxiumize DMA transaction to reduce overhead. 1472 */ 1473 switch (ssi->fifo_depth) { 1474 case 15: 1475 /* 1476 * Set to 8 as a balanced configuration -- When TX FIFO has 8 1477 * empty slots, send a DMA request to fill these 8 slots. The 1478 * remaining 7 slots should be able to allow DMA to finish the 1479 * transaction before TX FIFO underruns; Same applies to RX. 1480 * 1481 * Tested with cases running at 48kHz @ 16 bits x 16 channels 1482 */ 1483 ssi->fifo_watermark = 8; 1484 ssi->dma_maxburst = 8; 1485 break; 1486 case 8: 1487 default: 1488 /* Safely use old watermark configurations for older chips */ 1489 ssi->fifo_watermark = ssi->fifo_depth - 2; 1490 ssi->dma_maxburst = ssi->fifo_depth - 2; 1491 break; 1492 } 1493 1494 dev_set_drvdata(dev, ssi); 1495 1496 if (ssi->soc->imx) { 1497 ret = fsl_ssi_imx_probe(pdev, ssi, iomem); 1498 if (ret) 1499 return ret; 1500 } 1501 1502 if (fsl_ssi_is_ac97(ssi)) { 1503 mutex_init(&ssi->ac97_reg_lock); 1504 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); 1505 if (ret) { 1506 dev_err(dev, "failed to set AC'97 ops\n"); 1507 goto error_ac97_ops; 1508 } 1509 } 1510 1511 ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, 1512 &ssi->cpu_dai_drv, 1); 1513 if (ret) { 1514 dev_err(dev, "failed to register DAI: %d\n", ret); 1515 goto error_asoc_register; 1516 } 1517 1518 if (ssi->use_dma) { 1519 ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, 1520 dev_name(dev), ssi); 1521 if (ret < 0) { 1522 dev_err(dev, "failed to claim irq %u\n", ssi->irq); 1523 goto error_asoc_register; 1524 } 1525 } 1526 1527 ret = fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); 1528 if (ret) 1529 goto error_asoc_register; 1530 1531 /* Bypass it if using newer DT bindings of ASoC machine drivers */ 1532 if (!of_get_property(np, "codec-handle", NULL)) 1533 goto done; 1534 1535 /* 1536 * Backward compatible for older bindings by manually triggering the 1537 * machine driver's probe(). Use /compatible property, including the 1538 * address of CPU DAI driver structure, as the name of machine driver. 1539 */ 1540 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); 1541 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ 1542 p = strrchr(sprop, ','); 1543 if (p) 1544 sprop = p + 1; 1545 snprintf(name, sizeof(name), "snd-soc-%s", sprop); 1546 make_lowercase(name); 1547 1548 ssi->pdev = platform_device_register_data(dev, name, 0, NULL, 0); 1549 if (IS_ERR(ssi->pdev)) { 1550 ret = PTR_ERR(ssi->pdev); 1551 dev_err(dev, "failed to register platform: %d\n", ret); 1552 goto error_sound_card; 1553 } 1554 1555 done: 1556 if (ssi->dai_fmt) 1557 _fsl_ssi_set_dai_fmt(dev, ssi, ssi->dai_fmt); 1558 1559 if (fsl_ssi_is_ac97(ssi)) { 1560 u32 ssi_idx; 1561 1562 ret = of_property_read_u32(np, "cell-index", &ssi_idx); 1563 if (ret) { 1564 dev_err(dev, "failed to get SSI index property\n"); 1565 goto error_sound_card; 1566 } 1567 1568 ssi->pdev = platform_device_register_data(NULL, "ac97-codec", 1569 ssi_idx, NULL, 0); 1570 if (IS_ERR(ssi->pdev)) { 1571 ret = PTR_ERR(ssi->pdev); 1572 dev_err(dev, 1573 "failed to register AC97 codec platform: %d\n", 1574 ret); 1575 goto error_sound_card; 1576 } 1577 } 1578 1579 return 0; 1580 1581 error_sound_card: 1582 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1583 error_asoc_register: 1584 if (fsl_ssi_is_ac97(ssi)) 1585 snd_soc_set_ac97_ops(NULL); 1586 error_ac97_ops: 1587 if (fsl_ssi_is_ac97(ssi)) 1588 mutex_destroy(&ssi->ac97_reg_lock); 1589 1590 if (ssi->soc->imx) 1591 fsl_ssi_imx_clean(pdev, ssi); 1592 1593 return ret; 1594 } 1595 1596 static int fsl_ssi_remove(struct platform_device *pdev) 1597 { 1598 struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); 1599 1600 fsl_ssi_debugfs_remove(&ssi->dbg_stats); 1601 1602 if (ssi->pdev) 1603 platform_device_unregister(ssi->pdev); 1604 1605 if (ssi->soc->imx) 1606 fsl_ssi_imx_clean(pdev, ssi); 1607 1608 if (fsl_ssi_is_ac97(ssi)) { 1609 snd_soc_set_ac97_ops(NULL); 1610 mutex_destroy(&ssi->ac97_reg_lock); 1611 } 1612 1613 return 0; 1614 } 1615 1616 #ifdef CONFIG_PM_SLEEP 1617 static int fsl_ssi_suspend(struct device *dev) 1618 { 1619 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1620 struct regmap *regs = ssi->regs; 1621 1622 regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); 1623 regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); 1624 1625 regcache_cache_only(regs, true); 1626 regcache_mark_dirty(regs); 1627 1628 return 0; 1629 } 1630 1631 static int fsl_ssi_resume(struct device *dev) 1632 { 1633 struct fsl_ssi *ssi = dev_get_drvdata(dev); 1634 struct regmap *regs = ssi->regs; 1635 1636 regcache_cache_only(regs, false); 1637 1638 regmap_update_bits(regs, REG_SSI_SFCSR, 1639 SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | 1640 SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, 1641 ssi->regcache_sfcsr); 1642 regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); 1643 1644 return regcache_sync(regs); 1645 } 1646 #endif /* CONFIG_PM_SLEEP */ 1647 1648 static const struct dev_pm_ops fsl_ssi_pm = { 1649 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) 1650 }; 1651 1652 static struct platform_driver fsl_ssi_driver = { 1653 .driver = { 1654 .name = "fsl-ssi-dai", 1655 .of_match_table = fsl_ssi_ids, 1656 .pm = &fsl_ssi_pm, 1657 }, 1658 .probe = fsl_ssi_probe, 1659 .remove = fsl_ssi_remove, 1660 }; 1661 1662 module_platform_driver(fsl_ssi_driver); 1663 1664 MODULE_ALIAS("platform:fsl-ssi-dai"); 1665 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); 1666 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); 1667 MODULE_LICENSE("GPL v2"); 1668