1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SPDIF_TXFIFO_WML 0x8 29 #define FSL_SPDIF_RXFIFO_WML 0x8 30 31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 35 INT_LOSS_LOCK | INT_DPLL_LOCKED) 36 37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 38 39 /* Index list for the values that has if (DPLL Locked) condition */ 40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 41 #define SRPC_NODPLL_START1 0x5 42 #define SRPC_NODPLL_START2 0xc 43 44 #define DEFAULT_RXCLK_SRC 1 45 46 /** 47 * struct fsl_spdif_soc_data: soc specific data 48 * 49 * @imx: for imx platform 50 * @shared_root_clock: flag of sharing a clock source with others; 51 * so the driver shouldn't set root clock rate 52 * @raw_capture_mode: if raw capture mode support 53 * @interrupts: interrupt number 54 * @tx_burst: tx maxburst size 55 * @rx_burst: rx maxburst size 56 * @tx_formats: tx supported data format 57 */ 58 struct fsl_spdif_soc_data { 59 bool imx; 60 bool shared_root_clock; 61 bool raw_capture_mode; 62 u32 interrupts; 63 u32 tx_burst; 64 u32 rx_burst; 65 u64 tx_formats; 66 }; 67 68 /* 69 * SPDIF control structure 70 * Defines channel status, subcode and Q sub 71 */ 72 struct spdif_mixer_control { 73 /* spinlock to access control data */ 74 spinlock_t ctl_lock; 75 76 /* IEC958 channel tx status bit */ 77 unsigned char ch_status[4]; 78 79 /* User bits */ 80 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 81 82 /* Q subcode part of user bits */ 83 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 84 85 /* Buffer offset for U/Q */ 86 u32 upos; 87 u32 qpos; 88 89 /* Ready buffer index of the two buffers */ 90 u32 ready_buf; 91 }; 92 93 /** 94 * struct fsl_spdif_priv - Freescale SPDIF private data 95 * @soc: SPDIF soc data 96 * @fsl_spdif_control: SPDIF control data 97 * @cpu_dai_drv: cpu dai driver 98 * @pdev: platform device pointer 99 * @regmap: regmap handler 100 * @dpll_locked: dpll lock flag 101 * @txrate: the best rates for playback 102 * @txclk_df: STC_TXCLK_DF dividers value for playback 103 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 104 * @txclk_src: STC_TXCLK_SRC values for playback 105 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 106 * @txclk: tx clock sources for playback 107 * @rxclk: rx clock sources for capture 108 * @coreclk: core clock for register access via DMA 109 * @sysclk: system clock for rx clock rate measurement 110 * @spbaclk: SPBA clock (optional, depending on SoC design) 111 * @dma_params_tx: DMA parameters for transmit channel 112 * @dma_params_rx: DMA parameters for receive channel 113 * @regcache_srpc: regcache for SRPC 114 * @bypass: status of bypass input to output 115 */ 116 struct fsl_spdif_priv { 117 const struct fsl_spdif_soc_data *soc; 118 struct spdif_mixer_control fsl_spdif_control; 119 struct snd_soc_dai_driver cpu_dai_drv; 120 struct platform_device *pdev; 121 struct regmap *regmap; 122 bool dpll_locked; 123 u32 txrate[SPDIF_TXRATE_MAX]; 124 u8 txclk_df[SPDIF_TXRATE_MAX]; 125 u16 sysclk_df[SPDIF_TXRATE_MAX]; 126 u8 txclk_src[SPDIF_TXRATE_MAX]; 127 u8 rxclk_src; 128 struct clk *txclk[SPDIF_TXRATE_MAX]; 129 struct clk *rxclk; 130 struct clk *coreclk; 131 struct clk *sysclk; 132 struct clk *spbaclk; 133 struct snd_dmaengine_dai_dma_data dma_params_tx; 134 struct snd_dmaengine_dai_dma_data dma_params_rx; 135 /* regcache for SRPC */ 136 u32 regcache_srpc; 137 bool bypass; 138 }; 139 140 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 141 .imx = false, 142 .shared_root_clock = false, 143 .raw_capture_mode = false, 144 .interrupts = 1, 145 .tx_burst = FSL_SPDIF_TXFIFO_WML, 146 .rx_burst = FSL_SPDIF_RXFIFO_WML, 147 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 148 }; 149 150 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 151 .imx = true, 152 .shared_root_clock = false, 153 .raw_capture_mode = false, 154 .interrupts = 1, 155 .tx_burst = FSL_SPDIF_TXFIFO_WML, 156 .rx_burst = FSL_SPDIF_RXFIFO_WML, 157 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 158 }; 159 160 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 161 .imx = true, 162 .shared_root_clock = true, 163 .raw_capture_mode = false, 164 .interrupts = 1, 165 .tx_burst = FSL_SPDIF_TXFIFO_WML, 166 .rx_burst = FSL_SPDIF_RXFIFO_WML, 167 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 168 169 }; 170 171 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 172 .imx = true, 173 .shared_root_clock = true, 174 .raw_capture_mode = false, 175 .interrupts = 2, 176 .tx_burst = 2, /* Applied for EDMA */ 177 .rx_burst = 2, /* Applied for EDMA */ 178 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 179 }; 180 181 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 182 .imx = true, 183 .shared_root_clock = false, 184 .raw_capture_mode = true, 185 .interrupts = 1, 186 .tx_burst = FSL_SPDIF_TXFIFO_WML, 187 .rx_burst = FSL_SPDIF_RXFIFO_WML, 188 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 189 }; 190 191 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = { 192 .imx = true, 193 .shared_root_clock = true, 194 .raw_capture_mode = false, 195 .interrupts = 1, 196 .tx_burst = 2, /* Applied for EDMA */ 197 .rx_burst = 2, /* Applied for EDMA */ 198 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 199 }; 200 201 /* Check if clk is a root clock that does not share clock source with others */ 202 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 203 { 204 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 205 } 206 207 /* DPLL locked and lock loss interrupt handler */ 208 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 209 { 210 struct regmap *regmap = spdif_priv->regmap; 211 struct platform_device *pdev = spdif_priv->pdev; 212 u32 locked; 213 214 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 215 locked &= SRPC_DPLL_LOCKED; 216 217 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 218 locked ? "locked" : "loss lock"); 219 220 spdif_priv->dpll_locked = locked ? true : false; 221 } 222 223 /* Receiver found illegal symbol interrupt handler */ 224 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 225 { 226 struct regmap *regmap = spdif_priv->regmap; 227 struct platform_device *pdev = spdif_priv->pdev; 228 229 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 230 231 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 232 if (!spdif_priv->dpll_locked) 233 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 234 } 235 236 /* U/Q Channel receive register full */ 237 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 238 { 239 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 240 struct regmap *regmap = spdif_priv->regmap; 241 struct platform_device *pdev = spdif_priv->pdev; 242 u32 *pos, size, val, reg; 243 244 switch (name) { 245 case 'U': 246 pos = &ctrl->upos; 247 size = SPDIF_UBITS_SIZE; 248 reg = REG_SPDIF_SRU; 249 break; 250 case 'Q': 251 pos = &ctrl->qpos; 252 size = SPDIF_QSUB_SIZE; 253 reg = REG_SPDIF_SRQ; 254 break; 255 default: 256 dev_err(&pdev->dev, "unsupported channel name\n"); 257 return; 258 } 259 260 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 261 262 if (*pos >= size * 2) { 263 *pos = 0; 264 } else if (unlikely((*pos % size) + 3 > size)) { 265 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 266 return; 267 } 268 269 regmap_read(regmap, reg, &val); 270 ctrl->subcode[*pos++] = val >> 16; 271 ctrl->subcode[*pos++] = val >> 8; 272 ctrl->subcode[*pos++] = val; 273 } 274 275 /* U/Q Channel sync found */ 276 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 277 { 278 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 279 struct platform_device *pdev = spdif_priv->pdev; 280 281 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 282 283 /* U/Q buffer reset */ 284 if (ctrl->qpos == 0) 285 return; 286 287 /* Set ready to this buffer */ 288 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 289 } 290 291 /* U/Q Channel framing error */ 292 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 293 { 294 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 295 struct regmap *regmap = spdif_priv->regmap; 296 struct platform_device *pdev = spdif_priv->pdev; 297 u32 val; 298 299 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 300 301 /* Read U/Q data to clear the irq and do buffer reset */ 302 regmap_read(regmap, REG_SPDIF_SRU, &val); 303 regmap_read(regmap, REG_SPDIF_SRQ, &val); 304 305 /* Drop this U/Q buffer */ 306 ctrl->ready_buf = 0; 307 ctrl->upos = 0; 308 ctrl->qpos = 0; 309 } 310 311 /* Get spdif interrupt status and clear the interrupt */ 312 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 313 { 314 struct regmap *regmap = spdif_priv->regmap; 315 u32 val, val2; 316 317 regmap_read(regmap, REG_SPDIF_SIS, &val); 318 regmap_read(regmap, REG_SPDIF_SIE, &val2); 319 320 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 321 322 return val; 323 } 324 325 static irqreturn_t spdif_isr(int irq, void *devid) 326 { 327 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 328 struct platform_device *pdev = spdif_priv->pdev; 329 u32 sis; 330 331 sis = spdif_intr_status_clear(spdif_priv); 332 333 if (sis & INT_DPLL_LOCKED) 334 spdif_irq_dpll_lock(spdif_priv); 335 336 if (sis & INT_TXFIFO_UNOV) 337 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 338 339 if (sis & INT_TXFIFO_RESYNC) 340 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 341 342 if (sis & INT_CNEW) 343 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 344 345 if (sis & INT_VAL_NOGOOD) 346 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 347 348 if (sis & INT_SYM_ERR) 349 spdif_irq_sym_error(spdif_priv); 350 351 if (sis & INT_BIT_ERR) 352 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 353 354 if (sis & INT_URX_FUL) 355 spdif_irq_uqrx_full(spdif_priv, 'U'); 356 357 if (sis & INT_URX_OV) 358 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 359 360 if (sis & INT_QRX_FUL) 361 spdif_irq_uqrx_full(spdif_priv, 'Q'); 362 363 if (sis & INT_QRX_OV) 364 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 365 366 if (sis & INT_UQ_SYNC) 367 spdif_irq_uq_sync(spdif_priv); 368 369 if (sis & INT_UQ_ERR) 370 spdif_irq_uq_err(spdif_priv); 371 372 if (sis & INT_RXFIFO_UNOV) 373 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 374 375 if (sis & INT_RXFIFO_RESYNC) 376 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 377 378 if (sis & INT_LOSS_LOCK) 379 spdif_irq_dpll_lock(spdif_priv); 380 381 /* FIXME: Write Tx FIFO to clear TxEm */ 382 if (sis & INT_TX_EM) 383 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 384 385 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 386 if (sis & INT_RXFIFO_FUL) 387 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 388 389 return IRQ_HANDLED; 390 } 391 392 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 393 { 394 struct regmap *regmap = spdif_priv->regmap; 395 u32 val, cycle = 1000; 396 397 regcache_cache_bypass(regmap, true); 398 399 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 400 401 /* 402 * RESET bit would be cleared after finishing its reset procedure, 403 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 404 */ 405 do { 406 regmap_read(regmap, REG_SPDIF_SCR, &val); 407 } while ((val & SCR_SOFT_RESET) && cycle--); 408 409 regcache_cache_bypass(regmap, false); 410 regcache_mark_dirty(regmap); 411 regcache_sync(regmap); 412 413 if (cycle) 414 return 0; 415 else 416 return -EBUSY; 417 } 418 419 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 420 u8 mask, u8 cstatus) 421 { 422 ctrl->ch_status[3] &= ~mask; 423 ctrl->ch_status[3] |= cstatus & mask; 424 } 425 426 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 427 { 428 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 429 struct regmap *regmap = spdif_priv->regmap; 430 struct platform_device *pdev = spdif_priv->pdev; 431 u32 ch_status; 432 433 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 434 (bitrev8(ctrl->ch_status[1]) << 8) | 435 bitrev8(ctrl->ch_status[2]); 436 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 437 438 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 439 440 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 441 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 442 443 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 444 } 445 446 /* Set SPDIF PhaseConfig register for rx clock */ 447 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 448 enum spdif_gainsel gainsel, int dpll_locked) 449 { 450 struct regmap *regmap = spdif_priv->regmap; 451 u8 clksrc = spdif_priv->rxclk_src; 452 453 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 454 return -EINVAL; 455 456 regmap_update_bits(regmap, REG_SPDIF_SRPC, 457 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 458 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 459 460 return 0; 461 } 462 463 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 464 int sample_rate) 465 { 466 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 467 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 468 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 469 struct regmap *regmap = spdif_priv->regmap; 470 struct platform_device *pdev = spdif_priv->pdev; 471 unsigned long csfs = 0; 472 u32 stc, mask, rate; 473 u16 sysclk_df; 474 u8 clk, txclk_df; 475 int ret; 476 477 switch (sample_rate) { 478 case 32000: 479 rate = SPDIF_TXRATE_32000; 480 csfs = IEC958_AES3_CON_FS_32000; 481 break; 482 case 44100: 483 rate = SPDIF_TXRATE_44100; 484 csfs = IEC958_AES3_CON_FS_44100; 485 break; 486 case 48000: 487 rate = SPDIF_TXRATE_48000; 488 csfs = IEC958_AES3_CON_FS_48000; 489 break; 490 case 88200: 491 rate = SPDIF_TXRATE_88200; 492 csfs = IEC958_AES3_CON_FS_88200; 493 break; 494 case 96000: 495 rate = SPDIF_TXRATE_96000; 496 csfs = IEC958_AES3_CON_FS_96000; 497 break; 498 case 176400: 499 rate = SPDIF_TXRATE_176400; 500 csfs = IEC958_AES3_CON_FS_176400; 501 break; 502 case 192000: 503 rate = SPDIF_TXRATE_192000; 504 csfs = IEC958_AES3_CON_FS_192000; 505 break; 506 default: 507 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 508 return -EINVAL; 509 } 510 511 clk = spdif_priv->txclk_src[rate]; 512 if (clk >= STC_TXCLK_SRC_MAX) { 513 dev_err(&pdev->dev, "tx clock source is out of range\n"); 514 return -EINVAL; 515 } 516 517 txclk_df = spdif_priv->txclk_df[rate]; 518 if (txclk_df == 0) { 519 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 520 return -EINVAL; 521 } 522 523 sysclk_df = spdif_priv->sysclk_df[rate]; 524 525 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 526 goto clk_set_bypass; 527 528 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 529 ret = clk_set_rate(spdif_priv->txclk[rate], 530 64 * sample_rate * txclk_df); 531 if (ret) { 532 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 533 return ret; 534 } 535 536 clk_set_bypass: 537 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 538 (64 * sample_rate * txclk_df * sysclk_df)); 539 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 540 clk_get_rate(spdif_priv->txclk[rate])); 541 542 /* set fs field in consumer channel status */ 543 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 544 545 /* select clock source and divisor */ 546 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 547 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 548 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 549 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 550 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 551 552 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 553 spdif_priv->txrate[rate], sample_rate); 554 555 return 0; 556 } 557 558 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 559 struct snd_soc_dai *cpu_dai) 560 { 561 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 562 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 563 struct platform_device *pdev = spdif_priv->pdev; 564 struct regmap *regmap = spdif_priv->regmap; 565 u32 scr, mask; 566 int ret; 567 568 /* Reset module and interrupts only for first initialization */ 569 if (!snd_soc_dai_active(cpu_dai)) { 570 ret = spdif_softreset(spdif_priv); 571 if (ret) { 572 dev_err(&pdev->dev, "failed to soft reset\n"); 573 return ret; 574 } 575 576 /* Disable all the interrupts */ 577 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 578 } 579 580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 581 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 582 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 583 SCR_TXFIFO_FSEL_IF8; 584 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 585 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 586 SCR_TXFIFO_FSEL_MASK; 587 } else { 588 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 589 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 590 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 591 } 592 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 593 594 /* Power up SPDIF module */ 595 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 596 597 return 0; 598 } 599 600 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 601 struct snd_soc_dai *cpu_dai) 602 { 603 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 604 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 605 struct regmap *regmap = spdif_priv->regmap; 606 u32 scr, mask; 607 608 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 609 scr = 0; 610 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 611 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 612 SCR_TXFIFO_FSEL_MASK; 613 } else { 614 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 615 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 616 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 617 } 618 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 619 620 /* Power down SPDIF module only if tx&rx are both inactive */ 621 if (!snd_soc_dai_active(cpu_dai)) { 622 spdif_intr_status_clear(spdif_priv); 623 regmap_update_bits(regmap, REG_SPDIF_SCR, 624 SCR_LOW_POWER, SCR_LOW_POWER); 625 } 626 } 627 628 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 629 struct snd_pcm_hw_params *params, 630 struct snd_soc_dai *dai) 631 { 632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 633 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 634 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 635 struct platform_device *pdev = spdif_priv->pdev; 636 u32 sample_rate = params_rate(params); 637 int ret = 0; 638 639 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 640 ret = spdif_set_sample_rate(substream, sample_rate); 641 if (ret) { 642 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 643 __func__, sample_rate); 644 return ret; 645 } 646 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 647 IEC958_AES3_CON_CLOCK_1000PPM); 648 spdif_write_channel_status(spdif_priv); 649 } else { 650 /* Setup rx clock source */ 651 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 652 } 653 654 return ret; 655 } 656 657 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 658 int cmd, struct snd_soc_dai *dai) 659 { 660 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 661 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 662 struct regmap *regmap = spdif_priv->regmap; 663 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 664 u32 intr = SIE_INTR_FOR(tx); 665 u32 dmaen = SCR_DMA_xX_EN(tx); 666 667 switch (cmd) { 668 case SNDRV_PCM_TRIGGER_START: 669 case SNDRV_PCM_TRIGGER_RESUME: 670 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 671 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 672 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 673 break; 674 case SNDRV_PCM_TRIGGER_STOP: 675 case SNDRV_PCM_TRIGGER_SUSPEND: 676 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 677 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 678 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 679 break; 680 default: 681 return -EINVAL; 682 } 683 684 return 0; 685 } 686 687 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 688 .startup = fsl_spdif_startup, 689 .hw_params = fsl_spdif_hw_params, 690 .trigger = fsl_spdif_trigger, 691 .shutdown = fsl_spdif_shutdown, 692 }; 693 694 695 /* 696 * FSL SPDIF IEC958 controller(mixer) functions 697 * 698 * Channel status get/put control 699 * User bit value get/put control 700 * Valid bit value get control 701 * DPLL lock status get control 702 * User bit sync mode selection control 703 */ 704 705 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 706 struct snd_ctl_elem_info *uinfo) 707 { 708 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 709 uinfo->count = 1; 710 711 return 0; 712 } 713 714 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 715 struct snd_ctl_elem_value *uvalue) 716 { 717 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 718 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 719 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 720 721 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 722 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 723 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 724 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 725 726 return 0; 727 } 728 729 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 730 struct snd_ctl_elem_value *uvalue) 731 { 732 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 733 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 734 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 735 736 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 737 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 738 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 739 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 740 741 spdif_write_channel_status(spdif_priv); 742 743 return 0; 744 } 745 746 /* Get channel status from SPDIF_RX_CCHAN register */ 747 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 748 struct snd_ctl_elem_value *ucontrol) 749 { 750 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 751 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 752 struct regmap *regmap = spdif_priv->regmap; 753 u32 cstatus, val; 754 755 regmap_read(regmap, REG_SPDIF_SIS, &val); 756 if (!(val & INT_CNEW)) 757 return -EAGAIN; 758 759 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 760 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 761 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 762 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 763 764 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 765 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 766 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 767 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 768 769 /* Clear intr */ 770 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 771 772 return 0; 773 } 774 775 /* 776 * Get User bits (subcode) from chip value which readed out 777 * in UChannel register. 778 */ 779 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 780 struct snd_ctl_elem_value *ucontrol) 781 { 782 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 783 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 784 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 785 unsigned long flags; 786 int ret = -EAGAIN; 787 788 spin_lock_irqsave(&ctrl->ctl_lock, flags); 789 if (ctrl->ready_buf) { 790 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 791 memcpy(&ucontrol->value.iec958.subcode[0], 792 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 793 ret = 0; 794 } 795 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 796 797 return ret; 798 } 799 800 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 801 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 802 struct snd_ctl_elem_info *uinfo) 803 { 804 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 805 uinfo->count = SPDIF_QSUB_SIZE; 806 807 return 0; 808 } 809 810 /* Get Q subcode from chip value which readed out in QChannel register */ 811 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 812 struct snd_ctl_elem_value *ucontrol) 813 { 814 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 815 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 816 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 817 unsigned long flags; 818 int ret = -EAGAIN; 819 820 spin_lock_irqsave(&ctrl->ctl_lock, flags); 821 if (ctrl->ready_buf) { 822 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 823 memcpy(&ucontrol->value.bytes.data[0], 824 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 825 ret = 0; 826 } 827 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 828 829 return ret; 830 } 831 832 /* Get valid good bit from interrupt status register */ 833 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 834 struct snd_ctl_elem_value *ucontrol) 835 { 836 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 837 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 838 struct regmap *regmap = spdif_priv->regmap; 839 u32 val; 840 841 regmap_read(regmap, REG_SPDIF_SIS, &val); 842 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 843 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 844 845 return 0; 846 } 847 848 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 849 struct snd_ctl_elem_value *ucontrol) 850 { 851 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 852 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 853 struct regmap *regmap = spdif_priv->regmap; 854 u32 val; 855 856 regmap_read(regmap, REG_SPDIF_SCR, &val); 857 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 858 val = 1 - val; 859 ucontrol->value.integer.value[0] = val; 860 861 return 0; 862 } 863 864 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 865 struct snd_ctl_elem_value *ucontrol) 866 { 867 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 868 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 869 struct regmap *regmap = spdif_priv->regmap; 870 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 871 872 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 873 874 return 0; 875 } 876 877 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 878 struct snd_ctl_elem_value *ucontrol) 879 { 880 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 881 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 882 struct regmap *regmap = spdif_priv->regmap; 883 u32 val; 884 885 regmap_read(regmap, REG_SPDIF_SCR, &val); 886 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 887 ucontrol->value.integer.value[0] = val; 888 889 return 0; 890 } 891 892 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 893 struct snd_ctl_elem_value *ucontrol) 894 { 895 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 896 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 897 struct regmap *regmap = spdif_priv->regmap; 898 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 899 900 if (val) 901 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 902 else 903 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 904 905 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 906 907 return 0; 908 } 909 910 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol, 911 struct snd_ctl_elem_value *ucontrol) 912 { 913 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 914 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 915 916 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; 917 918 return 0; 919 } 920 921 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol, 922 struct snd_ctl_elem_value *ucontrol) 923 { 924 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 925 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 926 struct snd_soc_card *card = dai->component->card; 927 bool set = (ucontrol->value.integer.value[0] != 0); 928 struct regmap *regmap = priv->regmap; 929 struct snd_soc_pcm_runtime *rtd; 930 u32 scr, mask; 931 int stream; 932 933 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 934 935 if (priv->bypass == set) 936 return 0; /* nothing to do */ 937 938 if (snd_soc_dai_active(dai)) { 939 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); 940 return -EBUSY; 941 } 942 943 pm_runtime_get_sync(dai->dev); 944 945 if (set) { 946 /* Disable interrupts */ 947 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 948 949 /* Configure BYPASS mode */ 950 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF; 951 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK | 952 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK; 953 /* Power up SPDIF module */ 954 mask |= SCR_LOW_POWER; 955 } else { 956 /* Power down SPDIF module, disable TX */ 957 scr = SCR_LOW_POWER | SCR_TXSEL_OFF; 958 mask = SCR_LOW_POWER | SCR_TXSEL_MASK; 959 } 960 961 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 962 963 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */ 964 for_each_pcm_streams(stream) 965 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); 966 967 priv->bypass = set; 968 pm_runtime_put_sync(dai->dev); 969 970 return 0; 971 } 972 973 /* DPLL lock information */ 974 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 975 struct snd_ctl_elem_info *uinfo) 976 { 977 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 978 uinfo->count = 1; 979 uinfo->value.integer.min = 16000; 980 uinfo->value.integer.max = 192000; 981 982 return 0; 983 } 984 985 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 986 24, 16, 12, 8, 6, 4, 3, 987 }; 988 989 /* Get RX data clock rate given the SPDIF bus_clk */ 990 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 991 enum spdif_gainsel gainsel) 992 { 993 struct regmap *regmap = spdif_priv->regmap; 994 struct platform_device *pdev = spdif_priv->pdev; 995 u64 tmpval64, busclk_freq = 0; 996 u32 freqmeas, phaseconf; 997 u8 clksrc; 998 999 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 1000 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 1001 1002 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 1003 1004 /* Get bus clock from system */ 1005 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 1006 busclk_freq = clk_get_rate(spdif_priv->sysclk); 1007 1008 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 1009 tmpval64 = (u64) busclk_freq * freqmeas; 1010 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 1011 do_div(tmpval64, 128 * 1024); 1012 1013 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 1014 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 1015 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 1016 1017 return (int)tmpval64; 1018 } 1019 1020 /* 1021 * Get DPLL lock or not info from stable interrupt status register. 1022 * User application must use this control to get locked, 1023 * then can do next PCM operation 1024 */ 1025 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 1026 struct snd_ctl_elem_value *ucontrol) 1027 { 1028 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1029 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1030 int rate = 0; 1031 1032 if (spdif_priv->dpll_locked) 1033 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 1034 1035 ucontrol->value.integer.value[0] = rate; 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * User bit sync mode: 1042 * 1 CD User channel subcode 1043 * 0 Non-CD data 1044 */ 1045 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 1046 struct snd_ctl_elem_value *ucontrol) 1047 { 1048 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1049 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1050 struct regmap *regmap = spdif_priv->regmap; 1051 u32 val; 1052 1053 regmap_read(regmap, REG_SPDIF_SRCD, &val); 1054 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 1055 1056 return 0; 1057 } 1058 1059 /* 1060 * User bit sync mode: 1061 * 1 CD User channel subcode 1062 * 0 Non-CD data 1063 */ 1064 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 1065 struct snd_ctl_elem_value *ucontrol) 1066 { 1067 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1068 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1069 struct regmap *regmap = spdif_priv->regmap; 1070 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 1071 1072 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 1073 1074 return 0; 1075 } 1076 1077 /* FSL SPDIF IEC958 controller defines */ 1078 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1079 /* Status cchanel controller */ 1080 { 1081 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1082 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1083 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1084 SNDRV_CTL_ELEM_ACCESS_WRITE | 1085 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1086 .info = fsl_spdif_info, 1087 .get = fsl_spdif_pb_get, 1088 .put = fsl_spdif_pb_put, 1089 }, 1090 { 1091 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1092 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1093 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1094 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1095 .info = fsl_spdif_info, 1096 .get = fsl_spdif_capture_get, 1097 }, 1098 /* User bits controller */ 1099 { 1100 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1101 .name = "IEC958 Subcode Capture Default", 1102 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1103 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1104 .info = fsl_spdif_info, 1105 .get = fsl_spdif_subcode_get, 1106 }, 1107 { 1108 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1109 .name = "IEC958 Q-subcode Capture Default", 1110 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1111 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1112 .info = fsl_spdif_qinfo, 1113 .get = fsl_spdif_qget, 1114 }, 1115 /* Valid bit error controller */ 1116 { 1117 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1118 .name = "IEC958 RX V-Bit Errors", 1119 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1120 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1121 .info = snd_ctl_boolean_mono_info, 1122 .get = fsl_spdif_rx_vbit_get, 1123 }, 1124 { 1125 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1126 .name = "IEC958 TX V-Bit", 1127 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1128 SNDRV_CTL_ELEM_ACCESS_WRITE | 1129 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1130 .info = snd_ctl_boolean_mono_info, 1131 .get = fsl_spdif_tx_vbit_get, 1132 .put = fsl_spdif_tx_vbit_put, 1133 }, 1134 /* DPLL lock info get controller */ 1135 { 1136 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1137 .name = "RX Sample Rate", 1138 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1139 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1140 .info = fsl_spdif_rxrate_info, 1141 .get = fsl_spdif_rxrate_get, 1142 }, 1143 /* RX bypass controller */ 1144 { 1145 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1146 .name = "Bypass Mode", 1147 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1148 .info = snd_ctl_boolean_mono_info, 1149 .get = fsl_spdif_bypass_get, 1150 .put = fsl_spdif_bypass_put, 1151 }, 1152 /* User bit sync mode set/get controller */ 1153 { 1154 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1155 .name = "IEC958 USyncMode CDText", 1156 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1157 SNDRV_CTL_ELEM_ACCESS_WRITE | 1158 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1159 .info = snd_ctl_boolean_mono_info, 1160 .get = fsl_spdif_usync_get, 1161 .put = fsl_spdif_usync_put, 1162 }, 1163 }; 1164 1165 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1166 { 1167 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1168 .name = "IEC958 Raw Capture Mode", 1169 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1170 SNDRV_CTL_ELEM_ACCESS_WRITE | 1171 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1172 .info = snd_ctl_boolean_mono_info, 1173 .get = fsl_spdif_rx_rcm_get, 1174 .put = fsl_spdif_rx_rcm_put, 1175 }, 1176 }; 1177 1178 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1179 { 1180 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1181 1182 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1183 &spdif_private->dma_params_rx); 1184 1185 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1186 1187 if (spdif_private->soc->raw_capture_mode) 1188 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1189 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1190 1191 /*Clear the val bit for Tx*/ 1192 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1193 SCR_VAL_MASK, SCR_VAL_CLEAR); 1194 1195 return 0; 1196 } 1197 1198 static struct snd_soc_dai_driver fsl_spdif_dai = { 1199 .probe = &fsl_spdif_dai_probe, 1200 .playback = { 1201 .stream_name = "CPU-Playback", 1202 .channels_min = 2, 1203 .channels_max = 2, 1204 .rates = FSL_SPDIF_RATES_PLAYBACK, 1205 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1206 }, 1207 .capture = { 1208 .stream_name = "CPU-Capture", 1209 .channels_min = 2, 1210 .channels_max = 2, 1211 .rates = FSL_SPDIF_RATES_CAPTURE, 1212 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1213 }, 1214 .ops = &fsl_spdif_dai_ops, 1215 }; 1216 1217 static const struct snd_soc_component_driver fsl_spdif_component = { 1218 .name = "fsl-spdif", 1219 }; 1220 1221 /* FSL SPDIF REGMAP */ 1222 static const struct reg_default fsl_spdif_reg_defaults[] = { 1223 {REG_SPDIF_SCR, 0x00000400}, 1224 {REG_SPDIF_SRCD, 0x00000000}, 1225 {REG_SPDIF_SIE, 0x00000000}, 1226 {REG_SPDIF_STL, 0x00000000}, 1227 {REG_SPDIF_STR, 0x00000000}, 1228 {REG_SPDIF_STCSCH, 0x00000000}, 1229 {REG_SPDIF_STCSCL, 0x00000000}, 1230 {REG_SPDIF_STC, 0x00020f00}, 1231 }; 1232 1233 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1234 { 1235 switch (reg) { 1236 case REG_SPDIF_SCR: 1237 case REG_SPDIF_SRCD: 1238 case REG_SPDIF_SRPC: 1239 case REG_SPDIF_SIE: 1240 case REG_SPDIF_SIS: 1241 case REG_SPDIF_SRL: 1242 case REG_SPDIF_SRR: 1243 case REG_SPDIF_SRCSH: 1244 case REG_SPDIF_SRCSL: 1245 case REG_SPDIF_SRU: 1246 case REG_SPDIF_SRQ: 1247 case REG_SPDIF_STCSCH: 1248 case REG_SPDIF_STCSCL: 1249 case REG_SPDIF_SRFM: 1250 case REG_SPDIF_STC: 1251 return true; 1252 default: 1253 return false; 1254 } 1255 } 1256 1257 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1258 { 1259 switch (reg) { 1260 case REG_SPDIF_SRPC: 1261 case REG_SPDIF_SIS: 1262 case REG_SPDIF_SRL: 1263 case REG_SPDIF_SRR: 1264 case REG_SPDIF_SRCSH: 1265 case REG_SPDIF_SRCSL: 1266 case REG_SPDIF_SRU: 1267 case REG_SPDIF_SRQ: 1268 case REG_SPDIF_SRFM: 1269 return true; 1270 default: 1271 return false; 1272 } 1273 } 1274 1275 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1276 { 1277 switch (reg) { 1278 case REG_SPDIF_SCR: 1279 case REG_SPDIF_SRCD: 1280 case REG_SPDIF_SRPC: 1281 case REG_SPDIF_SIE: 1282 case REG_SPDIF_SIC: 1283 case REG_SPDIF_STL: 1284 case REG_SPDIF_STR: 1285 case REG_SPDIF_STCSCH: 1286 case REG_SPDIF_STCSCL: 1287 case REG_SPDIF_STC: 1288 return true; 1289 default: 1290 return false; 1291 } 1292 } 1293 1294 static const struct regmap_config fsl_spdif_regmap_config = { 1295 .reg_bits = 32, 1296 .reg_stride = 4, 1297 .val_bits = 32, 1298 1299 .max_register = REG_SPDIF_STC, 1300 .reg_defaults = fsl_spdif_reg_defaults, 1301 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1302 .readable_reg = fsl_spdif_readable_reg, 1303 .volatile_reg = fsl_spdif_volatile_reg, 1304 .writeable_reg = fsl_spdif_writeable_reg, 1305 .cache_type = REGCACHE_FLAT, 1306 }; 1307 1308 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1309 struct clk *clk, u64 savesub, 1310 enum spdif_txrate index, bool round) 1311 { 1312 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1313 192000, }; 1314 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1315 u64 rate_ideal, rate_actual, sub; 1316 u32 arate; 1317 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1318 u8 txclk_df; 1319 1320 /* The sysclk has an extra divisor [2, 512] */ 1321 sysclk_dfmin = is_sysclk ? 2 : 1; 1322 sysclk_dfmax = is_sysclk ? 512 : 1; 1323 1324 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1325 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1326 rate_ideal = rate[index] * txclk_df * 64ULL; 1327 if (round) 1328 rate_actual = clk_round_rate(clk, rate_ideal); 1329 else 1330 rate_actual = clk_get_rate(clk); 1331 1332 arate = rate_actual / 64; 1333 arate /= txclk_df * sysclk_df; 1334 1335 if (arate == rate[index]) { 1336 /* We are lucky */ 1337 savesub = 0; 1338 spdif_priv->txclk_df[index] = txclk_df; 1339 spdif_priv->sysclk_df[index] = sysclk_df; 1340 spdif_priv->txrate[index] = arate; 1341 goto out; 1342 } else if (arate / rate[index] == 1) { 1343 /* A little bigger than expect */ 1344 sub = (u64)(arate - rate[index]) * 100000; 1345 do_div(sub, rate[index]); 1346 if (sub >= savesub) 1347 continue; 1348 savesub = sub; 1349 spdif_priv->txclk_df[index] = txclk_df; 1350 spdif_priv->sysclk_df[index] = sysclk_df; 1351 spdif_priv->txrate[index] = arate; 1352 } else if (rate[index] / arate == 1) { 1353 /* A little smaller than expect */ 1354 sub = (u64)(rate[index] - arate) * 100000; 1355 do_div(sub, rate[index]); 1356 if (sub >= savesub) 1357 continue; 1358 savesub = sub; 1359 spdif_priv->txclk_df[index] = txclk_df; 1360 spdif_priv->sysclk_df[index] = sysclk_df; 1361 spdif_priv->txrate[index] = arate; 1362 } 1363 } 1364 } 1365 1366 out: 1367 return savesub; 1368 } 1369 1370 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1371 enum spdif_txrate index) 1372 { 1373 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1374 192000, }; 1375 struct platform_device *pdev = spdif_priv->pdev; 1376 struct device *dev = &pdev->dev; 1377 u64 savesub = 100000, ret; 1378 struct clk *clk; 1379 char tmp[16]; 1380 int i; 1381 1382 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1383 sprintf(tmp, "rxtx%d", i); 1384 clk = devm_clk_get(dev, tmp); 1385 if (IS_ERR(clk)) { 1386 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1387 return PTR_ERR(clk); 1388 } 1389 if (!clk_get_rate(clk)) 1390 continue; 1391 1392 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1393 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1394 if (savesub == ret) 1395 continue; 1396 1397 savesub = ret; 1398 spdif_priv->txclk[index] = clk; 1399 spdif_priv->txclk_src[index] = i; 1400 1401 /* To quick catch a divisor, we allow a 0.1% deviation */ 1402 if (savesub < 100) 1403 break; 1404 } 1405 1406 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1407 spdif_priv->txclk_src[index], rate[index]); 1408 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1409 spdif_priv->txclk_df[index], rate[index]); 1410 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1411 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1412 spdif_priv->sysclk_df[index], rate[index]); 1413 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1414 rate[index], spdif_priv->txrate[index]); 1415 1416 return 0; 1417 } 1418 1419 static int fsl_spdif_probe(struct platform_device *pdev) 1420 { 1421 struct fsl_spdif_priv *spdif_priv; 1422 struct spdif_mixer_control *ctrl; 1423 struct resource *res; 1424 void __iomem *regs; 1425 int irq, ret, i; 1426 1427 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1428 if (!spdif_priv) 1429 return -ENOMEM; 1430 1431 spdif_priv->pdev = pdev; 1432 1433 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1434 1435 /* Initialize this copy of the CPU DAI driver structure */ 1436 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1437 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1438 spdif_priv->cpu_dai_drv.playback.formats = 1439 spdif_priv->soc->tx_formats; 1440 1441 /* Get the addresses and IRQ */ 1442 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1443 if (IS_ERR(regs)) 1444 return PTR_ERR(regs); 1445 1446 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1447 if (IS_ERR(spdif_priv->regmap)) { 1448 dev_err(&pdev->dev, "regmap init failed\n"); 1449 return PTR_ERR(spdif_priv->regmap); 1450 } 1451 1452 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1453 irq = platform_get_irq(pdev, i); 1454 if (irq < 0) 1455 return irq; 1456 1457 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1458 dev_name(&pdev->dev), spdif_priv); 1459 if (ret) { 1460 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1461 return ret; 1462 } 1463 } 1464 1465 /* Get system clock for rx clock rate calculation */ 1466 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1467 if (IS_ERR(spdif_priv->sysclk)) { 1468 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1469 return PTR_ERR(spdif_priv->sysclk); 1470 } 1471 1472 /* Get core clock for data register access via DMA */ 1473 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1474 if (IS_ERR(spdif_priv->coreclk)) { 1475 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1476 return PTR_ERR(spdif_priv->coreclk); 1477 } 1478 1479 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1480 if (IS_ERR(spdif_priv->spbaclk)) 1481 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1482 1483 /* Select clock source for rx/tx clock */ 1484 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1485 if (IS_ERR(spdif_priv->rxclk)) { 1486 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1487 return PTR_ERR(spdif_priv->rxclk); 1488 } 1489 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1490 1491 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1492 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1493 if (ret) 1494 return ret; 1495 } 1496 1497 /* Initial spinlock for control data */ 1498 ctrl = &spdif_priv->fsl_spdif_control; 1499 spin_lock_init(&ctrl->ctl_lock); 1500 1501 /* Init tx channel status default value */ 1502 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1503 IEC958_AES0_CON_EMPHASIS_5015; 1504 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1505 ctrl->ch_status[2] = 0x00; 1506 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1507 IEC958_AES3_CON_CLOCK_1000PPM; 1508 1509 spdif_priv->dpll_locked = false; 1510 1511 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1512 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1513 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1514 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1515 1516 /* Register with ASoC */ 1517 dev_set_drvdata(&pdev->dev, spdif_priv); 1518 pm_runtime_enable(&pdev->dev); 1519 regcache_cache_only(spdif_priv->regmap, true); 1520 1521 /* 1522 * Register platform component before registering cpu dai for there 1523 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1524 */ 1525 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1526 if (ret) { 1527 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1528 goto err_pm_disable; 1529 } 1530 1531 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1532 &spdif_priv->cpu_dai_drv, 1); 1533 if (ret) { 1534 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1535 goto err_pm_disable; 1536 } 1537 1538 return ret; 1539 1540 err_pm_disable: 1541 pm_runtime_disable(&pdev->dev); 1542 return ret; 1543 } 1544 1545 static int fsl_spdif_remove(struct platform_device *pdev) 1546 { 1547 pm_runtime_disable(&pdev->dev); 1548 1549 return 0; 1550 } 1551 1552 #ifdef CONFIG_PM 1553 static int fsl_spdif_runtime_suspend(struct device *dev) 1554 { 1555 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1556 int i; 1557 1558 /* Disable all the interrupts */ 1559 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1560 1561 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1562 &spdif_priv->regcache_srpc); 1563 regcache_cache_only(spdif_priv->regmap, true); 1564 1565 clk_disable_unprepare(spdif_priv->rxclk); 1566 1567 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 1568 clk_disable_unprepare(spdif_priv->txclk[i]); 1569 1570 if (!IS_ERR(spdif_priv->spbaclk)) 1571 clk_disable_unprepare(spdif_priv->spbaclk); 1572 clk_disable_unprepare(spdif_priv->coreclk); 1573 1574 return 0; 1575 } 1576 1577 static int fsl_spdif_runtime_resume(struct device *dev) 1578 { 1579 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1580 int ret; 1581 int i; 1582 1583 ret = clk_prepare_enable(spdif_priv->coreclk); 1584 if (ret) { 1585 dev_err(dev, "failed to enable core clock\n"); 1586 return ret; 1587 } 1588 1589 if (!IS_ERR(spdif_priv->spbaclk)) { 1590 ret = clk_prepare_enable(spdif_priv->spbaclk); 1591 if (ret) { 1592 dev_err(dev, "failed to enable spba clock\n"); 1593 goto disable_core_clk; 1594 } 1595 } 1596 1597 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1598 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1599 if (ret) 1600 goto disable_tx_clk; 1601 } 1602 1603 ret = clk_prepare_enable(spdif_priv->rxclk); 1604 if (ret) 1605 goto disable_tx_clk; 1606 1607 regcache_cache_only(spdif_priv->regmap, false); 1608 regcache_mark_dirty(spdif_priv->regmap); 1609 1610 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1611 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1612 spdif_priv->regcache_srpc); 1613 1614 ret = regcache_sync(spdif_priv->regmap); 1615 if (ret) 1616 goto disable_rx_clk; 1617 1618 return 0; 1619 1620 disable_rx_clk: 1621 clk_disable_unprepare(spdif_priv->rxclk); 1622 disable_tx_clk: 1623 for (i--; i >= 0; i--) 1624 clk_disable_unprepare(spdif_priv->txclk[i]); 1625 if (!IS_ERR(spdif_priv->spbaclk)) 1626 clk_disable_unprepare(spdif_priv->spbaclk); 1627 disable_core_clk: 1628 clk_disable_unprepare(spdif_priv->coreclk); 1629 1630 return ret; 1631 } 1632 #endif /* CONFIG_PM */ 1633 1634 static const struct dev_pm_ops fsl_spdif_pm = { 1635 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1636 pm_runtime_force_resume) 1637 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1638 NULL) 1639 }; 1640 1641 static const struct of_device_id fsl_spdif_dt_ids[] = { 1642 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1643 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1644 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1645 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1646 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1647 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, }, 1648 {} 1649 }; 1650 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1651 1652 static struct platform_driver fsl_spdif_driver = { 1653 .driver = { 1654 .name = "fsl-spdif-dai", 1655 .of_match_table = fsl_spdif_dt_ids, 1656 .pm = &fsl_spdif_pm, 1657 }, 1658 .probe = fsl_spdif_probe, 1659 .remove = fsl_spdif_remove, 1660 }; 1661 1662 module_platform_driver(fsl_spdif_driver); 1663 1664 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1665 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1666 MODULE_LICENSE("GPL v2"); 1667 MODULE_ALIAS("platform:fsl-spdif-dai"); 1668