1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SPDIF_TXFIFO_WML 0x8 29 #define FSL_SPDIF_RXFIFO_WML 0x8 30 31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 35 INT_LOSS_LOCK | INT_DPLL_LOCKED) 36 37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 38 39 /* Index list for the values that has if (DPLL Locked) condition */ 40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 41 #define SRPC_NODPLL_START1 0x5 42 #define SRPC_NODPLL_START2 0xc 43 44 #define DEFAULT_RXCLK_SRC 1 45 46 /** 47 * struct fsl_spdif_soc_data: soc specific data 48 * 49 * @imx: for imx platform 50 * @shared_root_clock: flag of sharing a clock source with others; 51 * so the driver shouldn't set root clock rate 52 * @interrupts: interrupt number 53 * @tx_burst: tx maxburst size 54 * @rx_burst: rx maxburst size 55 * @tx_formats: tx supported data format 56 */ 57 struct fsl_spdif_soc_data { 58 bool imx; 59 bool shared_root_clock; 60 u32 interrupts; 61 u32 tx_burst; 62 u32 rx_burst; 63 u64 tx_formats; 64 }; 65 66 /* 67 * SPDIF control structure 68 * Defines channel status, subcode and Q sub 69 */ 70 struct spdif_mixer_control { 71 /* spinlock to access control data */ 72 spinlock_t ctl_lock; 73 74 /* IEC958 channel tx status bit */ 75 unsigned char ch_status[4]; 76 77 /* User bits */ 78 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 79 80 /* Q subcode part of user bits */ 81 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 82 83 /* Buffer offset for U/Q */ 84 u32 upos; 85 u32 qpos; 86 87 /* Ready buffer index of the two buffers */ 88 u32 ready_buf; 89 }; 90 91 /** 92 * struct fsl_spdif_priv - Freescale SPDIF private data 93 * @soc: SPDIF soc data 94 * @fsl_spdif_control: SPDIF control data 95 * @cpu_dai_drv: cpu dai driver 96 * @pdev: platform device pointer 97 * @regmap: regmap handler 98 * @dpll_locked: dpll lock flag 99 * @txrate: the best rates for playback 100 * @txclk_df: STC_TXCLK_DF dividers value for playback 101 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 102 * @txclk_src: STC_TXCLK_SRC values for playback 103 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 104 * @txclk: tx clock sources for playback 105 * @rxclk: rx clock sources for capture 106 * @coreclk: core clock for register access via DMA 107 * @sysclk: system clock for rx clock rate measurement 108 * @spbaclk: SPBA clock (optional, depending on SoC design) 109 * @dma_params_tx: DMA parameters for transmit channel 110 * @dma_params_rx: DMA parameters for receive channel 111 * @regcache_srpc: regcache for SRPC 112 */ 113 struct fsl_spdif_priv { 114 const struct fsl_spdif_soc_data *soc; 115 struct spdif_mixer_control fsl_spdif_control; 116 struct snd_soc_dai_driver cpu_dai_drv; 117 struct platform_device *pdev; 118 struct regmap *regmap; 119 bool dpll_locked; 120 u32 txrate[SPDIF_TXRATE_MAX]; 121 u8 txclk_df[SPDIF_TXRATE_MAX]; 122 u16 sysclk_df[SPDIF_TXRATE_MAX]; 123 u8 txclk_src[SPDIF_TXRATE_MAX]; 124 u8 rxclk_src; 125 struct clk *txclk[SPDIF_TXRATE_MAX]; 126 struct clk *rxclk; 127 struct clk *coreclk; 128 struct clk *sysclk; 129 struct clk *spbaclk; 130 struct snd_dmaengine_dai_dma_data dma_params_tx; 131 struct snd_dmaengine_dai_dma_data dma_params_rx; 132 /* regcache for SRPC */ 133 u32 regcache_srpc; 134 }; 135 136 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 137 .imx = false, 138 .shared_root_clock = false, 139 .interrupts = 1, 140 .tx_burst = FSL_SPDIF_TXFIFO_WML, 141 .rx_burst = FSL_SPDIF_RXFIFO_WML, 142 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 143 }; 144 145 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 146 .imx = true, 147 .shared_root_clock = false, 148 .interrupts = 1, 149 .tx_burst = FSL_SPDIF_TXFIFO_WML, 150 .rx_burst = FSL_SPDIF_RXFIFO_WML, 151 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 152 }; 153 154 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 155 .imx = true, 156 .shared_root_clock = true, 157 .interrupts = 1, 158 .tx_burst = FSL_SPDIF_TXFIFO_WML, 159 .rx_burst = FSL_SPDIF_RXFIFO_WML, 160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 161 162 }; 163 164 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 165 .imx = true, 166 .shared_root_clock = true, 167 .interrupts = 2, 168 .tx_burst = 2, /* Applied for EDMA */ 169 .rx_burst = 2, /* Applied for EDMA */ 170 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 171 }; 172 173 /* Check if clk is a root clock that does not share clock source with others */ 174 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 175 { 176 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 177 } 178 179 /* DPLL locked and lock loss interrupt handler */ 180 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 181 { 182 struct regmap *regmap = spdif_priv->regmap; 183 struct platform_device *pdev = spdif_priv->pdev; 184 u32 locked; 185 186 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 187 locked &= SRPC_DPLL_LOCKED; 188 189 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 190 locked ? "locked" : "loss lock"); 191 192 spdif_priv->dpll_locked = locked ? true : false; 193 } 194 195 /* Receiver found illegal symbol interrupt handler */ 196 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 197 { 198 struct regmap *regmap = spdif_priv->regmap; 199 struct platform_device *pdev = spdif_priv->pdev; 200 201 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 202 203 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 204 if (!spdif_priv->dpll_locked) 205 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 206 } 207 208 /* U/Q Channel receive register full */ 209 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 210 { 211 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 212 struct regmap *regmap = spdif_priv->regmap; 213 struct platform_device *pdev = spdif_priv->pdev; 214 u32 *pos, size, val, reg; 215 216 switch (name) { 217 case 'U': 218 pos = &ctrl->upos; 219 size = SPDIF_UBITS_SIZE; 220 reg = REG_SPDIF_SRU; 221 break; 222 case 'Q': 223 pos = &ctrl->qpos; 224 size = SPDIF_QSUB_SIZE; 225 reg = REG_SPDIF_SRQ; 226 break; 227 default: 228 dev_err(&pdev->dev, "unsupported channel name\n"); 229 return; 230 } 231 232 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 233 234 if (*pos >= size * 2) { 235 *pos = 0; 236 } else if (unlikely((*pos % size) + 3 > size)) { 237 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 238 return; 239 } 240 241 regmap_read(regmap, reg, &val); 242 ctrl->subcode[*pos++] = val >> 16; 243 ctrl->subcode[*pos++] = val >> 8; 244 ctrl->subcode[*pos++] = val; 245 } 246 247 /* U/Q Channel sync found */ 248 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 249 { 250 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 251 struct platform_device *pdev = spdif_priv->pdev; 252 253 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 254 255 /* U/Q buffer reset */ 256 if (ctrl->qpos == 0) 257 return; 258 259 /* Set ready to this buffer */ 260 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 261 } 262 263 /* U/Q Channel framing error */ 264 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 265 { 266 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 267 struct regmap *regmap = spdif_priv->regmap; 268 struct platform_device *pdev = spdif_priv->pdev; 269 u32 val; 270 271 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 272 273 /* Read U/Q data to clear the irq and do buffer reset */ 274 regmap_read(regmap, REG_SPDIF_SRU, &val); 275 regmap_read(regmap, REG_SPDIF_SRQ, &val); 276 277 /* Drop this U/Q buffer */ 278 ctrl->ready_buf = 0; 279 ctrl->upos = 0; 280 ctrl->qpos = 0; 281 } 282 283 /* Get spdif interrupt status and clear the interrupt */ 284 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 285 { 286 struct regmap *regmap = spdif_priv->regmap; 287 u32 val, val2; 288 289 regmap_read(regmap, REG_SPDIF_SIS, &val); 290 regmap_read(regmap, REG_SPDIF_SIE, &val2); 291 292 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 293 294 return val; 295 } 296 297 static irqreturn_t spdif_isr(int irq, void *devid) 298 { 299 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 300 struct platform_device *pdev = spdif_priv->pdev; 301 u32 sis; 302 303 sis = spdif_intr_status_clear(spdif_priv); 304 305 if (sis & INT_DPLL_LOCKED) 306 spdif_irq_dpll_lock(spdif_priv); 307 308 if (sis & INT_TXFIFO_UNOV) 309 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 310 311 if (sis & INT_TXFIFO_RESYNC) 312 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 313 314 if (sis & INT_CNEW) 315 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 316 317 if (sis & INT_VAL_NOGOOD) 318 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 319 320 if (sis & INT_SYM_ERR) 321 spdif_irq_sym_error(spdif_priv); 322 323 if (sis & INT_BIT_ERR) 324 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 325 326 if (sis & INT_URX_FUL) 327 spdif_irq_uqrx_full(spdif_priv, 'U'); 328 329 if (sis & INT_URX_OV) 330 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 331 332 if (sis & INT_QRX_FUL) 333 spdif_irq_uqrx_full(spdif_priv, 'Q'); 334 335 if (sis & INT_QRX_OV) 336 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 337 338 if (sis & INT_UQ_SYNC) 339 spdif_irq_uq_sync(spdif_priv); 340 341 if (sis & INT_UQ_ERR) 342 spdif_irq_uq_err(spdif_priv); 343 344 if (sis & INT_RXFIFO_UNOV) 345 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 346 347 if (sis & INT_RXFIFO_RESYNC) 348 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 349 350 if (sis & INT_LOSS_LOCK) 351 spdif_irq_dpll_lock(spdif_priv); 352 353 /* FIXME: Write Tx FIFO to clear TxEm */ 354 if (sis & INT_TX_EM) 355 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 356 357 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 358 if (sis & INT_RXFIFO_FUL) 359 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 360 361 return IRQ_HANDLED; 362 } 363 364 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 365 { 366 struct regmap *regmap = spdif_priv->regmap; 367 u32 val, cycle = 1000; 368 369 regcache_cache_bypass(regmap, true); 370 371 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 372 373 /* 374 * RESET bit would be cleared after finishing its reset procedure, 375 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 376 */ 377 do { 378 regmap_read(regmap, REG_SPDIF_SCR, &val); 379 } while ((val & SCR_SOFT_RESET) && cycle--); 380 381 regcache_cache_bypass(regmap, false); 382 regcache_mark_dirty(regmap); 383 regcache_sync(regmap); 384 385 if (cycle) 386 return 0; 387 else 388 return -EBUSY; 389 } 390 391 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 392 u8 mask, u8 cstatus) 393 { 394 ctrl->ch_status[3] &= ~mask; 395 ctrl->ch_status[3] |= cstatus & mask; 396 } 397 398 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 399 { 400 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 401 struct regmap *regmap = spdif_priv->regmap; 402 struct platform_device *pdev = spdif_priv->pdev; 403 u32 ch_status; 404 405 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 406 (bitrev8(ctrl->ch_status[1]) << 8) | 407 bitrev8(ctrl->ch_status[2]); 408 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 409 410 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 411 412 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 413 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 414 415 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 416 } 417 418 /* Set SPDIF PhaseConfig register for rx clock */ 419 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 420 enum spdif_gainsel gainsel, int dpll_locked) 421 { 422 struct regmap *regmap = spdif_priv->regmap; 423 u8 clksrc = spdif_priv->rxclk_src; 424 425 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 426 return -EINVAL; 427 428 regmap_update_bits(regmap, REG_SPDIF_SRPC, 429 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 430 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 431 432 return 0; 433 } 434 435 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 436 int sample_rate) 437 { 438 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 439 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 440 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 441 struct regmap *regmap = spdif_priv->regmap; 442 struct platform_device *pdev = spdif_priv->pdev; 443 unsigned long csfs = 0; 444 u32 stc, mask, rate; 445 u16 sysclk_df; 446 u8 clk, txclk_df; 447 int ret; 448 449 switch (sample_rate) { 450 case 32000: 451 rate = SPDIF_TXRATE_32000; 452 csfs = IEC958_AES3_CON_FS_32000; 453 break; 454 case 44100: 455 rate = SPDIF_TXRATE_44100; 456 csfs = IEC958_AES3_CON_FS_44100; 457 break; 458 case 48000: 459 rate = SPDIF_TXRATE_48000; 460 csfs = IEC958_AES3_CON_FS_48000; 461 break; 462 case 88200: 463 rate = SPDIF_TXRATE_88200; 464 csfs = IEC958_AES3_CON_FS_88200; 465 break; 466 case 96000: 467 rate = SPDIF_TXRATE_96000; 468 csfs = IEC958_AES3_CON_FS_96000; 469 break; 470 case 176400: 471 rate = SPDIF_TXRATE_176400; 472 csfs = IEC958_AES3_CON_FS_176400; 473 break; 474 case 192000: 475 rate = SPDIF_TXRATE_192000; 476 csfs = IEC958_AES3_CON_FS_192000; 477 break; 478 default: 479 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 480 return -EINVAL; 481 } 482 483 clk = spdif_priv->txclk_src[rate]; 484 if (clk >= STC_TXCLK_SRC_MAX) { 485 dev_err(&pdev->dev, "tx clock source is out of range\n"); 486 return -EINVAL; 487 } 488 489 txclk_df = spdif_priv->txclk_df[rate]; 490 if (txclk_df == 0) { 491 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 492 return -EINVAL; 493 } 494 495 sysclk_df = spdif_priv->sysclk_df[rate]; 496 497 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 498 goto clk_set_bypass; 499 500 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 501 ret = clk_set_rate(spdif_priv->txclk[rate], 502 64 * sample_rate * txclk_df); 503 if (ret) { 504 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 505 return ret; 506 } 507 508 clk_set_bypass: 509 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 510 (64 * sample_rate * txclk_df * sysclk_df)); 511 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 512 clk_get_rate(spdif_priv->txclk[rate])); 513 514 /* set fs field in consumer channel status */ 515 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 516 517 /* select clock source and divisor */ 518 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 519 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 520 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 521 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 522 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 523 524 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 525 spdif_priv->txrate[rate], sample_rate); 526 527 return 0; 528 } 529 530 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 531 struct snd_soc_dai *cpu_dai) 532 { 533 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 534 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 535 struct platform_device *pdev = spdif_priv->pdev; 536 struct regmap *regmap = spdif_priv->regmap; 537 u32 scr, mask; 538 int ret; 539 540 /* Reset module and interrupts only for first initialization */ 541 if (!snd_soc_dai_active(cpu_dai)) { 542 ret = spdif_softreset(spdif_priv); 543 if (ret) { 544 dev_err(&pdev->dev, "failed to soft reset\n"); 545 return ret; 546 } 547 548 /* Disable all the interrupts */ 549 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 550 } 551 552 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 553 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 554 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 555 SCR_TXFIFO_FSEL_IF8; 556 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 557 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 558 SCR_TXFIFO_FSEL_MASK; 559 } else { 560 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 561 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 562 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 563 } 564 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 565 566 /* Power up SPDIF module */ 567 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 568 569 return 0; 570 } 571 572 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 573 struct snd_soc_dai *cpu_dai) 574 { 575 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 576 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 577 struct regmap *regmap = spdif_priv->regmap; 578 u32 scr, mask; 579 580 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 581 scr = 0; 582 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 583 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 584 SCR_TXFIFO_FSEL_MASK; 585 } else { 586 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 587 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 588 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 589 } 590 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 591 592 /* Power down SPDIF module only if tx&rx are both inactive */ 593 if (!snd_soc_dai_active(cpu_dai)) { 594 spdif_intr_status_clear(spdif_priv); 595 regmap_update_bits(regmap, REG_SPDIF_SCR, 596 SCR_LOW_POWER, SCR_LOW_POWER); 597 } 598 } 599 600 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 601 struct snd_pcm_hw_params *params, 602 struct snd_soc_dai *dai) 603 { 604 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 605 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 606 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 607 struct platform_device *pdev = spdif_priv->pdev; 608 u32 sample_rate = params_rate(params); 609 int ret = 0; 610 611 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 612 ret = spdif_set_sample_rate(substream, sample_rate); 613 if (ret) { 614 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 615 __func__, sample_rate); 616 return ret; 617 } 618 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 619 IEC958_AES3_CON_CLOCK_1000PPM); 620 spdif_write_channel_status(spdif_priv); 621 } else { 622 /* Setup rx clock source */ 623 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 624 } 625 626 return ret; 627 } 628 629 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 630 int cmd, struct snd_soc_dai *dai) 631 { 632 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 633 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 634 struct regmap *regmap = spdif_priv->regmap; 635 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 636 u32 intr = SIE_INTR_FOR(tx); 637 u32 dmaen = SCR_DMA_xX_EN(tx); 638 639 switch (cmd) { 640 case SNDRV_PCM_TRIGGER_START: 641 case SNDRV_PCM_TRIGGER_RESUME: 642 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 643 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 644 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 645 break; 646 case SNDRV_PCM_TRIGGER_STOP: 647 case SNDRV_PCM_TRIGGER_SUSPEND: 648 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 649 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 650 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return 0; 657 } 658 659 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 660 .startup = fsl_spdif_startup, 661 .hw_params = fsl_spdif_hw_params, 662 .trigger = fsl_spdif_trigger, 663 .shutdown = fsl_spdif_shutdown, 664 }; 665 666 667 /* 668 * FSL SPDIF IEC958 controller(mixer) functions 669 * 670 * Channel status get/put control 671 * User bit value get/put control 672 * Valid bit value get control 673 * DPLL lock status get control 674 * User bit sync mode selection control 675 */ 676 677 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 678 struct snd_ctl_elem_info *uinfo) 679 { 680 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 681 uinfo->count = 1; 682 683 return 0; 684 } 685 686 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 687 struct snd_ctl_elem_value *uvalue) 688 { 689 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 690 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 691 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 692 693 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 694 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 695 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 696 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 697 698 return 0; 699 } 700 701 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 702 struct snd_ctl_elem_value *uvalue) 703 { 704 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 705 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 706 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 707 708 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 709 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 710 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 711 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 712 713 spdif_write_channel_status(spdif_priv); 714 715 return 0; 716 } 717 718 /* Get channel status from SPDIF_RX_CCHAN register */ 719 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 720 struct snd_ctl_elem_value *ucontrol) 721 { 722 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 723 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 724 struct regmap *regmap = spdif_priv->regmap; 725 u32 cstatus, val; 726 727 regmap_read(regmap, REG_SPDIF_SIS, &val); 728 if (!(val & INT_CNEW)) 729 return -EAGAIN; 730 731 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 732 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 733 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 734 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 735 736 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 737 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 738 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 739 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 740 741 /* Clear intr */ 742 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 743 744 return 0; 745 } 746 747 /* 748 * Get User bits (subcode) from chip value which readed out 749 * in UChannel register. 750 */ 751 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 752 struct snd_ctl_elem_value *ucontrol) 753 { 754 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 755 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 756 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 757 unsigned long flags; 758 int ret = -EAGAIN; 759 760 spin_lock_irqsave(&ctrl->ctl_lock, flags); 761 if (ctrl->ready_buf) { 762 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 763 memcpy(&ucontrol->value.iec958.subcode[0], 764 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 765 ret = 0; 766 } 767 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 768 769 return ret; 770 } 771 772 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 773 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 774 struct snd_ctl_elem_info *uinfo) 775 { 776 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 777 uinfo->count = SPDIF_QSUB_SIZE; 778 779 return 0; 780 } 781 782 /* Get Q subcode from chip value which readed out in QChannel register */ 783 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 784 struct snd_ctl_elem_value *ucontrol) 785 { 786 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 787 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 788 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 789 unsigned long flags; 790 int ret = -EAGAIN; 791 792 spin_lock_irqsave(&ctrl->ctl_lock, flags); 793 if (ctrl->ready_buf) { 794 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 795 memcpy(&ucontrol->value.bytes.data[0], 796 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 797 ret = 0; 798 } 799 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 800 801 return ret; 802 } 803 804 /* Valid bit information */ 805 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, 806 struct snd_ctl_elem_info *uinfo) 807 { 808 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 809 uinfo->count = 1; 810 uinfo->value.integer.min = 0; 811 uinfo->value.integer.max = 1; 812 813 return 0; 814 } 815 816 /* Get valid good bit from interrupt status register */ 817 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 818 struct snd_ctl_elem_value *ucontrol) 819 { 820 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 821 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 822 struct regmap *regmap = spdif_priv->regmap; 823 u32 val; 824 825 regmap_read(regmap, REG_SPDIF_SIS, &val); 826 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 827 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 828 829 return 0; 830 } 831 832 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 833 struct snd_ctl_elem_value *ucontrol) 834 { 835 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 836 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 837 struct regmap *regmap = spdif_priv->regmap; 838 u32 val; 839 840 regmap_read(regmap, REG_SPDIF_SCR, &val); 841 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 842 val = 1 - val; 843 ucontrol->value.integer.value[0] = val; 844 845 return 0; 846 } 847 848 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 849 struct snd_ctl_elem_value *ucontrol) 850 { 851 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 852 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 853 struct regmap *regmap = spdif_priv->regmap; 854 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 855 856 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 857 858 return 0; 859 } 860 861 /* DPLL lock information */ 862 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 863 struct snd_ctl_elem_info *uinfo) 864 { 865 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 866 uinfo->count = 1; 867 uinfo->value.integer.min = 16000; 868 uinfo->value.integer.max = 192000; 869 870 return 0; 871 } 872 873 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 874 24, 16, 12, 8, 6, 4, 3, 875 }; 876 877 /* Get RX data clock rate given the SPDIF bus_clk */ 878 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 879 enum spdif_gainsel gainsel) 880 { 881 struct regmap *regmap = spdif_priv->regmap; 882 struct platform_device *pdev = spdif_priv->pdev; 883 u64 tmpval64, busclk_freq = 0; 884 u32 freqmeas, phaseconf; 885 u8 clksrc; 886 887 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 888 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 889 890 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 891 892 /* Get bus clock from system */ 893 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 894 busclk_freq = clk_get_rate(spdif_priv->sysclk); 895 896 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 897 tmpval64 = (u64) busclk_freq * freqmeas; 898 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 899 do_div(tmpval64, 128 * 1024); 900 901 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 902 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 903 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 904 905 return (int)tmpval64; 906 } 907 908 /* 909 * Get DPLL lock or not info from stable interrupt status register. 910 * User application must use this control to get locked, 911 * then can do next PCM operation 912 */ 913 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 914 struct snd_ctl_elem_value *ucontrol) 915 { 916 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 917 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 918 int rate = 0; 919 920 if (spdif_priv->dpll_locked) 921 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 922 923 ucontrol->value.integer.value[0] = rate; 924 925 return 0; 926 } 927 928 /* User bit sync mode info */ 929 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, 930 struct snd_ctl_elem_info *uinfo) 931 { 932 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 933 uinfo->count = 1; 934 uinfo->value.integer.min = 0; 935 uinfo->value.integer.max = 1; 936 937 return 0; 938 } 939 940 /* 941 * User bit sync mode: 942 * 1 CD User channel subcode 943 * 0 Non-CD data 944 */ 945 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 946 struct snd_ctl_elem_value *ucontrol) 947 { 948 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 949 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 950 struct regmap *regmap = spdif_priv->regmap; 951 u32 val; 952 953 regmap_read(regmap, REG_SPDIF_SRCD, &val); 954 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 955 956 return 0; 957 } 958 959 /* 960 * User bit sync mode: 961 * 1 CD User channel subcode 962 * 0 Non-CD data 963 */ 964 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 965 struct snd_ctl_elem_value *ucontrol) 966 { 967 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 968 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 969 struct regmap *regmap = spdif_priv->regmap; 970 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 971 972 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 973 974 return 0; 975 } 976 977 /* FSL SPDIF IEC958 controller defines */ 978 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 979 /* Status cchanel controller */ 980 { 981 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 982 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 983 .access = SNDRV_CTL_ELEM_ACCESS_READ | 984 SNDRV_CTL_ELEM_ACCESS_WRITE | 985 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 986 .info = fsl_spdif_info, 987 .get = fsl_spdif_pb_get, 988 .put = fsl_spdif_pb_put, 989 }, 990 { 991 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 992 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 993 .access = SNDRV_CTL_ELEM_ACCESS_READ | 994 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 995 .info = fsl_spdif_info, 996 .get = fsl_spdif_capture_get, 997 }, 998 /* User bits controller */ 999 { 1000 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1001 .name = "IEC958 Subcode Capture Default", 1002 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1003 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1004 .info = fsl_spdif_info, 1005 .get = fsl_spdif_subcode_get, 1006 }, 1007 { 1008 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1009 .name = "IEC958 Q-subcode Capture Default", 1010 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1011 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1012 .info = fsl_spdif_qinfo, 1013 .get = fsl_spdif_qget, 1014 }, 1015 /* Valid bit error controller */ 1016 { 1017 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1018 .name = "IEC958 RX V-Bit Errors", 1019 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1020 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1021 .info = fsl_spdif_vbit_info, 1022 .get = fsl_spdif_rx_vbit_get, 1023 }, 1024 { 1025 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1026 .name = "IEC958 TX V-Bit", 1027 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1028 SNDRV_CTL_ELEM_ACCESS_WRITE | 1029 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1030 .info = fsl_spdif_vbit_info, 1031 .get = fsl_spdif_tx_vbit_get, 1032 .put = fsl_spdif_tx_vbit_put, 1033 }, 1034 /* DPLL lock info get controller */ 1035 { 1036 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1037 .name = "RX Sample Rate", 1038 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1039 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1040 .info = fsl_spdif_rxrate_info, 1041 .get = fsl_spdif_rxrate_get, 1042 }, 1043 /* User bit sync mode set/get controller */ 1044 { 1045 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1046 .name = "IEC958 USyncMode CDText", 1047 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1048 SNDRV_CTL_ELEM_ACCESS_WRITE | 1049 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1050 .info = fsl_spdif_usync_info, 1051 .get = fsl_spdif_usync_get, 1052 .put = fsl_spdif_usync_put, 1053 }, 1054 }; 1055 1056 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1057 { 1058 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1059 1060 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1061 &spdif_private->dma_params_rx); 1062 1063 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1064 1065 /*Clear the val bit for Tx*/ 1066 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1067 SCR_VAL_MASK, SCR_VAL_CLEAR); 1068 1069 return 0; 1070 } 1071 1072 static struct snd_soc_dai_driver fsl_spdif_dai = { 1073 .probe = &fsl_spdif_dai_probe, 1074 .playback = { 1075 .stream_name = "CPU-Playback", 1076 .channels_min = 2, 1077 .channels_max = 2, 1078 .rates = FSL_SPDIF_RATES_PLAYBACK, 1079 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1080 }, 1081 .capture = { 1082 .stream_name = "CPU-Capture", 1083 .channels_min = 2, 1084 .channels_max = 2, 1085 .rates = FSL_SPDIF_RATES_CAPTURE, 1086 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1087 }, 1088 .ops = &fsl_spdif_dai_ops, 1089 }; 1090 1091 static const struct snd_soc_component_driver fsl_spdif_component = { 1092 .name = "fsl-spdif", 1093 }; 1094 1095 /* FSL SPDIF REGMAP */ 1096 static const struct reg_default fsl_spdif_reg_defaults[] = { 1097 {REG_SPDIF_SCR, 0x00000400}, 1098 {REG_SPDIF_SRCD, 0x00000000}, 1099 {REG_SPDIF_SIE, 0x00000000}, 1100 {REG_SPDIF_STL, 0x00000000}, 1101 {REG_SPDIF_STR, 0x00000000}, 1102 {REG_SPDIF_STCSCH, 0x00000000}, 1103 {REG_SPDIF_STCSCL, 0x00000000}, 1104 {REG_SPDIF_STC, 0x00020f00}, 1105 }; 1106 1107 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1108 { 1109 switch (reg) { 1110 case REG_SPDIF_SCR: 1111 case REG_SPDIF_SRCD: 1112 case REG_SPDIF_SRPC: 1113 case REG_SPDIF_SIE: 1114 case REG_SPDIF_SIS: 1115 case REG_SPDIF_SRL: 1116 case REG_SPDIF_SRR: 1117 case REG_SPDIF_SRCSH: 1118 case REG_SPDIF_SRCSL: 1119 case REG_SPDIF_SRU: 1120 case REG_SPDIF_SRQ: 1121 case REG_SPDIF_STCSCH: 1122 case REG_SPDIF_STCSCL: 1123 case REG_SPDIF_SRFM: 1124 case REG_SPDIF_STC: 1125 return true; 1126 default: 1127 return false; 1128 } 1129 } 1130 1131 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1132 { 1133 switch (reg) { 1134 case REG_SPDIF_SRPC: 1135 case REG_SPDIF_SIS: 1136 case REG_SPDIF_SRL: 1137 case REG_SPDIF_SRR: 1138 case REG_SPDIF_SRCSH: 1139 case REG_SPDIF_SRCSL: 1140 case REG_SPDIF_SRU: 1141 case REG_SPDIF_SRQ: 1142 case REG_SPDIF_SRFM: 1143 return true; 1144 default: 1145 return false; 1146 } 1147 } 1148 1149 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1150 { 1151 switch (reg) { 1152 case REG_SPDIF_SCR: 1153 case REG_SPDIF_SRCD: 1154 case REG_SPDIF_SRPC: 1155 case REG_SPDIF_SIE: 1156 case REG_SPDIF_SIC: 1157 case REG_SPDIF_STL: 1158 case REG_SPDIF_STR: 1159 case REG_SPDIF_STCSCH: 1160 case REG_SPDIF_STCSCL: 1161 case REG_SPDIF_STC: 1162 return true; 1163 default: 1164 return false; 1165 } 1166 } 1167 1168 static const struct regmap_config fsl_spdif_regmap_config = { 1169 .reg_bits = 32, 1170 .reg_stride = 4, 1171 .val_bits = 32, 1172 1173 .max_register = REG_SPDIF_STC, 1174 .reg_defaults = fsl_spdif_reg_defaults, 1175 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1176 .readable_reg = fsl_spdif_readable_reg, 1177 .volatile_reg = fsl_spdif_volatile_reg, 1178 .writeable_reg = fsl_spdif_writeable_reg, 1179 .cache_type = REGCACHE_FLAT, 1180 }; 1181 1182 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1183 struct clk *clk, u64 savesub, 1184 enum spdif_txrate index, bool round) 1185 { 1186 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1187 192000, }; 1188 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1189 u64 rate_ideal, rate_actual, sub; 1190 u32 arate; 1191 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1192 u8 txclk_df; 1193 1194 /* The sysclk has an extra divisor [2, 512] */ 1195 sysclk_dfmin = is_sysclk ? 2 : 1; 1196 sysclk_dfmax = is_sysclk ? 512 : 1; 1197 1198 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1199 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1200 rate_ideal = rate[index] * txclk_df * 64ULL; 1201 if (round) 1202 rate_actual = clk_round_rate(clk, rate_ideal); 1203 else 1204 rate_actual = clk_get_rate(clk); 1205 1206 arate = rate_actual / 64; 1207 arate /= txclk_df * sysclk_df; 1208 1209 if (arate == rate[index]) { 1210 /* We are lucky */ 1211 savesub = 0; 1212 spdif_priv->txclk_df[index] = txclk_df; 1213 spdif_priv->sysclk_df[index] = sysclk_df; 1214 spdif_priv->txrate[index] = arate; 1215 goto out; 1216 } else if (arate / rate[index] == 1) { 1217 /* A little bigger than expect */ 1218 sub = (u64)(arate - rate[index]) * 100000; 1219 do_div(sub, rate[index]); 1220 if (sub >= savesub) 1221 continue; 1222 savesub = sub; 1223 spdif_priv->txclk_df[index] = txclk_df; 1224 spdif_priv->sysclk_df[index] = sysclk_df; 1225 spdif_priv->txrate[index] = arate; 1226 } else if (rate[index] / arate == 1) { 1227 /* A little smaller than expect */ 1228 sub = (u64)(rate[index] - arate) * 100000; 1229 do_div(sub, rate[index]); 1230 if (sub >= savesub) 1231 continue; 1232 savesub = sub; 1233 spdif_priv->txclk_df[index] = txclk_df; 1234 spdif_priv->sysclk_df[index] = sysclk_df; 1235 spdif_priv->txrate[index] = arate; 1236 } 1237 } 1238 } 1239 1240 out: 1241 return savesub; 1242 } 1243 1244 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1245 enum spdif_txrate index) 1246 { 1247 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1248 192000, }; 1249 struct platform_device *pdev = spdif_priv->pdev; 1250 struct device *dev = &pdev->dev; 1251 u64 savesub = 100000, ret; 1252 struct clk *clk; 1253 char tmp[16]; 1254 int i; 1255 1256 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1257 sprintf(tmp, "rxtx%d", i); 1258 clk = devm_clk_get(&pdev->dev, tmp); 1259 if (IS_ERR(clk)) { 1260 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1261 return PTR_ERR(clk); 1262 } 1263 if (!clk_get_rate(clk)) 1264 continue; 1265 1266 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1267 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1268 if (savesub == ret) 1269 continue; 1270 1271 savesub = ret; 1272 spdif_priv->txclk[index] = clk; 1273 spdif_priv->txclk_src[index] = i; 1274 1275 /* To quick catch a divisor, we allow a 0.1% deviation */ 1276 if (savesub < 100) 1277 break; 1278 } 1279 1280 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1281 spdif_priv->txclk_src[index], rate[index]); 1282 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", 1283 spdif_priv->txclk_df[index], rate[index]); 1284 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1285 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", 1286 spdif_priv->sysclk_df[index], rate[index]); 1287 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", 1288 rate[index], spdif_priv->txrate[index]); 1289 1290 return 0; 1291 } 1292 1293 static int fsl_spdif_probe(struct platform_device *pdev) 1294 { 1295 struct fsl_spdif_priv *spdif_priv; 1296 struct spdif_mixer_control *ctrl; 1297 struct resource *res; 1298 void __iomem *regs; 1299 int irq, ret, i; 1300 1301 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1302 if (!spdif_priv) 1303 return -ENOMEM; 1304 1305 spdif_priv->pdev = pdev; 1306 1307 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1308 if (!spdif_priv->soc) { 1309 dev_err(&pdev->dev, "failed to get soc data\n"); 1310 return -ENODEV; 1311 } 1312 1313 /* Initialize this copy of the CPU DAI driver structure */ 1314 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1315 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1316 spdif_priv->cpu_dai_drv.playback.formats = 1317 spdif_priv->soc->tx_formats; 1318 1319 /* Get the addresses and IRQ */ 1320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1321 regs = devm_ioremap_resource(&pdev->dev, res); 1322 if (IS_ERR(regs)) 1323 return PTR_ERR(regs); 1324 1325 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1326 "core", regs, &fsl_spdif_regmap_config); 1327 if (IS_ERR(spdif_priv->regmap)) { 1328 dev_err(&pdev->dev, "regmap init failed\n"); 1329 return PTR_ERR(spdif_priv->regmap); 1330 } 1331 1332 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1333 irq = platform_get_irq(pdev, i); 1334 if (irq < 0) { 1335 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1336 return irq; 1337 } 1338 1339 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1340 dev_name(&pdev->dev), spdif_priv); 1341 if (ret) { 1342 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1343 return ret; 1344 } 1345 } 1346 1347 /* Get system clock for rx clock rate calculation */ 1348 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1349 if (IS_ERR(spdif_priv->sysclk)) { 1350 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1351 return PTR_ERR(spdif_priv->sysclk); 1352 } 1353 1354 /* Get core clock for data register access via DMA */ 1355 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1356 if (IS_ERR(spdif_priv->coreclk)) { 1357 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1358 return PTR_ERR(spdif_priv->coreclk); 1359 } 1360 1361 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1362 if (IS_ERR(spdif_priv->spbaclk)) 1363 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1364 1365 /* Select clock source for rx/tx clock */ 1366 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1367 if (IS_ERR(spdif_priv->rxclk)) { 1368 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1369 return PTR_ERR(spdif_priv->rxclk); 1370 } 1371 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1372 1373 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1374 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1375 if (ret) 1376 return ret; 1377 } 1378 1379 /* Initial spinlock for control data */ 1380 ctrl = &spdif_priv->fsl_spdif_control; 1381 spin_lock_init(&ctrl->ctl_lock); 1382 1383 /* Init tx channel status default value */ 1384 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1385 IEC958_AES0_CON_EMPHASIS_5015; 1386 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1387 ctrl->ch_status[2] = 0x00; 1388 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1389 IEC958_AES3_CON_CLOCK_1000PPM; 1390 1391 spdif_priv->dpll_locked = false; 1392 1393 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1394 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1395 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1396 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1397 1398 /* Register with ASoC */ 1399 dev_set_drvdata(&pdev->dev, spdif_priv); 1400 pm_runtime_enable(&pdev->dev); 1401 regcache_cache_only(spdif_priv->regmap, true); 1402 1403 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1404 &spdif_priv->cpu_dai_drv, 1); 1405 if (ret) { 1406 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1407 return ret; 1408 } 1409 1410 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1411 if (ret && ret != -EPROBE_DEFER) 1412 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); 1413 1414 return ret; 1415 } 1416 1417 #ifdef CONFIG_PM 1418 static int fsl_spdif_runtime_suspend(struct device *dev) 1419 { 1420 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1421 int i; 1422 1423 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1424 &spdif_priv->regcache_srpc); 1425 regcache_cache_only(spdif_priv->regmap, true); 1426 1427 clk_disable_unprepare(spdif_priv->rxclk); 1428 1429 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 1430 clk_disable_unprepare(spdif_priv->txclk[i]); 1431 1432 if (!IS_ERR(spdif_priv->spbaclk)) 1433 clk_disable_unprepare(spdif_priv->spbaclk); 1434 clk_disable_unprepare(spdif_priv->coreclk); 1435 1436 return 0; 1437 } 1438 1439 static int fsl_spdif_runtime_resume(struct device *dev) 1440 { 1441 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1442 int ret; 1443 int i; 1444 1445 ret = clk_prepare_enable(spdif_priv->coreclk); 1446 if (ret) { 1447 dev_err(dev, "failed to enable core clock\n"); 1448 return ret; 1449 } 1450 1451 if (!IS_ERR(spdif_priv->spbaclk)) { 1452 ret = clk_prepare_enable(spdif_priv->spbaclk); 1453 if (ret) { 1454 dev_err(dev, "failed to enable spba clock\n"); 1455 goto disable_core_clk; 1456 } 1457 } 1458 1459 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1460 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1461 if (ret) 1462 goto disable_tx_clk; 1463 } 1464 1465 ret = clk_prepare_enable(spdif_priv->rxclk); 1466 if (ret) 1467 goto disable_tx_clk; 1468 1469 regcache_cache_only(spdif_priv->regmap, false); 1470 regcache_mark_dirty(spdif_priv->regmap); 1471 1472 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1473 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1474 spdif_priv->regcache_srpc); 1475 1476 ret = regcache_sync(spdif_priv->regmap); 1477 if (ret) 1478 goto disable_rx_clk; 1479 1480 return 0; 1481 1482 disable_rx_clk: 1483 clk_disable_unprepare(spdif_priv->rxclk); 1484 disable_tx_clk: 1485 for (i--; i >= 0; i--) 1486 clk_disable_unprepare(spdif_priv->txclk[i]); 1487 if (!IS_ERR(spdif_priv->spbaclk)) 1488 clk_disable_unprepare(spdif_priv->spbaclk); 1489 disable_core_clk: 1490 clk_disable_unprepare(spdif_priv->coreclk); 1491 1492 return ret; 1493 } 1494 #endif /* CONFIG_PM */ 1495 1496 static const struct dev_pm_ops fsl_spdif_pm = { 1497 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1498 pm_runtime_force_resume) 1499 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1500 NULL) 1501 }; 1502 1503 static const struct of_device_id fsl_spdif_dt_ids[] = { 1504 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1505 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1506 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1507 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1508 {} 1509 }; 1510 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1511 1512 static struct platform_driver fsl_spdif_driver = { 1513 .driver = { 1514 .name = "fsl-spdif-dai", 1515 .of_match_table = fsl_spdif_dt_ids, 1516 .pm = &fsl_spdif_pm, 1517 }, 1518 .probe = fsl_spdif_probe, 1519 }; 1520 1521 module_platform_driver(fsl_spdif_driver); 1522 1523 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1524 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1525 MODULE_LICENSE("GPL v2"); 1526 MODULE_ALIAS("platform:fsl-spdif-dai"); 1527