1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SPDIF_TXFIFO_WML 0x8 29 #define FSL_SPDIF_RXFIFO_WML 0x8 30 31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 35 INT_LOSS_LOCK | INT_DPLL_LOCKED) 36 37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 38 39 /* Index list for the values that has if (DPLL Locked) condition */ 40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 41 #define SRPC_NODPLL_START1 0x5 42 #define SRPC_NODPLL_START2 0xc 43 44 #define DEFAULT_RXCLK_SRC 1 45 46 /** 47 * struct fsl_spdif_soc_data: soc specific data 48 * 49 * @imx: for imx platform 50 * @shared_root_clock: flag of sharing a clock source with others; 51 * so the driver shouldn't set root clock rate 52 */ 53 struct fsl_spdif_soc_data { 54 bool imx; 55 bool shared_root_clock; 56 }; 57 58 /* 59 * SPDIF control structure 60 * Defines channel status, subcode and Q sub 61 */ 62 struct spdif_mixer_control { 63 /* spinlock to access control data */ 64 spinlock_t ctl_lock; 65 66 /* IEC958 channel tx status bit */ 67 unsigned char ch_status[4]; 68 69 /* User bits */ 70 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 71 72 /* Q subcode part of user bits */ 73 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 74 75 /* Buffer offset for U/Q */ 76 u32 upos; 77 u32 qpos; 78 79 /* Ready buffer index of the two buffers */ 80 u32 ready_buf; 81 }; 82 83 /** 84 * struct fsl_spdif_priv - Freescale SPDIF private data 85 * @soc: SPDIF soc data 86 * @fsl_spdif_control: SPDIF control data 87 * @cpu_dai_drv: cpu dai driver 88 * @pdev: platform device pointer 89 * @regmap: regmap handler 90 * @dpll_locked: dpll lock flag 91 * @txrate: the best rates for playback 92 * @txclk_df: STC_TXCLK_DF dividers value for playback 93 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 94 * @txclk_src: STC_TXCLK_SRC values for playback 95 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 96 * @txclk: tx clock sources for playback 97 * @rxclk: rx clock sources for capture 98 * @coreclk: core clock for register access via DMA 99 * @sysclk: system clock for rx clock rate measurement 100 * @spbaclk: SPBA clock (optional, depending on SoC design) 101 * @dma_params_tx: DMA parameters for transmit channel 102 * @dma_params_rx: DMA parameters for receive channel 103 * @regcache_srpc: regcache for SRPC 104 */ 105 struct fsl_spdif_priv { 106 const struct fsl_spdif_soc_data *soc; 107 struct spdif_mixer_control fsl_spdif_control; 108 struct snd_soc_dai_driver cpu_dai_drv; 109 struct platform_device *pdev; 110 struct regmap *regmap; 111 bool dpll_locked; 112 u32 txrate[SPDIF_TXRATE_MAX]; 113 u8 txclk_df[SPDIF_TXRATE_MAX]; 114 u16 sysclk_df[SPDIF_TXRATE_MAX]; 115 u8 txclk_src[SPDIF_TXRATE_MAX]; 116 u8 rxclk_src; 117 struct clk *txclk[SPDIF_TXRATE_MAX]; 118 struct clk *rxclk; 119 struct clk *coreclk; 120 struct clk *sysclk; 121 struct clk *spbaclk; 122 struct snd_dmaengine_dai_dma_data dma_params_tx; 123 struct snd_dmaengine_dai_dma_data dma_params_rx; 124 /* regcache for SRPC */ 125 u32 regcache_srpc; 126 }; 127 128 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 129 .imx = false, 130 .shared_root_clock = false, 131 }; 132 133 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 134 .imx = true, 135 .shared_root_clock = false, 136 }; 137 138 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 139 .imx = true, 140 .shared_root_clock = true, 141 }; 142 143 /* Check if clk is a root clock that does not share clock source with others */ 144 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 145 { 146 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 147 } 148 149 /* DPLL locked and lock loss interrupt handler */ 150 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 151 { 152 struct regmap *regmap = spdif_priv->regmap; 153 struct platform_device *pdev = spdif_priv->pdev; 154 u32 locked; 155 156 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 157 locked &= SRPC_DPLL_LOCKED; 158 159 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 160 locked ? "locked" : "loss lock"); 161 162 spdif_priv->dpll_locked = locked ? true : false; 163 } 164 165 /* Receiver found illegal symbol interrupt handler */ 166 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 167 { 168 struct regmap *regmap = spdif_priv->regmap; 169 struct platform_device *pdev = spdif_priv->pdev; 170 171 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 172 173 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 174 if (!spdif_priv->dpll_locked) 175 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 176 } 177 178 /* U/Q Channel receive register full */ 179 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 180 { 181 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 182 struct regmap *regmap = spdif_priv->regmap; 183 struct platform_device *pdev = spdif_priv->pdev; 184 u32 *pos, size, val, reg; 185 186 switch (name) { 187 case 'U': 188 pos = &ctrl->upos; 189 size = SPDIF_UBITS_SIZE; 190 reg = REG_SPDIF_SRU; 191 break; 192 case 'Q': 193 pos = &ctrl->qpos; 194 size = SPDIF_QSUB_SIZE; 195 reg = REG_SPDIF_SRQ; 196 break; 197 default: 198 dev_err(&pdev->dev, "unsupported channel name\n"); 199 return; 200 } 201 202 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 203 204 if (*pos >= size * 2) { 205 *pos = 0; 206 } else if (unlikely((*pos % size) + 3 > size)) { 207 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 208 return; 209 } 210 211 regmap_read(regmap, reg, &val); 212 ctrl->subcode[*pos++] = val >> 16; 213 ctrl->subcode[*pos++] = val >> 8; 214 ctrl->subcode[*pos++] = val; 215 } 216 217 /* U/Q Channel sync found */ 218 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 219 { 220 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 221 struct platform_device *pdev = spdif_priv->pdev; 222 223 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 224 225 /* U/Q buffer reset */ 226 if (ctrl->qpos == 0) 227 return; 228 229 /* Set ready to this buffer */ 230 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 231 } 232 233 /* U/Q Channel framing error */ 234 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 235 { 236 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 237 struct regmap *regmap = spdif_priv->regmap; 238 struct platform_device *pdev = spdif_priv->pdev; 239 u32 val; 240 241 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 242 243 /* Read U/Q data to clear the irq and do buffer reset */ 244 regmap_read(regmap, REG_SPDIF_SRU, &val); 245 regmap_read(regmap, REG_SPDIF_SRQ, &val); 246 247 /* Drop this U/Q buffer */ 248 ctrl->ready_buf = 0; 249 ctrl->upos = 0; 250 ctrl->qpos = 0; 251 } 252 253 /* Get spdif interrupt status and clear the interrupt */ 254 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 255 { 256 struct regmap *regmap = spdif_priv->regmap; 257 u32 val, val2; 258 259 regmap_read(regmap, REG_SPDIF_SIS, &val); 260 regmap_read(regmap, REG_SPDIF_SIE, &val2); 261 262 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 263 264 return val; 265 } 266 267 static irqreturn_t spdif_isr(int irq, void *devid) 268 { 269 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 270 struct platform_device *pdev = spdif_priv->pdev; 271 u32 sis; 272 273 sis = spdif_intr_status_clear(spdif_priv); 274 275 if (sis & INT_DPLL_LOCKED) 276 spdif_irq_dpll_lock(spdif_priv); 277 278 if (sis & INT_TXFIFO_UNOV) 279 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 280 281 if (sis & INT_TXFIFO_RESYNC) 282 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 283 284 if (sis & INT_CNEW) 285 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 286 287 if (sis & INT_VAL_NOGOOD) 288 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 289 290 if (sis & INT_SYM_ERR) 291 spdif_irq_sym_error(spdif_priv); 292 293 if (sis & INT_BIT_ERR) 294 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 295 296 if (sis & INT_URX_FUL) 297 spdif_irq_uqrx_full(spdif_priv, 'U'); 298 299 if (sis & INT_URX_OV) 300 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 301 302 if (sis & INT_QRX_FUL) 303 spdif_irq_uqrx_full(spdif_priv, 'Q'); 304 305 if (sis & INT_QRX_OV) 306 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 307 308 if (sis & INT_UQ_SYNC) 309 spdif_irq_uq_sync(spdif_priv); 310 311 if (sis & INT_UQ_ERR) 312 spdif_irq_uq_err(spdif_priv); 313 314 if (sis & INT_RXFIFO_UNOV) 315 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 316 317 if (sis & INT_RXFIFO_RESYNC) 318 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 319 320 if (sis & INT_LOSS_LOCK) 321 spdif_irq_dpll_lock(spdif_priv); 322 323 /* FIXME: Write Tx FIFO to clear TxEm */ 324 if (sis & INT_TX_EM) 325 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 326 327 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 328 if (sis & INT_RXFIFO_FUL) 329 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 330 331 return IRQ_HANDLED; 332 } 333 334 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 335 { 336 struct regmap *regmap = spdif_priv->regmap; 337 u32 val, cycle = 1000; 338 339 regcache_cache_bypass(regmap, true); 340 341 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 342 343 /* 344 * RESET bit would be cleared after finishing its reset procedure, 345 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 346 */ 347 do { 348 regmap_read(regmap, REG_SPDIF_SCR, &val); 349 } while ((val & SCR_SOFT_RESET) && cycle--); 350 351 regcache_cache_bypass(regmap, false); 352 regcache_mark_dirty(regmap); 353 regcache_sync(regmap); 354 355 if (cycle) 356 return 0; 357 else 358 return -EBUSY; 359 } 360 361 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 362 u8 mask, u8 cstatus) 363 { 364 ctrl->ch_status[3] &= ~mask; 365 ctrl->ch_status[3] |= cstatus & mask; 366 } 367 368 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 369 { 370 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 371 struct regmap *regmap = spdif_priv->regmap; 372 struct platform_device *pdev = spdif_priv->pdev; 373 u32 ch_status; 374 375 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 376 (bitrev8(ctrl->ch_status[1]) << 8) | 377 bitrev8(ctrl->ch_status[2]); 378 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 379 380 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 381 382 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 383 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 384 385 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 386 } 387 388 /* Set SPDIF PhaseConfig register for rx clock */ 389 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 390 enum spdif_gainsel gainsel, int dpll_locked) 391 { 392 struct regmap *regmap = spdif_priv->regmap; 393 u8 clksrc = spdif_priv->rxclk_src; 394 395 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 396 return -EINVAL; 397 398 regmap_update_bits(regmap, REG_SPDIF_SRPC, 399 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 400 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 401 402 return 0; 403 } 404 405 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 406 int sample_rate) 407 { 408 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 409 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 410 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 411 struct regmap *regmap = spdif_priv->regmap; 412 struct platform_device *pdev = spdif_priv->pdev; 413 unsigned long csfs = 0; 414 u32 stc, mask, rate; 415 u16 sysclk_df; 416 u8 clk, txclk_df; 417 int ret; 418 419 switch (sample_rate) { 420 case 32000: 421 rate = SPDIF_TXRATE_32000; 422 csfs = IEC958_AES3_CON_FS_32000; 423 break; 424 case 44100: 425 rate = SPDIF_TXRATE_44100; 426 csfs = IEC958_AES3_CON_FS_44100; 427 break; 428 case 48000: 429 rate = SPDIF_TXRATE_48000; 430 csfs = IEC958_AES3_CON_FS_48000; 431 break; 432 case 96000: 433 rate = SPDIF_TXRATE_96000; 434 csfs = IEC958_AES3_CON_FS_96000; 435 break; 436 case 192000: 437 rate = SPDIF_TXRATE_192000; 438 csfs = IEC958_AES3_CON_FS_192000; 439 break; 440 default: 441 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 442 return -EINVAL; 443 } 444 445 clk = spdif_priv->txclk_src[rate]; 446 if (clk >= STC_TXCLK_SRC_MAX) { 447 dev_err(&pdev->dev, "tx clock source is out of range\n"); 448 return -EINVAL; 449 } 450 451 txclk_df = spdif_priv->txclk_df[rate]; 452 if (txclk_df == 0) { 453 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 454 return -EINVAL; 455 } 456 457 sysclk_df = spdif_priv->sysclk_df[rate]; 458 459 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 460 goto clk_set_bypass; 461 462 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 463 ret = clk_set_rate(spdif_priv->txclk[rate], 464 64 * sample_rate * txclk_df); 465 if (ret) { 466 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 467 return ret; 468 } 469 470 clk_set_bypass: 471 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 472 (64 * sample_rate * txclk_df * sysclk_df)); 473 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 474 clk_get_rate(spdif_priv->txclk[rate])); 475 476 /* set fs field in consumer channel status */ 477 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 478 479 /* select clock source and divisor */ 480 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 481 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 482 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 483 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 484 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 485 486 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 487 spdif_priv->txrate[rate], sample_rate); 488 489 return 0; 490 } 491 492 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 493 struct snd_soc_dai *cpu_dai) 494 { 495 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 496 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 497 struct platform_device *pdev = spdif_priv->pdev; 498 struct regmap *regmap = spdif_priv->regmap; 499 u32 scr, mask; 500 int ret; 501 502 /* Reset module and interrupts only for first initialization */ 503 if (!snd_soc_dai_active(cpu_dai)) { 504 ret = spdif_softreset(spdif_priv); 505 if (ret) { 506 dev_err(&pdev->dev, "failed to soft reset\n"); 507 return ret; 508 } 509 510 /* Disable all the interrupts */ 511 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 512 } 513 514 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 515 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 516 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 517 SCR_TXFIFO_FSEL_IF8; 518 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 519 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 520 SCR_TXFIFO_FSEL_MASK; 521 } else { 522 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 523 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 524 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 525 } 526 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 527 528 /* Power up SPDIF module */ 529 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 530 531 return 0; 532 } 533 534 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 535 struct snd_soc_dai *cpu_dai) 536 { 537 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 538 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 539 struct regmap *regmap = spdif_priv->regmap; 540 u32 scr, mask; 541 542 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 543 scr = 0; 544 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 545 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 546 SCR_TXFIFO_FSEL_MASK; 547 } else { 548 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 549 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 550 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 551 } 552 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 553 554 /* Power down SPDIF module only if tx&rx are both inactive */ 555 if (!snd_soc_dai_active(cpu_dai)) { 556 spdif_intr_status_clear(spdif_priv); 557 regmap_update_bits(regmap, REG_SPDIF_SCR, 558 SCR_LOW_POWER, SCR_LOW_POWER); 559 } 560 } 561 562 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 563 struct snd_pcm_hw_params *params, 564 struct snd_soc_dai *dai) 565 { 566 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 567 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 568 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 569 struct platform_device *pdev = spdif_priv->pdev; 570 u32 sample_rate = params_rate(params); 571 int ret = 0; 572 573 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 574 ret = spdif_set_sample_rate(substream, sample_rate); 575 if (ret) { 576 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 577 __func__, sample_rate); 578 return ret; 579 } 580 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 581 IEC958_AES3_CON_CLOCK_1000PPM); 582 spdif_write_channel_status(spdif_priv); 583 } else { 584 /* Setup rx clock source */ 585 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 586 } 587 588 return ret; 589 } 590 591 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 592 int cmd, struct snd_soc_dai *dai) 593 { 594 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 595 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 596 struct regmap *regmap = spdif_priv->regmap; 597 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 598 u32 intr = SIE_INTR_FOR(tx); 599 u32 dmaen = SCR_DMA_xX_EN(tx); 600 601 switch (cmd) { 602 case SNDRV_PCM_TRIGGER_START: 603 case SNDRV_PCM_TRIGGER_RESUME: 604 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 605 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 606 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 607 break; 608 case SNDRV_PCM_TRIGGER_STOP: 609 case SNDRV_PCM_TRIGGER_SUSPEND: 610 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 611 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 612 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 return 0; 619 } 620 621 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 622 .startup = fsl_spdif_startup, 623 .hw_params = fsl_spdif_hw_params, 624 .trigger = fsl_spdif_trigger, 625 .shutdown = fsl_spdif_shutdown, 626 }; 627 628 629 /* 630 * FSL SPDIF IEC958 controller(mixer) functions 631 * 632 * Channel status get/put control 633 * User bit value get/put control 634 * Valid bit value get control 635 * DPLL lock status get control 636 * User bit sync mode selection control 637 */ 638 639 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 640 struct snd_ctl_elem_info *uinfo) 641 { 642 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 643 uinfo->count = 1; 644 645 return 0; 646 } 647 648 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 649 struct snd_ctl_elem_value *uvalue) 650 { 651 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 652 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 653 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 654 655 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 656 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 657 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 658 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 659 660 return 0; 661 } 662 663 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 664 struct snd_ctl_elem_value *uvalue) 665 { 666 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 667 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 668 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 669 670 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 671 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 672 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 673 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 674 675 spdif_write_channel_status(spdif_priv); 676 677 return 0; 678 } 679 680 /* Get channel status from SPDIF_RX_CCHAN register */ 681 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 682 struct snd_ctl_elem_value *ucontrol) 683 { 684 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 685 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 686 struct regmap *regmap = spdif_priv->regmap; 687 u32 cstatus, val; 688 689 regmap_read(regmap, REG_SPDIF_SIS, &val); 690 if (!(val & INT_CNEW)) 691 return -EAGAIN; 692 693 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 694 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 695 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 696 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 697 698 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 699 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 700 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 701 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 702 703 /* Clear intr */ 704 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 705 706 return 0; 707 } 708 709 /* 710 * Get User bits (subcode) from chip value which readed out 711 * in UChannel register. 712 */ 713 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 714 struct snd_ctl_elem_value *ucontrol) 715 { 716 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 717 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 718 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 719 unsigned long flags; 720 int ret = -EAGAIN; 721 722 spin_lock_irqsave(&ctrl->ctl_lock, flags); 723 if (ctrl->ready_buf) { 724 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 725 memcpy(&ucontrol->value.iec958.subcode[0], 726 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 727 ret = 0; 728 } 729 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 730 731 return ret; 732 } 733 734 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 735 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 736 struct snd_ctl_elem_info *uinfo) 737 { 738 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 739 uinfo->count = SPDIF_QSUB_SIZE; 740 741 return 0; 742 } 743 744 /* Get Q subcode from chip value which readed out in QChannel register */ 745 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 746 struct snd_ctl_elem_value *ucontrol) 747 { 748 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 749 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 750 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 751 unsigned long flags; 752 int ret = -EAGAIN; 753 754 spin_lock_irqsave(&ctrl->ctl_lock, flags); 755 if (ctrl->ready_buf) { 756 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 757 memcpy(&ucontrol->value.bytes.data[0], 758 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 759 ret = 0; 760 } 761 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 762 763 return ret; 764 } 765 766 /* Valid bit information */ 767 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, 768 struct snd_ctl_elem_info *uinfo) 769 { 770 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 771 uinfo->count = 1; 772 uinfo->value.integer.min = 0; 773 uinfo->value.integer.max = 1; 774 775 return 0; 776 } 777 778 /* Get valid good bit from interrupt status register */ 779 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 780 struct snd_ctl_elem_value *ucontrol) 781 { 782 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 783 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 784 struct regmap *regmap = spdif_priv->regmap; 785 u32 val; 786 787 regmap_read(regmap, REG_SPDIF_SIS, &val); 788 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 789 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 790 791 return 0; 792 } 793 794 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 795 struct snd_ctl_elem_value *ucontrol) 796 { 797 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 798 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 799 struct regmap *regmap = spdif_priv->regmap; 800 u32 val; 801 802 regmap_read(regmap, REG_SPDIF_SCR, &val); 803 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 804 val = 1 - val; 805 ucontrol->value.integer.value[0] = val; 806 807 return 0; 808 } 809 810 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 811 struct snd_ctl_elem_value *ucontrol) 812 { 813 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 814 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 815 struct regmap *regmap = spdif_priv->regmap; 816 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 817 818 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 819 820 return 0; 821 } 822 823 /* DPLL lock information */ 824 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 825 struct snd_ctl_elem_info *uinfo) 826 { 827 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 828 uinfo->count = 1; 829 uinfo->value.integer.min = 16000; 830 uinfo->value.integer.max = 96000; 831 832 return 0; 833 } 834 835 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 836 24, 16, 12, 8, 6, 4, 3, 837 }; 838 839 /* Get RX data clock rate given the SPDIF bus_clk */ 840 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 841 enum spdif_gainsel gainsel) 842 { 843 struct regmap *regmap = spdif_priv->regmap; 844 struct platform_device *pdev = spdif_priv->pdev; 845 u64 tmpval64, busclk_freq = 0; 846 u32 freqmeas, phaseconf; 847 u8 clksrc; 848 849 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 850 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 851 852 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 853 854 /* Get bus clock from system */ 855 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 856 busclk_freq = clk_get_rate(spdif_priv->sysclk); 857 858 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 859 tmpval64 = (u64) busclk_freq * freqmeas; 860 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 861 do_div(tmpval64, 128 * 1024); 862 863 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 864 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 865 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 866 867 return (int)tmpval64; 868 } 869 870 /* 871 * Get DPLL lock or not info from stable interrupt status register. 872 * User application must use this control to get locked, 873 * then can do next PCM operation 874 */ 875 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 876 struct snd_ctl_elem_value *ucontrol) 877 { 878 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 879 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 880 int rate = 0; 881 882 if (spdif_priv->dpll_locked) 883 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 884 885 ucontrol->value.integer.value[0] = rate; 886 887 return 0; 888 } 889 890 /* User bit sync mode info */ 891 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, 892 struct snd_ctl_elem_info *uinfo) 893 { 894 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 895 uinfo->count = 1; 896 uinfo->value.integer.min = 0; 897 uinfo->value.integer.max = 1; 898 899 return 0; 900 } 901 902 /* 903 * User bit sync mode: 904 * 1 CD User channel subcode 905 * 0 Non-CD data 906 */ 907 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 908 struct snd_ctl_elem_value *ucontrol) 909 { 910 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 911 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 912 struct regmap *regmap = spdif_priv->regmap; 913 u32 val; 914 915 regmap_read(regmap, REG_SPDIF_SRCD, &val); 916 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 917 918 return 0; 919 } 920 921 /* 922 * User bit sync mode: 923 * 1 CD User channel subcode 924 * 0 Non-CD data 925 */ 926 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 927 struct snd_ctl_elem_value *ucontrol) 928 { 929 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 930 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 931 struct regmap *regmap = spdif_priv->regmap; 932 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 933 934 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 935 936 return 0; 937 } 938 939 /* FSL SPDIF IEC958 controller defines */ 940 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 941 /* Status cchanel controller */ 942 { 943 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 944 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 945 .access = SNDRV_CTL_ELEM_ACCESS_READ | 946 SNDRV_CTL_ELEM_ACCESS_WRITE | 947 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 948 .info = fsl_spdif_info, 949 .get = fsl_spdif_pb_get, 950 .put = fsl_spdif_pb_put, 951 }, 952 { 953 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 954 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 955 .access = SNDRV_CTL_ELEM_ACCESS_READ | 956 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 957 .info = fsl_spdif_info, 958 .get = fsl_spdif_capture_get, 959 }, 960 /* User bits controller */ 961 { 962 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 963 .name = "IEC958 Subcode Capture Default", 964 .access = SNDRV_CTL_ELEM_ACCESS_READ | 965 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 966 .info = fsl_spdif_info, 967 .get = fsl_spdif_subcode_get, 968 }, 969 { 970 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 971 .name = "IEC958 Q-subcode Capture Default", 972 .access = SNDRV_CTL_ELEM_ACCESS_READ | 973 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 974 .info = fsl_spdif_qinfo, 975 .get = fsl_spdif_qget, 976 }, 977 /* Valid bit error controller */ 978 { 979 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 980 .name = "IEC958 RX V-Bit Errors", 981 .access = SNDRV_CTL_ELEM_ACCESS_READ | 982 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 983 .info = fsl_spdif_vbit_info, 984 .get = fsl_spdif_rx_vbit_get, 985 }, 986 { 987 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 988 .name = "IEC958 TX V-Bit", 989 .access = SNDRV_CTL_ELEM_ACCESS_READ | 990 SNDRV_CTL_ELEM_ACCESS_WRITE | 991 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 992 .info = fsl_spdif_vbit_info, 993 .get = fsl_spdif_tx_vbit_get, 994 .put = fsl_spdif_tx_vbit_put, 995 }, 996 /* DPLL lock info get controller */ 997 { 998 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 999 .name = "RX Sample Rate", 1000 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1001 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1002 .info = fsl_spdif_rxrate_info, 1003 .get = fsl_spdif_rxrate_get, 1004 }, 1005 /* User bit sync mode set/get controller */ 1006 { 1007 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1008 .name = "IEC958 USyncMode CDText", 1009 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1010 SNDRV_CTL_ELEM_ACCESS_WRITE | 1011 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1012 .info = fsl_spdif_usync_info, 1013 .get = fsl_spdif_usync_get, 1014 .put = fsl_spdif_usync_put, 1015 }, 1016 }; 1017 1018 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1019 { 1020 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1021 1022 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1023 &spdif_private->dma_params_rx); 1024 1025 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1026 1027 /*Clear the val bit for Tx*/ 1028 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1029 SCR_VAL_MASK, SCR_VAL_CLEAR); 1030 1031 return 0; 1032 } 1033 1034 static struct snd_soc_dai_driver fsl_spdif_dai = { 1035 .probe = &fsl_spdif_dai_probe, 1036 .playback = { 1037 .stream_name = "CPU-Playback", 1038 .channels_min = 2, 1039 .channels_max = 2, 1040 .rates = FSL_SPDIF_RATES_PLAYBACK, 1041 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1042 }, 1043 .capture = { 1044 .stream_name = "CPU-Capture", 1045 .channels_min = 2, 1046 .channels_max = 2, 1047 .rates = FSL_SPDIF_RATES_CAPTURE, 1048 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1049 }, 1050 .ops = &fsl_spdif_dai_ops, 1051 }; 1052 1053 static const struct snd_soc_component_driver fsl_spdif_component = { 1054 .name = "fsl-spdif", 1055 }; 1056 1057 /* FSL SPDIF REGMAP */ 1058 static const struct reg_default fsl_spdif_reg_defaults[] = { 1059 {REG_SPDIF_SCR, 0x00000400}, 1060 {REG_SPDIF_SRCD, 0x00000000}, 1061 {REG_SPDIF_SIE, 0x00000000}, 1062 {REG_SPDIF_STL, 0x00000000}, 1063 {REG_SPDIF_STR, 0x00000000}, 1064 {REG_SPDIF_STCSCH, 0x00000000}, 1065 {REG_SPDIF_STCSCL, 0x00000000}, 1066 {REG_SPDIF_STC, 0x00020f00}, 1067 }; 1068 1069 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1070 { 1071 switch (reg) { 1072 case REG_SPDIF_SCR: 1073 case REG_SPDIF_SRCD: 1074 case REG_SPDIF_SRPC: 1075 case REG_SPDIF_SIE: 1076 case REG_SPDIF_SIS: 1077 case REG_SPDIF_SRL: 1078 case REG_SPDIF_SRR: 1079 case REG_SPDIF_SRCSH: 1080 case REG_SPDIF_SRCSL: 1081 case REG_SPDIF_SRU: 1082 case REG_SPDIF_SRQ: 1083 case REG_SPDIF_STCSCH: 1084 case REG_SPDIF_STCSCL: 1085 case REG_SPDIF_SRFM: 1086 case REG_SPDIF_STC: 1087 return true; 1088 default: 1089 return false; 1090 } 1091 } 1092 1093 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1094 { 1095 switch (reg) { 1096 case REG_SPDIF_SRPC: 1097 case REG_SPDIF_SIS: 1098 case REG_SPDIF_SRL: 1099 case REG_SPDIF_SRR: 1100 case REG_SPDIF_SRCSH: 1101 case REG_SPDIF_SRCSL: 1102 case REG_SPDIF_SRU: 1103 case REG_SPDIF_SRQ: 1104 case REG_SPDIF_SRFM: 1105 return true; 1106 default: 1107 return false; 1108 } 1109 } 1110 1111 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1112 { 1113 switch (reg) { 1114 case REG_SPDIF_SCR: 1115 case REG_SPDIF_SRCD: 1116 case REG_SPDIF_SRPC: 1117 case REG_SPDIF_SIE: 1118 case REG_SPDIF_SIC: 1119 case REG_SPDIF_STL: 1120 case REG_SPDIF_STR: 1121 case REG_SPDIF_STCSCH: 1122 case REG_SPDIF_STCSCL: 1123 case REG_SPDIF_STC: 1124 return true; 1125 default: 1126 return false; 1127 } 1128 } 1129 1130 static const struct regmap_config fsl_spdif_regmap_config = { 1131 .reg_bits = 32, 1132 .reg_stride = 4, 1133 .val_bits = 32, 1134 1135 .max_register = REG_SPDIF_STC, 1136 .reg_defaults = fsl_spdif_reg_defaults, 1137 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1138 .readable_reg = fsl_spdif_readable_reg, 1139 .volatile_reg = fsl_spdif_volatile_reg, 1140 .writeable_reg = fsl_spdif_writeable_reg, 1141 .cache_type = REGCACHE_FLAT, 1142 }; 1143 1144 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1145 struct clk *clk, u64 savesub, 1146 enum spdif_txrate index, bool round) 1147 { 1148 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1149 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1150 u64 rate_ideal, rate_actual, sub; 1151 u32 arate; 1152 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1153 u8 txclk_df; 1154 1155 /* The sysclk has an extra divisor [2, 512] */ 1156 sysclk_dfmin = is_sysclk ? 2 : 1; 1157 sysclk_dfmax = is_sysclk ? 512 : 1; 1158 1159 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1160 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1161 rate_ideal = rate[index] * txclk_df * 64ULL; 1162 if (round) 1163 rate_actual = clk_round_rate(clk, rate_ideal); 1164 else 1165 rate_actual = clk_get_rate(clk); 1166 1167 arate = rate_actual / 64; 1168 arate /= txclk_df * sysclk_df; 1169 1170 if (arate == rate[index]) { 1171 /* We are lucky */ 1172 savesub = 0; 1173 spdif_priv->txclk_df[index] = txclk_df; 1174 spdif_priv->sysclk_df[index] = sysclk_df; 1175 spdif_priv->txrate[index] = arate; 1176 goto out; 1177 } else if (arate / rate[index] == 1) { 1178 /* A little bigger than expect */ 1179 sub = (u64)(arate - rate[index]) * 100000; 1180 do_div(sub, rate[index]); 1181 if (sub >= savesub) 1182 continue; 1183 savesub = sub; 1184 spdif_priv->txclk_df[index] = txclk_df; 1185 spdif_priv->sysclk_df[index] = sysclk_df; 1186 spdif_priv->txrate[index] = arate; 1187 } else if (rate[index] / arate == 1) { 1188 /* A little smaller than expect */ 1189 sub = (u64)(rate[index] - arate) * 100000; 1190 do_div(sub, rate[index]); 1191 if (sub >= savesub) 1192 continue; 1193 savesub = sub; 1194 spdif_priv->txclk_df[index] = txclk_df; 1195 spdif_priv->sysclk_df[index] = sysclk_df; 1196 spdif_priv->txrate[index] = arate; 1197 } 1198 } 1199 } 1200 1201 out: 1202 return savesub; 1203 } 1204 1205 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1206 enum spdif_txrate index) 1207 { 1208 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1209 struct platform_device *pdev = spdif_priv->pdev; 1210 struct device *dev = &pdev->dev; 1211 u64 savesub = 100000, ret; 1212 struct clk *clk; 1213 char tmp[16]; 1214 int i; 1215 1216 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1217 sprintf(tmp, "rxtx%d", i); 1218 clk = devm_clk_get(&pdev->dev, tmp); 1219 if (IS_ERR(clk)) { 1220 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1221 return PTR_ERR(clk); 1222 } 1223 if (!clk_get_rate(clk)) 1224 continue; 1225 1226 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1227 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1228 if (savesub == ret) 1229 continue; 1230 1231 savesub = ret; 1232 spdif_priv->txclk[index] = clk; 1233 spdif_priv->txclk_src[index] = i; 1234 1235 /* To quick catch a divisor, we allow a 0.1% deviation */ 1236 if (savesub < 100) 1237 break; 1238 } 1239 1240 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1241 spdif_priv->txclk_src[index], rate[index]); 1242 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", 1243 spdif_priv->txclk_df[index], rate[index]); 1244 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1245 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", 1246 spdif_priv->sysclk_df[index], rate[index]); 1247 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", 1248 rate[index], spdif_priv->txrate[index]); 1249 1250 return 0; 1251 } 1252 1253 static int fsl_spdif_probe(struct platform_device *pdev) 1254 { 1255 struct device_node *np = pdev->dev.of_node; 1256 struct fsl_spdif_priv *spdif_priv; 1257 struct spdif_mixer_control *ctrl; 1258 struct resource *res; 1259 void __iomem *regs; 1260 int irq, ret, i; 1261 1262 if (!np) 1263 return -ENODEV; 1264 1265 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1266 if (!spdif_priv) 1267 return -ENOMEM; 1268 1269 spdif_priv->pdev = pdev; 1270 1271 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1272 if (!spdif_priv->soc) { 1273 dev_err(&pdev->dev, "failed to get soc data\n"); 1274 return -ENODEV; 1275 } 1276 1277 /* Initialize this copy of the CPU DAI driver structure */ 1278 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1279 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1280 1281 /* Get the addresses and IRQ */ 1282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1283 regs = devm_ioremap_resource(&pdev->dev, res); 1284 if (IS_ERR(regs)) 1285 return PTR_ERR(regs); 1286 1287 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1288 "core", regs, &fsl_spdif_regmap_config); 1289 if (IS_ERR(spdif_priv->regmap)) { 1290 dev_err(&pdev->dev, "regmap init failed\n"); 1291 return PTR_ERR(spdif_priv->regmap); 1292 } 1293 1294 irq = platform_get_irq(pdev, 0); 1295 if (irq < 0) 1296 return irq; 1297 1298 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1299 dev_name(&pdev->dev), spdif_priv); 1300 if (ret) { 1301 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1302 return ret; 1303 } 1304 1305 /* Get system clock for rx clock rate calculation */ 1306 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1307 if (IS_ERR(spdif_priv->sysclk)) { 1308 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1309 return PTR_ERR(spdif_priv->sysclk); 1310 } 1311 1312 /* Get core clock for data register access via DMA */ 1313 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1314 if (IS_ERR(spdif_priv->coreclk)) { 1315 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1316 return PTR_ERR(spdif_priv->coreclk); 1317 } 1318 1319 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1320 if (IS_ERR(spdif_priv->spbaclk)) 1321 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1322 1323 /* Select clock source for rx/tx clock */ 1324 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1325 if (IS_ERR(spdif_priv->rxclk)) { 1326 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1327 return PTR_ERR(spdif_priv->rxclk); 1328 } 1329 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1330 1331 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1332 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1333 if (ret) 1334 return ret; 1335 } 1336 1337 /* Initial spinlock for control data */ 1338 ctrl = &spdif_priv->fsl_spdif_control; 1339 spin_lock_init(&ctrl->ctl_lock); 1340 1341 /* Init tx channel status default value */ 1342 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1343 IEC958_AES0_CON_EMPHASIS_5015; 1344 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1345 ctrl->ch_status[2] = 0x00; 1346 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1347 IEC958_AES3_CON_CLOCK_1000PPM; 1348 1349 spdif_priv->dpll_locked = false; 1350 1351 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; 1352 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; 1353 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1354 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1355 1356 /* Register with ASoC */ 1357 dev_set_drvdata(&pdev->dev, spdif_priv); 1358 pm_runtime_enable(&pdev->dev); 1359 regcache_cache_only(spdif_priv->regmap, true); 1360 1361 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1362 &spdif_priv->cpu_dai_drv, 1); 1363 if (ret) { 1364 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1365 return ret; 1366 } 1367 1368 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1369 if (ret && ret != -EPROBE_DEFER) 1370 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); 1371 1372 return ret; 1373 } 1374 1375 #ifdef CONFIG_PM 1376 static int fsl_spdif_runtime_suspend(struct device *dev) 1377 { 1378 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1379 int i; 1380 1381 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1382 &spdif_priv->regcache_srpc); 1383 regcache_cache_only(spdif_priv->regmap, true); 1384 1385 clk_disable_unprepare(spdif_priv->rxclk); 1386 1387 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 1388 clk_disable_unprepare(spdif_priv->txclk[i]); 1389 1390 if (!IS_ERR(spdif_priv->spbaclk)) 1391 clk_disable_unprepare(spdif_priv->spbaclk); 1392 clk_disable_unprepare(spdif_priv->coreclk); 1393 1394 return 0; 1395 } 1396 1397 static int fsl_spdif_runtime_resume(struct device *dev) 1398 { 1399 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1400 int ret; 1401 int i; 1402 1403 ret = clk_prepare_enable(spdif_priv->coreclk); 1404 if (ret) { 1405 dev_err(dev, "failed to enable core clock\n"); 1406 return ret; 1407 } 1408 1409 if (!IS_ERR(spdif_priv->spbaclk)) { 1410 ret = clk_prepare_enable(spdif_priv->spbaclk); 1411 if (ret) { 1412 dev_err(dev, "failed to enable spba clock\n"); 1413 goto disable_core_clk; 1414 } 1415 } 1416 1417 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1418 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1419 if (ret) 1420 goto disable_tx_clk; 1421 } 1422 1423 ret = clk_prepare_enable(spdif_priv->rxclk); 1424 if (ret) 1425 goto disable_tx_clk; 1426 1427 regcache_cache_only(spdif_priv->regmap, false); 1428 regcache_mark_dirty(spdif_priv->regmap); 1429 1430 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1431 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1432 spdif_priv->regcache_srpc); 1433 1434 ret = regcache_sync(spdif_priv->regmap); 1435 if (ret) 1436 goto disable_rx_clk; 1437 1438 return 0; 1439 1440 disable_rx_clk: 1441 clk_disable_unprepare(spdif_priv->rxclk); 1442 disable_tx_clk: 1443 for (i--; i >= 0; i--) 1444 clk_disable_unprepare(spdif_priv->txclk[i]); 1445 if (!IS_ERR(spdif_priv->spbaclk)) 1446 clk_disable_unprepare(spdif_priv->spbaclk); 1447 disable_core_clk: 1448 clk_disable_unprepare(spdif_priv->coreclk); 1449 1450 return ret; 1451 } 1452 #endif /* CONFIG_PM */ 1453 1454 static const struct dev_pm_ops fsl_spdif_pm = { 1455 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1456 pm_runtime_force_resume) 1457 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1458 NULL) 1459 }; 1460 1461 static const struct of_device_id fsl_spdif_dt_ids[] = { 1462 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1463 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1464 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1465 {} 1466 }; 1467 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1468 1469 static struct platform_driver fsl_spdif_driver = { 1470 .driver = { 1471 .name = "fsl-spdif-dai", 1472 .of_match_table = fsl_spdif_dt_ids, 1473 .pm = &fsl_spdif_pm, 1474 }, 1475 .probe = fsl_spdif_probe, 1476 }; 1477 1478 module_platform_driver(fsl_spdif_driver); 1479 1480 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1481 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1482 MODULE_LICENSE("GPL v2"); 1483 MODULE_ALIAS("platform:fsl-spdif-dai"); 1484