1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 20 #include <sound/asoundef.h> 21 #include <sound/dmaengine_pcm.h> 22 #include <sound/soc.h> 23 24 #include "fsl_spdif.h" 25 #include "imx-pcm.h" 26 27 #define FSL_SPDIF_TXFIFO_WML 0x8 28 #define FSL_SPDIF_RXFIFO_WML 0x8 29 30 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 31 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 32 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 33 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 34 INT_LOSS_LOCK | INT_DPLL_LOCKED) 35 36 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 37 38 /* Index list for the values that has if (DPLL Locked) condition */ 39 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 40 #define SRPC_NODPLL_START1 0x5 41 #define SRPC_NODPLL_START2 0xc 42 43 #define DEFAULT_RXCLK_SRC 1 44 45 /* 46 * SPDIF control structure 47 * Defines channel status, subcode and Q sub 48 */ 49 struct spdif_mixer_control { 50 /* spinlock to access control data */ 51 spinlock_t ctl_lock; 52 53 /* IEC958 channel tx status bit */ 54 unsigned char ch_status[4]; 55 56 /* User bits */ 57 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 58 59 /* Q subcode part of user bits */ 60 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 61 62 /* Buffer offset for U/Q */ 63 u32 upos; 64 u32 qpos; 65 66 /* Ready buffer index of the two buffers */ 67 u32 ready_buf; 68 }; 69 70 /** 71 * fsl_spdif_priv: Freescale SPDIF private data 72 * 73 * @fsl_spdif_control: SPDIF control data 74 * @cpu_dai_drv: cpu dai driver 75 * @pdev: platform device pointer 76 * @regmap: regmap handler 77 * @dpll_locked: dpll lock flag 78 * @txrate: the best rates for playback 79 * @txclk_df: STC_TXCLK_DF dividers value for playback 80 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 81 * @txclk_src: STC_TXCLK_SRC values for playback 82 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 83 * @txclk: tx clock sources for playback 84 * @rxclk: rx clock sources for capture 85 * @coreclk: core clock for register access via DMA 86 * @sysclk: system clock for rx clock rate measurement 87 * @spbaclk: SPBA clock (optional, depending on SoC design) 88 * @dma_params_tx: DMA parameters for transmit channel 89 * @dma_params_rx: DMA parameters for receive channel 90 */ 91 struct fsl_spdif_priv { 92 struct spdif_mixer_control fsl_spdif_control; 93 struct snd_soc_dai_driver cpu_dai_drv; 94 struct platform_device *pdev; 95 struct regmap *regmap; 96 bool dpll_locked; 97 u32 txrate[SPDIF_TXRATE_MAX]; 98 u8 txclk_df[SPDIF_TXRATE_MAX]; 99 u8 sysclk_df[SPDIF_TXRATE_MAX]; 100 u8 txclk_src[SPDIF_TXRATE_MAX]; 101 u8 rxclk_src; 102 struct clk *txclk[SPDIF_TXRATE_MAX]; 103 struct clk *rxclk; 104 struct clk *coreclk; 105 struct clk *sysclk; 106 struct clk *spbaclk; 107 struct snd_dmaengine_dai_dma_data dma_params_tx; 108 struct snd_dmaengine_dai_dma_data dma_params_rx; 109 /* regcache for SRPC */ 110 u32 regcache_srpc; 111 }; 112 113 /* DPLL locked and lock loss interrupt handler */ 114 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 115 { 116 struct regmap *regmap = spdif_priv->regmap; 117 struct platform_device *pdev = spdif_priv->pdev; 118 u32 locked; 119 120 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 121 locked &= SRPC_DPLL_LOCKED; 122 123 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 124 locked ? "locked" : "loss lock"); 125 126 spdif_priv->dpll_locked = locked ? true : false; 127 } 128 129 /* Receiver found illegal symbol interrupt handler */ 130 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 131 { 132 struct regmap *regmap = spdif_priv->regmap; 133 struct platform_device *pdev = spdif_priv->pdev; 134 135 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 136 137 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 138 if (!spdif_priv->dpll_locked) 139 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 140 } 141 142 /* U/Q Channel receive register full */ 143 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 144 { 145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 146 struct regmap *regmap = spdif_priv->regmap; 147 struct platform_device *pdev = spdif_priv->pdev; 148 u32 *pos, size, val, reg; 149 150 switch (name) { 151 case 'U': 152 pos = &ctrl->upos; 153 size = SPDIF_UBITS_SIZE; 154 reg = REG_SPDIF_SRU; 155 break; 156 case 'Q': 157 pos = &ctrl->qpos; 158 size = SPDIF_QSUB_SIZE; 159 reg = REG_SPDIF_SRQ; 160 break; 161 default: 162 dev_err(&pdev->dev, "unsupported channel name\n"); 163 return; 164 } 165 166 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 167 168 if (*pos >= size * 2) { 169 *pos = 0; 170 } else if (unlikely((*pos % size) + 3 > size)) { 171 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 172 return; 173 } 174 175 regmap_read(regmap, reg, &val); 176 ctrl->subcode[*pos++] = val >> 16; 177 ctrl->subcode[*pos++] = val >> 8; 178 ctrl->subcode[*pos++] = val; 179 } 180 181 /* U/Q Channel sync found */ 182 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 183 { 184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 185 struct platform_device *pdev = spdif_priv->pdev; 186 187 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 188 189 /* U/Q buffer reset */ 190 if (ctrl->qpos == 0) 191 return; 192 193 /* Set ready to this buffer */ 194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 195 } 196 197 /* U/Q Channel framing error */ 198 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 199 { 200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 201 struct regmap *regmap = spdif_priv->regmap; 202 struct platform_device *pdev = spdif_priv->pdev; 203 u32 val; 204 205 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 206 207 /* Read U/Q data to clear the irq and do buffer reset */ 208 regmap_read(regmap, REG_SPDIF_SRU, &val); 209 regmap_read(regmap, REG_SPDIF_SRQ, &val); 210 211 /* Drop this U/Q buffer */ 212 ctrl->ready_buf = 0; 213 ctrl->upos = 0; 214 ctrl->qpos = 0; 215 } 216 217 /* Get spdif interrupt status and clear the interrupt */ 218 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 219 { 220 struct regmap *regmap = spdif_priv->regmap; 221 u32 val, val2; 222 223 regmap_read(regmap, REG_SPDIF_SIS, &val); 224 regmap_read(regmap, REG_SPDIF_SIE, &val2); 225 226 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 227 228 return val; 229 } 230 231 static irqreturn_t spdif_isr(int irq, void *devid) 232 { 233 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 234 struct platform_device *pdev = spdif_priv->pdev; 235 u32 sis; 236 237 sis = spdif_intr_status_clear(spdif_priv); 238 239 if (sis & INT_DPLL_LOCKED) 240 spdif_irq_dpll_lock(spdif_priv); 241 242 if (sis & INT_TXFIFO_UNOV) 243 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 244 245 if (sis & INT_TXFIFO_RESYNC) 246 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 247 248 if (sis & INT_CNEW) 249 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 250 251 if (sis & INT_VAL_NOGOOD) 252 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 253 254 if (sis & INT_SYM_ERR) 255 spdif_irq_sym_error(spdif_priv); 256 257 if (sis & INT_BIT_ERR) 258 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 259 260 if (sis & INT_URX_FUL) 261 spdif_irq_uqrx_full(spdif_priv, 'U'); 262 263 if (sis & INT_URX_OV) 264 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 265 266 if (sis & INT_QRX_FUL) 267 spdif_irq_uqrx_full(spdif_priv, 'Q'); 268 269 if (sis & INT_QRX_OV) 270 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 271 272 if (sis & INT_UQ_SYNC) 273 spdif_irq_uq_sync(spdif_priv); 274 275 if (sis & INT_UQ_ERR) 276 spdif_irq_uq_err(spdif_priv); 277 278 if (sis & INT_RXFIFO_UNOV) 279 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 280 281 if (sis & INT_RXFIFO_RESYNC) 282 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 283 284 if (sis & INT_LOSS_LOCK) 285 spdif_irq_dpll_lock(spdif_priv); 286 287 /* FIXME: Write Tx FIFO to clear TxEm */ 288 if (sis & INT_TX_EM) 289 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 290 291 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 292 if (sis & INT_RXFIFO_FUL) 293 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 294 295 return IRQ_HANDLED; 296 } 297 298 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 299 { 300 struct regmap *regmap = spdif_priv->regmap; 301 u32 val, cycle = 1000; 302 303 regcache_cache_bypass(regmap, true); 304 305 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 306 307 /* 308 * RESET bit would be cleared after finishing its reset procedure, 309 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 310 */ 311 do { 312 regmap_read(regmap, REG_SPDIF_SCR, &val); 313 } while ((val & SCR_SOFT_RESET) && cycle--); 314 315 regcache_cache_bypass(regmap, false); 316 regcache_mark_dirty(regmap); 317 regcache_sync(regmap); 318 319 if (cycle) 320 return 0; 321 else 322 return -EBUSY; 323 } 324 325 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 326 u8 mask, u8 cstatus) 327 { 328 ctrl->ch_status[3] &= ~mask; 329 ctrl->ch_status[3] |= cstatus & mask; 330 } 331 332 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 333 { 334 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 335 struct regmap *regmap = spdif_priv->regmap; 336 struct platform_device *pdev = spdif_priv->pdev; 337 u32 ch_status; 338 339 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 340 (bitrev8(ctrl->ch_status[1]) << 8) | 341 bitrev8(ctrl->ch_status[2]); 342 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 343 344 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 345 346 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 347 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 348 349 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 350 } 351 352 /* Set SPDIF PhaseConfig register for rx clock */ 353 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 354 enum spdif_gainsel gainsel, int dpll_locked) 355 { 356 struct regmap *regmap = spdif_priv->regmap; 357 u8 clksrc = spdif_priv->rxclk_src; 358 359 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 360 return -EINVAL; 361 362 regmap_update_bits(regmap, REG_SPDIF_SRPC, 363 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 364 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 365 366 return 0; 367 } 368 369 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 370 int sample_rate) 371 { 372 struct snd_soc_pcm_runtime *rtd = substream->private_data; 373 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 374 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 375 struct regmap *regmap = spdif_priv->regmap; 376 struct platform_device *pdev = spdif_priv->pdev; 377 unsigned long csfs = 0; 378 u32 stc, mask, rate; 379 u8 clk, txclk_df, sysclk_df; 380 int ret; 381 382 switch (sample_rate) { 383 case 32000: 384 rate = SPDIF_TXRATE_32000; 385 csfs = IEC958_AES3_CON_FS_32000; 386 break; 387 case 44100: 388 rate = SPDIF_TXRATE_44100; 389 csfs = IEC958_AES3_CON_FS_44100; 390 break; 391 case 48000: 392 rate = SPDIF_TXRATE_48000; 393 csfs = IEC958_AES3_CON_FS_48000; 394 break; 395 case 96000: 396 rate = SPDIF_TXRATE_96000; 397 csfs = IEC958_AES3_CON_FS_96000; 398 break; 399 case 192000: 400 rate = SPDIF_TXRATE_192000; 401 csfs = IEC958_AES3_CON_FS_192000; 402 break; 403 default: 404 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 405 return -EINVAL; 406 } 407 408 clk = spdif_priv->txclk_src[rate]; 409 if (clk >= STC_TXCLK_SRC_MAX) { 410 dev_err(&pdev->dev, "tx clock source is out of range\n"); 411 return -EINVAL; 412 } 413 414 txclk_df = spdif_priv->txclk_df[rate]; 415 if (txclk_df == 0) { 416 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 417 return -EINVAL; 418 } 419 420 sysclk_df = spdif_priv->sysclk_df[rate]; 421 422 /* Don't mess up the clocks from other modules */ 423 if (clk != STC_TXCLK_SPDIF_ROOT) 424 goto clk_set_bypass; 425 426 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 427 ret = clk_set_rate(spdif_priv->txclk[rate], 428 64 * sample_rate * txclk_df); 429 if (ret) { 430 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 431 return ret; 432 } 433 434 clk_set_bypass: 435 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 436 (64 * sample_rate * txclk_df * sysclk_df)); 437 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 438 clk_get_rate(spdif_priv->txclk[rate])); 439 440 /* set fs field in consumer channel status */ 441 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 442 443 /* select clock source and divisor */ 444 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 445 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 446 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 447 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 448 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 449 450 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 451 spdif_priv->txrate[rate], sample_rate); 452 453 return 0; 454 } 455 456 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 457 struct snd_soc_dai *cpu_dai) 458 { 459 struct snd_soc_pcm_runtime *rtd = substream->private_data; 460 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 461 struct platform_device *pdev = spdif_priv->pdev; 462 struct regmap *regmap = spdif_priv->regmap; 463 u32 scr, mask; 464 int i; 465 int ret; 466 467 /* Reset module and interrupts only for first initialization */ 468 if (!cpu_dai->active) { 469 ret = clk_prepare_enable(spdif_priv->coreclk); 470 if (ret) { 471 dev_err(&pdev->dev, "failed to enable core clock\n"); 472 return ret; 473 } 474 475 if (!IS_ERR(spdif_priv->spbaclk)) { 476 ret = clk_prepare_enable(spdif_priv->spbaclk); 477 if (ret) { 478 dev_err(&pdev->dev, "failed to enable spba clock\n"); 479 goto err_spbaclk; 480 } 481 } 482 483 ret = spdif_softreset(spdif_priv); 484 if (ret) { 485 dev_err(&pdev->dev, "failed to soft reset\n"); 486 goto err; 487 } 488 489 /* Disable all the interrupts */ 490 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 491 } 492 493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 494 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 495 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 496 SCR_TXFIFO_FSEL_IF8; 497 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 498 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 499 SCR_TXFIFO_FSEL_MASK; 500 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 501 ret = clk_prepare_enable(spdif_priv->txclk[i]); 502 if (ret) 503 goto disable_txclk; 504 } 505 } else { 506 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 507 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 508 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 509 ret = clk_prepare_enable(spdif_priv->rxclk); 510 if (ret) 511 goto err; 512 } 513 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 514 515 /* Power up SPDIF module */ 516 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 517 518 return 0; 519 520 disable_txclk: 521 for (i--; i >= 0; i--) 522 clk_disable_unprepare(spdif_priv->txclk[i]); 523 err: 524 if (!IS_ERR(spdif_priv->spbaclk)) 525 clk_disable_unprepare(spdif_priv->spbaclk); 526 err_spbaclk: 527 clk_disable_unprepare(spdif_priv->coreclk); 528 529 return ret; 530 } 531 532 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 533 struct snd_soc_dai *cpu_dai) 534 { 535 struct snd_soc_pcm_runtime *rtd = substream->private_data; 536 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 537 struct regmap *regmap = spdif_priv->regmap; 538 u32 scr, mask, i; 539 540 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 541 scr = 0; 542 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 543 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 544 SCR_TXFIFO_FSEL_MASK; 545 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 546 clk_disable_unprepare(spdif_priv->txclk[i]); 547 } else { 548 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 549 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 550 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 551 clk_disable_unprepare(spdif_priv->rxclk); 552 } 553 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 554 555 /* Power down SPDIF module only if tx&rx are both inactive */ 556 if (!cpu_dai->active) { 557 spdif_intr_status_clear(spdif_priv); 558 regmap_update_bits(regmap, REG_SPDIF_SCR, 559 SCR_LOW_POWER, SCR_LOW_POWER); 560 if (!IS_ERR(spdif_priv->spbaclk)) 561 clk_disable_unprepare(spdif_priv->spbaclk); 562 clk_disable_unprepare(spdif_priv->coreclk); 563 } 564 } 565 566 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 567 struct snd_pcm_hw_params *params, 568 struct snd_soc_dai *dai) 569 { 570 struct snd_soc_pcm_runtime *rtd = substream->private_data; 571 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 572 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 573 struct platform_device *pdev = spdif_priv->pdev; 574 u32 sample_rate = params_rate(params); 575 int ret = 0; 576 577 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 578 ret = spdif_set_sample_rate(substream, sample_rate); 579 if (ret) { 580 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 581 __func__, sample_rate); 582 return ret; 583 } 584 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 585 IEC958_AES3_CON_CLOCK_1000PPM); 586 spdif_write_channel_status(spdif_priv); 587 } else { 588 /* Setup rx clock source */ 589 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 590 } 591 592 return ret; 593 } 594 595 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 596 int cmd, struct snd_soc_dai *dai) 597 { 598 struct snd_soc_pcm_runtime *rtd = substream->private_data; 599 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai); 600 struct regmap *regmap = spdif_priv->regmap; 601 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 602 u32 intr = SIE_INTR_FOR(tx); 603 u32 dmaen = SCR_DMA_xX_EN(tx); 604 605 switch (cmd) { 606 case SNDRV_PCM_TRIGGER_START: 607 case SNDRV_PCM_TRIGGER_RESUME: 608 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 609 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 610 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 611 break; 612 case SNDRV_PCM_TRIGGER_STOP: 613 case SNDRV_PCM_TRIGGER_SUSPEND: 614 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 615 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 616 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 617 break; 618 default: 619 return -EINVAL; 620 } 621 622 return 0; 623 } 624 625 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 626 .startup = fsl_spdif_startup, 627 .hw_params = fsl_spdif_hw_params, 628 .trigger = fsl_spdif_trigger, 629 .shutdown = fsl_spdif_shutdown, 630 }; 631 632 633 /* 634 * FSL SPDIF IEC958 controller(mixer) functions 635 * 636 * Channel status get/put control 637 * User bit value get/put control 638 * Valid bit value get control 639 * DPLL lock status get control 640 * User bit sync mode selection control 641 */ 642 643 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 644 struct snd_ctl_elem_info *uinfo) 645 { 646 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 647 uinfo->count = 1; 648 649 return 0; 650 } 651 652 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 653 struct snd_ctl_elem_value *uvalue) 654 { 655 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 656 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 657 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 658 659 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 660 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 661 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 662 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 663 664 return 0; 665 } 666 667 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 668 struct snd_ctl_elem_value *uvalue) 669 { 670 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 671 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 672 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 673 674 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 675 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 676 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 677 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 678 679 spdif_write_channel_status(spdif_priv); 680 681 return 0; 682 } 683 684 /* Get channel status from SPDIF_RX_CCHAN register */ 685 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 686 struct snd_ctl_elem_value *ucontrol) 687 { 688 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 689 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 690 struct regmap *regmap = spdif_priv->regmap; 691 u32 cstatus, val; 692 693 regmap_read(regmap, REG_SPDIF_SIS, &val); 694 if (!(val & INT_CNEW)) 695 return -EAGAIN; 696 697 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 698 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 699 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 700 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 701 702 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 703 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 704 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 705 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 706 707 /* Clear intr */ 708 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 709 710 return 0; 711 } 712 713 /* 714 * Get User bits (subcode) from chip value which readed out 715 * in UChannel register. 716 */ 717 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 718 struct snd_ctl_elem_value *ucontrol) 719 { 720 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 721 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 722 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 723 unsigned long flags; 724 int ret = -EAGAIN; 725 726 spin_lock_irqsave(&ctrl->ctl_lock, flags); 727 if (ctrl->ready_buf) { 728 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 729 memcpy(&ucontrol->value.iec958.subcode[0], 730 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 731 ret = 0; 732 } 733 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 734 735 return ret; 736 } 737 738 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 739 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 740 struct snd_ctl_elem_info *uinfo) 741 { 742 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 743 uinfo->count = SPDIF_QSUB_SIZE; 744 745 return 0; 746 } 747 748 /* Get Q subcode from chip value which readed out in QChannel register */ 749 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 750 struct snd_ctl_elem_value *ucontrol) 751 { 752 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 753 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 754 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 755 unsigned long flags; 756 int ret = -EAGAIN; 757 758 spin_lock_irqsave(&ctrl->ctl_lock, flags); 759 if (ctrl->ready_buf) { 760 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 761 memcpy(&ucontrol->value.bytes.data[0], 762 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 763 ret = 0; 764 } 765 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 766 767 return ret; 768 } 769 770 /* Valid bit information */ 771 static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol, 772 struct snd_ctl_elem_info *uinfo) 773 { 774 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 775 uinfo->count = 1; 776 uinfo->value.integer.min = 0; 777 uinfo->value.integer.max = 1; 778 779 return 0; 780 } 781 782 /* Get valid good bit from interrupt status register */ 783 static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol, 784 struct snd_ctl_elem_value *ucontrol) 785 { 786 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 787 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 788 struct regmap *regmap = spdif_priv->regmap; 789 u32 val; 790 791 regmap_read(regmap, REG_SPDIF_SIS, &val); 792 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 793 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 794 795 return 0; 796 } 797 798 /* DPLL lock information */ 799 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 800 struct snd_ctl_elem_info *uinfo) 801 { 802 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 803 uinfo->count = 1; 804 uinfo->value.integer.min = 16000; 805 uinfo->value.integer.max = 96000; 806 807 return 0; 808 } 809 810 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 811 24, 16, 12, 8, 6, 4, 3, 812 }; 813 814 /* Get RX data clock rate given the SPDIF bus_clk */ 815 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 816 enum spdif_gainsel gainsel) 817 { 818 struct regmap *regmap = spdif_priv->regmap; 819 struct platform_device *pdev = spdif_priv->pdev; 820 u64 tmpval64, busclk_freq = 0; 821 u32 freqmeas, phaseconf; 822 u8 clksrc; 823 824 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 825 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 826 827 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 828 829 /* Get bus clock from system */ 830 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 831 busclk_freq = clk_get_rate(spdif_priv->sysclk); 832 833 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 834 tmpval64 = (u64) busclk_freq * freqmeas; 835 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 836 do_div(tmpval64, 128 * 1024); 837 838 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 839 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 840 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 841 842 return (int)tmpval64; 843 } 844 845 /* 846 * Get DPLL lock or not info from stable interrupt status register. 847 * User application must use this control to get locked, 848 * then can do next PCM operation 849 */ 850 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 851 struct snd_ctl_elem_value *ucontrol) 852 { 853 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 854 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 855 int rate = 0; 856 857 if (spdif_priv->dpll_locked) 858 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 859 860 ucontrol->value.integer.value[0] = rate; 861 862 return 0; 863 } 864 865 /* User bit sync mode info */ 866 static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol, 867 struct snd_ctl_elem_info *uinfo) 868 { 869 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 870 uinfo->count = 1; 871 uinfo->value.integer.min = 0; 872 uinfo->value.integer.max = 1; 873 874 return 0; 875 } 876 877 /* 878 * User bit sync mode: 879 * 1 CD User channel subcode 880 * 0 Non-CD data 881 */ 882 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 883 struct snd_ctl_elem_value *ucontrol) 884 { 885 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 886 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 887 struct regmap *regmap = spdif_priv->regmap; 888 u32 val; 889 890 regmap_read(regmap, REG_SPDIF_SRCD, &val); 891 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 892 893 return 0; 894 } 895 896 /* 897 * User bit sync mode: 898 * 1 CD User channel subcode 899 * 0 Non-CD data 900 */ 901 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 902 struct snd_ctl_elem_value *ucontrol) 903 { 904 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 905 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 906 struct regmap *regmap = spdif_priv->regmap; 907 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 908 909 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 910 911 return 0; 912 } 913 914 /* FSL SPDIF IEC958 controller defines */ 915 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 916 /* Status cchanel controller */ 917 { 918 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 919 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 920 .access = SNDRV_CTL_ELEM_ACCESS_READ | 921 SNDRV_CTL_ELEM_ACCESS_WRITE | 922 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 923 .info = fsl_spdif_info, 924 .get = fsl_spdif_pb_get, 925 .put = fsl_spdif_pb_put, 926 }, 927 { 928 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 929 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 930 .access = SNDRV_CTL_ELEM_ACCESS_READ | 931 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 932 .info = fsl_spdif_info, 933 .get = fsl_spdif_capture_get, 934 }, 935 /* User bits controller */ 936 { 937 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 938 .name = "IEC958 Subcode Capture Default", 939 .access = SNDRV_CTL_ELEM_ACCESS_READ | 940 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 941 .info = fsl_spdif_info, 942 .get = fsl_spdif_subcode_get, 943 }, 944 { 945 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 946 .name = "IEC958 Q-subcode Capture Default", 947 .access = SNDRV_CTL_ELEM_ACCESS_READ | 948 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 949 .info = fsl_spdif_qinfo, 950 .get = fsl_spdif_qget, 951 }, 952 /* Valid bit error controller */ 953 { 954 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 955 .name = "IEC958 V-Bit Errors", 956 .access = SNDRV_CTL_ELEM_ACCESS_READ | 957 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 958 .info = fsl_spdif_vbit_info, 959 .get = fsl_spdif_vbit_get, 960 }, 961 /* DPLL lock info get controller */ 962 { 963 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 964 .name = "RX Sample Rate", 965 .access = SNDRV_CTL_ELEM_ACCESS_READ | 966 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 967 .info = fsl_spdif_rxrate_info, 968 .get = fsl_spdif_rxrate_get, 969 }, 970 /* User bit sync mode set/get controller */ 971 { 972 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 973 .name = "IEC958 USyncMode CDText", 974 .access = SNDRV_CTL_ELEM_ACCESS_READ | 975 SNDRV_CTL_ELEM_ACCESS_WRITE | 976 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 977 .info = fsl_spdif_usync_info, 978 .get = fsl_spdif_usync_get, 979 .put = fsl_spdif_usync_put, 980 }, 981 }; 982 983 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 984 { 985 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 986 987 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 988 &spdif_private->dma_params_rx); 989 990 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 991 992 return 0; 993 } 994 995 static struct snd_soc_dai_driver fsl_spdif_dai = { 996 .probe = &fsl_spdif_dai_probe, 997 .playback = { 998 .stream_name = "CPU-Playback", 999 .channels_min = 2, 1000 .channels_max = 2, 1001 .rates = FSL_SPDIF_RATES_PLAYBACK, 1002 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1003 }, 1004 .capture = { 1005 .stream_name = "CPU-Capture", 1006 .channels_min = 2, 1007 .channels_max = 2, 1008 .rates = FSL_SPDIF_RATES_CAPTURE, 1009 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1010 }, 1011 .ops = &fsl_spdif_dai_ops, 1012 }; 1013 1014 static const struct snd_soc_component_driver fsl_spdif_component = { 1015 .name = "fsl-spdif", 1016 }; 1017 1018 /* FSL SPDIF REGMAP */ 1019 static const struct reg_default fsl_spdif_reg_defaults[] = { 1020 {REG_SPDIF_SCR, 0x00000400}, 1021 {REG_SPDIF_SRCD, 0x00000000}, 1022 {REG_SPDIF_SIE, 0x00000000}, 1023 {REG_SPDIF_STL, 0x00000000}, 1024 {REG_SPDIF_STR, 0x00000000}, 1025 {REG_SPDIF_STCSCH, 0x00000000}, 1026 {REG_SPDIF_STCSCL, 0x00000000}, 1027 {REG_SPDIF_STC, 0x00020f00}, 1028 }; 1029 1030 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1031 { 1032 switch (reg) { 1033 case REG_SPDIF_SCR: 1034 case REG_SPDIF_SRCD: 1035 case REG_SPDIF_SRPC: 1036 case REG_SPDIF_SIE: 1037 case REG_SPDIF_SIS: 1038 case REG_SPDIF_SRL: 1039 case REG_SPDIF_SRR: 1040 case REG_SPDIF_SRCSH: 1041 case REG_SPDIF_SRCSL: 1042 case REG_SPDIF_SRU: 1043 case REG_SPDIF_SRQ: 1044 case REG_SPDIF_STCSCH: 1045 case REG_SPDIF_STCSCL: 1046 case REG_SPDIF_SRFM: 1047 case REG_SPDIF_STC: 1048 return true; 1049 default: 1050 return false; 1051 } 1052 } 1053 1054 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1055 { 1056 switch (reg) { 1057 case REG_SPDIF_SRPC: 1058 case REG_SPDIF_SIS: 1059 case REG_SPDIF_SRL: 1060 case REG_SPDIF_SRR: 1061 case REG_SPDIF_SRCSH: 1062 case REG_SPDIF_SRCSL: 1063 case REG_SPDIF_SRU: 1064 case REG_SPDIF_SRQ: 1065 case REG_SPDIF_SRFM: 1066 return true; 1067 default: 1068 return false; 1069 } 1070 } 1071 1072 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1073 { 1074 switch (reg) { 1075 case REG_SPDIF_SCR: 1076 case REG_SPDIF_SRCD: 1077 case REG_SPDIF_SRPC: 1078 case REG_SPDIF_SIE: 1079 case REG_SPDIF_SIC: 1080 case REG_SPDIF_STL: 1081 case REG_SPDIF_STR: 1082 case REG_SPDIF_STCSCH: 1083 case REG_SPDIF_STCSCL: 1084 case REG_SPDIF_STC: 1085 return true; 1086 default: 1087 return false; 1088 } 1089 } 1090 1091 static const struct regmap_config fsl_spdif_regmap_config = { 1092 .reg_bits = 32, 1093 .reg_stride = 4, 1094 .val_bits = 32, 1095 1096 .max_register = REG_SPDIF_STC, 1097 .reg_defaults = fsl_spdif_reg_defaults, 1098 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1099 .readable_reg = fsl_spdif_readable_reg, 1100 .volatile_reg = fsl_spdif_volatile_reg, 1101 .writeable_reg = fsl_spdif_writeable_reg, 1102 .cache_type = REGCACHE_FLAT, 1103 }; 1104 1105 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1106 struct clk *clk, u64 savesub, 1107 enum spdif_txrate index, bool round) 1108 { 1109 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1110 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1111 u64 rate_ideal, rate_actual, sub; 1112 u32 sysclk_dfmin, sysclk_dfmax; 1113 u32 txclk_df, sysclk_df, arate; 1114 1115 /* The sysclk has an extra divisor [2, 512] */ 1116 sysclk_dfmin = is_sysclk ? 2 : 1; 1117 sysclk_dfmax = is_sysclk ? 512 : 1; 1118 1119 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1120 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1121 rate_ideal = rate[index] * txclk_df * 64; 1122 if (round) 1123 rate_actual = clk_round_rate(clk, rate_ideal); 1124 else 1125 rate_actual = clk_get_rate(clk); 1126 1127 arate = rate_actual / 64; 1128 arate /= txclk_df * sysclk_df; 1129 1130 if (arate == rate[index]) { 1131 /* We are lucky */ 1132 savesub = 0; 1133 spdif_priv->txclk_df[index] = txclk_df; 1134 spdif_priv->sysclk_df[index] = sysclk_df; 1135 spdif_priv->txrate[index] = arate; 1136 goto out; 1137 } else if (arate / rate[index] == 1) { 1138 /* A little bigger than expect */ 1139 sub = (u64)(arate - rate[index]) * 100000; 1140 do_div(sub, rate[index]); 1141 if (sub >= savesub) 1142 continue; 1143 savesub = sub; 1144 spdif_priv->txclk_df[index] = txclk_df; 1145 spdif_priv->sysclk_df[index] = sysclk_df; 1146 spdif_priv->txrate[index] = arate; 1147 } else if (rate[index] / arate == 1) { 1148 /* A little smaller than expect */ 1149 sub = (u64)(rate[index] - arate) * 100000; 1150 do_div(sub, rate[index]); 1151 if (sub >= savesub) 1152 continue; 1153 savesub = sub; 1154 spdif_priv->txclk_df[index] = txclk_df; 1155 spdif_priv->sysclk_df[index] = sysclk_df; 1156 spdif_priv->txrate[index] = arate; 1157 } 1158 } 1159 } 1160 1161 out: 1162 return savesub; 1163 } 1164 1165 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1166 enum spdif_txrate index) 1167 { 1168 static const u32 rate[] = { 32000, 44100, 48000, 96000, 192000 }; 1169 struct platform_device *pdev = spdif_priv->pdev; 1170 struct device *dev = &pdev->dev; 1171 u64 savesub = 100000, ret; 1172 struct clk *clk; 1173 char tmp[16]; 1174 int i; 1175 1176 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1177 sprintf(tmp, "rxtx%d", i); 1178 clk = devm_clk_get(&pdev->dev, tmp); 1179 if (IS_ERR(clk)) { 1180 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1181 return PTR_ERR(clk); 1182 } 1183 if (!clk_get_rate(clk)) 1184 continue; 1185 1186 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1187 i == STC_TXCLK_SPDIF_ROOT); 1188 if (savesub == ret) 1189 continue; 1190 1191 savesub = ret; 1192 spdif_priv->txclk[index] = clk; 1193 spdif_priv->txclk_src[index] = i; 1194 1195 /* To quick catch a divisor, we allow a 0.1% deviation */ 1196 if (savesub < 100) 1197 break; 1198 } 1199 1200 dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1201 spdif_priv->txclk_src[index], rate[index]); 1202 dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n", 1203 spdif_priv->txclk_df[index], rate[index]); 1204 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1205 dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n", 1206 spdif_priv->sysclk_df[index], rate[index]); 1207 dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n", 1208 rate[index], spdif_priv->txrate[index]); 1209 1210 return 0; 1211 } 1212 1213 static int fsl_spdif_probe(struct platform_device *pdev) 1214 { 1215 struct device_node *np = pdev->dev.of_node; 1216 struct fsl_spdif_priv *spdif_priv; 1217 struct spdif_mixer_control *ctrl; 1218 struct resource *res; 1219 void __iomem *regs; 1220 int irq, ret, i; 1221 1222 if (!np) 1223 return -ENODEV; 1224 1225 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1226 if (!spdif_priv) 1227 return -ENOMEM; 1228 1229 spdif_priv->pdev = pdev; 1230 1231 /* Initialize this copy of the CPU DAI driver structure */ 1232 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1233 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1234 1235 /* Get the addresses and IRQ */ 1236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1237 regs = devm_ioremap_resource(&pdev->dev, res); 1238 if (IS_ERR(regs)) 1239 return PTR_ERR(regs); 1240 1241 spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 1242 "core", regs, &fsl_spdif_regmap_config); 1243 if (IS_ERR(spdif_priv->regmap)) { 1244 dev_err(&pdev->dev, "regmap init failed\n"); 1245 return PTR_ERR(spdif_priv->regmap); 1246 } 1247 1248 irq = platform_get_irq(pdev, 0); 1249 if (irq < 0) { 1250 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 1251 return irq; 1252 } 1253 1254 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1255 dev_name(&pdev->dev), spdif_priv); 1256 if (ret) { 1257 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1258 return ret; 1259 } 1260 1261 /* Get system clock for rx clock rate calculation */ 1262 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1263 if (IS_ERR(spdif_priv->sysclk)) { 1264 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1265 return PTR_ERR(spdif_priv->sysclk); 1266 } 1267 1268 /* Get core clock for data register access via DMA */ 1269 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1270 if (IS_ERR(spdif_priv->coreclk)) { 1271 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1272 return PTR_ERR(spdif_priv->coreclk); 1273 } 1274 1275 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1276 if (IS_ERR(spdif_priv->spbaclk)) 1277 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1278 1279 /* Select clock source for rx/tx clock */ 1280 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1281 if (IS_ERR(spdif_priv->rxclk)) { 1282 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1283 return PTR_ERR(spdif_priv->rxclk); 1284 } 1285 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1286 1287 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1288 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1289 if (ret) 1290 return ret; 1291 } 1292 1293 /* Initial spinlock for control data */ 1294 ctrl = &spdif_priv->fsl_spdif_control; 1295 spin_lock_init(&ctrl->ctl_lock); 1296 1297 /* Init tx channel status default value */ 1298 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1299 IEC958_AES0_CON_EMPHASIS_5015; 1300 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1301 ctrl->ch_status[2] = 0x00; 1302 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1303 IEC958_AES3_CON_CLOCK_1000PPM; 1304 1305 spdif_priv->dpll_locked = false; 1306 1307 spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML; 1308 spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML; 1309 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1310 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1311 1312 /* Register with ASoC */ 1313 dev_set_drvdata(&pdev->dev, spdif_priv); 1314 1315 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1316 &spdif_priv->cpu_dai_drv, 1); 1317 if (ret) { 1318 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1319 return ret; 1320 } 1321 1322 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1323 if (ret) 1324 dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret); 1325 1326 return ret; 1327 } 1328 1329 #ifdef CONFIG_PM_SLEEP 1330 static int fsl_spdif_suspend(struct device *dev) 1331 { 1332 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1333 1334 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1335 &spdif_priv->regcache_srpc); 1336 1337 regcache_cache_only(spdif_priv->regmap, true); 1338 regcache_mark_dirty(spdif_priv->regmap); 1339 1340 return 0; 1341 } 1342 1343 static int fsl_spdif_resume(struct device *dev) 1344 { 1345 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1346 1347 regcache_cache_only(spdif_priv->regmap, false); 1348 1349 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1350 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1351 spdif_priv->regcache_srpc); 1352 1353 return regcache_sync(spdif_priv->regmap); 1354 } 1355 #endif /* CONFIG_PM_SLEEP */ 1356 1357 static const struct dev_pm_ops fsl_spdif_pm = { 1358 SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume) 1359 }; 1360 1361 static const struct of_device_id fsl_spdif_dt_ids[] = { 1362 { .compatible = "fsl,imx35-spdif", }, 1363 { .compatible = "fsl,vf610-spdif", }, 1364 {} 1365 }; 1366 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1367 1368 static struct platform_driver fsl_spdif_driver = { 1369 .driver = { 1370 .name = "fsl-spdif-dai", 1371 .of_match_table = fsl_spdif_dt_ids, 1372 .pm = &fsl_spdif_pm, 1373 }, 1374 .probe = fsl_spdif_probe, 1375 }; 1376 1377 module_platform_driver(fsl_spdif_driver); 1378 1379 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1380 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1381 MODULE_LICENSE("GPL v2"); 1382 MODULE_ALIAS("platform:fsl-spdif-dai"); 1383