1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SPDIF_TXFIFO_WML 0x8 30 #define FSL_SPDIF_RXFIFO_WML 0x8 31 32 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 33 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 34 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 35 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 36 INT_LOSS_LOCK | INT_DPLL_LOCKED) 37 38 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 39 40 /* Index list for the values that has if (DPLL Locked) condition */ 41 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 42 #define SRPC_NODPLL_START1 0x5 43 #define SRPC_NODPLL_START2 0xc 44 45 #define DEFAULT_RXCLK_SRC 1 46 47 #define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate" 48 49 /** 50 * struct fsl_spdif_soc_data: soc specific data 51 * 52 * @imx: for imx platform 53 * @shared_root_clock: flag of sharing a clock source with others; 54 * so the driver shouldn't set root clock rate 55 * @raw_capture_mode: if raw capture mode support 56 * @cchannel_192b: if there are registers for 192bits C channel data 57 * @interrupts: interrupt number 58 * @tx_burst: tx maxburst size 59 * @rx_burst: rx maxburst size 60 * @tx_formats: tx supported data format 61 */ 62 struct fsl_spdif_soc_data { 63 bool imx; 64 bool shared_root_clock; 65 bool raw_capture_mode; 66 bool cchannel_192b; 67 u32 interrupts; 68 u32 tx_burst; 69 u32 rx_burst; 70 u64 tx_formats; 71 }; 72 73 /* 74 * SPDIF control structure 75 * Defines channel status, subcode and Q sub 76 */ 77 struct spdif_mixer_control { 78 /* spinlock to access control data */ 79 spinlock_t ctl_lock; 80 81 /* IEC958 channel tx status bit */ 82 unsigned char ch_status[4]; 83 84 /* User bits */ 85 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 86 87 /* Q subcode part of user bits */ 88 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 89 90 /* Buffer offset for U/Q */ 91 u32 upos; 92 u32 qpos; 93 94 /* Ready buffer index of the two buffers */ 95 u32 ready_buf; 96 }; 97 98 /** 99 * struct fsl_spdif_priv - Freescale SPDIF private data 100 * @soc: SPDIF soc data 101 * @fsl_spdif_control: SPDIF control data 102 * @cpu_dai_drv: cpu dai driver 103 * @snd_card: sound card pointer 104 * @rxrate_kcontrol: kcontrol for RX Sample Rate 105 * @pdev: platform device pointer 106 * @regmap: regmap handler 107 * @dpll_locked: dpll lock flag 108 * @txrate: the best rates for playback 109 * @txclk_df: STC_TXCLK_DF dividers value for playback 110 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 111 * @txclk_src: STC_TXCLK_SRC values for playback 112 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 113 * @txclk: tx clock sources for playback 114 * @rxclk: rx clock sources for capture 115 * @coreclk: core clock for register access via DMA 116 * @sysclk: system clock for rx clock rate measurement 117 * @spbaclk: SPBA clock (optional, depending on SoC design) 118 * @dma_params_tx: DMA parameters for transmit channel 119 * @dma_params_rx: DMA parameters for receive channel 120 * @regcache_srpc: regcache for SRPC 121 * @bypass: status of bypass input to output 122 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz 123 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz 124 */ 125 struct fsl_spdif_priv { 126 const struct fsl_spdif_soc_data *soc; 127 struct spdif_mixer_control fsl_spdif_control; 128 struct snd_soc_dai_driver cpu_dai_drv; 129 struct snd_card *snd_card; 130 struct snd_kcontrol *rxrate_kcontrol; 131 struct platform_device *pdev; 132 struct regmap *regmap; 133 bool dpll_locked; 134 u32 txrate[SPDIF_TXRATE_MAX]; 135 u8 txclk_df[SPDIF_TXRATE_MAX]; 136 u16 sysclk_df[SPDIF_TXRATE_MAX]; 137 u8 txclk_src[SPDIF_TXRATE_MAX]; 138 u8 rxclk_src; 139 struct clk *txclk[STC_TXCLK_SRC_MAX]; 140 struct clk *rxclk; 141 struct clk *coreclk; 142 struct clk *sysclk; 143 struct clk *spbaclk; 144 struct snd_dmaengine_dai_dma_data dma_params_tx; 145 struct snd_dmaengine_dai_dma_data dma_params_rx; 146 /* regcache for SRPC */ 147 u32 regcache_srpc; 148 bool bypass; 149 struct clk *pll8k_clk; 150 struct clk *pll11k_clk; 151 }; 152 153 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 154 .imx = false, 155 .shared_root_clock = false, 156 .raw_capture_mode = false, 157 .interrupts = 1, 158 .tx_burst = FSL_SPDIF_TXFIFO_WML, 159 .rx_burst = FSL_SPDIF_RXFIFO_WML, 160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 161 }; 162 163 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 164 .imx = true, 165 .shared_root_clock = false, 166 .raw_capture_mode = false, 167 .interrupts = 1, 168 .tx_burst = FSL_SPDIF_TXFIFO_WML, 169 .rx_burst = FSL_SPDIF_RXFIFO_WML, 170 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 171 }; 172 173 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 174 .imx = true, 175 .shared_root_clock = true, 176 .raw_capture_mode = false, 177 .interrupts = 1, 178 .tx_burst = FSL_SPDIF_TXFIFO_WML, 179 .rx_burst = FSL_SPDIF_RXFIFO_WML, 180 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 181 182 }; 183 184 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 185 .imx = true, 186 .shared_root_clock = true, 187 .raw_capture_mode = false, 188 .interrupts = 2, 189 .tx_burst = 2, /* Applied for EDMA */ 190 .rx_burst = 2, /* Applied for EDMA */ 191 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 192 }; 193 194 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 195 .imx = true, 196 .shared_root_clock = false, 197 .raw_capture_mode = true, 198 .interrupts = 1, 199 .tx_burst = FSL_SPDIF_TXFIFO_WML, 200 .rx_burst = FSL_SPDIF_RXFIFO_WML, 201 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 202 }; 203 204 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = { 205 .imx = true, 206 .shared_root_clock = true, 207 .raw_capture_mode = false, 208 .interrupts = 1, 209 .tx_burst = 2, /* Applied for EDMA */ 210 .rx_burst = 2, /* Applied for EDMA */ 211 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 212 .cchannel_192b = true, 213 }; 214 215 /* Check if clk is a root clock that does not share clock source with others */ 216 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 217 { 218 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 219 } 220 221 /* DPLL locked and lock loss interrupt handler */ 222 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 223 { 224 struct regmap *regmap = spdif_priv->regmap; 225 struct platform_device *pdev = spdif_priv->pdev; 226 u32 locked; 227 228 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 229 locked &= SRPC_DPLL_LOCKED; 230 231 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 232 locked ? "locked" : "loss lock"); 233 234 spdif_priv->dpll_locked = locked ? true : false; 235 236 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) { 237 snd_ctl_notify(spdif_priv->snd_card, 238 SNDRV_CTL_EVENT_MASK_VALUE, 239 &spdif_priv->rxrate_kcontrol->id); 240 } 241 } 242 243 /* Receiver found illegal symbol interrupt handler */ 244 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 245 { 246 struct regmap *regmap = spdif_priv->regmap; 247 struct platform_device *pdev = spdif_priv->pdev; 248 249 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 250 251 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 252 if (!spdif_priv->dpll_locked) 253 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 254 } 255 256 /* U/Q Channel receive register full */ 257 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 258 { 259 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 260 struct regmap *regmap = spdif_priv->regmap; 261 struct platform_device *pdev = spdif_priv->pdev; 262 u32 *pos, size, val, reg; 263 264 switch (name) { 265 case 'U': 266 pos = &ctrl->upos; 267 size = SPDIF_UBITS_SIZE; 268 reg = REG_SPDIF_SRU; 269 break; 270 case 'Q': 271 pos = &ctrl->qpos; 272 size = SPDIF_QSUB_SIZE; 273 reg = REG_SPDIF_SRQ; 274 break; 275 default: 276 dev_err(&pdev->dev, "unsupported channel name\n"); 277 return; 278 } 279 280 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 281 282 if (*pos >= size * 2) { 283 *pos = 0; 284 } else if (unlikely((*pos % size) + 3 > size)) { 285 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 286 return; 287 } 288 289 regmap_read(regmap, reg, &val); 290 ctrl->subcode[*pos++] = val >> 16; 291 ctrl->subcode[*pos++] = val >> 8; 292 ctrl->subcode[*pos++] = val; 293 } 294 295 /* U/Q Channel sync found */ 296 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 297 { 298 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 299 struct platform_device *pdev = spdif_priv->pdev; 300 301 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 302 303 /* U/Q buffer reset */ 304 if (ctrl->qpos == 0) 305 return; 306 307 /* Set ready to this buffer */ 308 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 309 } 310 311 /* U/Q Channel framing error */ 312 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 313 { 314 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 315 struct regmap *regmap = spdif_priv->regmap; 316 struct platform_device *pdev = spdif_priv->pdev; 317 u32 val; 318 319 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 320 321 /* Read U/Q data to clear the irq and do buffer reset */ 322 regmap_read(regmap, REG_SPDIF_SRU, &val); 323 regmap_read(regmap, REG_SPDIF_SRQ, &val); 324 325 /* Drop this U/Q buffer */ 326 ctrl->ready_buf = 0; 327 ctrl->upos = 0; 328 ctrl->qpos = 0; 329 } 330 331 /* Get spdif interrupt status and clear the interrupt */ 332 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 333 { 334 struct regmap *regmap = spdif_priv->regmap; 335 u32 val, val2; 336 337 regmap_read(regmap, REG_SPDIF_SIS, &val); 338 regmap_read(regmap, REG_SPDIF_SIE, &val2); 339 340 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 341 342 return val; 343 } 344 345 static irqreturn_t spdif_isr(int irq, void *devid) 346 { 347 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 348 struct platform_device *pdev = spdif_priv->pdev; 349 u32 sis; 350 351 sis = spdif_intr_status_clear(spdif_priv); 352 353 if (sis & INT_DPLL_LOCKED) 354 spdif_irq_dpll_lock(spdif_priv); 355 356 if (sis & INT_TXFIFO_UNOV) 357 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 358 359 if (sis & INT_TXFIFO_RESYNC) 360 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 361 362 if (sis & INT_CNEW) 363 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 364 365 if (sis & INT_VAL_NOGOOD) 366 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 367 368 if (sis & INT_SYM_ERR) 369 spdif_irq_sym_error(spdif_priv); 370 371 if (sis & INT_BIT_ERR) 372 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 373 374 if (sis & INT_URX_FUL) 375 spdif_irq_uqrx_full(spdif_priv, 'U'); 376 377 if (sis & INT_URX_OV) 378 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 379 380 if (sis & INT_QRX_FUL) 381 spdif_irq_uqrx_full(spdif_priv, 'Q'); 382 383 if (sis & INT_QRX_OV) 384 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 385 386 if (sis & INT_UQ_SYNC) 387 spdif_irq_uq_sync(spdif_priv); 388 389 if (sis & INT_UQ_ERR) 390 spdif_irq_uq_err(spdif_priv); 391 392 if (sis & INT_RXFIFO_UNOV) 393 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 394 395 if (sis & INT_RXFIFO_RESYNC) 396 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 397 398 if (sis & INT_LOSS_LOCK) 399 spdif_irq_dpll_lock(spdif_priv); 400 401 /* FIXME: Write Tx FIFO to clear TxEm */ 402 if (sis & INT_TX_EM) 403 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 404 405 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 406 if (sis & INT_RXFIFO_FUL) 407 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 408 409 return IRQ_HANDLED; 410 } 411 412 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 413 { 414 struct regmap *regmap = spdif_priv->regmap; 415 u32 val, cycle = 1000; 416 417 regcache_cache_bypass(regmap, true); 418 419 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 420 421 /* 422 * RESET bit would be cleared after finishing its reset procedure, 423 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 424 */ 425 do { 426 regmap_read(regmap, REG_SPDIF_SCR, &val); 427 } while ((val & SCR_SOFT_RESET) && cycle--); 428 429 regcache_cache_bypass(regmap, false); 430 regcache_mark_dirty(regmap); 431 regcache_sync(regmap); 432 433 if (cycle) 434 return 0; 435 else 436 return -EBUSY; 437 } 438 439 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 440 u8 mask, u8 cstatus) 441 { 442 ctrl->ch_status[3] &= ~mask; 443 ctrl->ch_status[3] |= cstatus & mask; 444 } 445 446 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 447 { 448 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 449 struct regmap *regmap = spdif_priv->regmap; 450 struct platform_device *pdev = spdif_priv->pdev; 451 u32 ch_status; 452 453 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 454 (bitrev8(ctrl->ch_status[1]) << 8) | 455 bitrev8(ctrl->ch_status[2]); 456 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 457 458 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 459 460 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 461 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 462 463 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 464 465 if (spdif_priv->soc->cchannel_192b) { 466 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | 467 (bitrev8(ctrl->ch_status[1]) << 16) | 468 (bitrev8(ctrl->ch_status[2]) << 8) | 469 bitrev8(ctrl->ch_status[3]); 470 471 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000); 472 473 /* 474 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register, 475 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP 476 * then can get correct result with HDMI analyzer capture. 477 * There is a hardware bug here. 478 */ 479 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status); 480 } 481 } 482 483 /* Set SPDIF PhaseConfig register for rx clock */ 484 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 485 enum spdif_gainsel gainsel, int dpll_locked) 486 { 487 struct regmap *regmap = spdif_priv->regmap; 488 u8 clksrc = spdif_priv->rxclk_src; 489 490 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 491 return -EINVAL; 492 493 regmap_update_bits(regmap, REG_SPDIF_SRPC, 494 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 495 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 496 497 return 0; 498 } 499 500 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index); 501 502 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 503 int sample_rate) 504 { 505 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 506 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 507 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 508 struct regmap *regmap = spdif_priv->regmap; 509 struct platform_device *pdev = spdif_priv->pdev; 510 unsigned long csfs = 0; 511 u32 stc, mask, rate; 512 u16 sysclk_df; 513 u8 clk, txclk_df; 514 int ret; 515 516 switch (sample_rate) { 517 case 22050: 518 rate = SPDIF_TXRATE_22050; 519 csfs = IEC958_AES3_CON_FS_22050; 520 break; 521 case 32000: 522 rate = SPDIF_TXRATE_32000; 523 csfs = IEC958_AES3_CON_FS_32000; 524 break; 525 case 44100: 526 rate = SPDIF_TXRATE_44100; 527 csfs = IEC958_AES3_CON_FS_44100; 528 break; 529 case 48000: 530 rate = SPDIF_TXRATE_48000; 531 csfs = IEC958_AES3_CON_FS_48000; 532 break; 533 case 88200: 534 rate = SPDIF_TXRATE_88200; 535 csfs = IEC958_AES3_CON_FS_88200; 536 break; 537 case 96000: 538 rate = SPDIF_TXRATE_96000; 539 csfs = IEC958_AES3_CON_FS_96000; 540 break; 541 case 176400: 542 rate = SPDIF_TXRATE_176400; 543 csfs = IEC958_AES3_CON_FS_176400; 544 break; 545 case 192000: 546 rate = SPDIF_TXRATE_192000; 547 csfs = IEC958_AES3_CON_FS_192000; 548 break; 549 default: 550 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 551 return -EINVAL; 552 } 553 554 ret = fsl_spdif_probe_txclk(spdif_priv, rate); 555 if (ret) 556 return ret; 557 558 clk = spdif_priv->txclk_src[rate]; 559 if (clk >= STC_TXCLK_SRC_MAX) { 560 dev_err(&pdev->dev, "tx clock source is out of range\n"); 561 return -EINVAL; 562 } 563 564 txclk_df = spdif_priv->txclk_df[rate]; 565 if (txclk_df == 0) { 566 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 567 return -EINVAL; 568 } 569 570 sysclk_df = spdif_priv->sysclk_df[rate]; 571 572 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 573 goto clk_set_bypass; 574 575 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 576 ret = clk_set_rate(spdif_priv->txclk[clk], 577 64 * sample_rate * txclk_df); 578 if (ret) { 579 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 580 return ret; 581 } 582 583 clk_set_bypass: 584 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 585 (64 * sample_rate * txclk_df * sysclk_df)); 586 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 587 clk_get_rate(spdif_priv->txclk[clk])); 588 589 /* set fs field in consumer channel status */ 590 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 591 592 /* select clock source and divisor */ 593 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 594 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 595 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 596 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 597 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 598 599 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 600 spdif_priv->txrate[rate], sample_rate); 601 602 return 0; 603 } 604 605 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 606 struct snd_soc_dai *cpu_dai) 607 { 608 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 609 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 610 struct platform_device *pdev = spdif_priv->pdev; 611 struct regmap *regmap = spdif_priv->regmap; 612 u32 scr, mask; 613 int ret; 614 615 /* Reset module and interrupts only for first initialization */ 616 if (!snd_soc_dai_active(cpu_dai)) { 617 ret = spdif_softreset(spdif_priv); 618 if (ret) { 619 dev_err(&pdev->dev, "failed to soft reset\n"); 620 return ret; 621 } 622 623 /* Disable all the interrupts */ 624 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 625 } 626 627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 628 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 629 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 630 SCR_TXFIFO_FSEL_IF8; 631 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 632 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 633 SCR_TXFIFO_FSEL_MASK; 634 } else { 635 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 636 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 637 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 638 } 639 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 640 641 /* Power up SPDIF module */ 642 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 643 644 return 0; 645 } 646 647 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 648 struct snd_soc_dai *cpu_dai) 649 { 650 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 651 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 652 struct regmap *regmap = spdif_priv->regmap; 653 u32 scr, mask; 654 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 656 scr = 0; 657 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 658 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 659 SCR_TXFIFO_FSEL_MASK; 660 /* Disable TX clock */ 661 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0); 662 } else { 663 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 664 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 665 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 666 } 667 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 668 669 /* Power down SPDIF module only if tx&rx are both inactive */ 670 if (!snd_soc_dai_active(cpu_dai)) { 671 spdif_intr_status_clear(spdif_priv); 672 regmap_update_bits(regmap, REG_SPDIF_SCR, 673 SCR_LOW_POWER, SCR_LOW_POWER); 674 } 675 } 676 677 static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate) 678 { 679 struct platform_device *pdev = spdif_priv->pdev; 680 struct clk *clk; 681 int ret; 682 683 /* Reparent clock if required condition is true */ 684 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT)) 685 return 0; 686 687 /* Get root clock */ 688 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; 689 690 /* Disable clock first, for it was enabled by pm_runtime */ 691 clk_disable_unprepare(clk); 692 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, 693 spdif_priv->pll11k_clk, sample_rate); 694 ret = clk_prepare_enable(clk); 695 if (ret) 696 return ret; 697 698 return 0; 699 } 700 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 701 struct snd_pcm_hw_params *params, 702 struct snd_soc_dai *dai) 703 { 704 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 705 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 706 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 707 struct platform_device *pdev = spdif_priv->pdev; 708 u32 sample_rate = params_rate(params); 709 int ret = 0; 710 711 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 712 ret = spdif_reparent_rootclk(spdif_priv, sample_rate); 713 if (ret) { 714 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", 715 __func__, sample_rate); 716 return ret; 717 } 718 719 ret = spdif_set_sample_rate(substream, sample_rate); 720 if (ret) { 721 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 722 __func__, sample_rate); 723 return ret; 724 } 725 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 726 IEC958_AES3_CON_CLOCK_1000PPM); 727 spdif_write_channel_status(spdif_priv); 728 } else { 729 /* Setup rx clock source */ 730 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 731 } 732 733 return ret; 734 } 735 736 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 737 int cmd, struct snd_soc_dai *dai) 738 { 739 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 740 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 741 struct regmap *regmap = spdif_priv->regmap; 742 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 743 u32 intr = SIE_INTR_FOR(tx); 744 u32 dmaen = SCR_DMA_xX_EN(tx); 745 746 switch (cmd) { 747 case SNDRV_PCM_TRIGGER_START: 748 case SNDRV_PCM_TRIGGER_RESUME: 749 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 750 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 751 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 752 break; 753 case SNDRV_PCM_TRIGGER_STOP: 754 case SNDRV_PCM_TRIGGER_SUSPEND: 755 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 756 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 757 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 return 0; 764 } 765 766 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 767 .startup = fsl_spdif_startup, 768 .hw_params = fsl_spdif_hw_params, 769 .trigger = fsl_spdif_trigger, 770 .shutdown = fsl_spdif_shutdown, 771 }; 772 773 774 /* 775 * FSL SPDIF IEC958 controller(mixer) functions 776 * 777 * Channel status get/put control 778 * User bit value get/put control 779 * Valid bit value get control 780 * DPLL lock status get control 781 * User bit sync mode selection control 782 */ 783 784 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 785 struct snd_ctl_elem_info *uinfo) 786 { 787 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 788 uinfo->count = 1; 789 790 return 0; 791 } 792 793 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 794 struct snd_ctl_elem_value *uvalue) 795 { 796 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 797 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 798 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 799 800 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 801 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 802 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 803 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 804 805 return 0; 806 } 807 808 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 809 struct snd_ctl_elem_value *uvalue) 810 { 811 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 812 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 813 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 814 815 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 816 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 817 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 818 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 819 820 spdif_write_channel_status(spdif_priv); 821 822 return 0; 823 } 824 825 /* Get channel status from SPDIF_RX_CCHAN register */ 826 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 827 struct snd_ctl_elem_value *ucontrol) 828 { 829 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 830 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 831 struct regmap *regmap = spdif_priv->regmap; 832 u32 cstatus, val; 833 834 regmap_read(regmap, REG_SPDIF_SIS, &val); 835 if (!(val & INT_CNEW)) 836 return -EAGAIN; 837 838 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 839 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 840 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 841 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 842 843 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 844 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 845 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 846 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 847 848 /* Clear intr */ 849 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 850 851 return 0; 852 } 853 854 /* 855 * Get User bits (subcode) from chip value which readed out 856 * in UChannel register. 857 */ 858 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 859 struct snd_ctl_elem_value *ucontrol) 860 { 861 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 862 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 863 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 864 unsigned long flags; 865 int ret = -EAGAIN; 866 867 spin_lock_irqsave(&ctrl->ctl_lock, flags); 868 if (ctrl->ready_buf) { 869 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 870 memcpy(&ucontrol->value.iec958.subcode[0], 871 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 872 ret = 0; 873 } 874 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 875 876 return ret; 877 } 878 879 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 880 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 881 struct snd_ctl_elem_info *uinfo) 882 { 883 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 884 uinfo->count = SPDIF_QSUB_SIZE; 885 886 return 0; 887 } 888 889 /* Get Q subcode from chip value which readed out in QChannel register */ 890 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 891 struct snd_ctl_elem_value *ucontrol) 892 { 893 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 894 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 895 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 896 unsigned long flags; 897 int ret = -EAGAIN; 898 899 spin_lock_irqsave(&ctrl->ctl_lock, flags); 900 if (ctrl->ready_buf) { 901 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 902 memcpy(&ucontrol->value.bytes.data[0], 903 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 904 ret = 0; 905 } 906 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 907 908 return ret; 909 } 910 911 /* Get valid good bit from interrupt status register */ 912 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 913 struct snd_ctl_elem_value *ucontrol) 914 { 915 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 916 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 917 struct regmap *regmap = spdif_priv->regmap; 918 u32 val; 919 920 regmap_read(regmap, REG_SPDIF_SIS, &val); 921 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 922 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 923 924 return 0; 925 } 926 927 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 928 struct snd_ctl_elem_value *ucontrol) 929 { 930 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 931 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 932 struct regmap *regmap = spdif_priv->regmap; 933 u32 val; 934 935 regmap_read(regmap, REG_SPDIF_SCR, &val); 936 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 937 val = 1 - val; 938 ucontrol->value.integer.value[0] = val; 939 940 return 0; 941 } 942 943 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 944 struct snd_ctl_elem_value *ucontrol) 945 { 946 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 947 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 948 struct regmap *regmap = spdif_priv->regmap; 949 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 950 951 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 952 953 return 0; 954 } 955 956 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 957 struct snd_ctl_elem_value *ucontrol) 958 { 959 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 960 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 961 struct regmap *regmap = spdif_priv->regmap; 962 u32 val; 963 964 regmap_read(regmap, REG_SPDIF_SCR, &val); 965 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 966 ucontrol->value.integer.value[0] = val; 967 968 return 0; 969 } 970 971 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 972 struct snd_ctl_elem_value *ucontrol) 973 { 974 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 975 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 976 struct regmap *regmap = spdif_priv->regmap; 977 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 978 979 if (val) 980 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 981 else 982 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 983 984 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 985 986 return 0; 987 } 988 989 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol, 990 struct snd_ctl_elem_value *ucontrol) 991 { 992 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 993 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 994 995 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; 996 997 return 0; 998 } 999 1000 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol, 1001 struct snd_ctl_elem_value *ucontrol) 1002 { 1003 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1004 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 1005 struct snd_soc_card *card = dai->component->card; 1006 bool set = (ucontrol->value.integer.value[0] != 0); 1007 struct regmap *regmap = priv->regmap; 1008 struct snd_soc_pcm_runtime *rtd; 1009 u32 scr, mask; 1010 int stream; 1011 1012 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 1013 1014 if (priv->bypass == set) 1015 return 0; /* nothing to do */ 1016 1017 if (snd_soc_dai_active(dai)) { 1018 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); 1019 return -EBUSY; 1020 } 1021 1022 pm_runtime_get_sync(dai->dev); 1023 1024 if (set) { 1025 /* Disable interrupts */ 1026 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 1027 1028 /* Configure BYPASS mode */ 1029 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF; 1030 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK | 1031 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK; 1032 /* Power up SPDIF module */ 1033 mask |= SCR_LOW_POWER; 1034 } else { 1035 /* Power down SPDIF module, disable TX */ 1036 scr = SCR_LOW_POWER | SCR_TXSEL_OFF; 1037 mask = SCR_LOW_POWER | SCR_TXSEL_MASK; 1038 } 1039 1040 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 1041 1042 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */ 1043 for_each_pcm_streams(stream) 1044 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); 1045 1046 priv->bypass = set; 1047 pm_runtime_put_sync(dai->dev); 1048 1049 return 0; 1050 } 1051 1052 /* DPLL lock information */ 1053 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 1054 struct snd_ctl_elem_info *uinfo) 1055 { 1056 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1057 uinfo->count = 1; 1058 uinfo->value.integer.min = 16000; 1059 uinfo->value.integer.max = 192000; 1060 1061 return 0; 1062 } 1063 1064 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 1065 24, 16, 12, 8, 6, 4, 3, 1066 }; 1067 1068 /* Get RX data clock rate given the SPDIF bus_clk */ 1069 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 1070 enum spdif_gainsel gainsel) 1071 { 1072 struct regmap *regmap = spdif_priv->regmap; 1073 struct platform_device *pdev = spdif_priv->pdev; 1074 u64 tmpval64, busclk_freq = 0; 1075 u32 freqmeas, phaseconf; 1076 u8 clksrc; 1077 1078 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 1079 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 1080 1081 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 1082 1083 /* Get bus clock from system */ 1084 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 1085 busclk_freq = clk_get_rate(spdif_priv->sysclk); 1086 1087 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 1088 tmpval64 = (u64) busclk_freq * freqmeas; 1089 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 1090 do_div(tmpval64, 128 * 1024); 1091 1092 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 1093 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 1094 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 1095 1096 return (int)tmpval64; 1097 } 1098 1099 /* 1100 * Get DPLL lock or not info from stable interrupt status register. 1101 * User application must use this control to get locked, 1102 * then can do next PCM operation 1103 */ 1104 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 1105 struct snd_ctl_elem_value *ucontrol) 1106 { 1107 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1108 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1109 int rate = 0; 1110 1111 if (spdif_priv->dpll_locked) 1112 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 1113 1114 ucontrol->value.integer.value[0] = rate; 1115 1116 return 0; 1117 } 1118 1119 /* 1120 * User bit sync mode: 1121 * 1 CD User channel subcode 1122 * 0 Non-CD data 1123 */ 1124 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 1125 struct snd_ctl_elem_value *ucontrol) 1126 { 1127 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1128 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1129 struct regmap *regmap = spdif_priv->regmap; 1130 u32 val; 1131 1132 regmap_read(regmap, REG_SPDIF_SRCD, &val); 1133 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 1134 1135 return 0; 1136 } 1137 1138 /* 1139 * User bit sync mode: 1140 * 1 CD User channel subcode 1141 * 0 Non-CD data 1142 */ 1143 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 1144 struct snd_ctl_elem_value *ucontrol) 1145 { 1146 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1147 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1148 struct regmap *regmap = spdif_priv->regmap; 1149 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 1150 1151 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 1152 1153 return 0; 1154 } 1155 1156 /* FSL SPDIF IEC958 controller defines */ 1157 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1158 /* Status cchanel controller */ 1159 { 1160 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1161 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1162 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1163 SNDRV_CTL_ELEM_ACCESS_WRITE | 1164 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1165 .info = fsl_spdif_info, 1166 .get = fsl_spdif_pb_get, 1167 .put = fsl_spdif_pb_put, 1168 }, 1169 { 1170 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1171 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1172 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1173 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1174 .info = fsl_spdif_info, 1175 .get = fsl_spdif_capture_get, 1176 }, 1177 /* User bits controller */ 1178 { 1179 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1180 .name = "IEC958 Subcode Capture Default", 1181 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1182 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1183 .info = fsl_spdif_info, 1184 .get = fsl_spdif_subcode_get, 1185 }, 1186 { 1187 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1188 .name = "IEC958 Q-subcode Capture Default", 1189 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1190 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1191 .info = fsl_spdif_qinfo, 1192 .get = fsl_spdif_qget, 1193 }, 1194 /* Valid bit error controller */ 1195 { 1196 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1197 .name = "IEC958 RX V-Bit Errors", 1198 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1199 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1200 .info = snd_ctl_boolean_mono_info, 1201 .get = fsl_spdif_rx_vbit_get, 1202 }, 1203 { 1204 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1205 .name = "IEC958 TX V-Bit", 1206 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1207 SNDRV_CTL_ELEM_ACCESS_WRITE | 1208 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1209 .info = snd_ctl_boolean_mono_info, 1210 .get = fsl_spdif_tx_vbit_get, 1211 .put = fsl_spdif_tx_vbit_put, 1212 }, 1213 /* DPLL lock info get controller */ 1214 { 1215 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1216 .name = RX_SAMPLE_RATE_KCONTROL, 1217 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1218 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1219 .info = fsl_spdif_rxrate_info, 1220 .get = fsl_spdif_rxrate_get, 1221 }, 1222 /* RX bypass controller */ 1223 { 1224 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1225 .name = "Bypass Mode", 1226 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1227 .info = snd_ctl_boolean_mono_info, 1228 .get = fsl_spdif_bypass_get, 1229 .put = fsl_spdif_bypass_put, 1230 }, 1231 /* User bit sync mode set/get controller */ 1232 { 1233 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1234 .name = "IEC958 USyncMode CDText", 1235 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1236 SNDRV_CTL_ELEM_ACCESS_WRITE | 1237 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1238 .info = snd_ctl_boolean_mono_info, 1239 .get = fsl_spdif_usync_get, 1240 .put = fsl_spdif_usync_put, 1241 }, 1242 }; 1243 1244 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1245 { 1246 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1247 .name = "IEC958 Raw Capture Mode", 1248 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1249 SNDRV_CTL_ELEM_ACCESS_WRITE | 1250 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1251 .info = snd_ctl_boolean_mono_info, 1252 .get = fsl_spdif_rx_rcm_get, 1253 .put = fsl_spdif_rx_rcm_put, 1254 }, 1255 }; 1256 1257 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1258 { 1259 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1260 1261 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1262 &spdif_private->dma_params_rx); 1263 1264 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1265 1266 if (spdif_private->soc->raw_capture_mode) 1267 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1268 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1269 1270 spdif_private->snd_card = dai->component->card->snd_card; 1271 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card, 1272 RX_SAMPLE_RATE_KCONTROL); 1273 if (!spdif_private->rxrate_kcontrol) 1274 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n", 1275 RX_SAMPLE_RATE_KCONTROL); 1276 1277 /*Clear the val bit for Tx*/ 1278 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1279 SCR_VAL_MASK, SCR_VAL_CLEAR); 1280 1281 return 0; 1282 } 1283 1284 static struct snd_soc_dai_driver fsl_spdif_dai = { 1285 .probe = &fsl_spdif_dai_probe, 1286 .playback = { 1287 .stream_name = "CPU-Playback", 1288 .channels_min = 2, 1289 .channels_max = 2, 1290 .rates = FSL_SPDIF_RATES_PLAYBACK, 1291 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1292 }, 1293 .capture = { 1294 .stream_name = "CPU-Capture", 1295 .channels_min = 2, 1296 .channels_max = 2, 1297 .rates = FSL_SPDIF_RATES_CAPTURE, 1298 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1299 }, 1300 .ops = &fsl_spdif_dai_ops, 1301 }; 1302 1303 static const struct snd_soc_component_driver fsl_spdif_component = { 1304 .name = "fsl-spdif", 1305 .legacy_dai_naming = 1, 1306 }; 1307 1308 /* FSL SPDIF REGMAP */ 1309 static const struct reg_default fsl_spdif_reg_defaults[] = { 1310 {REG_SPDIF_SCR, 0x00000400}, 1311 {REG_SPDIF_SRCD, 0x00000000}, 1312 {REG_SPDIF_SIE, 0x00000000}, 1313 {REG_SPDIF_STL, 0x00000000}, 1314 {REG_SPDIF_STR, 0x00000000}, 1315 {REG_SPDIF_STCSCH, 0x00000000}, 1316 {REG_SPDIF_STCSCL, 0x00000000}, 1317 {REG_SPDIF_STCSPH, 0x00000000}, 1318 {REG_SPDIF_STCSPL, 0x00000000}, 1319 {REG_SPDIF_STC, 0x00020f00}, 1320 }; 1321 1322 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1323 { 1324 switch (reg) { 1325 case REG_SPDIF_SCR: 1326 case REG_SPDIF_SRCD: 1327 case REG_SPDIF_SRPC: 1328 case REG_SPDIF_SIE: 1329 case REG_SPDIF_SIS: 1330 case REG_SPDIF_SRL: 1331 case REG_SPDIF_SRR: 1332 case REG_SPDIF_SRCSH: 1333 case REG_SPDIF_SRCSL: 1334 case REG_SPDIF_SRU: 1335 case REG_SPDIF_SRQ: 1336 case REG_SPDIF_STCSCH: 1337 case REG_SPDIF_STCSCL: 1338 case REG_SPDIF_STCSPH: 1339 case REG_SPDIF_STCSPL: 1340 case REG_SPDIF_SRFM: 1341 case REG_SPDIF_STC: 1342 case REG_SPDIF_SRCCA_31_0: 1343 case REG_SPDIF_SRCCA_63_32: 1344 case REG_SPDIF_SRCCA_95_64: 1345 case REG_SPDIF_SRCCA_127_96: 1346 case REG_SPDIF_SRCCA_159_128: 1347 case REG_SPDIF_SRCCA_191_160: 1348 case REG_SPDIF_STCCA_31_0: 1349 case REG_SPDIF_STCCA_63_32: 1350 case REG_SPDIF_STCCA_95_64: 1351 case REG_SPDIF_STCCA_127_96: 1352 case REG_SPDIF_STCCA_159_128: 1353 case REG_SPDIF_STCCA_191_160: 1354 return true; 1355 default: 1356 return false; 1357 } 1358 } 1359 1360 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1361 { 1362 switch (reg) { 1363 case REG_SPDIF_SRPC: 1364 case REG_SPDIF_SIS: 1365 case REG_SPDIF_SRL: 1366 case REG_SPDIF_SRR: 1367 case REG_SPDIF_SRCSH: 1368 case REG_SPDIF_SRCSL: 1369 case REG_SPDIF_SRU: 1370 case REG_SPDIF_SRQ: 1371 case REG_SPDIF_SRFM: 1372 case REG_SPDIF_SRCCA_31_0: 1373 case REG_SPDIF_SRCCA_63_32: 1374 case REG_SPDIF_SRCCA_95_64: 1375 case REG_SPDIF_SRCCA_127_96: 1376 case REG_SPDIF_SRCCA_159_128: 1377 case REG_SPDIF_SRCCA_191_160: 1378 return true; 1379 default: 1380 return false; 1381 } 1382 } 1383 1384 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1385 { 1386 switch (reg) { 1387 case REG_SPDIF_SCR: 1388 case REG_SPDIF_SRCD: 1389 case REG_SPDIF_SRPC: 1390 case REG_SPDIF_SIE: 1391 case REG_SPDIF_SIC: 1392 case REG_SPDIF_STL: 1393 case REG_SPDIF_STR: 1394 case REG_SPDIF_STCSCH: 1395 case REG_SPDIF_STCSCL: 1396 case REG_SPDIF_STCSPH: 1397 case REG_SPDIF_STCSPL: 1398 case REG_SPDIF_STC: 1399 case REG_SPDIF_STCCA_31_0: 1400 case REG_SPDIF_STCCA_63_32: 1401 case REG_SPDIF_STCCA_95_64: 1402 case REG_SPDIF_STCCA_127_96: 1403 case REG_SPDIF_STCCA_159_128: 1404 case REG_SPDIF_STCCA_191_160: 1405 return true; 1406 default: 1407 return false; 1408 } 1409 } 1410 1411 static const struct regmap_config fsl_spdif_regmap_config = { 1412 .reg_bits = 32, 1413 .reg_stride = 4, 1414 .val_bits = 32, 1415 1416 .max_register = REG_SPDIF_STCCA_191_160, 1417 .reg_defaults = fsl_spdif_reg_defaults, 1418 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1419 .readable_reg = fsl_spdif_readable_reg, 1420 .volatile_reg = fsl_spdif_volatile_reg, 1421 .writeable_reg = fsl_spdif_writeable_reg, 1422 .cache_type = REGCACHE_FLAT, 1423 }; 1424 1425 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1426 struct clk *clk, u64 savesub, 1427 enum spdif_txrate index, bool round) 1428 { 1429 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400, 1430 192000, }; 1431 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1432 u64 rate_ideal, rate_actual, sub; 1433 u32 arate; 1434 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1435 u8 txclk_df; 1436 1437 /* The sysclk has an extra divisor [2, 512] */ 1438 sysclk_dfmin = is_sysclk ? 2 : 1; 1439 sysclk_dfmax = is_sysclk ? 512 : 1; 1440 1441 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1442 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1443 rate_ideal = rate[index] * txclk_df * 64ULL; 1444 if (round) 1445 rate_actual = clk_round_rate(clk, rate_ideal); 1446 else 1447 rate_actual = clk_get_rate(clk); 1448 1449 arate = rate_actual / 64; 1450 arate /= txclk_df * sysclk_df; 1451 1452 if (arate == rate[index]) { 1453 /* We are lucky */ 1454 savesub = 0; 1455 spdif_priv->txclk_df[index] = txclk_df; 1456 spdif_priv->sysclk_df[index] = sysclk_df; 1457 spdif_priv->txrate[index] = arate; 1458 goto out; 1459 } else if (arate / rate[index] == 1) { 1460 /* A little bigger than expect */ 1461 sub = (u64)(arate - rate[index]) * 100000; 1462 do_div(sub, rate[index]); 1463 if (sub >= savesub) 1464 continue; 1465 savesub = sub; 1466 spdif_priv->txclk_df[index] = txclk_df; 1467 spdif_priv->sysclk_df[index] = sysclk_df; 1468 spdif_priv->txrate[index] = arate; 1469 } else if (rate[index] / arate == 1) { 1470 /* A little smaller than expect */ 1471 sub = (u64)(rate[index] - arate) * 100000; 1472 do_div(sub, rate[index]); 1473 if (sub >= savesub) 1474 continue; 1475 savesub = sub; 1476 spdif_priv->txclk_df[index] = txclk_df; 1477 spdif_priv->sysclk_df[index] = sysclk_df; 1478 spdif_priv->txrate[index] = arate; 1479 } 1480 } 1481 } 1482 1483 out: 1484 return savesub; 1485 } 1486 1487 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1488 enum spdif_txrate index) 1489 { 1490 static const u32 rate[] = { 22050, 32000, 44100, 48000, 88200, 96000, 176400, 1491 192000, }; 1492 struct platform_device *pdev = spdif_priv->pdev; 1493 struct device *dev = &pdev->dev; 1494 u64 savesub = 100000, ret; 1495 struct clk *clk; 1496 int i; 1497 1498 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1499 clk = spdif_priv->txclk[i]; 1500 if (IS_ERR(clk)) { 1501 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1502 return PTR_ERR(clk); 1503 } 1504 if (!clk_get_rate(clk)) 1505 continue; 1506 1507 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1508 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1509 if (savesub == ret) 1510 continue; 1511 1512 savesub = ret; 1513 spdif_priv->txclk_src[index] = i; 1514 1515 /* To quick catch a divisor, we allow a 0.1% deviation */ 1516 if (savesub < 100) 1517 break; 1518 } 1519 1520 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1521 spdif_priv->txclk_src[index], rate[index]); 1522 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1523 spdif_priv->txclk_df[index], rate[index]); 1524 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) 1525 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1526 spdif_priv->sysclk_df[index], rate[index]); 1527 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1528 rate[index], spdif_priv->txrate[index]); 1529 1530 return 0; 1531 } 1532 1533 static int fsl_spdif_probe(struct platform_device *pdev) 1534 { 1535 struct fsl_spdif_priv *spdif_priv; 1536 struct spdif_mixer_control *ctrl; 1537 struct resource *res; 1538 void __iomem *regs; 1539 int irq, ret, i; 1540 char tmp[16]; 1541 1542 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1543 if (!spdif_priv) 1544 return -ENOMEM; 1545 1546 spdif_priv->pdev = pdev; 1547 1548 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1549 1550 /* Initialize this copy of the CPU DAI driver structure */ 1551 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1552 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1553 spdif_priv->cpu_dai_drv.playback.formats = 1554 spdif_priv->soc->tx_formats; 1555 1556 /* Get the addresses and IRQ */ 1557 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1558 if (IS_ERR(regs)) 1559 return PTR_ERR(regs); 1560 1561 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1562 if (IS_ERR(spdif_priv->regmap)) { 1563 dev_err(&pdev->dev, "regmap init failed\n"); 1564 return PTR_ERR(spdif_priv->regmap); 1565 } 1566 1567 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1568 irq = platform_get_irq(pdev, i); 1569 if (irq < 0) 1570 return irq; 1571 1572 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1573 dev_name(&pdev->dev), spdif_priv); 1574 if (ret) { 1575 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1576 return ret; 1577 } 1578 } 1579 1580 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1581 sprintf(tmp, "rxtx%d", i); 1582 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); 1583 if (IS_ERR(spdif_priv->txclk[i])) { 1584 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); 1585 return PTR_ERR(spdif_priv->txclk[i]); 1586 } 1587 } 1588 1589 /* Get system clock for rx clock rate calculation */ 1590 spdif_priv->sysclk = spdif_priv->txclk[5]; 1591 if (IS_ERR(spdif_priv->sysclk)) { 1592 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1593 return PTR_ERR(spdif_priv->sysclk); 1594 } 1595 1596 /* Get core clock for data register access via DMA */ 1597 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1598 if (IS_ERR(spdif_priv->coreclk)) { 1599 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1600 return PTR_ERR(spdif_priv->coreclk); 1601 } 1602 1603 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1604 if (IS_ERR(spdif_priv->spbaclk)) 1605 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1606 1607 /* Select clock source for rx/tx clock */ 1608 spdif_priv->rxclk = spdif_priv->txclk[1]; 1609 if (IS_ERR(spdif_priv->rxclk)) { 1610 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1611 return PTR_ERR(spdif_priv->rxclk); 1612 } 1613 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1614 1615 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, 1616 &spdif_priv->pll11k_clk); 1617 1618 /* Initial spinlock for control data */ 1619 ctrl = &spdif_priv->fsl_spdif_control; 1620 spin_lock_init(&ctrl->ctl_lock); 1621 1622 /* Init tx channel status default value */ 1623 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1624 IEC958_AES0_CON_EMPHASIS_5015; 1625 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1626 ctrl->ch_status[2] = 0x00; 1627 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1628 IEC958_AES3_CON_CLOCK_1000PPM; 1629 1630 spdif_priv->dpll_locked = false; 1631 1632 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1633 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1634 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1635 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1636 1637 /* Register with ASoC */ 1638 dev_set_drvdata(&pdev->dev, spdif_priv); 1639 pm_runtime_enable(&pdev->dev); 1640 regcache_cache_only(spdif_priv->regmap, true); 1641 1642 /* 1643 * Register platform component before registering cpu dai for there 1644 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1645 */ 1646 ret = imx_pcm_dma_init(pdev); 1647 if (ret) { 1648 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1649 goto err_pm_disable; 1650 } 1651 1652 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1653 &spdif_priv->cpu_dai_drv, 1); 1654 if (ret) { 1655 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1656 goto err_pm_disable; 1657 } 1658 1659 return ret; 1660 1661 err_pm_disable: 1662 pm_runtime_disable(&pdev->dev); 1663 return ret; 1664 } 1665 1666 static void fsl_spdif_remove(struct platform_device *pdev) 1667 { 1668 pm_runtime_disable(&pdev->dev); 1669 } 1670 1671 #ifdef CONFIG_PM 1672 static int fsl_spdif_runtime_suspend(struct device *dev) 1673 { 1674 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1675 int i; 1676 1677 /* Disable all the interrupts */ 1678 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1679 1680 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1681 &spdif_priv->regcache_srpc); 1682 regcache_cache_only(spdif_priv->regmap, true); 1683 1684 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) 1685 clk_disable_unprepare(spdif_priv->txclk[i]); 1686 1687 if (!IS_ERR(spdif_priv->spbaclk)) 1688 clk_disable_unprepare(spdif_priv->spbaclk); 1689 clk_disable_unprepare(spdif_priv->coreclk); 1690 1691 return 0; 1692 } 1693 1694 static int fsl_spdif_runtime_resume(struct device *dev) 1695 { 1696 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1697 int ret; 1698 int i; 1699 1700 ret = clk_prepare_enable(spdif_priv->coreclk); 1701 if (ret) { 1702 dev_err(dev, "failed to enable core clock\n"); 1703 return ret; 1704 } 1705 1706 if (!IS_ERR(spdif_priv->spbaclk)) { 1707 ret = clk_prepare_enable(spdif_priv->spbaclk); 1708 if (ret) { 1709 dev_err(dev, "failed to enable spba clock\n"); 1710 goto disable_core_clk; 1711 } 1712 } 1713 1714 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1715 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1716 if (ret) 1717 goto disable_tx_clk; 1718 } 1719 1720 regcache_cache_only(spdif_priv->regmap, false); 1721 regcache_mark_dirty(spdif_priv->regmap); 1722 1723 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1724 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1725 spdif_priv->regcache_srpc); 1726 1727 ret = regcache_sync(spdif_priv->regmap); 1728 if (ret) 1729 goto disable_tx_clk; 1730 1731 return 0; 1732 1733 disable_tx_clk: 1734 for (i--; i >= 0; i--) 1735 clk_disable_unprepare(spdif_priv->txclk[i]); 1736 if (!IS_ERR(spdif_priv->spbaclk)) 1737 clk_disable_unprepare(spdif_priv->spbaclk); 1738 disable_core_clk: 1739 clk_disable_unprepare(spdif_priv->coreclk); 1740 1741 return ret; 1742 } 1743 #endif /* CONFIG_PM */ 1744 1745 static const struct dev_pm_ops fsl_spdif_pm = { 1746 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1747 pm_runtime_force_resume) 1748 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1749 NULL) 1750 }; 1751 1752 static const struct of_device_id fsl_spdif_dt_ids[] = { 1753 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1754 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1755 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1756 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1757 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1758 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, }, 1759 {} 1760 }; 1761 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1762 1763 static struct platform_driver fsl_spdif_driver = { 1764 .driver = { 1765 .name = "fsl-spdif-dai", 1766 .of_match_table = fsl_spdif_dt_ids, 1767 .pm = &fsl_spdif_pm, 1768 }, 1769 .probe = fsl_spdif_probe, 1770 .remove_new = fsl_spdif_remove, 1771 }; 1772 1773 module_platform_driver(fsl_spdif_driver); 1774 1775 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1776 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1777 MODULE_LICENSE("GPL v2"); 1778 MODULE_ALIAS("platform:fsl-spdif-dai"); 1779