1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SPDIF_TXFIFO_WML 0x8 30 #define FSL_SPDIF_RXFIFO_WML 0x8 31 32 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 33 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 34 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 35 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 36 INT_LOSS_LOCK | INT_DPLL_LOCKED) 37 38 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 39 40 /* Index list for the values that has if (DPLL Locked) condition */ 41 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 42 #define SRPC_NODPLL_START1 0x5 43 #define SRPC_NODPLL_START2 0xc 44 45 #define DEFAULT_RXCLK_SRC 1 46 47 #define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate" 48 49 /** 50 * struct fsl_spdif_soc_data: soc specific data 51 * 52 * @imx: for imx platform 53 * @shared_root_clock: flag of sharing a clock source with others; 54 * so the driver shouldn't set root clock rate 55 * @raw_capture_mode: if raw capture mode support 56 * @cchannel_192b: if there are registers for 192bits C channel data 57 * @interrupts: interrupt number 58 * @tx_burst: tx maxburst size 59 * @rx_burst: rx maxburst size 60 * @tx_formats: tx supported data format 61 */ 62 struct fsl_spdif_soc_data { 63 bool imx; 64 bool shared_root_clock; 65 bool raw_capture_mode; 66 bool cchannel_192b; 67 u32 interrupts; 68 u32 tx_burst; 69 u32 rx_burst; 70 u64 tx_formats; 71 }; 72 73 /* 74 * SPDIF control structure 75 * Defines channel status, subcode and Q sub 76 */ 77 struct spdif_mixer_control { 78 /* spinlock to access control data */ 79 spinlock_t ctl_lock; 80 81 /* IEC958 channel tx status bit */ 82 unsigned char ch_status[4]; 83 84 /* User bits */ 85 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 86 87 /* Q subcode part of user bits */ 88 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 89 90 /* Buffer offset for U/Q */ 91 u32 upos; 92 u32 qpos; 93 94 /* Ready buffer index of the two buffers */ 95 u32 ready_buf; 96 }; 97 98 /** 99 * struct fsl_spdif_priv - Freescale SPDIF private data 100 * @soc: SPDIF soc data 101 * @fsl_spdif_control: SPDIF control data 102 * @cpu_dai_drv: cpu dai driver 103 * @snd_card: sound card pointer 104 * @rxrate_kcontrol: kcontrol for RX Sample Rate 105 * @pdev: platform device pointer 106 * @regmap: regmap handler 107 * @dpll_locked: dpll lock flag 108 * @txrate: the best rates for playback 109 * @txclk_df: STC_TXCLK_DF dividers value for playback 110 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 111 * @txclk_src: STC_TXCLK_SRC values for playback 112 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 113 * @txclk: tx clock sources for playback 114 * @rxclk: rx clock sources for capture 115 * @coreclk: core clock for register access via DMA 116 * @sysclk: system clock for rx clock rate measurement 117 * @spbaclk: SPBA clock (optional, depending on SoC design) 118 * @dma_params_tx: DMA parameters for transmit channel 119 * @dma_params_rx: DMA parameters for receive channel 120 * @regcache_srpc: regcache for SRPC 121 * @bypass: status of bypass input to output 122 * @pll8k_clk: PLL clock for the rate of multiply of 8kHz 123 * @pll11k_clk: PLL clock for the rate of multiply of 11kHz 124 */ 125 struct fsl_spdif_priv { 126 const struct fsl_spdif_soc_data *soc; 127 struct spdif_mixer_control fsl_spdif_control; 128 struct snd_soc_dai_driver cpu_dai_drv; 129 struct snd_card *snd_card; 130 struct snd_kcontrol *rxrate_kcontrol; 131 struct platform_device *pdev; 132 struct regmap *regmap; 133 bool dpll_locked; 134 u32 txrate[SPDIF_TXRATE_MAX]; 135 u8 txclk_df[SPDIF_TXRATE_MAX]; 136 u16 sysclk_df[SPDIF_TXRATE_MAX]; 137 u8 txclk_src[SPDIF_TXRATE_MAX]; 138 u8 rxclk_src; 139 struct clk *txclk[STC_TXCLK_SRC_MAX]; 140 struct clk *rxclk; 141 struct clk *coreclk; 142 struct clk *sysclk; 143 struct clk *spbaclk; 144 struct snd_dmaengine_dai_dma_data dma_params_tx; 145 struct snd_dmaengine_dai_dma_data dma_params_rx; 146 /* regcache for SRPC */ 147 u32 regcache_srpc; 148 bool bypass; 149 struct clk *pll8k_clk; 150 struct clk *pll11k_clk; 151 }; 152 153 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 154 .imx = false, 155 .shared_root_clock = false, 156 .raw_capture_mode = false, 157 .interrupts = 1, 158 .tx_burst = FSL_SPDIF_TXFIFO_WML, 159 .rx_burst = FSL_SPDIF_RXFIFO_WML, 160 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 161 }; 162 163 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 164 .imx = true, 165 .shared_root_clock = false, 166 .raw_capture_mode = false, 167 .interrupts = 1, 168 .tx_burst = FSL_SPDIF_TXFIFO_WML, 169 .rx_burst = FSL_SPDIF_RXFIFO_WML, 170 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 171 }; 172 173 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 174 .imx = true, 175 .shared_root_clock = true, 176 .raw_capture_mode = false, 177 .interrupts = 1, 178 .tx_burst = FSL_SPDIF_TXFIFO_WML, 179 .rx_burst = FSL_SPDIF_RXFIFO_WML, 180 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 181 182 }; 183 184 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 185 .imx = true, 186 .shared_root_clock = true, 187 .raw_capture_mode = false, 188 .interrupts = 2, 189 .tx_burst = 2, /* Applied for EDMA */ 190 .rx_burst = 2, /* Applied for EDMA */ 191 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 192 }; 193 194 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 195 .imx = true, 196 .shared_root_clock = false, 197 .raw_capture_mode = true, 198 .interrupts = 1, 199 .tx_burst = FSL_SPDIF_TXFIFO_WML, 200 .rx_burst = FSL_SPDIF_RXFIFO_WML, 201 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 202 }; 203 204 static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = { 205 .imx = true, 206 .shared_root_clock = true, 207 .raw_capture_mode = false, 208 .interrupts = 1, 209 .tx_burst = 2, /* Applied for EDMA */ 210 .rx_burst = 2, /* Applied for EDMA */ 211 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 212 .cchannel_192b = true, 213 }; 214 215 /* Check if clk is a root clock that does not share clock source with others */ 216 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 217 { 218 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 219 } 220 221 /* DPLL locked and lock loss interrupt handler */ 222 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 223 { 224 struct regmap *regmap = spdif_priv->regmap; 225 struct platform_device *pdev = spdif_priv->pdev; 226 u32 locked; 227 228 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 229 locked &= SRPC_DPLL_LOCKED; 230 231 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 232 locked ? "locked" : "loss lock"); 233 234 spdif_priv->dpll_locked = locked ? true : false; 235 236 if (spdif_priv->snd_card && spdif_priv->rxrate_kcontrol) { 237 snd_ctl_notify(spdif_priv->snd_card, 238 SNDRV_CTL_EVENT_MASK_VALUE, 239 &spdif_priv->rxrate_kcontrol->id); 240 } 241 } 242 243 /* Receiver found illegal symbol interrupt handler */ 244 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 245 { 246 struct regmap *regmap = spdif_priv->regmap; 247 struct platform_device *pdev = spdif_priv->pdev; 248 249 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 250 251 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 252 if (!spdif_priv->dpll_locked) 253 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 254 } 255 256 /* U/Q Channel receive register full */ 257 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 258 { 259 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 260 struct regmap *regmap = spdif_priv->regmap; 261 struct platform_device *pdev = spdif_priv->pdev; 262 u32 *pos, size, val, reg; 263 264 switch (name) { 265 case 'U': 266 pos = &ctrl->upos; 267 size = SPDIF_UBITS_SIZE; 268 reg = REG_SPDIF_SRU; 269 break; 270 case 'Q': 271 pos = &ctrl->qpos; 272 size = SPDIF_QSUB_SIZE; 273 reg = REG_SPDIF_SRQ; 274 break; 275 default: 276 dev_err(&pdev->dev, "unsupported channel name\n"); 277 return; 278 } 279 280 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 281 282 if (*pos >= size * 2) { 283 *pos = 0; 284 } else if (unlikely((*pos % size) + 3 > size)) { 285 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 286 return; 287 } 288 289 regmap_read(regmap, reg, &val); 290 ctrl->subcode[*pos++] = val >> 16; 291 ctrl->subcode[*pos++] = val >> 8; 292 ctrl->subcode[*pos++] = val; 293 } 294 295 /* U/Q Channel sync found */ 296 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 297 { 298 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 299 struct platform_device *pdev = spdif_priv->pdev; 300 301 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 302 303 /* U/Q buffer reset */ 304 if (ctrl->qpos == 0) 305 return; 306 307 /* Set ready to this buffer */ 308 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 309 } 310 311 /* U/Q Channel framing error */ 312 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 313 { 314 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 315 struct regmap *regmap = spdif_priv->regmap; 316 struct platform_device *pdev = spdif_priv->pdev; 317 u32 val; 318 319 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 320 321 /* Read U/Q data to clear the irq and do buffer reset */ 322 regmap_read(regmap, REG_SPDIF_SRU, &val); 323 regmap_read(regmap, REG_SPDIF_SRQ, &val); 324 325 /* Drop this U/Q buffer */ 326 ctrl->ready_buf = 0; 327 ctrl->upos = 0; 328 ctrl->qpos = 0; 329 } 330 331 /* Get spdif interrupt status and clear the interrupt */ 332 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 333 { 334 struct regmap *regmap = spdif_priv->regmap; 335 u32 val, val2; 336 337 regmap_read(regmap, REG_SPDIF_SIS, &val); 338 regmap_read(regmap, REG_SPDIF_SIE, &val2); 339 340 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 341 342 return val; 343 } 344 345 static irqreturn_t spdif_isr(int irq, void *devid) 346 { 347 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 348 struct platform_device *pdev = spdif_priv->pdev; 349 u32 sis; 350 351 sis = spdif_intr_status_clear(spdif_priv); 352 353 if (sis & INT_DPLL_LOCKED) 354 spdif_irq_dpll_lock(spdif_priv); 355 356 if (sis & INT_TXFIFO_UNOV) 357 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 358 359 if (sis & INT_TXFIFO_RESYNC) 360 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 361 362 if (sis & INT_CNEW) 363 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 364 365 if (sis & INT_VAL_NOGOOD) 366 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 367 368 if (sis & INT_SYM_ERR) 369 spdif_irq_sym_error(spdif_priv); 370 371 if (sis & INT_BIT_ERR) 372 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 373 374 if (sis & INT_URX_FUL) 375 spdif_irq_uqrx_full(spdif_priv, 'U'); 376 377 if (sis & INT_URX_OV) 378 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 379 380 if (sis & INT_QRX_FUL) 381 spdif_irq_uqrx_full(spdif_priv, 'Q'); 382 383 if (sis & INT_QRX_OV) 384 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 385 386 if (sis & INT_UQ_SYNC) 387 spdif_irq_uq_sync(spdif_priv); 388 389 if (sis & INT_UQ_ERR) 390 spdif_irq_uq_err(spdif_priv); 391 392 if (sis & INT_RXFIFO_UNOV) 393 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 394 395 if (sis & INT_RXFIFO_RESYNC) 396 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 397 398 if (sis & INT_LOSS_LOCK) 399 spdif_irq_dpll_lock(spdif_priv); 400 401 /* FIXME: Write Tx FIFO to clear TxEm */ 402 if (sis & INT_TX_EM) 403 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 404 405 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 406 if (sis & INT_RXFIFO_FUL) 407 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 408 409 return IRQ_HANDLED; 410 } 411 412 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 413 { 414 struct regmap *regmap = spdif_priv->regmap; 415 u32 val, cycle = 1000; 416 417 regcache_cache_bypass(regmap, true); 418 419 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 420 421 /* 422 * RESET bit would be cleared after finishing its reset procedure, 423 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 424 */ 425 do { 426 regmap_read(regmap, REG_SPDIF_SCR, &val); 427 } while ((val & SCR_SOFT_RESET) && cycle--); 428 429 regcache_cache_bypass(regmap, false); 430 regcache_mark_dirty(regmap); 431 regcache_sync(regmap); 432 433 if (cycle) 434 return 0; 435 else 436 return -EBUSY; 437 } 438 439 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 440 u8 mask, u8 cstatus) 441 { 442 ctrl->ch_status[3] &= ~mask; 443 ctrl->ch_status[3] |= cstatus & mask; 444 } 445 446 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 447 { 448 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 449 struct regmap *regmap = spdif_priv->regmap; 450 struct platform_device *pdev = spdif_priv->pdev; 451 u32 ch_status; 452 453 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 454 (bitrev8(ctrl->ch_status[1]) << 8) | 455 bitrev8(ctrl->ch_status[2]); 456 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 457 458 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 459 460 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 461 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 462 463 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 464 465 if (spdif_priv->soc->cchannel_192b) { 466 ch_status = (bitrev8(ctrl->ch_status[0]) << 24) | 467 (bitrev8(ctrl->ch_status[1]) << 16) | 468 (bitrev8(ctrl->ch_status[2]) << 8) | 469 bitrev8(ctrl->ch_status[3]); 470 471 regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000); 472 473 /* 474 * The first 32bit should be in REG_SPDIF_STCCA_31_0 register, 475 * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP 476 * then can get correct result with HDMI analyzer capture. 477 * There is a hardware bug here. 478 */ 479 regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status); 480 } 481 } 482 483 /* Set SPDIF PhaseConfig register for rx clock */ 484 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 485 enum spdif_gainsel gainsel, int dpll_locked) 486 { 487 struct regmap *regmap = spdif_priv->regmap; 488 u8 clksrc = spdif_priv->rxclk_src; 489 490 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 491 return -EINVAL; 492 493 regmap_update_bits(regmap, REG_SPDIF_SRPC, 494 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 495 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 496 497 return 0; 498 } 499 500 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum spdif_txrate index); 501 502 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 503 int sample_rate) 504 { 505 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 506 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 507 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 508 struct regmap *regmap = spdif_priv->regmap; 509 struct platform_device *pdev = spdif_priv->pdev; 510 unsigned long csfs = 0; 511 u32 stc, mask, rate; 512 u16 sysclk_df; 513 u8 clk, txclk_df; 514 int ret; 515 516 switch (sample_rate) { 517 case 32000: 518 rate = SPDIF_TXRATE_32000; 519 csfs = IEC958_AES3_CON_FS_32000; 520 break; 521 case 44100: 522 rate = SPDIF_TXRATE_44100; 523 csfs = IEC958_AES3_CON_FS_44100; 524 break; 525 case 48000: 526 rate = SPDIF_TXRATE_48000; 527 csfs = IEC958_AES3_CON_FS_48000; 528 break; 529 case 88200: 530 rate = SPDIF_TXRATE_88200; 531 csfs = IEC958_AES3_CON_FS_88200; 532 break; 533 case 96000: 534 rate = SPDIF_TXRATE_96000; 535 csfs = IEC958_AES3_CON_FS_96000; 536 break; 537 case 176400: 538 rate = SPDIF_TXRATE_176400; 539 csfs = IEC958_AES3_CON_FS_176400; 540 break; 541 case 192000: 542 rate = SPDIF_TXRATE_192000; 543 csfs = IEC958_AES3_CON_FS_192000; 544 break; 545 default: 546 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 547 return -EINVAL; 548 } 549 550 ret = fsl_spdif_probe_txclk(spdif_priv, rate); 551 if (ret) 552 return ret; 553 554 clk = spdif_priv->txclk_src[rate]; 555 if (clk >= STC_TXCLK_SRC_MAX) { 556 dev_err(&pdev->dev, "tx clock source is out of range\n"); 557 return -EINVAL; 558 } 559 560 txclk_df = spdif_priv->txclk_df[rate]; 561 if (txclk_df == 0) { 562 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 563 return -EINVAL; 564 } 565 566 sysclk_df = spdif_priv->sysclk_df[rate]; 567 568 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 569 goto clk_set_bypass; 570 571 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 572 ret = clk_set_rate(spdif_priv->txclk[clk], 573 64 * sample_rate * txclk_df); 574 if (ret) { 575 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 576 return ret; 577 } 578 579 clk_set_bypass: 580 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 581 (64 * sample_rate * txclk_df * sysclk_df)); 582 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 583 clk_get_rate(spdif_priv->txclk[clk])); 584 585 /* set fs field in consumer channel status */ 586 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 587 588 /* select clock source and divisor */ 589 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 590 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 591 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 592 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 593 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 594 595 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 596 spdif_priv->txrate[rate], sample_rate); 597 598 return 0; 599 } 600 601 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 602 struct snd_soc_dai *cpu_dai) 603 { 604 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 605 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 606 struct platform_device *pdev = spdif_priv->pdev; 607 struct regmap *regmap = spdif_priv->regmap; 608 u32 scr, mask; 609 int ret; 610 611 /* Reset module and interrupts only for first initialization */ 612 if (!snd_soc_dai_active(cpu_dai)) { 613 ret = spdif_softreset(spdif_priv); 614 if (ret) { 615 dev_err(&pdev->dev, "failed to soft reset\n"); 616 return ret; 617 } 618 619 /* Disable all the interrupts */ 620 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 621 } 622 623 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 624 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 625 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 626 SCR_TXFIFO_FSEL_IF8; 627 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 628 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 629 SCR_TXFIFO_FSEL_MASK; 630 } else { 631 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 632 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 633 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 634 } 635 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 636 637 /* Power up SPDIF module */ 638 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 639 640 return 0; 641 } 642 643 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 644 struct snd_soc_dai *cpu_dai) 645 { 646 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 647 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 648 struct regmap *regmap = spdif_priv->regmap; 649 u32 scr, mask; 650 651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 652 scr = 0; 653 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 654 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 655 SCR_TXFIFO_FSEL_MASK; 656 /* Disable TX clock */ 657 regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0); 658 } else { 659 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 660 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 661 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 662 } 663 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 664 665 /* Power down SPDIF module only if tx&rx are both inactive */ 666 if (!snd_soc_dai_active(cpu_dai)) { 667 spdif_intr_status_clear(spdif_priv); 668 regmap_update_bits(regmap, REG_SPDIF_SCR, 669 SCR_LOW_POWER, SCR_LOW_POWER); 670 } 671 } 672 673 static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsigned int sample_rate) 674 { 675 struct platform_device *pdev = spdif_priv->pdev; 676 struct clk *clk; 677 int ret; 678 679 /* Reparent clock if required condition is true */ 680 if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT)) 681 return 0; 682 683 /* Get root clock */ 684 clk = spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; 685 686 /* Disable clock first, for it was enabled by pm_runtime */ 687 clk_disable_unprepare(clk); 688 fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, 689 spdif_priv->pll11k_clk, sample_rate); 690 ret = clk_prepare_enable(clk); 691 if (ret) 692 return ret; 693 694 return 0; 695 } 696 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 697 struct snd_pcm_hw_params *params, 698 struct snd_soc_dai *dai) 699 { 700 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 701 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 702 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 703 struct platform_device *pdev = spdif_priv->pdev; 704 u32 sample_rate = params_rate(params); 705 int ret = 0; 706 707 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 708 ret = spdif_reparent_rootclk(spdif_priv, sample_rate); 709 if (ret) { 710 dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", 711 __func__, sample_rate); 712 return ret; 713 } 714 715 ret = spdif_set_sample_rate(substream, sample_rate); 716 if (ret) { 717 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 718 __func__, sample_rate); 719 return ret; 720 } 721 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 722 IEC958_AES3_CON_CLOCK_1000PPM); 723 spdif_write_channel_status(spdif_priv); 724 } else { 725 /* Setup rx clock source */ 726 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 727 } 728 729 return ret; 730 } 731 732 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 733 int cmd, struct snd_soc_dai *dai) 734 { 735 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 736 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 737 struct regmap *regmap = spdif_priv->regmap; 738 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 739 u32 intr = SIE_INTR_FOR(tx); 740 u32 dmaen = SCR_DMA_xX_EN(tx); 741 742 switch (cmd) { 743 case SNDRV_PCM_TRIGGER_START: 744 case SNDRV_PCM_TRIGGER_RESUME: 745 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 746 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 747 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 748 break; 749 case SNDRV_PCM_TRIGGER_STOP: 750 case SNDRV_PCM_TRIGGER_SUSPEND: 751 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 752 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 753 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 754 break; 755 default: 756 return -EINVAL; 757 } 758 759 return 0; 760 } 761 762 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 763 .startup = fsl_spdif_startup, 764 .hw_params = fsl_spdif_hw_params, 765 .trigger = fsl_spdif_trigger, 766 .shutdown = fsl_spdif_shutdown, 767 }; 768 769 770 /* 771 * FSL SPDIF IEC958 controller(mixer) functions 772 * 773 * Channel status get/put control 774 * User bit value get/put control 775 * Valid bit value get control 776 * DPLL lock status get control 777 * User bit sync mode selection control 778 */ 779 780 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 781 struct snd_ctl_elem_info *uinfo) 782 { 783 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 784 uinfo->count = 1; 785 786 return 0; 787 } 788 789 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 790 struct snd_ctl_elem_value *uvalue) 791 { 792 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 793 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 794 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 795 796 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 797 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 798 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 799 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 800 801 return 0; 802 } 803 804 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 805 struct snd_ctl_elem_value *uvalue) 806 { 807 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 808 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 809 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 810 811 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 812 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 813 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 814 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 815 816 spdif_write_channel_status(spdif_priv); 817 818 return 0; 819 } 820 821 /* Get channel status from SPDIF_RX_CCHAN register */ 822 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 823 struct snd_ctl_elem_value *ucontrol) 824 { 825 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 826 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 827 struct regmap *regmap = spdif_priv->regmap; 828 u32 cstatus, val; 829 830 regmap_read(regmap, REG_SPDIF_SIS, &val); 831 if (!(val & INT_CNEW)) 832 return -EAGAIN; 833 834 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 835 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 836 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 837 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 838 839 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 840 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 841 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 842 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 843 844 /* Clear intr */ 845 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 846 847 return 0; 848 } 849 850 /* 851 * Get User bits (subcode) from chip value which readed out 852 * in UChannel register. 853 */ 854 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 855 struct snd_ctl_elem_value *ucontrol) 856 { 857 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 858 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 859 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 860 unsigned long flags; 861 int ret = -EAGAIN; 862 863 spin_lock_irqsave(&ctrl->ctl_lock, flags); 864 if (ctrl->ready_buf) { 865 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 866 memcpy(&ucontrol->value.iec958.subcode[0], 867 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 868 ret = 0; 869 } 870 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 871 872 return ret; 873 } 874 875 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 876 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 877 struct snd_ctl_elem_info *uinfo) 878 { 879 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 880 uinfo->count = SPDIF_QSUB_SIZE; 881 882 return 0; 883 } 884 885 /* Get Q subcode from chip value which readed out in QChannel register */ 886 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 887 struct snd_ctl_elem_value *ucontrol) 888 { 889 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 890 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 891 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 892 unsigned long flags; 893 int ret = -EAGAIN; 894 895 spin_lock_irqsave(&ctrl->ctl_lock, flags); 896 if (ctrl->ready_buf) { 897 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 898 memcpy(&ucontrol->value.bytes.data[0], 899 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 900 ret = 0; 901 } 902 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 903 904 return ret; 905 } 906 907 /* Get valid good bit from interrupt status register */ 908 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 909 struct snd_ctl_elem_value *ucontrol) 910 { 911 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 912 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 913 struct regmap *regmap = spdif_priv->regmap; 914 u32 val; 915 916 regmap_read(regmap, REG_SPDIF_SIS, &val); 917 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 918 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 919 920 return 0; 921 } 922 923 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 924 struct snd_ctl_elem_value *ucontrol) 925 { 926 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 927 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 928 struct regmap *regmap = spdif_priv->regmap; 929 u32 val; 930 931 regmap_read(regmap, REG_SPDIF_SCR, &val); 932 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 933 val = 1 - val; 934 ucontrol->value.integer.value[0] = val; 935 936 return 0; 937 } 938 939 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 940 struct snd_ctl_elem_value *ucontrol) 941 { 942 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 943 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 944 struct regmap *regmap = spdif_priv->regmap; 945 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 946 947 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 948 949 return 0; 950 } 951 952 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 953 struct snd_ctl_elem_value *ucontrol) 954 { 955 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 956 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 957 struct regmap *regmap = spdif_priv->regmap; 958 u32 val; 959 960 regmap_read(regmap, REG_SPDIF_SCR, &val); 961 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 962 ucontrol->value.integer.value[0] = val; 963 964 return 0; 965 } 966 967 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 968 struct snd_ctl_elem_value *ucontrol) 969 { 970 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 971 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 972 struct regmap *regmap = spdif_priv->regmap; 973 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 974 975 if (val) 976 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 977 else 978 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 979 980 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 981 982 return 0; 983 } 984 985 static int fsl_spdif_bypass_get(struct snd_kcontrol *kcontrol, 986 struct snd_ctl_elem_value *ucontrol) 987 { 988 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 989 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 990 991 ucontrol->value.integer.value[0] = priv->bypass ? 1 : 0; 992 993 return 0; 994 } 995 996 static int fsl_spdif_bypass_put(struct snd_kcontrol *kcontrol, 997 struct snd_ctl_elem_value *ucontrol) 998 { 999 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol); 1000 struct fsl_spdif_priv *priv = snd_soc_dai_get_drvdata(dai); 1001 struct snd_soc_card *card = dai->component->card; 1002 bool set = (ucontrol->value.integer.value[0] != 0); 1003 struct regmap *regmap = priv->regmap; 1004 struct snd_soc_pcm_runtime *rtd; 1005 u32 scr, mask; 1006 int stream; 1007 1008 rtd = snd_soc_get_pcm_runtime(card, card->dai_link); 1009 1010 if (priv->bypass == set) 1011 return 0; /* nothing to do */ 1012 1013 if (snd_soc_dai_active(dai)) { 1014 dev_err(dai->dev, "Cannot change BYPASS mode while stream is running.\n"); 1015 return -EBUSY; 1016 } 1017 1018 pm_runtime_get_sync(dai->dev); 1019 1020 if (set) { 1021 /* Disable interrupts */ 1022 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 1023 1024 /* Configure BYPASS mode */ 1025 scr = SCR_TXSEL_RX | SCR_RXFIFO_OFF; 1026 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK | 1027 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK | SCR_TXSEL_MASK; 1028 /* Power up SPDIF module */ 1029 mask |= SCR_LOW_POWER; 1030 } else { 1031 /* Power down SPDIF module, disable TX */ 1032 scr = SCR_LOW_POWER | SCR_TXSEL_OFF; 1033 mask = SCR_LOW_POWER | SCR_TXSEL_MASK; 1034 } 1035 1036 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 1037 1038 /* Disable playback & capture if BYPASS mode is enabled, enable otherwise */ 1039 for_each_pcm_streams(stream) 1040 rtd->pcm->streams[stream].substream_count = (set ? 0 : 1); 1041 1042 priv->bypass = set; 1043 pm_runtime_put_sync(dai->dev); 1044 1045 return 0; 1046 } 1047 1048 /* DPLL lock information */ 1049 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 1050 struct snd_ctl_elem_info *uinfo) 1051 { 1052 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1053 uinfo->count = 1; 1054 uinfo->value.integer.min = 16000; 1055 uinfo->value.integer.max = 192000; 1056 1057 return 0; 1058 } 1059 1060 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 1061 24, 16, 12, 8, 6, 4, 3, 1062 }; 1063 1064 /* Get RX data clock rate given the SPDIF bus_clk */ 1065 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 1066 enum spdif_gainsel gainsel) 1067 { 1068 struct regmap *regmap = spdif_priv->regmap; 1069 struct platform_device *pdev = spdif_priv->pdev; 1070 u64 tmpval64, busclk_freq = 0; 1071 u32 freqmeas, phaseconf; 1072 u8 clksrc; 1073 1074 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 1075 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 1076 1077 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 1078 1079 /* Get bus clock from system */ 1080 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 1081 busclk_freq = clk_get_rate(spdif_priv->sysclk); 1082 1083 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 1084 tmpval64 = (u64) busclk_freq * freqmeas; 1085 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 1086 do_div(tmpval64, 128 * 1024); 1087 1088 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 1089 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 1090 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 1091 1092 return (int)tmpval64; 1093 } 1094 1095 /* 1096 * Get DPLL lock or not info from stable interrupt status register. 1097 * User application must use this control to get locked, 1098 * then can do next PCM operation 1099 */ 1100 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 1101 struct snd_ctl_elem_value *ucontrol) 1102 { 1103 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1104 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1105 int rate = 0; 1106 1107 if (spdif_priv->dpll_locked) 1108 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 1109 1110 ucontrol->value.integer.value[0] = rate; 1111 1112 return 0; 1113 } 1114 1115 /* 1116 * User bit sync mode: 1117 * 1 CD User channel subcode 1118 * 0 Non-CD data 1119 */ 1120 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 1121 struct snd_ctl_elem_value *ucontrol) 1122 { 1123 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1124 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1125 struct regmap *regmap = spdif_priv->regmap; 1126 u32 val; 1127 1128 regmap_read(regmap, REG_SPDIF_SRCD, &val); 1129 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 1130 1131 return 0; 1132 } 1133 1134 /* 1135 * User bit sync mode: 1136 * 1 CD User channel subcode 1137 * 0 Non-CD data 1138 */ 1139 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 1140 struct snd_ctl_elem_value *ucontrol) 1141 { 1142 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1143 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 1144 struct regmap *regmap = spdif_priv->regmap; 1145 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 1146 1147 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 1148 1149 return 0; 1150 } 1151 1152 /* FSL SPDIF IEC958 controller defines */ 1153 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1154 /* Status cchanel controller */ 1155 { 1156 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1157 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1158 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1159 SNDRV_CTL_ELEM_ACCESS_WRITE | 1160 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1161 .info = fsl_spdif_info, 1162 .get = fsl_spdif_pb_get, 1163 .put = fsl_spdif_pb_put, 1164 }, 1165 { 1166 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1167 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1168 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1169 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1170 .info = fsl_spdif_info, 1171 .get = fsl_spdif_capture_get, 1172 }, 1173 /* User bits controller */ 1174 { 1175 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1176 .name = "IEC958 Subcode Capture Default", 1177 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1178 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1179 .info = fsl_spdif_info, 1180 .get = fsl_spdif_subcode_get, 1181 }, 1182 { 1183 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1184 .name = "IEC958 Q-subcode Capture Default", 1185 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1186 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1187 .info = fsl_spdif_qinfo, 1188 .get = fsl_spdif_qget, 1189 }, 1190 /* Valid bit error controller */ 1191 { 1192 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1193 .name = "IEC958 RX V-Bit Errors", 1194 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1195 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1196 .info = snd_ctl_boolean_mono_info, 1197 .get = fsl_spdif_rx_vbit_get, 1198 }, 1199 { 1200 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1201 .name = "IEC958 TX V-Bit", 1202 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1203 SNDRV_CTL_ELEM_ACCESS_WRITE | 1204 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1205 .info = snd_ctl_boolean_mono_info, 1206 .get = fsl_spdif_tx_vbit_get, 1207 .put = fsl_spdif_tx_vbit_put, 1208 }, 1209 /* DPLL lock info get controller */ 1210 { 1211 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1212 .name = RX_SAMPLE_RATE_KCONTROL, 1213 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1214 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1215 .info = fsl_spdif_rxrate_info, 1216 .get = fsl_spdif_rxrate_get, 1217 }, 1218 /* RX bypass controller */ 1219 { 1220 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1221 .name = "Bypass Mode", 1222 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, 1223 .info = snd_ctl_boolean_mono_info, 1224 .get = fsl_spdif_bypass_get, 1225 .put = fsl_spdif_bypass_put, 1226 }, 1227 /* User bit sync mode set/get controller */ 1228 { 1229 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1230 .name = "IEC958 USyncMode CDText", 1231 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1232 SNDRV_CTL_ELEM_ACCESS_WRITE | 1233 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1234 .info = snd_ctl_boolean_mono_info, 1235 .get = fsl_spdif_usync_get, 1236 .put = fsl_spdif_usync_put, 1237 }, 1238 }; 1239 1240 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1241 { 1242 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1243 .name = "IEC958 Raw Capture Mode", 1244 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1245 SNDRV_CTL_ELEM_ACCESS_WRITE | 1246 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1247 .info = snd_ctl_boolean_mono_info, 1248 .get = fsl_spdif_rx_rcm_get, 1249 .put = fsl_spdif_rx_rcm_put, 1250 }, 1251 }; 1252 1253 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1254 { 1255 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1256 1257 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1258 &spdif_private->dma_params_rx); 1259 1260 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1261 1262 if (spdif_private->soc->raw_capture_mode) 1263 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1264 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1265 1266 spdif_private->snd_card = dai->component->card->snd_card; 1267 spdif_private->rxrate_kcontrol = snd_soc_card_get_kcontrol(dai->component->card, 1268 RX_SAMPLE_RATE_KCONTROL); 1269 if (!spdif_private->rxrate_kcontrol) 1270 dev_err(&spdif_private->pdev->dev, "failed to get %s kcontrol\n", 1271 RX_SAMPLE_RATE_KCONTROL); 1272 1273 /*Clear the val bit for Tx*/ 1274 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1275 SCR_VAL_MASK, SCR_VAL_CLEAR); 1276 1277 return 0; 1278 } 1279 1280 static struct snd_soc_dai_driver fsl_spdif_dai = { 1281 .probe = &fsl_spdif_dai_probe, 1282 .playback = { 1283 .stream_name = "CPU-Playback", 1284 .channels_min = 2, 1285 .channels_max = 2, 1286 .rates = FSL_SPDIF_RATES_PLAYBACK, 1287 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1288 }, 1289 .capture = { 1290 .stream_name = "CPU-Capture", 1291 .channels_min = 2, 1292 .channels_max = 2, 1293 .rates = FSL_SPDIF_RATES_CAPTURE, 1294 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1295 }, 1296 .ops = &fsl_spdif_dai_ops, 1297 }; 1298 1299 static const struct snd_soc_component_driver fsl_spdif_component = { 1300 .name = "fsl-spdif", 1301 .legacy_dai_naming = 1, 1302 }; 1303 1304 /* FSL SPDIF REGMAP */ 1305 static const struct reg_default fsl_spdif_reg_defaults[] = { 1306 {REG_SPDIF_SCR, 0x00000400}, 1307 {REG_SPDIF_SRCD, 0x00000000}, 1308 {REG_SPDIF_SIE, 0x00000000}, 1309 {REG_SPDIF_STL, 0x00000000}, 1310 {REG_SPDIF_STR, 0x00000000}, 1311 {REG_SPDIF_STCSCH, 0x00000000}, 1312 {REG_SPDIF_STCSCL, 0x00000000}, 1313 {REG_SPDIF_STCSPH, 0x00000000}, 1314 {REG_SPDIF_STCSPL, 0x00000000}, 1315 {REG_SPDIF_STC, 0x00020f00}, 1316 }; 1317 1318 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1319 { 1320 switch (reg) { 1321 case REG_SPDIF_SCR: 1322 case REG_SPDIF_SRCD: 1323 case REG_SPDIF_SRPC: 1324 case REG_SPDIF_SIE: 1325 case REG_SPDIF_SIS: 1326 case REG_SPDIF_SRL: 1327 case REG_SPDIF_SRR: 1328 case REG_SPDIF_SRCSH: 1329 case REG_SPDIF_SRCSL: 1330 case REG_SPDIF_SRU: 1331 case REG_SPDIF_SRQ: 1332 case REG_SPDIF_STCSCH: 1333 case REG_SPDIF_STCSCL: 1334 case REG_SPDIF_STCSPH: 1335 case REG_SPDIF_STCSPL: 1336 case REG_SPDIF_SRFM: 1337 case REG_SPDIF_STC: 1338 case REG_SPDIF_SRCCA_31_0: 1339 case REG_SPDIF_SRCCA_63_32: 1340 case REG_SPDIF_SRCCA_95_64: 1341 case REG_SPDIF_SRCCA_127_96: 1342 case REG_SPDIF_SRCCA_159_128: 1343 case REG_SPDIF_SRCCA_191_160: 1344 case REG_SPDIF_STCCA_31_0: 1345 case REG_SPDIF_STCCA_63_32: 1346 case REG_SPDIF_STCCA_95_64: 1347 case REG_SPDIF_STCCA_127_96: 1348 case REG_SPDIF_STCCA_159_128: 1349 case REG_SPDIF_STCCA_191_160: 1350 return true; 1351 default: 1352 return false; 1353 } 1354 } 1355 1356 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1357 { 1358 switch (reg) { 1359 case REG_SPDIF_SRPC: 1360 case REG_SPDIF_SIS: 1361 case REG_SPDIF_SRL: 1362 case REG_SPDIF_SRR: 1363 case REG_SPDIF_SRCSH: 1364 case REG_SPDIF_SRCSL: 1365 case REG_SPDIF_SRU: 1366 case REG_SPDIF_SRQ: 1367 case REG_SPDIF_SRFM: 1368 case REG_SPDIF_SRCCA_31_0: 1369 case REG_SPDIF_SRCCA_63_32: 1370 case REG_SPDIF_SRCCA_95_64: 1371 case REG_SPDIF_SRCCA_127_96: 1372 case REG_SPDIF_SRCCA_159_128: 1373 case REG_SPDIF_SRCCA_191_160: 1374 return true; 1375 default: 1376 return false; 1377 } 1378 } 1379 1380 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1381 { 1382 switch (reg) { 1383 case REG_SPDIF_SCR: 1384 case REG_SPDIF_SRCD: 1385 case REG_SPDIF_SRPC: 1386 case REG_SPDIF_SIE: 1387 case REG_SPDIF_SIC: 1388 case REG_SPDIF_STL: 1389 case REG_SPDIF_STR: 1390 case REG_SPDIF_STCSCH: 1391 case REG_SPDIF_STCSCL: 1392 case REG_SPDIF_STCSPH: 1393 case REG_SPDIF_STCSPL: 1394 case REG_SPDIF_STC: 1395 case REG_SPDIF_STCCA_31_0: 1396 case REG_SPDIF_STCCA_63_32: 1397 case REG_SPDIF_STCCA_95_64: 1398 case REG_SPDIF_STCCA_127_96: 1399 case REG_SPDIF_STCCA_159_128: 1400 case REG_SPDIF_STCCA_191_160: 1401 return true; 1402 default: 1403 return false; 1404 } 1405 } 1406 1407 static const struct regmap_config fsl_spdif_regmap_config = { 1408 .reg_bits = 32, 1409 .reg_stride = 4, 1410 .val_bits = 32, 1411 1412 .max_register = REG_SPDIF_STCCA_191_160, 1413 .reg_defaults = fsl_spdif_reg_defaults, 1414 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1415 .readable_reg = fsl_spdif_readable_reg, 1416 .volatile_reg = fsl_spdif_volatile_reg, 1417 .writeable_reg = fsl_spdif_writeable_reg, 1418 .cache_type = REGCACHE_FLAT, 1419 }; 1420 1421 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1422 struct clk *clk, u64 savesub, 1423 enum spdif_txrate index, bool round) 1424 { 1425 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1426 192000, }; 1427 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1428 u64 rate_ideal, rate_actual, sub; 1429 u32 arate; 1430 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1431 u8 txclk_df; 1432 1433 /* The sysclk has an extra divisor [2, 512] */ 1434 sysclk_dfmin = is_sysclk ? 2 : 1; 1435 sysclk_dfmax = is_sysclk ? 512 : 1; 1436 1437 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1438 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1439 rate_ideal = rate[index] * txclk_df * 64ULL; 1440 if (round) 1441 rate_actual = clk_round_rate(clk, rate_ideal); 1442 else 1443 rate_actual = clk_get_rate(clk); 1444 1445 arate = rate_actual / 64; 1446 arate /= txclk_df * sysclk_df; 1447 1448 if (arate == rate[index]) { 1449 /* We are lucky */ 1450 savesub = 0; 1451 spdif_priv->txclk_df[index] = txclk_df; 1452 spdif_priv->sysclk_df[index] = sysclk_df; 1453 spdif_priv->txrate[index] = arate; 1454 goto out; 1455 } else if (arate / rate[index] == 1) { 1456 /* A little bigger than expect */ 1457 sub = (u64)(arate - rate[index]) * 100000; 1458 do_div(sub, rate[index]); 1459 if (sub >= savesub) 1460 continue; 1461 savesub = sub; 1462 spdif_priv->txclk_df[index] = txclk_df; 1463 spdif_priv->sysclk_df[index] = sysclk_df; 1464 spdif_priv->txrate[index] = arate; 1465 } else if (rate[index] / arate == 1) { 1466 /* A little smaller than expect */ 1467 sub = (u64)(rate[index] - arate) * 100000; 1468 do_div(sub, rate[index]); 1469 if (sub >= savesub) 1470 continue; 1471 savesub = sub; 1472 spdif_priv->txclk_df[index] = txclk_df; 1473 spdif_priv->sysclk_df[index] = sysclk_df; 1474 spdif_priv->txrate[index] = arate; 1475 } 1476 } 1477 } 1478 1479 out: 1480 return savesub; 1481 } 1482 1483 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1484 enum spdif_txrate index) 1485 { 1486 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1487 192000, }; 1488 struct platform_device *pdev = spdif_priv->pdev; 1489 struct device *dev = &pdev->dev; 1490 u64 savesub = 100000, ret; 1491 struct clk *clk; 1492 int i; 1493 1494 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1495 clk = spdif_priv->txclk[i]; 1496 if (IS_ERR(clk)) { 1497 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1498 return PTR_ERR(clk); 1499 } 1500 if (!clk_get_rate(clk)) 1501 continue; 1502 1503 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1504 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1505 if (savesub == ret) 1506 continue; 1507 1508 savesub = ret; 1509 spdif_priv->txclk_src[index] = i; 1510 1511 /* To quick catch a divisor, we allow a 0.1% deviation */ 1512 if (savesub < 100) 1513 break; 1514 } 1515 1516 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1517 spdif_priv->txclk_src[index], rate[index]); 1518 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1519 spdif_priv->txclk_df[index], rate[index]); 1520 if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk)) 1521 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1522 spdif_priv->sysclk_df[index], rate[index]); 1523 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1524 rate[index], spdif_priv->txrate[index]); 1525 1526 return 0; 1527 } 1528 1529 static int fsl_spdif_probe(struct platform_device *pdev) 1530 { 1531 struct fsl_spdif_priv *spdif_priv; 1532 struct spdif_mixer_control *ctrl; 1533 struct resource *res; 1534 void __iomem *regs; 1535 int irq, ret, i; 1536 char tmp[16]; 1537 1538 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1539 if (!spdif_priv) 1540 return -ENOMEM; 1541 1542 spdif_priv->pdev = pdev; 1543 1544 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1545 1546 /* Initialize this copy of the CPU DAI driver structure */ 1547 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1548 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1549 spdif_priv->cpu_dai_drv.playback.formats = 1550 spdif_priv->soc->tx_formats; 1551 1552 /* Get the addresses and IRQ */ 1553 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1554 if (IS_ERR(regs)) 1555 return PTR_ERR(regs); 1556 1557 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1558 if (IS_ERR(spdif_priv->regmap)) { 1559 dev_err(&pdev->dev, "regmap init failed\n"); 1560 return PTR_ERR(spdif_priv->regmap); 1561 } 1562 1563 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1564 irq = platform_get_irq(pdev, i); 1565 if (irq < 0) 1566 return irq; 1567 1568 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1569 dev_name(&pdev->dev), spdif_priv); 1570 if (ret) { 1571 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1572 return ret; 1573 } 1574 } 1575 1576 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1577 sprintf(tmp, "rxtx%d", i); 1578 spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp); 1579 if (IS_ERR(spdif_priv->txclk[i])) { 1580 dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i); 1581 return PTR_ERR(spdif_priv->txclk[i]); 1582 } 1583 } 1584 1585 /* Get system clock for rx clock rate calculation */ 1586 spdif_priv->sysclk = spdif_priv->txclk[5]; 1587 if (IS_ERR(spdif_priv->sysclk)) { 1588 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1589 return PTR_ERR(spdif_priv->sysclk); 1590 } 1591 1592 /* Get core clock for data register access via DMA */ 1593 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1594 if (IS_ERR(spdif_priv->coreclk)) { 1595 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1596 return PTR_ERR(spdif_priv->coreclk); 1597 } 1598 1599 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1600 if (IS_ERR(spdif_priv->spbaclk)) 1601 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1602 1603 /* Select clock source for rx/tx clock */ 1604 spdif_priv->rxclk = spdif_priv->txclk[1]; 1605 if (IS_ERR(spdif_priv->rxclk)) { 1606 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1607 return PTR_ERR(spdif_priv->rxclk); 1608 } 1609 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1610 1611 fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, 1612 &spdif_priv->pll11k_clk); 1613 1614 /* Initial spinlock for control data */ 1615 ctrl = &spdif_priv->fsl_spdif_control; 1616 spin_lock_init(&ctrl->ctl_lock); 1617 1618 /* Init tx channel status default value */ 1619 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1620 IEC958_AES0_CON_EMPHASIS_5015; 1621 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1622 ctrl->ch_status[2] = 0x00; 1623 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1624 IEC958_AES3_CON_CLOCK_1000PPM; 1625 1626 spdif_priv->dpll_locked = false; 1627 1628 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1629 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1630 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1631 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1632 1633 /* Register with ASoC */ 1634 dev_set_drvdata(&pdev->dev, spdif_priv); 1635 pm_runtime_enable(&pdev->dev); 1636 regcache_cache_only(spdif_priv->regmap, true); 1637 1638 /* 1639 * Register platform component before registering cpu dai for there 1640 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1641 */ 1642 ret = imx_pcm_dma_init(pdev); 1643 if (ret) { 1644 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1645 goto err_pm_disable; 1646 } 1647 1648 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1649 &spdif_priv->cpu_dai_drv, 1); 1650 if (ret) { 1651 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1652 goto err_pm_disable; 1653 } 1654 1655 return ret; 1656 1657 err_pm_disable: 1658 pm_runtime_disable(&pdev->dev); 1659 return ret; 1660 } 1661 1662 static int fsl_spdif_remove(struct platform_device *pdev) 1663 { 1664 pm_runtime_disable(&pdev->dev); 1665 1666 return 0; 1667 } 1668 1669 #ifdef CONFIG_PM 1670 static int fsl_spdif_runtime_suspend(struct device *dev) 1671 { 1672 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1673 int i; 1674 1675 /* Disable all the interrupts */ 1676 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1677 1678 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1679 &spdif_priv->regcache_srpc); 1680 regcache_cache_only(spdif_priv->regmap, true); 1681 1682 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) 1683 clk_disable_unprepare(spdif_priv->txclk[i]); 1684 1685 if (!IS_ERR(spdif_priv->spbaclk)) 1686 clk_disable_unprepare(spdif_priv->spbaclk); 1687 clk_disable_unprepare(spdif_priv->coreclk); 1688 1689 return 0; 1690 } 1691 1692 static int fsl_spdif_runtime_resume(struct device *dev) 1693 { 1694 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1695 int ret; 1696 int i; 1697 1698 ret = clk_prepare_enable(spdif_priv->coreclk); 1699 if (ret) { 1700 dev_err(dev, "failed to enable core clock\n"); 1701 return ret; 1702 } 1703 1704 if (!IS_ERR(spdif_priv->spbaclk)) { 1705 ret = clk_prepare_enable(spdif_priv->spbaclk); 1706 if (ret) { 1707 dev_err(dev, "failed to enable spba clock\n"); 1708 goto disable_core_clk; 1709 } 1710 } 1711 1712 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1713 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1714 if (ret) 1715 goto disable_tx_clk; 1716 } 1717 1718 regcache_cache_only(spdif_priv->regmap, false); 1719 regcache_mark_dirty(spdif_priv->regmap); 1720 1721 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1722 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1723 spdif_priv->regcache_srpc); 1724 1725 ret = regcache_sync(spdif_priv->regmap); 1726 if (ret) 1727 goto disable_tx_clk; 1728 1729 return 0; 1730 1731 disable_tx_clk: 1732 for (i--; i >= 0; i--) 1733 clk_disable_unprepare(spdif_priv->txclk[i]); 1734 if (!IS_ERR(spdif_priv->spbaclk)) 1735 clk_disable_unprepare(spdif_priv->spbaclk); 1736 disable_core_clk: 1737 clk_disable_unprepare(spdif_priv->coreclk); 1738 1739 return ret; 1740 } 1741 #endif /* CONFIG_PM */ 1742 1743 static const struct dev_pm_ops fsl_spdif_pm = { 1744 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1745 pm_runtime_force_resume) 1746 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1747 NULL) 1748 }; 1749 1750 static const struct of_device_id fsl_spdif_dt_ids[] = { 1751 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1752 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1753 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1754 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1755 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1756 { .compatible = "fsl,imx8ulp-spdif", .data = &fsl_spdif_imx8ulp, }, 1757 {} 1758 }; 1759 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1760 1761 static struct platform_driver fsl_spdif_driver = { 1762 .driver = { 1763 .name = "fsl-spdif-dai", 1764 .of_match_table = fsl_spdif_dt_ids, 1765 .pm = &fsl_spdif_pm, 1766 }, 1767 .probe = fsl_spdif_probe, 1768 .remove = fsl_spdif_remove, 1769 }; 1770 1771 module_platform_driver(fsl_spdif_driver); 1772 1773 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1774 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1775 MODULE_LICENSE("GPL v2"); 1776 MODULE_ALIAS("platform:fsl-spdif-dai"); 1777