1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2013 Freescale Semiconductor, Inc. 6 // 7 // Based on stmp3xxx_spdif_dai.c 8 // Vladimir Barinov <vbarinov@embeddedalley.com> 9 // Copyright 2008 SigmaTel, Inc 10 // Copyright 2008 Embedded Alley Solutions, Inc 11 12 #include <linux/bitrev.h> 13 #include <linux/clk.h> 14 #include <linux/module.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/regmap.h> 19 #include <linux/pm_runtime.h> 20 21 #include <sound/asoundef.h> 22 #include <sound/dmaengine_pcm.h> 23 #include <sound/soc.h> 24 25 #include "fsl_spdif.h" 26 #include "imx-pcm.h" 27 28 #define FSL_SPDIF_TXFIFO_WML 0x8 29 #define FSL_SPDIF_RXFIFO_WML 0x8 30 31 #define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC) 32 #define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\ 33 INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\ 34 INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\ 35 INT_LOSS_LOCK | INT_DPLL_LOCKED) 36 37 #define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE) 38 39 /* Index list for the values that has if (DPLL Locked) condition */ 40 static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb }; 41 #define SRPC_NODPLL_START1 0x5 42 #define SRPC_NODPLL_START2 0xc 43 44 #define DEFAULT_RXCLK_SRC 1 45 46 /** 47 * struct fsl_spdif_soc_data: soc specific data 48 * 49 * @imx: for imx platform 50 * @shared_root_clock: flag of sharing a clock source with others; 51 * so the driver shouldn't set root clock rate 52 * @raw_capture_mode: if raw capture mode support 53 * @interrupts: interrupt number 54 * @tx_burst: tx maxburst size 55 * @rx_burst: rx maxburst size 56 * @tx_formats: tx supported data format 57 */ 58 struct fsl_spdif_soc_data { 59 bool imx; 60 bool shared_root_clock; 61 bool raw_capture_mode; 62 u32 interrupts; 63 u32 tx_burst; 64 u32 rx_burst; 65 u64 tx_formats; 66 }; 67 68 /* 69 * SPDIF control structure 70 * Defines channel status, subcode and Q sub 71 */ 72 struct spdif_mixer_control { 73 /* spinlock to access control data */ 74 spinlock_t ctl_lock; 75 76 /* IEC958 channel tx status bit */ 77 unsigned char ch_status[4]; 78 79 /* User bits */ 80 unsigned char subcode[2 * SPDIF_UBITS_SIZE]; 81 82 /* Q subcode part of user bits */ 83 unsigned char qsub[2 * SPDIF_QSUB_SIZE]; 84 85 /* Buffer offset for U/Q */ 86 u32 upos; 87 u32 qpos; 88 89 /* Ready buffer index of the two buffers */ 90 u32 ready_buf; 91 }; 92 93 /** 94 * struct fsl_spdif_priv - Freescale SPDIF private data 95 * @soc: SPDIF soc data 96 * @fsl_spdif_control: SPDIF control data 97 * @cpu_dai_drv: cpu dai driver 98 * @pdev: platform device pointer 99 * @regmap: regmap handler 100 * @dpll_locked: dpll lock flag 101 * @txrate: the best rates for playback 102 * @txclk_df: STC_TXCLK_DF dividers value for playback 103 * @sysclk_df: STC_SYSCLK_DF dividers value for playback 104 * @txclk_src: STC_TXCLK_SRC values for playback 105 * @rxclk_src: SRPC_CLKSRC_SEL values for capture 106 * @txclk: tx clock sources for playback 107 * @rxclk: rx clock sources for capture 108 * @coreclk: core clock for register access via DMA 109 * @sysclk: system clock for rx clock rate measurement 110 * @spbaclk: SPBA clock (optional, depending on SoC design) 111 * @dma_params_tx: DMA parameters for transmit channel 112 * @dma_params_rx: DMA parameters for receive channel 113 * @regcache_srpc: regcache for SRPC 114 */ 115 struct fsl_spdif_priv { 116 const struct fsl_spdif_soc_data *soc; 117 struct spdif_mixer_control fsl_spdif_control; 118 struct snd_soc_dai_driver cpu_dai_drv; 119 struct platform_device *pdev; 120 struct regmap *regmap; 121 bool dpll_locked; 122 u32 txrate[SPDIF_TXRATE_MAX]; 123 u8 txclk_df[SPDIF_TXRATE_MAX]; 124 u16 sysclk_df[SPDIF_TXRATE_MAX]; 125 u8 txclk_src[SPDIF_TXRATE_MAX]; 126 u8 rxclk_src; 127 struct clk *txclk[SPDIF_TXRATE_MAX]; 128 struct clk *rxclk; 129 struct clk *coreclk; 130 struct clk *sysclk; 131 struct clk *spbaclk; 132 struct snd_dmaengine_dai_dma_data dma_params_tx; 133 struct snd_dmaengine_dai_dma_data dma_params_rx; 134 /* regcache for SRPC */ 135 u32 regcache_srpc; 136 }; 137 138 static struct fsl_spdif_soc_data fsl_spdif_vf610 = { 139 .imx = false, 140 .shared_root_clock = false, 141 .raw_capture_mode = false, 142 .interrupts = 1, 143 .tx_burst = FSL_SPDIF_TXFIFO_WML, 144 .rx_burst = FSL_SPDIF_RXFIFO_WML, 145 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 146 }; 147 148 static struct fsl_spdif_soc_data fsl_spdif_imx35 = { 149 .imx = true, 150 .shared_root_clock = false, 151 .raw_capture_mode = false, 152 .interrupts = 1, 153 .tx_burst = FSL_SPDIF_TXFIFO_WML, 154 .rx_burst = FSL_SPDIF_RXFIFO_WML, 155 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 156 }; 157 158 static struct fsl_spdif_soc_data fsl_spdif_imx6sx = { 159 .imx = true, 160 .shared_root_clock = true, 161 .raw_capture_mode = false, 162 .interrupts = 1, 163 .tx_burst = FSL_SPDIF_TXFIFO_WML, 164 .rx_burst = FSL_SPDIF_RXFIFO_WML, 165 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 166 167 }; 168 169 static struct fsl_spdif_soc_data fsl_spdif_imx8qm = { 170 .imx = true, 171 .shared_root_clock = true, 172 .raw_capture_mode = false, 173 .interrupts = 2, 174 .tx_burst = 2, /* Applied for EDMA */ 175 .rx_burst = 2, /* Applied for EDMA */ 176 .tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */ 177 }; 178 179 static struct fsl_spdif_soc_data fsl_spdif_imx8mm = { 180 .imx = true, 181 .shared_root_clock = false, 182 .raw_capture_mode = true, 183 .interrupts = 1, 184 .tx_burst = FSL_SPDIF_TXFIFO_WML, 185 .rx_burst = FSL_SPDIF_RXFIFO_WML, 186 .tx_formats = FSL_SPDIF_FORMATS_PLAYBACK, 187 }; 188 189 /* Check if clk is a root clock that does not share clock source with others */ 190 static inline bool fsl_spdif_can_set_clk_rate(struct fsl_spdif_priv *spdif, int clk) 191 { 192 return (clk == STC_TXCLK_SPDIF_ROOT) && !spdif->soc->shared_root_clock; 193 } 194 195 /* DPLL locked and lock loss interrupt handler */ 196 static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv) 197 { 198 struct regmap *regmap = spdif_priv->regmap; 199 struct platform_device *pdev = spdif_priv->pdev; 200 u32 locked; 201 202 regmap_read(regmap, REG_SPDIF_SRPC, &locked); 203 locked &= SRPC_DPLL_LOCKED; 204 205 dev_dbg(&pdev->dev, "isr: Rx dpll %s \n", 206 locked ? "locked" : "loss lock"); 207 208 spdif_priv->dpll_locked = locked ? true : false; 209 } 210 211 /* Receiver found illegal symbol interrupt handler */ 212 static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv) 213 { 214 struct regmap *regmap = spdif_priv->regmap; 215 struct platform_device *pdev = spdif_priv->pdev; 216 217 dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n"); 218 219 /* Clear illegal symbol if DPLL unlocked since no audio stream */ 220 if (!spdif_priv->dpll_locked) 221 regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0); 222 } 223 224 /* U/Q Channel receive register full */ 225 static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name) 226 { 227 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 228 struct regmap *regmap = spdif_priv->regmap; 229 struct platform_device *pdev = spdif_priv->pdev; 230 u32 *pos, size, val, reg; 231 232 switch (name) { 233 case 'U': 234 pos = &ctrl->upos; 235 size = SPDIF_UBITS_SIZE; 236 reg = REG_SPDIF_SRU; 237 break; 238 case 'Q': 239 pos = &ctrl->qpos; 240 size = SPDIF_QSUB_SIZE; 241 reg = REG_SPDIF_SRQ; 242 break; 243 default: 244 dev_err(&pdev->dev, "unsupported channel name\n"); 245 return; 246 } 247 248 dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name); 249 250 if (*pos >= size * 2) { 251 *pos = 0; 252 } else if (unlikely((*pos % size) + 3 > size)) { 253 dev_err(&pdev->dev, "User bit receive buffer overflow\n"); 254 return; 255 } 256 257 regmap_read(regmap, reg, &val); 258 ctrl->subcode[*pos++] = val >> 16; 259 ctrl->subcode[*pos++] = val >> 8; 260 ctrl->subcode[*pos++] = val; 261 } 262 263 /* U/Q Channel sync found */ 264 static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv) 265 { 266 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 267 struct platform_device *pdev = spdif_priv->pdev; 268 269 dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n"); 270 271 /* U/Q buffer reset */ 272 if (ctrl->qpos == 0) 273 return; 274 275 /* Set ready to this buffer */ 276 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; 277 } 278 279 /* U/Q Channel framing error */ 280 static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv) 281 { 282 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 283 struct regmap *regmap = spdif_priv->regmap; 284 struct platform_device *pdev = spdif_priv->pdev; 285 u32 val; 286 287 dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n"); 288 289 /* Read U/Q data to clear the irq and do buffer reset */ 290 regmap_read(regmap, REG_SPDIF_SRU, &val); 291 regmap_read(regmap, REG_SPDIF_SRQ, &val); 292 293 /* Drop this U/Q buffer */ 294 ctrl->ready_buf = 0; 295 ctrl->upos = 0; 296 ctrl->qpos = 0; 297 } 298 299 /* Get spdif interrupt status and clear the interrupt */ 300 static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv) 301 { 302 struct regmap *regmap = spdif_priv->regmap; 303 u32 val, val2; 304 305 regmap_read(regmap, REG_SPDIF_SIS, &val); 306 regmap_read(regmap, REG_SPDIF_SIE, &val2); 307 308 regmap_write(regmap, REG_SPDIF_SIC, val & val2); 309 310 return val; 311 } 312 313 static irqreturn_t spdif_isr(int irq, void *devid) 314 { 315 struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid; 316 struct platform_device *pdev = spdif_priv->pdev; 317 u32 sis; 318 319 sis = spdif_intr_status_clear(spdif_priv); 320 321 if (sis & INT_DPLL_LOCKED) 322 spdif_irq_dpll_lock(spdif_priv); 323 324 if (sis & INT_TXFIFO_UNOV) 325 dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n"); 326 327 if (sis & INT_TXFIFO_RESYNC) 328 dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n"); 329 330 if (sis & INT_CNEW) 331 dev_dbg(&pdev->dev, "isr: cstatus new\n"); 332 333 if (sis & INT_VAL_NOGOOD) 334 dev_dbg(&pdev->dev, "isr: validity flag no good\n"); 335 336 if (sis & INT_SYM_ERR) 337 spdif_irq_sym_error(spdif_priv); 338 339 if (sis & INT_BIT_ERR) 340 dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n"); 341 342 if (sis & INT_URX_FUL) 343 spdif_irq_uqrx_full(spdif_priv, 'U'); 344 345 if (sis & INT_URX_OV) 346 dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n"); 347 348 if (sis & INT_QRX_FUL) 349 spdif_irq_uqrx_full(spdif_priv, 'Q'); 350 351 if (sis & INT_QRX_OV) 352 dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n"); 353 354 if (sis & INT_UQ_SYNC) 355 spdif_irq_uq_sync(spdif_priv); 356 357 if (sis & INT_UQ_ERR) 358 spdif_irq_uq_err(spdif_priv); 359 360 if (sis & INT_RXFIFO_UNOV) 361 dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n"); 362 363 if (sis & INT_RXFIFO_RESYNC) 364 dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n"); 365 366 if (sis & INT_LOSS_LOCK) 367 spdif_irq_dpll_lock(spdif_priv); 368 369 /* FIXME: Write Tx FIFO to clear TxEm */ 370 if (sis & INT_TX_EM) 371 dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n"); 372 373 /* FIXME: Read Rx FIFO to clear RxFIFOFul */ 374 if (sis & INT_RXFIFO_FUL) 375 dev_dbg(&pdev->dev, "isr: Rx FIFO full\n"); 376 377 return IRQ_HANDLED; 378 } 379 380 static int spdif_softreset(struct fsl_spdif_priv *spdif_priv) 381 { 382 struct regmap *regmap = spdif_priv->regmap; 383 u32 val, cycle = 1000; 384 385 regcache_cache_bypass(regmap, true); 386 387 regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET); 388 389 /* 390 * RESET bit would be cleared after finishing its reset procedure, 391 * which typically lasts 8 cycles. 1000 cycles will keep it safe. 392 */ 393 do { 394 regmap_read(regmap, REG_SPDIF_SCR, &val); 395 } while ((val & SCR_SOFT_RESET) && cycle--); 396 397 regcache_cache_bypass(regmap, false); 398 regcache_mark_dirty(regmap); 399 regcache_sync(regmap); 400 401 if (cycle) 402 return 0; 403 else 404 return -EBUSY; 405 } 406 407 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, 408 u8 mask, u8 cstatus) 409 { 410 ctrl->ch_status[3] &= ~mask; 411 ctrl->ch_status[3] |= cstatus & mask; 412 } 413 414 static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv) 415 { 416 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 417 struct regmap *regmap = spdif_priv->regmap; 418 struct platform_device *pdev = spdif_priv->pdev; 419 u32 ch_status; 420 421 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | 422 (bitrev8(ctrl->ch_status[1]) << 8) | 423 bitrev8(ctrl->ch_status[2]); 424 regmap_write(regmap, REG_SPDIF_STCSCH, ch_status); 425 426 dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status); 427 428 ch_status = bitrev8(ctrl->ch_status[3]) << 16; 429 regmap_write(regmap, REG_SPDIF_STCSCL, ch_status); 430 431 dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status); 432 } 433 434 /* Set SPDIF PhaseConfig register for rx clock */ 435 static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv, 436 enum spdif_gainsel gainsel, int dpll_locked) 437 { 438 struct regmap *regmap = spdif_priv->regmap; 439 u8 clksrc = spdif_priv->rxclk_src; 440 441 if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX) 442 return -EINVAL; 443 444 regmap_update_bits(regmap, REG_SPDIF_SRPC, 445 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 446 SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel)); 447 448 return 0; 449 } 450 451 static int spdif_set_sample_rate(struct snd_pcm_substream *substream, 452 int sample_rate) 453 { 454 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 455 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 456 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 457 struct regmap *regmap = spdif_priv->regmap; 458 struct platform_device *pdev = spdif_priv->pdev; 459 unsigned long csfs = 0; 460 u32 stc, mask, rate; 461 u16 sysclk_df; 462 u8 clk, txclk_df; 463 int ret; 464 465 switch (sample_rate) { 466 case 32000: 467 rate = SPDIF_TXRATE_32000; 468 csfs = IEC958_AES3_CON_FS_32000; 469 break; 470 case 44100: 471 rate = SPDIF_TXRATE_44100; 472 csfs = IEC958_AES3_CON_FS_44100; 473 break; 474 case 48000: 475 rate = SPDIF_TXRATE_48000; 476 csfs = IEC958_AES3_CON_FS_48000; 477 break; 478 case 88200: 479 rate = SPDIF_TXRATE_88200; 480 csfs = IEC958_AES3_CON_FS_88200; 481 break; 482 case 96000: 483 rate = SPDIF_TXRATE_96000; 484 csfs = IEC958_AES3_CON_FS_96000; 485 break; 486 case 176400: 487 rate = SPDIF_TXRATE_176400; 488 csfs = IEC958_AES3_CON_FS_176400; 489 break; 490 case 192000: 491 rate = SPDIF_TXRATE_192000; 492 csfs = IEC958_AES3_CON_FS_192000; 493 break; 494 default: 495 dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate); 496 return -EINVAL; 497 } 498 499 clk = spdif_priv->txclk_src[rate]; 500 if (clk >= STC_TXCLK_SRC_MAX) { 501 dev_err(&pdev->dev, "tx clock source is out of range\n"); 502 return -EINVAL; 503 } 504 505 txclk_df = spdif_priv->txclk_df[rate]; 506 if (txclk_df == 0) { 507 dev_err(&pdev->dev, "the txclk_df can't be zero\n"); 508 return -EINVAL; 509 } 510 511 sysclk_df = spdif_priv->sysclk_df[rate]; 512 513 if (!fsl_spdif_can_set_clk_rate(spdif_priv, clk)) 514 goto clk_set_bypass; 515 516 /* The S/PDIF block needs a clock of 64 * fs * txclk_df */ 517 ret = clk_set_rate(spdif_priv->txclk[rate], 518 64 * sample_rate * txclk_df); 519 if (ret) { 520 dev_err(&pdev->dev, "failed to set tx clock rate\n"); 521 return ret; 522 } 523 524 clk_set_bypass: 525 dev_dbg(&pdev->dev, "expected clock rate = %d\n", 526 (64 * sample_rate * txclk_df * sysclk_df)); 527 dev_dbg(&pdev->dev, "actual clock rate = %ld\n", 528 clk_get_rate(spdif_priv->txclk[rate])); 529 530 /* set fs field in consumer channel status */ 531 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); 532 533 /* select clock source and divisor */ 534 stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | 535 STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df); 536 mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | 537 STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK; 538 regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc); 539 540 dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n", 541 spdif_priv->txrate[rate], sample_rate); 542 543 return 0; 544 } 545 546 static int fsl_spdif_startup(struct snd_pcm_substream *substream, 547 struct snd_soc_dai *cpu_dai) 548 { 549 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 550 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 551 struct platform_device *pdev = spdif_priv->pdev; 552 struct regmap *regmap = spdif_priv->regmap; 553 u32 scr, mask; 554 int ret; 555 556 /* Reset module and interrupts only for first initialization */ 557 if (!snd_soc_dai_active(cpu_dai)) { 558 ret = spdif_softreset(spdif_priv); 559 if (ret) { 560 dev_err(&pdev->dev, "failed to soft reset\n"); 561 return ret; 562 } 563 564 /* Disable all the interrupts */ 565 regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0); 566 } 567 568 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 569 scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | 570 SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | 571 SCR_TXFIFO_FSEL_IF8; 572 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 573 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 574 SCR_TXFIFO_FSEL_MASK; 575 } else { 576 scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; 577 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 578 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 579 } 580 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 581 582 /* Power up SPDIF module */ 583 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); 584 585 return 0; 586 } 587 588 static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, 589 struct snd_soc_dai *cpu_dai) 590 { 591 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 592 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 593 struct regmap *regmap = spdif_priv->regmap; 594 u32 scr, mask; 595 596 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 597 scr = 0; 598 mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | 599 SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | 600 SCR_TXFIFO_FSEL_MASK; 601 } else { 602 scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO; 603 mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| 604 SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK; 605 } 606 regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr); 607 608 /* Power down SPDIF module only if tx&rx are both inactive */ 609 if (!snd_soc_dai_active(cpu_dai)) { 610 spdif_intr_status_clear(spdif_priv); 611 regmap_update_bits(regmap, REG_SPDIF_SCR, 612 SCR_LOW_POWER, SCR_LOW_POWER); 613 } 614 } 615 616 static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, 617 struct snd_pcm_hw_params *params, 618 struct snd_soc_dai *dai) 619 { 620 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 621 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 622 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 623 struct platform_device *pdev = spdif_priv->pdev; 624 u32 sample_rate = params_rate(params); 625 int ret = 0; 626 627 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 628 ret = spdif_set_sample_rate(substream, sample_rate); 629 if (ret) { 630 dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", 631 __func__, sample_rate); 632 return ret; 633 } 634 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, 635 IEC958_AES3_CON_CLOCK_1000PPM); 636 spdif_write_channel_status(spdif_priv); 637 } else { 638 /* Setup rx clock source */ 639 ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1); 640 } 641 642 return ret; 643 } 644 645 static int fsl_spdif_trigger(struct snd_pcm_substream *substream, 646 int cmd, struct snd_soc_dai *dai) 647 { 648 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 649 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0)); 650 struct regmap *regmap = spdif_priv->regmap; 651 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 652 u32 intr = SIE_INTR_FOR(tx); 653 u32 dmaen = SCR_DMA_xX_EN(tx); 654 655 switch (cmd) { 656 case SNDRV_PCM_TRIGGER_START: 657 case SNDRV_PCM_TRIGGER_RESUME: 658 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 659 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr); 660 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen); 661 break; 662 case SNDRV_PCM_TRIGGER_STOP: 663 case SNDRV_PCM_TRIGGER_SUSPEND: 664 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 665 regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); 666 regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); 667 break; 668 default: 669 return -EINVAL; 670 } 671 672 return 0; 673 } 674 675 static const struct snd_soc_dai_ops fsl_spdif_dai_ops = { 676 .startup = fsl_spdif_startup, 677 .hw_params = fsl_spdif_hw_params, 678 .trigger = fsl_spdif_trigger, 679 .shutdown = fsl_spdif_shutdown, 680 }; 681 682 683 /* 684 * FSL SPDIF IEC958 controller(mixer) functions 685 * 686 * Channel status get/put control 687 * User bit value get/put control 688 * Valid bit value get control 689 * DPLL lock status get control 690 * User bit sync mode selection control 691 */ 692 693 static int fsl_spdif_info(struct snd_kcontrol *kcontrol, 694 struct snd_ctl_elem_info *uinfo) 695 { 696 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 697 uinfo->count = 1; 698 699 return 0; 700 } 701 702 static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol, 703 struct snd_ctl_elem_value *uvalue) 704 { 705 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 706 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 707 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 708 709 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; 710 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; 711 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; 712 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; 713 714 return 0; 715 } 716 717 static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol, 718 struct snd_ctl_elem_value *uvalue) 719 { 720 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 721 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 722 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 723 724 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; 725 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; 726 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; 727 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; 728 729 spdif_write_channel_status(spdif_priv); 730 731 return 0; 732 } 733 734 /* Get channel status from SPDIF_RX_CCHAN register */ 735 static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol, 736 struct snd_ctl_elem_value *ucontrol) 737 { 738 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 739 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 740 struct regmap *regmap = spdif_priv->regmap; 741 u32 cstatus, val; 742 743 regmap_read(regmap, REG_SPDIF_SIS, &val); 744 if (!(val & INT_CNEW)) 745 return -EAGAIN; 746 747 regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus); 748 ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF; 749 ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF; 750 ucontrol->value.iec958.status[2] = cstatus & 0xFF; 751 752 regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus); 753 ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF; 754 ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF; 755 ucontrol->value.iec958.status[5] = cstatus & 0xFF; 756 757 /* Clear intr */ 758 regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW); 759 760 return 0; 761 } 762 763 /* 764 * Get User bits (subcode) from chip value which readed out 765 * in UChannel register. 766 */ 767 static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol, 768 struct snd_ctl_elem_value *ucontrol) 769 { 770 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 771 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 772 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 773 unsigned long flags; 774 int ret = -EAGAIN; 775 776 spin_lock_irqsave(&ctrl->ctl_lock, flags); 777 if (ctrl->ready_buf) { 778 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; 779 memcpy(&ucontrol->value.iec958.subcode[0], 780 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); 781 ret = 0; 782 } 783 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 784 785 return ret; 786 } 787 788 /* Q-subcode information. The byte size is SPDIF_UBITS_SIZE/8 */ 789 static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol, 790 struct snd_ctl_elem_info *uinfo) 791 { 792 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 793 uinfo->count = SPDIF_QSUB_SIZE; 794 795 return 0; 796 } 797 798 /* Get Q subcode from chip value which readed out in QChannel register */ 799 static int fsl_spdif_qget(struct snd_kcontrol *kcontrol, 800 struct snd_ctl_elem_value *ucontrol) 801 { 802 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 803 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 804 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; 805 unsigned long flags; 806 int ret = -EAGAIN; 807 808 spin_lock_irqsave(&ctrl->ctl_lock, flags); 809 if (ctrl->ready_buf) { 810 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; 811 memcpy(&ucontrol->value.bytes.data[0], 812 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); 813 ret = 0; 814 } 815 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); 816 817 return ret; 818 } 819 820 /* Get valid good bit from interrupt status register */ 821 static int fsl_spdif_rx_vbit_get(struct snd_kcontrol *kcontrol, 822 struct snd_ctl_elem_value *ucontrol) 823 { 824 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 825 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 826 struct regmap *regmap = spdif_priv->regmap; 827 u32 val; 828 829 regmap_read(regmap, REG_SPDIF_SIS, &val); 830 ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0; 831 regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD); 832 833 return 0; 834 } 835 836 static int fsl_spdif_tx_vbit_get(struct snd_kcontrol *kcontrol, 837 struct snd_ctl_elem_value *ucontrol) 838 { 839 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 840 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 841 struct regmap *regmap = spdif_priv->regmap; 842 u32 val; 843 844 regmap_read(regmap, REG_SPDIF_SCR, &val); 845 val = (val & SCR_VAL_MASK) >> SCR_VAL_OFFSET; 846 val = 1 - val; 847 ucontrol->value.integer.value[0] = val; 848 849 return 0; 850 } 851 852 static int fsl_spdif_tx_vbit_put(struct snd_kcontrol *kcontrol, 853 struct snd_ctl_elem_value *ucontrol) 854 { 855 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 856 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 857 struct regmap *regmap = spdif_priv->regmap; 858 u32 val = (1 - ucontrol->value.integer.value[0]) << SCR_VAL_OFFSET; 859 860 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK, val); 861 862 return 0; 863 } 864 865 static int fsl_spdif_rx_rcm_get(struct snd_kcontrol *kcontrol, 866 struct snd_ctl_elem_value *ucontrol) 867 { 868 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 869 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 870 struct regmap *regmap = spdif_priv->regmap; 871 u32 val; 872 873 regmap_read(regmap, REG_SPDIF_SCR, &val); 874 val = (val & SCR_RAW_CAPTURE_MODE) ? 1 : 0; 875 ucontrol->value.integer.value[0] = val; 876 877 return 0; 878 } 879 880 static int fsl_spdif_rx_rcm_put(struct snd_kcontrol *kcontrol, 881 struct snd_ctl_elem_value *ucontrol) 882 { 883 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 884 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 885 struct regmap *regmap = spdif_priv->regmap; 886 u32 val = (ucontrol->value.integer.value[0] ? SCR_RAW_CAPTURE_MODE : 0); 887 888 if (val) 889 cpu_dai->driver->capture.formats |= SNDRV_PCM_FMTBIT_S32_LE; 890 else 891 cpu_dai->driver->capture.formats &= ~SNDRV_PCM_FMTBIT_S32_LE; 892 893 regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_RAW_CAPTURE_MODE, val); 894 895 return 0; 896 } 897 898 /* DPLL lock information */ 899 static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol, 900 struct snd_ctl_elem_info *uinfo) 901 { 902 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 903 uinfo->count = 1; 904 uinfo->value.integer.min = 16000; 905 uinfo->value.integer.max = 192000; 906 907 return 0; 908 } 909 910 static u32 gainsel_multi[GAINSEL_MULTI_MAX] = { 911 24, 16, 12, 8, 6, 4, 3, 912 }; 913 914 /* Get RX data clock rate given the SPDIF bus_clk */ 915 static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv, 916 enum spdif_gainsel gainsel) 917 { 918 struct regmap *regmap = spdif_priv->regmap; 919 struct platform_device *pdev = spdif_priv->pdev; 920 u64 tmpval64, busclk_freq = 0; 921 u32 freqmeas, phaseconf; 922 u8 clksrc; 923 924 regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas); 925 regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf); 926 927 clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf; 928 929 /* Get bus clock from system */ 930 if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) 931 busclk_freq = clk_get_rate(spdif_priv->sysclk); 932 933 /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */ 934 tmpval64 = (u64) busclk_freq * freqmeas; 935 do_div(tmpval64, gainsel_multi[gainsel] * 1024); 936 do_div(tmpval64, 128 * 1024); 937 938 dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas); 939 dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq); 940 dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64); 941 942 return (int)tmpval64; 943 } 944 945 /* 946 * Get DPLL lock or not info from stable interrupt status register. 947 * User application must use this control to get locked, 948 * then can do next PCM operation 949 */ 950 static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol, 951 struct snd_ctl_elem_value *ucontrol) 952 { 953 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 954 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 955 int rate = 0; 956 957 if (spdif_priv->dpll_locked) 958 rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL); 959 960 ucontrol->value.integer.value[0] = rate; 961 962 return 0; 963 } 964 965 /* 966 * User bit sync mode: 967 * 1 CD User channel subcode 968 * 0 Non-CD data 969 */ 970 static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol, 971 struct snd_ctl_elem_value *ucontrol) 972 { 973 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 974 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 975 struct regmap *regmap = spdif_priv->regmap; 976 u32 val; 977 978 regmap_read(regmap, REG_SPDIF_SRCD, &val); 979 ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0; 980 981 return 0; 982 } 983 984 /* 985 * User bit sync mode: 986 * 1 CD User channel subcode 987 * 0 Non-CD data 988 */ 989 static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol, 990 struct snd_ctl_elem_value *ucontrol) 991 { 992 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 993 struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai); 994 struct regmap *regmap = spdif_priv->regmap; 995 u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET; 996 997 regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val); 998 999 return 0; 1000 } 1001 1002 /* FSL SPDIF IEC958 controller defines */ 1003 static struct snd_kcontrol_new fsl_spdif_ctrls[] = { 1004 /* Status cchanel controller */ 1005 { 1006 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1007 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1008 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1009 SNDRV_CTL_ELEM_ACCESS_WRITE | 1010 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1011 .info = fsl_spdif_info, 1012 .get = fsl_spdif_pb_get, 1013 .put = fsl_spdif_pb_put, 1014 }, 1015 { 1016 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1017 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT), 1018 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1019 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1020 .info = fsl_spdif_info, 1021 .get = fsl_spdif_capture_get, 1022 }, 1023 /* User bits controller */ 1024 { 1025 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1026 .name = "IEC958 Subcode Capture Default", 1027 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1028 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1029 .info = fsl_spdif_info, 1030 .get = fsl_spdif_subcode_get, 1031 }, 1032 { 1033 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1034 .name = "IEC958 Q-subcode Capture Default", 1035 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1036 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1037 .info = fsl_spdif_qinfo, 1038 .get = fsl_spdif_qget, 1039 }, 1040 /* Valid bit error controller */ 1041 { 1042 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1043 .name = "IEC958 RX V-Bit Errors", 1044 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1045 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1046 .info = snd_ctl_boolean_mono_info, 1047 .get = fsl_spdif_rx_vbit_get, 1048 }, 1049 { 1050 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1051 .name = "IEC958 TX V-Bit", 1052 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1053 SNDRV_CTL_ELEM_ACCESS_WRITE | 1054 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1055 .info = snd_ctl_boolean_mono_info, 1056 .get = fsl_spdif_tx_vbit_get, 1057 .put = fsl_spdif_tx_vbit_put, 1058 }, 1059 /* DPLL lock info get controller */ 1060 { 1061 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1062 .name = "RX Sample Rate", 1063 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1064 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1065 .info = fsl_spdif_rxrate_info, 1066 .get = fsl_spdif_rxrate_get, 1067 }, 1068 /* User bit sync mode set/get controller */ 1069 { 1070 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1071 .name = "IEC958 USyncMode CDText", 1072 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1073 SNDRV_CTL_ELEM_ACCESS_WRITE | 1074 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1075 .info = snd_ctl_boolean_mono_info, 1076 .get = fsl_spdif_usync_get, 1077 .put = fsl_spdif_usync_put, 1078 }, 1079 }; 1080 1081 static struct snd_kcontrol_new fsl_spdif_ctrls_rcm[] = { 1082 { 1083 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1084 .name = "IEC958 Raw Capture Mode", 1085 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1086 SNDRV_CTL_ELEM_ACCESS_WRITE | 1087 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1088 .info = snd_ctl_boolean_mono_info, 1089 .get = fsl_spdif_rx_rcm_get, 1090 .put = fsl_spdif_rx_rcm_put, 1091 }, 1092 }; 1093 1094 static int fsl_spdif_dai_probe(struct snd_soc_dai *dai) 1095 { 1096 struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai); 1097 1098 snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx, 1099 &spdif_private->dma_params_rx); 1100 1101 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls)); 1102 1103 if (spdif_private->soc->raw_capture_mode) 1104 snd_soc_add_dai_controls(dai, fsl_spdif_ctrls_rcm, 1105 ARRAY_SIZE(fsl_spdif_ctrls_rcm)); 1106 1107 /*Clear the val bit for Tx*/ 1108 regmap_update_bits(spdif_private->regmap, REG_SPDIF_SCR, 1109 SCR_VAL_MASK, SCR_VAL_CLEAR); 1110 1111 return 0; 1112 } 1113 1114 static struct snd_soc_dai_driver fsl_spdif_dai = { 1115 .probe = &fsl_spdif_dai_probe, 1116 .playback = { 1117 .stream_name = "CPU-Playback", 1118 .channels_min = 2, 1119 .channels_max = 2, 1120 .rates = FSL_SPDIF_RATES_PLAYBACK, 1121 .formats = FSL_SPDIF_FORMATS_PLAYBACK, 1122 }, 1123 .capture = { 1124 .stream_name = "CPU-Capture", 1125 .channels_min = 2, 1126 .channels_max = 2, 1127 .rates = FSL_SPDIF_RATES_CAPTURE, 1128 .formats = FSL_SPDIF_FORMATS_CAPTURE, 1129 }, 1130 .ops = &fsl_spdif_dai_ops, 1131 }; 1132 1133 static const struct snd_soc_component_driver fsl_spdif_component = { 1134 .name = "fsl-spdif", 1135 }; 1136 1137 /* FSL SPDIF REGMAP */ 1138 static const struct reg_default fsl_spdif_reg_defaults[] = { 1139 {REG_SPDIF_SCR, 0x00000400}, 1140 {REG_SPDIF_SRCD, 0x00000000}, 1141 {REG_SPDIF_SIE, 0x00000000}, 1142 {REG_SPDIF_STL, 0x00000000}, 1143 {REG_SPDIF_STR, 0x00000000}, 1144 {REG_SPDIF_STCSCH, 0x00000000}, 1145 {REG_SPDIF_STCSCL, 0x00000000}, 1146 {REG_SPDIF_STC, 0x00020f00}, 1147 }; 1148 1149 static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg) 1150 { 1151 switch (reg) { 1152 case REG_SPDIF_SCR: 1153 case REG_SPDIF_SRCD: 1154 case REG_SPDIF_SRPC: 1155 case REG_SPDIF_SIE: 1156 case REG_SPDIF_SIS: 1157 case REG_SPDIF_SRL: 1158 case REG_SPDIF_SRR: 1159 case REG_SPDIF_SRCSH: 1160 case REG_SPDIF_SRCSL: 1161 case REG_SPDIF_SRU: 1162 case REG_SPDIF_SRQ: 1163 case REG_SPDIF_STCSCH: 1164 case REG_SPDIF_STCSCL: 1165 case REG_SPDIF_SRFM: 1166 case REG_SPDIF_STC: 1167 return true; 1168 default: 1169 return false; 1170 } 1171 } 1172 1173 static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg) 1174 { 1175 switch (reg) { 1176 case REG_SPDIF_SRPC: 1177 case REG_SPDIF_SIS: 1178 case REG_SPDIF_SRL: 1179 case REG_SPDIF_SRR: 1180 case REG_SPDIF_SRCSH: 1181 case REG_SPDIF_SRCSL: 1182 case REG_SPDIF_SRU: 1183 case REG_SPDIF_SRQ: 1184 case REG_SPDIF_SRFM: 1185 return true; 1186 default: 1187 return false; 1188 } 1189 } 1190 1191 static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg) 1192 { 1193 switch (reg) { 1194 case REG_SPDIF_SCR: 1195 case REG_SPDIF_SRCD: 1196 case REG_SPDIF_SRPC: 1197 case REG_SPDIF_SIE: 1198 case REG_SPDIF_SIC: 1199 case REG_SPDIF_STL: 1200 case REG_SPDIF_STR: 1201 case REG_SPDIF_STCSCH: 1202 case REG_SPDIF_STCSCL: 1203 case REG_SPDIF_STC: 1204 return true; 1205 default: 1206 return false; 1207 } 1208 } 1209 1210 static const struct regmap_config fsl_spdif_regmap_config = { 1211 .reg_bits = 32, 1212 .reg_stride = 4, 1213 .val_bits = 32, 1214 1215 .max_register = REG_SPDIF_STC, 1216 .reg_defaults = fsl_spdif_reg_defaults, 1217 .num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults), 1218 .readable_reg = fsl_spdif_readable_reg, 1219 .volatile_reg = fsl_spdif_volatile_reg, 1220 .writeable_reg = fsl_spdif_writeable_reg, 1221 .cache_type = REGCACHE_FLAT, 1222 }; 1223 1224 static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv, 1225 struct clk *clk, u64 savesub, 1226 enum spdif_txrate index, bool round) 1227 { 1228 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1229 192000, }; 1230 bool is_sysclk = clk_is_match(clk, spdif_priv->sysclk); 1231 u64 rate_ideal, rate_actual, sub; 1232 u32 arate; 1233 u16 sysclk_dfmin, sysclk_dfmax, sysclk_df; 1234 u8 txclk_df; 1235 1236 /* The sysclk has an extra divisor [2, 512] */ 1237 sysclk_dfmin = is_sysclk ? 2 : 1; 1238 sysclk_dfmax = is_sysclk ? 512 : 1; 1239 1240 for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) { 1241 for (txclk_df = 1; txclk_df <= 128; txclk_df++) { 1242 rate_ideal = rate[index] * txclk_df * 64ULL; 1243 if (round) 1244 rate_actual = clk_round_rate(clk, rate_ideal); 1245 else 1246 rate_actual = clk_get_rate(clk); 1247 1248 arate = rate_actual / 64; 1249 arate /= txclk_df * sysclk_df; 1250 1251 if (arate == rate[index]) { 1252 /* We are lucky */ 1253 savesub = 0; 1254 spdif_priv->txclk_df[index] = txclk_df; 1255 spdif_priv->sysclk_df[index] = sysclk_df; 1256 spdif_priv->txrate[index] = arate; 1257 goto out; 1258 } else if (arate / rate[index] == 1) { 1259 /* A little bigger than expect */ 1260 sub = (u64)(arate - rate[index]) * 100000; 1261 do_div(sub, rate[index]); 1262 if (sub >= savesub) 1263 continue; 1264 savesub = sub; 1265 spdif_priv->txclk_df[index] = txclk_df; 1266 spdif_priv->sysclk_df[index] = sysclk_df; 1267 spdif_priv->txrate[index] = arate; 1268 } else if (rate[index] / arate == 1) { 1269 /* A little smaller than expect */ 1270 sub = (u64)(rate[index] - arate) * 100000; 1271 do_div(sub, rate[index]); 1272 if (sub >= savesub) 1273 continue; 1274 savesub = sub; 1275 spdif_priv->txclk_df[index] = txclk_df; 1276 spdif_priv->sysclk_df[index] = sysclk_df; 1277 spdif_priv->txrate[index] = arate; 1278 } 1279 } 1280 } 1281 1282 out: 1283 return savesub; 1284 } 1285 1286 static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, 1287 enum spdif_txrate index) 1288 { 1289 static const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 1290 192000, }; 1291 struct platform_device *pdev = spdif_priv->pdev; 1292 struct device *dev = &pdev->dev; 1293 u64 savesub = 100000, ret; 1294 struct clk *clk; 1295 char tmp[16]; 1296 int i; 1297 1298 for (i = 0; i < STC_TXCLK_SRC_MAX; i++) { 1299 sprintf(tmp, "rxtx%d", i); 1300 clk = devm_clk_get(dev, tmp); 1301 if (IS_ERR(clk)) { 1302 dev_err(dev, "no rxtx%d clock in devicetree\n", i); 1303 return PTR_ERR(clk); 1304 } 1305 if (!clk_get_rate(clk)) 1306 continue; 1307 1308 ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index, 1309 fsl_spdif_can_set_clk_rate(spdif_priv, i)); 1310 if (savesub == ret) 1311 continue; 1312 1313 savesub = ret; 1314 spdif_priv->txclk[index] = clk; 1315 spdif_priv->txclk_src[index] = i; 1316 1317 /* To quick catch a divisor, we allow a 0.1% deviation */ 1318 if (savesub < 100) 1319 break; 1320 } 1321 1322 dev_dbg(dev, "use rxtx%d as tx clock source for %dHz sample rate\n", 1323 spdif_priv->txclk_src[index], rate[index]); 1324 dev_dbg(dev, "use txclk df %d for %dHz sample rate\n", 1325 spdif_priv->txclk_df[index], rate[index]); 1326 if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk)) 1327 dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n", 1328 spdif_priv->sysclk_df[index], rate[index]); 1329 dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n", 1330 rate[index], spdif_priv->txrate[index]); 1331 1332 return 0; 1333 } 1334 1335 static int fsl_spdif_probe(struct platform_device *pdev) 1336 { 1337 struct fsl_spdif_priv *spdif_priv; 1338 struct spdif_mixer_control *ctrl; 1339 struct resource *res; 1340 void __iomem *regs; 1341 int irq, ret, i; 1342 1343 spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL); 1344 if (!spdif_priv) 1345 return -ENOMEM; 1346 1347 spdif_priv->pdev = pdev; 1348 1349 spdif_priv->soc = of_device_get_match_data(&pdev->dev); 1350 1351 /* Initialize this copy of the CPU DAI driver structure */ 1352 memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai)); 1353 spdif_priv->cpu_dai_drv.name = dev_name(&pdev->dev); 1354 spdif_priv->cpu_dai_drv.playback.formats = 1355 spdif_priv->soc->tx_formats; 1356 1357 /* Get the addresses and IRQ */ 1358 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1359 if (IS_ERR(regs)) 1360 return PTR_ERR(regs); 1361 1362 spdif_priv->regmap = devm_regmap_init_mmio(&pdev->dev, regs, &fsl_spdif_regmap_config); 1363 if (IS_ERR(spdif_priv->regmap)) { 1364 dev_err(&pdev->dev, "regmap init failed\n"); 1365 return PTR_ERR(spdif_priv->regmap); 1366 } 1367 1368 for (i = 0; i < spdif_priv->soc->interrupts; i++) { 1369 irq = platform_get_irq(pdev, i); 1370 if (irq < 0) 1371 return irq; 1372 1373 ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0, 1374 dev_name(&pdev->dev), spdif_priv); 1375 if (ret) { 1376 dev_err(&pdev->dev, "could not claim irq %u\n", irq); 1377 return ret; 1378 } 1379 } 1380 1381 /* Get system clock for rx clock rate calculation */ 1382 spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5"); 1383 if (IS_ERR(spdif_priv->sysclk)) { 1384 dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n"); 1385 return PTR_ERR(spdif_priv->sysclk); 1386 } 1387 1388 /* Get core clock for data register access via DMA */ 1389 spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 1390 if (IS_ERR(spdif_priv->coreclk)) { 1391 dev_err(&pdev->dev, "no core clock in devicetree\n"); 1392 return PTR_ERR(spdif_priv->coreclk); 1393 } 1394 1395 spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 1396 if (IS_ERR(spdif_priv->spbaclk)) 1397 dev_warn(&pdev->dev, "no spba clock in devicetree\n"); 1398 1399 /* Select clock source for rx/tx clock */ 1400 spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); 1401 if (IS_ERR(spdif_priv->rxclk)) { 1402 dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n"); 1403 return PTR_ERR(spdif_priv->rxclk); 1404 } 1405 spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC; 1406 1407 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1408 ret = fsl_spdif_probe_txclk(spdif_priv, i); 1409 if (ret) 1410 return ret; 1411 } 1412 1413 /* Initial spinlock for control data */ 1414 ctrl = &spdif_priv->fsl_spdif_control; 1415 spin_lock_init(&ctrl->ctl_lock); 1416 1417 /* Init tx channel status default value */ 1418 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | 1419 IEC958_AES0_CON_EMPHASIS_5015; 1420 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; 1421 ctrl->ch_status[2] = 0x00; 1422 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | 1423 IEC958_AES3_CON_CLOCK_1000PPM; 1424 1425 spdif_priv->dpll_locked = false; 1426 1427 spdif_priv->dma_params_tx.maxburst = spdif_priv->soc->tx_burst; 1428 spdif_priv->dma_params_rx.maxburst = spdif_priv->soc->rx_burst; 1429 spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL; 1430 spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL; 1431 1432 /* Register with ASoC */ 1433 dev_set_drvdata(&pdev->dev, spdif_priv); 1434 pm_runtime_enable(&pdev->dev); 1435 regcache_cache_only(spdif_priv->regmap, true); 1436 1437 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_spdif_component, 1438 &spdif_priv->cpu_dai_drv, 1); 1439 if (ret) { 1440 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1441 goto err_pm_disable; 1442 } 1443 1444 ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE); 1445 if (ret) { 1446 dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n"); 1447 goto err_pm_disable; 1448 } 1449 1450 return ret; 1451 1452 err_pm_disable: 1453 pm_runtime_disable(&pdev->dev); 1454 return ret; 1455 } 1456 1457 static int fsl_spdif_remove(struct platform_device *pdev) 1458 { 1459 pm_runtime_disable(&pdev->dev); 1460 1461 return 0; 1462 } 1463 1464 #ifdef CONFIG_PM 1465 static int fsl_spdif_runtime_suspend(struct device *dev) 1466 { 1467 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1468 int i; 1469 1470 /* Disable all the interrupts */ 1471 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SIE, 0xffffff, 0); 1472 1473 regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC, 1474 &spdif_priv->regcache_srpc); 1475 regcache_cache_only(spdif_priv->regmap, true); 1476 1477 clk_disable_unprepare(spdif_priv->rxclk); 1478 1479 for (i = 0; i < SPDIF_TXRATE_MAX; i++) 1480 clk_disable_unprepare(spdif_priv->txclk[i]); 1481 1482 if (!IS_ERR(spdif_priv->spbaclk)) 1483 clk_disable_unprepare(spdif_priv->spbaclk); 1484 clk_disable_unprepare(spdif_priv->coreclk); 1485 1486 return 0; 1487 } 1488 1489 static int fsl_spdif_runtime_resume(struct device *dev) 1490 { 1491 struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev); 1492 int ret; 1493 int i; 1494 1495 ret = clk_prepare_enable(spdif_priv->coreclk); 1496 if (ret) { 1497 dev_err(dev, "failed to enable core clock\n"); 1498 return ret; 1499 } 1500 1501 if (!IS_ERR(spdif_priv->spbaclk)) { 1502 ret = clk_prepare_enable(spdif_priv->spbaclk); 1503 if (ret) { 1504 dev_err(dev, "failed to enable spba clock\n"); 1505 goto disable_core_clk; 1506 } 1507 } 1508 1509 for (i = 0; i < SPDIF_TXRATE_MAX; i++) { 1510 ret = clk_prepare_enable(spdif_priv->txclk[i]); 1511 if (ret) 1512 goto disable_tx_clk; 1513 } 1514 1515 ret = clk_prepare_enable(spdif_priv->rxclk); 1516 if (ret) 1517 goto disable_tx_clk; 1518 1519 regcache_cache_only(spdif_priv->regmap, false); 1520 regcache_mark_dirty(spdif_priv->regmap); 1521 1522 regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC, 1523 SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK, 1524 spdif_priv->regcache_srpc); 1525 1526 ret = regcache_sync(spdif_priv->regmap); 1527 if (ret) 1528 goto disable_rx_clk; 1529 1530 return 0; 1531 1532 disable_rx_clk: 1533 clk_disable_unprepare(spdif_priv->rxclk); 1534 disable_tx_clk: 1535 for (i--; i >= 0; i--) 1536 clk_disable_unprepare(spdif_priv->txclk[i]); 1537 if (!IS_ERR(spdif_priv->spbaclk)) 1538 clk_disable_unprepare(spdif_priv->spbaclk); 1539 disable_core_clk: 1540 clk_disable_unprepare(spdif_priv->coreclk); 1541 1542 return ret; 1543 } 1544 #endif /* CONFIG_PM */ 1545 1546 static const struct dev_pm_ops fsl_spdif_pm = { 1547 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1548 pm_runtime_force_resume) 1549 SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend, fsl_spdif_runtime_resume, 1550 NULL) 1551 }; 1552 1553 static const struct of_device_id fsl_spdif_dt_ids[] = { 1554 { .compatible = "fsl,imx35-spdif", .data = &fsl_spdif_imx35, }, 1555 { .compatible = "fsl,vf610-spdif", .data = &fsl_spdif_vf610, }, 1556 { .compatible = "fsl,imx6sx-spdif", .data = &fsl_spdif_imx6sx, }, 1557 { .compatible = "fsl,imx8qm-spdif", .data = &fsl_spdif_imx8qm, }, 1558 { .compatible = "fsl,imx8mm-spdif", .data = &fsl_spdif_imx8mm, }, 1559 {} 1560 }; 1561 MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids); 1562 1563 static struct platform_driver fsl_spdif_driver = { 1564 .driver = { 1565 .name = "fsl-spdif-dai", 1566 .of_match_table = fsl_spdif_dt_ids, 1567 .pm = &fsl_spdif_pm, 1568 }, 1569 .probe = fsl_spdif_probe, 1570 .remove = fsl_spdif_remove, 1571 }; 1572 1573 module_platform_driver(fsl_spdif_driver); 1574 1575 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1576 MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver"); 1577 MODULE_LICENSE("GPL v2"); 1578 MODULE_ALIAS("platform:fsl-spdif-dai"); 1579