1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver. 4 // 5 // Copyright 2012-2015 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dmaengine.h> 10 #include <linux/module.h> 11 #include <linux/of_address.h> 12 #include <linux/of_device.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/pm_qos.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/time.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 24 25 #include "fsl_sai.h" 26 #include "fsl_utils.h" 27 #include "imx-pcm.h" 28 29 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ 30 FSL_SAI_CSR_FEIE) 31 32 static const unsigned int fsl_sai_rates[] = { 33 8000, 11025, 12000, 16000, 22050, 34 24000, 32000, 44100, 48000, 64000, 35 88200, 96000, 176400, 192000, 352800, 36 384000, 705600, 768000, 1411200, 2822400, 37 }; 38 39 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { 40 .count = ARRAY_SIZE(fsl_sai_rates), 41 .list = fsl_sai_rates, 42 }; 43 44 /** 45 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream 46 * 47 * SAI supports synchronous mode using bit/frame clocks of either Transmitter's 48 * or Receiver's for both streams. This function is used to check if clocks of 49 * the stream's are synced by the opposite stream. 50 * 51 * @sai: SAI context 52 * @dir: stream direction 53 */ 54 static inline bool fsl_sai_dir_is_synced(struct fsl_sai *sai, int dir) 55 { 56 int adir = (dir == TX) ? RX : TX; 57 58 /* current dir in async mode while opposite dir in sync mode */ 59 return !sai->synchronous[dir] && sai->synchronous[adir]; 60 } 61 62 static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u32 bclk) 63 { 64 struct pinctrl_state *state = NULL; 65 66 if (sai->is_pdm_mode) { 67 /* DSD512@44.1kHz, DSD512@48kHz */ 68 if (bclk >= 22579200) 69 state = pinctrl_lookup_state(sai->pinctrl, "dsd512"); 70 71 /* Get default DSD state */ 72 if (IS_ERR_OR_NULL(state)) 73 state = pinctrl_lookup_state(sai->pinctrl, "dsd"); 74 } else { 75 /* 706k32b2c, 768k32b2c, etc */ 76 if (bclk >= 45158400) 77 state = pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); 78 } 79 80 /* Get default state */ 81 if (IS_ERR_OR_NULL(state)) 82 state = pinctrl_lookup_state(sai->pinctrl, "default"); 83 84 return state; 85 } 86 87 static irqreturn_t fsl_sai_isr(int irq, void *devid) 88 { 89 struct fsl_sai *sai = (struct fsl_sai *)devid; 90 unsigned int ofs = sai->soc_data->reg_offset; 91 struct device *dev = &sai->pdev->dev; 92 u32 flags, xcsr, mask; 93 irqreturn_t iret = IRQ_NONE; 94 95 /* 96 * Both IRQ status bits and IRQ mask bits are in the xCSR but 97 * different shifts. And we here create a mask only for those 98 * IRQs that we activated. 99 */ 100 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; 101 102 /* Tx IRQ */ 103 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr); 104 flags = xcsr & mask; 105 106 if (flags) 107 iret = IRQ_HANDLED; 108 else 109 goto irq_rx; 110 111 if (flags & FSL_SAI_CSR_WSF) 112 dev_dbg(dev, "isr: Start of Tx word detected\n"); 113 114 if (flags & FSL_SAI_CSR_SEF) 115 dev_dbg(dev, "isr: Tx Frame sync error detected\n"); 116 117 if (flags & FSL_SAI_CSR_FEF) 118 dev_dbg(dev, "isr: Transmit underrun detected\n"); 119 120 if (flags & FSL_SAI_CSR_FWF) 121 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); 122 123 if (flags & FSL_SAI_CSR_FRF) 124 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); 125 126 flags &= FSL_SAI_CSR_xF_W_MASK; 127 xcsr &= ~FSL_SAI_CSR_xF_MASK; 128 129 if (flags) 130 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr); 131 132 irq_rx: 133 /* Rx IRQ */ 134 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr); 135 flags = xcsr & mask; 136 137 if (flags) 138 iret = IRQ_HANDLED; 139 else 140 goto out; 141 142 if (flags & FSL_SAI_CSR_WSF) 143 dev_dbg(dev, "isr: Start of Rx word detected\n"); 144 145 if (flags & FSL_SAI_CSR_SEF) 146 dev_dbg(dev, "isr: Rx Frame sync error detected\n"); 147 148 if (flags & FSL_SAI_CSR_FEF) 149 dev_dbg(dev, "isr: Receive overflow detected\n"); 150 151 if (flags & FSL_SAI_CSR_FWF) 152 dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); 153 154 if (flags & FSL_SAI_CSR_FRF) 155 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); 156 157 flags &= FSL_SAI_CSR_xF_W_MASK; 158 xcsr &= ~FSL_SAI_CSR_xF_MASK; 159 160 if (flags) 161 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr); 162 163 out: 164 return iret; 165 } 166 167 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 168 u32 rx_mask, int slots, int slot_width) 169 { 170 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 171 172 sai->slots = slots; 173 sai->slot_width = slot_width; 174 175 return 0; 176 } 177 178 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, 179 unsigned int ratio) 180 { 181 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 182 183 sai->bclk_ratio = ratio; 184 185 return 0; 186 } 187 188 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, 189 int clk_id, unsigned int freq, bool tx) 190 { 191 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 192 unsigned int ofs = sai->soc_data->reg_offset; 193 u32 val_cr2 = 0; 194 195 switch (clk_id) { 196 case FSL_SAI_CLK_BUS: 197 val_cr2 |= FSL_SAI_CR2_MSEL_BUS; 198 break; 199 case FSL_SAI_CLK_MAST1: 200 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; 201 break; 202 case FSL_SAI_CLK_MAST2: 203 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; 204 break; 205 case FSL_SAI_CLK_MAST3: 206 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 213 FSL_SAI_CR2_MSEL_MASK, val_cr2); 214 215 return 0; 216 } 217 218 static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsigned int freq) 219 { 220 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 221 int ret; 222 223 fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], 224 sai->pll8k_clk, sai->pll11k_clk, freq); 225 226 ret = clk_set_rate(sai->mclk_clk[clk_id], freq); 227 if (ret < 0) 228 dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); 229 230 return ret; 231 } 232 233 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 234 int clk_id, unsigned int freq, int dir) 235 { 236 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 237 int ret; 238 239 if (dir == SND_SOC_CLOCK_IN) 240 return 0; 241 242 if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) { 243 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) { 244 dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); 245 return -EINVAL; 246 } 247 248 if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { 249 dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); 250 return -EINVAL; 251 } 252 253 if (sai->mclk_streams == 0) { 254 ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); 255 if (ret < 0) 256 return ret; 257 } 258 } 259 260 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); 261 if (ret) { 262 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); 263 return ret; 264 } 265 266 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, false); 267 if (ret) 268 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); 269 270 return ret; 271 } 272 273 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, 274 unsigned int fmt, bool tx) 275 { 276 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 277 unsigned int ofs = sai->soc_data->reg_offset; 278 u32 val_cr2 = 0, val_cr4 = 0; 279 280 if (!sai->is_lsb_first) 281 val_cr4 |= FSL_SAI_CR4_MF; 282 283 sai->is_pdm_mode = false; 284 sai->is_dsp_mode = false; 285 /* DAI mode */ 286 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 287 case SND_SOC_DAIFMT_I2S: 288 /* 289 * Frame low, 1clk before data, one word length for frame sync, 290 * frame sync starts one serial clock cycle earlier, 291 * that is, together with the last bit of the previous 292 * data word. 293 */ 294 val_cr2 |= FSL_SAI_CR2_BCP; 295 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; 296 break; 297 case SND_SOC_DAIFMT_LEFT_J: 298 /* 299 * Frame high, one word length for frame sync, 300 * frame sync asserts with the first bit of the frame. 301 */ 302 val_cr2 |= FSL_SAI_CR2_BCP; 303 break; 304 case SND_SOC_DAIFMT_DSP_A: 305 /* 306 * Frame high, 1clk before data, one bit for frame sync, 307 * frame sync starts one serial clock cycle earlier, 308 * that is, together with the last bit of the previous 309 * data word. 310 */ 311 val_cr2 |= FSL_SAI_CR2_BCP; 312 val_cr4 |= FSL_SAI_CR4_FSE; 313 sai->is_dsp_mode = true; 314 break; 315 case SND_SOC_DAIFMT_DSP_B: 316 /* 317 * Frame high, one bit for frame sync, 318 * frame sync asserts with the first bit of the frame. 319 */ 320 val_cr2 |= FSL_SAI_CR2_BCP; 321 sai->is_dsp_mode = true; 322 break; 323 case SND_SOC_DAIFMT_PDM: 324 val_cr2 |= FSL_SAI_CR2_BCP; 325 val_cr4 &= ~FSL_SAI_CR4_MF; 326 sai->is_pdm_mode = true; 327 break; 328 case SND_SOC_DAIFMT_RIGHT_J: 329 /* To be done */ 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 /* Invert both clocks */ 338 val_cr2 ^= FSL_SAI_CR2_BCP; 339 val_cr4 ^= FSL_SAI_CR4_FSP; 340 break; 341 case SND_SOC_DAIFMT_IB_NF: 342 /* Invert bit clock */ 343 val_cr2 ^= FSL_SAI_CR2_BCP; 344 break; 345 case SND_SOC_DAIFMT_NB_IF: 346 /* Invert frame clock */ 347 val_cr4 ^= FSL_SAI_CR4_FSP; 348 break; 349 case SND_SOC_DAIFMT_NB_NF: 350 /* Nothing to do for both normal cases */ 351 break; 352 default: 353 return -EINVAL; 354 } 355 356 /* DAI clock provider masks */ 357 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 358 case SND_SOC_DAIFMT_BP_FP: 359 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 360 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 361 sai->is_consumer_mode = false; 362 break; 363 case SND_SOC_DAIFMT_BC_FC: 364 sai->is_consumer_mode = true; 365 break; 366 case SND_SOC_DAIFMT_BP_FC: 367 val_cr2 |= FSL_SAI_CR2_BCD_MSTR; 368 sai->is_consumer_mode = false; 369 break; 370 case SND_SOC_DAIFMT_BC_FP: 371 val_cr4 |= FSL_SAI_CR4_FSD_MSTR; 372 sai->is_consumer_mode = true; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), 379 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); 380 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 381 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | 382 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); 383 384 return 0; 385 } 386 387 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 388 { 389 int ret; 390 391 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, true); 392 if (ret) { 393 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); 394 return ret; 395 } 396 397 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, false); 398 if (ret) 399 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); 400 401 return ret; 402 } 403 404 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 405 { 406 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); 407 unsigned int reg, ofs = sai->soc_data->reg_offset; 408 unsigned long clk_rate; 409 u32 savediv = 0, ratio, bestdiff = freq; 410 int adir = tx ? RX : TX; 411 int dir = tx ? TX : RX; 412 u32 id; 413 bool support_1_1_ratio = sai->verid.version >= 0x0301; 414 415 /* Don't apply to consumer mode */ 416 if (sai->is_consumer_mode) 417 return 0; 418 419 /* 420 * There is no point in polling MCLK0 if it is identical to MCLK1. 421 * And given that MQS use case has to use MCLK1 though two clocks 422 * are the same, we simply skip MCLK0 and start to find from MCLK1. 423 */ 424 id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0; 425 426 for (; id < FSL_SAI_MCLK_MAX; id++) { 427 int diff; 428 429 clk_rate = clk_get_rate(sai->mclk_clk[id]); 430 if (!clk_rate) 431 continue; 432 433 ratio = DIV_ROUND_CLOSEST(clk_rate, freq); 434 if (!ratio || ratio > 512) 435 continue; 436 if (ratio == 1 && !support_1_1_ratio) 437 continue; 438 if ((ratio & 1) && ratio > 1) 439 continue; 440 441 diff = abs((long)clk_rate - ratio * freq); 442 443 /* 444 * Drop the source that can not be 445 * divided into the required rate. 446 */ 447 if (diff != 0 && clk_rate / diff < 1000) 448 continue; 449 450 dev_dbg(dai->dev, 451 "ratio %d for freq %dHz based on clock %ldHz\n", 452 ratio, freq, clk_rate); 453 454 455 if (diff < bestdiff) { 456 savediv = ratio; 457 sai->mclk_id[tx] = id; 458 bestdiff = diff; 459 } 460 461 if (diff == 0) 462 break; 463 } 464 465 if (savediv == 0) { 466 dev_err(dai->dev, "failed to derive required %cx rate: %d\n", 467 tx ? 'T' : 'R', freq); 468 return -EINVAL; 469 } 470 471 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", 472 sai->mclk_id[tx], savediv, bestdiff); 473 474 /* 475 * 1) For Asynchronous mode, we must set RCR2 register for capture, and 476 * set TCR2 register for playback. 477 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback 478 * and capture. 479 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback 480 * and capture. 481 * 4) For Tx and Rx are both Synchronous with another SAI, we just 482 * ignore it. 483 */ 484 if (fsl_sai_dir_is_synced(sai, adir)) 485 reg = FSL_SAI_xCR2(!tx, ofs); 486 else if (!sai->synchronous[dir]) 487 reg = FSL_SAI_xCR2(tx, ofs); 488 else 489 return 0; 490 491 regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, 492 FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); 493 494 if (savediv == 1) 495 regmap_update_bits(sai->regmap, reg, 496 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 497 FSL_SAI_CR2_BYP); 498 else 499 regmap_update_bits(sai->regmap, reg, 500 FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, 501 savediv / 2 - 1); 502 503 if (sai->soc_data->max_register >= FSL_SAI_MCTL) { 504 /* SAI is in master mode at this point, so enable MCLK */ 505 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 506 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 507 } 508 509 return 0; 510 } 511 512 static int fsl_sai_hw_params(struct snd_pcm_substream *substream, 513 struct snd_pcm_hw_params *params, 514 struct snd_soc_dai *cpu_dai) 515 { 516 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 517 unsigned int ofs = sai->soc_data->reg_offset; 518 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 519 unsigned int channels = params_channels(params); 520 struct snd_dmaengine_dai_dma_data *dma_params; 521 struct fsl_sai_dl_cfg *dl_cfg = sai->dl_cfg; 522 u32 word_width = params_width(params); 523 int trce_mask = 0, dl_cfg_idx = 0; 524 int dl_cfg_cnt = sai->dl_cfg_cnt; 525 u32 dl_type = FSL_SAI_DL_I2S; 526 u32 val_cr4 = 0, val_cr5 = 0; 527 u32 slots = (channels == 1) ? 2 : channels; 528 u32 slot_width = word_width; 529 int adir = tx ? RX : TX; 530 u32 pins, bclk; 531 u32 watermark; 532 int ret, i; 533 534 if (sai->slot_width) 535 slot_width = sai->slot_width; 536 537 if (sai->slots) 538 slots = sai->slots; 539 else if (sai->bclk_ratio) 540 slots = sai->bclk_ratio / slot_width; 541 542 pins = DIV_ROUND_UP(channels, slots); 543 544 /* 545 * PDM mode, channels are independent 546 * each channels are on one dataline/FIFO. 547 */ 548 if (sai->is_pdm_mode) { 549 pins = channels; 550 dl_type = FSL_SAI_DL_PDM; 551 } 552 553 for (i = 0; i < dl_cfg_cnt; i++) { 554 if (dl_cfg[i].type == dl_type && dl_cfg[i].pins[tx] == pins) { 555 dl_cfg_idx = i; 556 break; 557 } 558 } 559 560 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { 561 dev_err(cpu_dai->dev, "channel not supported\n"); 562 return -EINVAL; 563 } 564 565 bclk = params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots * slot_width); 566 567 if (!IS_ERR_OR_NULL(sai->pinctrl)) { 568 sai->pins_state = fsl_sai_get_pins_state(sai, bclk); 569 if (!IS_ERR_OR_NULL(sai->pins_state)) { 570 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 571 if (ret) { 572 dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); 573 return ret; 574 } 575 } 576 } 577 578 if (!sai->is_consumer_mode) { 579 ret = fsl_sai_set_bclk(cpu_dai, tx, bclk); 580 if (ret) 581 return ret; 582 583 /* Do not enable the clock if it is already enabled */ 584 if (!(sai->mclk_streams & BIT(substream->stream))) { 585 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); 586 if (ret) 587 return ret; 588 589 sai->mclk_streams |= BIT(substream->stream); 590 } 591 } 592 593 if (!sai->is_dsp_mode && !sai->is_pdm_mode) 594 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); 595 596 val_cr5 |= FSL_SAI_CR5_WNW(slot_width); 597 val_cr5 |= FSL_SAI_CR5_W0W(slot_width); 598 599 if (sai->is_lsb_first || sai->is_pdm_mode) 600 val_cr5 |= FSL_SAI_CR5_FBT(0); 601 else 602 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); 603 604 val_cr4 |= FSL_SAI_CR4_FRSZ(slots); 605 606 /* Set to output mode to avoid tri-stated data pins */ 607 if (tx) 608 val_cr4 |= FSL_SAI_CR4_CHMOD; 609 610 /* 611 * For SAI provider mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will 612 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), 613 * RCR5(TCR5) for playback(capture), or there will be sync error. 614 */ 615 616 if (!sai->is_consumer_mode && fsl_sai_dir_is_synced(sai, adir)) { 617 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs), 618 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 619 FSL_SAI_CR4_CHMOD_MASK, 620 val_cr4); 621 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs), 622 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 623 FSL_SAI_CR5_FBT_MASK, val_cr5); 624 } 625 626 /* 627 * Combine mode has limation: 628 * - Can't used for singel dataline/FIFO case except the FIFO0 629 * - Can't used for multi dataline/FIFO case except the enabled FIFOs 630 * are successive and start from FIFO0 631 * 632 * So for common usage, all multi fifo case disable the combine mode. 633 */ 634 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <= 1 || sai->is_multi_fifo_dma) 635 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 636 FSL_SAI_CR4_FCOMB_MASK, 0); 637 else 638 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 639 FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); 640 641 dma_params = tx ? &sai->dma_params_tx : &sai->dma_params_rx; 642 dma_params->addr = sai->res->start + FSL_SAI_xDR0(tx) + 643 dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; 644 645 if (sai->is_multi_fifo_dma) { 646 sai->audio_config[tx].words_per_fifo = min(slots, channels); 647 if (tx) { 648 sai->audio_config[tx].n_fifos_dst = pins; 649 sai->audio_config[tx].stride_fifos_dst = dl_cfg[dl_cfg_idx].next_off[tx]; 650 } else { 651 sai->audio_config[tx].n_fifos_src = pins; 652 sai->audio_config[tx].stride_fifos_src = dl_cfg[dl_cfg_idx].next_off[tx]; 653 } 654 dma_params->maxburst = sai->audio_config[tx].words_per_fifo * pins; 655 dma_params->peripheral_config = &sai->audio_config[tx]; 656 dma_params->peripheral_size = sizeof(sai->audio_config[tx]); 657 658 watermark = tx ? (sai->soc_data->fifo_depth - dma_params->maxburst) : 659 (dma_params->maxburst - 1); 660 regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx, ofs), 661 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 662 watermark); 663 } 664 665 /* Find a proper tcre setting */ 666 for (i = 0; i < sai->soc_data->pins; i++) { 667 trce_mask = (1 << (i + 1)) - 1; 668 if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) == pins) 669 break; 670 } 671 672 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 673 FSL_SAI_CR3_TRCE_MASK, 674 FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); 675 676 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), 677 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | 678 FSL_SAI_CR4_CHMOD_MASK, 679 val_cr4); 680 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs), 681 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | 682 FSL_SAI_CR5_FBT_MASK, val_cr5); 683 regmap_write(sai->regmap, FSL_SAI_xMR(tx), 684 ~0UL - ((1 << min(channels, slots)) - 1)); 685 686 return 0; 687 } 688 689 static int fsl_sai_hw_free(struct snd_pcm_substream *substream, 690 struct snd_soc_dai *cpu_dai) 691 { 692 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 693 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 694 unsigned int ofs = sai->soc_data->reg_offset; 695 696 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), 697 FSL_SAI_CR3_TRCE_MASK, 0); 698 699 if (!sai->is_consumer_mode && 700 sai->mclk_streams & BIT(substream->stream)) { 701 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); 702 sai->mclk_streams &= ~BIT(substream->stream); 703 } 704 705 return 0; 706 } 707 708 static void fsl_sai_config_disable(struct fsl_sai *sai, int dir) 709 { 710 unsigned int ofs = sai->soc_data->reg_offset; 711 bool tx = dir == TX; 712 u32 xcsr, count = 100; 713 714 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 715 FSL_SAI_CSR_TERE, 0); 716 717 /* TERE will remain set till the end of current frame */ 718 do { 719 udelay(10); 720 regmap_read(sai->regmap, FSL_SAI_xCSR(tx, ofs), &xcsr); 721 } while (--count && xcsr & FSL_SAI_CSR_TERE); 722 723 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 724 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); 725 726 /* 727 * For sai master mode, after several open/close sai, 728 * there will be no frame clock, and can't recover 729 * anymore. Add software reset to fix this issue. 730 * This is a hardware bug, and will be fix in the 731 * next sai version. 732 */ 733 if (!sai->is_consumer_mode) { 734 /* Software Reset */ 735 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), FSL_SAI_CSR_SR); 736 /* Clear SR bit to finish the reset */ 737 regmap_write(sai->regmap, FSL_SAI_xCSR(tx, ofs), 0); 738 } 739 } 740 741 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, 742 struct snd_soc_dai *cpu_dai) 743 { 744 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 745 unsigned int ofs = sai->soc_data->reg_offset; 746 747 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 748 int adir = tx ? RX : TX; 749 int dir = tx ? TX : RX; 750 u32 xcsr; 751 752 /* 753 * Asynchronous mode: Clear SYNC for both Tx and Rx. 754 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. 755 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. 756 */ 757 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC, 758 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); 759 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC, 760 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); 761 762 /* 763 * It is recommended that the transmitter is the last enabled 764 * and the first disabled. 765 */ 766 switch (cmd) { 767 case SNDRV_PCM_TRIGGER_START: 768 case SNDRV_PCM_TRIGGER_RESUME: 769 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 770 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 771 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); 772 773 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 774 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 775 /* 776 * Enable the opposite direction for synchronous mode 777 * 1. Tx sync with Rx: only set RE for Rx; set TE & RE for Tx 778 * 2. Rx sync with Tx: only set TE for Tx; set RE & TE for Rx 779 * 780 * RM recommends to enable RE after TE for case 1 and to enable 781 * TE after RE for case 2, but we here may not always guarantee 782 * that happens: "arecord 1.wav; aplay 2.wav" in case 1 enables 783 * TE after RE, which is against what RM recommends but should 784 * be safe to do, judging by years of testing results. 785 */ 786 if (fsl_sai_dir_is_synced(sai, adir)) 787 regmap_update_bits(sai->regmap, FSL_SAI_xCSR((!tx), ofs), 788 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); 789 790 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 791 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); 792 break; 793 case SNDRV_PCM_TRIGGER_STOP: 794 case SNDRV_PCM_TRIGGER_SUSPEND: 795 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 796 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 797 FSL_SAI_CSR_FRDE, 0); 798 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), 799 FSL_SAI_CSR_xIE_MASK, 0); 800 801 /* Check if the opposite FRDE is also disabled */ 802 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr); 803 804 /* 805 * If opposite stream provides clocks for synchronous mode and 806 * it is inactive, disable it before disabling the current one 807 */ 808 if (fsl_sai_dir_is_synced(sai, adir) && !(xcsr & FSL_SAI_CSR_FRDE)) 809 fsl_sai_config_disable(sai, adir); 810 811 /* 812 * Disable current stream if either of: 813 * 1. current stream doesn't provide clocks for synchronous mode 814 * 2. current stream provides clocks for synchronous mode but no 815 * more stream is active. 816 */ 817 if (!fsl_sai_dir_is_synced(sai, dir) || !(xcsr & FSL_SAI_CSR_FRDE)) 818 fsl_sai_config_disable(sai, dir); 819 820 break; 821 default: 822 return -EINVAL; 823 } 824 825 return 0; 826 } 827 828 static int fsl_sai_startup(struct snd_pcm_substream *substream, 829 struct snd_soc_dai *cpu_dai) 830 { 831 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); 832 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 833 int ret; 834 835 /* 836 * EDMA controller needs period size to be a multiple of 837 * tx/rx maxburst 838 */ 839 if (sai->soc_data->use_edma) 840 snd_pcm_hw_constraint_step(substream->runtime, 0, 841 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 842 tx ? sai->dma_params_tx.maxburst : 843 sai->dma_params_rx.maxburst); 844 845 ret = snd_pcm_hw_constraint_list(substream->runtime, 0, 846 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); 847 848 return ret; 849 } 850 851 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { 852 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio, 853 .set_sysclk = fsl_sai_set_dai_sysclk, 854 .set_fmt = fsl_sai_set_dai_fmt, 855 .set_tdm_slot = fsl_sai_set_dai_tdm_slot, 856 .hw_params = fsl_sai_hw_params, 857 .hw_free = fsl_sai_hw_free, 858 .trigger = fsl_sai_trigger, 859 .startup = fsl_sai_startup, 860 }; 861 862 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) 863 { 864 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); 865 unsigned int ofs = sai->soc_data->reg_offset; 866 867 /* Software Reset for both Tx and Rx */ 868 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 869 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 870 /* Clear SR bit to finish the reset */ 871 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 872 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 873 874 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs), 875 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 876 sai->soc_data->fifo_depth - sai->dma_params_tx.maxburst); 877 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs), 878 FSL_SAI_CR1_RFW_MASK(sai->soc_data->fifo_depth), 879 sai->dma_params_rx.maxburst - 1); 880 881 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, 882 &sai->dma_params_rx); 883 884 return 0; 885 } 886 887 static int fsl_sai_dai_resume(struct snd_soc_component *component) 888 { 889 struct fsl_sai *sai = snd_soc_component_get_drvdata(component); 890 struct device *dev = &sai->pdev->dev; 891 int ret; 892 893 if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { 894 ret = pinctrl_select_state(sai->pinctrl, sai->pins_state); 895 if (ret) { 896 dev_err(dev, "failed to set proper pins state: %d\n", ret); 897 return ret; 898 } 899 } 900 901 return 0; 902 } 903 904 static struct snd_soc_dai_driver fsl_sai_dai_template = { 905 .probe = fsl_sai_dai_probe, 906 .playback = { 907 .stream_name = "CPU-Playback", 908 .channels_min = 1, 909 .channels_max = 32, 910 .rate_min = 8000, 911 .rate_max = 2822400, 912 .rates = SNDRV_PCM_RATE_KNOT, 913 .formats = FSL_SAI_FORMATS, 914 }, 915 .capture = { 916 .stream_name = "CPU-Capture", 917 .channels_min = 1, 918 .channels_max = 32, 919 .rate_min = 8000, 920 .rate_max = 2822400, 921 .rates = SNDRV_PCM_RATE_KNOT, 922 .formats = FSL_SAI_FORMATS, 923 }, 924 .ops = &fsl_sai_pcm_dai_ops, 925 }; 926 927 static const struct snd_soc_component_driver fsl_component = { 928 .name = "fsl-sai", 929 .resume = fsl_sai_dai_resume, 930 .legacy_dai_naming = 1, 931 }; 932 933 static struct reg_default fsl_sai_reg_defaults_ofs0[] = { 934 {FSL_SAI_TCR1(0), 0}, 935 {FSL_SAI_TCR2(0), 0}, 936 {FSL_SAI_TCR3(0), 0}, 937 {FSL_SAI_TCR4(0), 0}, 938 {FSL_SAI_TCR5(0), 0}, 939 {FSL_SAI_TDR0, 0}, 940 {FSL_SAI_TDR1, 0}, 941 {FSL_SAI_TDR2, 0}, 942 {FSL_SAI_TDR3, 0}, 943 {FSL_SAI_TDR4, 0}, 944 {FSL_SAI_TDR5, 0}, 945 {FSL_SAI_TDR6, 0}, 946 {FSL_SAI_TDR7, 0}, 947 {FSL_SAI_TMR, 0}, 948 {FSL_SAI_RCR1(0), 0}, 949 {FSL_SAI_RCR2(0), 0}, 950 {FSL_SAI_RCR3(0), 0}, 951 {FSL_SAI_RCR4(0), 0}, 952 {FSL_SAI_RCR5(0), 0}, 953 {FSL_SAI_RMR, 0}, 954 }; 955 956 static struct reg_default fsl_sai_reg_defaults_ofs8[] = { 957 {FSL_SAI_TCR1(8), 0}, 958 {FSL_SAI_TCR2(8), 0}, 959 {FSL_SAI_TCR3(8), 0}, 960 {FSL_SAI_TCR4(8), 0}, 961 {FSL_SAI_TCR5(8), 0}, 962 {FSL_SAI_TDR0, 0}, 963 {FSL_SAI_TDR1, 0}, 964 {FSL_SAI_TDR2, 0}, 965 {FSL_SAI_TDR3, 0}, 966 {FSL_SAI_TDR4, 0}, 967 {FSL_SAI_TDR5, 0}, 968 {FSL_SAI_TDR6, 0}, 969 {FSL_SAI_TDR7, 0}, 970 {FSL_SAI_TMR, 0}, 971 {FSL_SAI_RCR1(8), 0}, 972 {FSL_SAI_RCR2(8), 0}, 973 {FSL_SAI_RCR3(8), 0}, 974 {FSL_SAI_RCR4(8), 0}, 975 {FSL_SAI_RCR5(8), 0}, 976 {FSL_SAI_RMR, 0}, 977 {FSL_SAI_MCTL, 0}, 978 {FSL_SAI_MDIV, 0}, 979 }; 980 981 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) 982 { 983 struct fsl_sai *sai = dev_get_drvdata(dev); 984 unsigned int ofs = sai->soc_data->reg_offset; 985 986 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 987 return true; 988 989 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 990 return true; 991 992 switch (reg) { 993 case FSL_SAI_TFR0: 994 case FSL_SAI_TFR1: 995 case FSL_SAI_TFR2: 996 case FSL_SAI_TFR3: 997 case FSL_SAI_TFR4: 998 case FSL_SAI_TFR5: 999 case FSL_SAI_TFR6: 1000 case FSL_SAI_TFR7: 1001 case FSL_SAI_TMR: 1002 case FSL_SAI_RDR0: 1003 case FSL_SAI_RDR1: 1004 case FSL_SAI_RDR2: 1005 case FSL_SAI_RDR3: 1006 case FSL_SAI_RDR4: 1007 case FSL_SAI_RDR5: 1008 case FSL_SAI_RDR6: 1009 case FSL_SAI_RDR7: 1010 case FSL_SAI_RFR0: 1011 case FSL_SAI_RFR1: 1012 case FSL_SAI_RFR2: 1013 case FSL_SAI_RFR3: 1014 case FSL_SAI_RFR4: 1015 case FSL_SAI_RFR5: 1016 case FSL_SAI_RFR6: 1017 case FSL_SAI_RFR7: 1018 case FSL_SAI_RMR: 1019 case FSL_SAI_MCTL: 1020 case FSL_SAI_MDIV: 1021 case FSL_SAI_VERID: 1022 case FSL_SAI_PARAM: 1023 case FSL_SAI_TTCTN: 1024 case FSL_SAI_RTCTN: 1025 case FSL_SAI_TTCTL: 1026 case FSL_SAI_TBCTN: 1027 case FSL_SAI_TTCAP: 1028 case FSL_SAI_RTCTL: 1029 case FSL_SAI_RBCTN: 1030 case FSL_SAI_RTCAP: 1031 return true; 1032 default: 1033 return false; 1034 } 1035 } 1036 1037 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) 1038 { 1039 struct fsl_sai *sai = dev_get_drvdata(dev); 1040 unsigned int ofs = sai->soc_data->reg_offset; 1041 1042 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs)) 1043 return true; 1044 1045 /* Set VERID and PARAM be volatile for reading value in probe */ 1046 if (ofs == 8 && (reg == FSL_SAI_VERID || reg == FSL_SAI_PARAM)) 1047 return true; 1048 1049 switch (reg) { 1050 case FSL_SAI_TFR0: 1051 case FSL_SAI_TFR1: 1052 case FSL_SAI_TFR2: 1053 case FSL_SAI_TFR3: 1054 case FSL_SAI_TFR4: 1055 case FSL_SAI_TFR5: 1056 case FSL_SAI_TFR6: 1057 case FSL_SAI_TFR7: 1058 case FSL_SAI_RFR0: 1059 case FSL_SAI_RFR1: 1060 case FSL_SAI_RFR2: 1061 case FSL_SAI_RFR3: 1062 case FSL_SAI_RFR4: 1063 case FSL_SAI_RFR5: 1064 case FSL_SAI_RFR6: 1065 case FSL_SAI_RFR7: 1066 case FSL_SAI_RDR0: 1067 case FSL_SAI_RDR1: 1068 case FSL_SAI_RDR2: 1069 case FSL_SAI_RDR3: 1070 case FSL_SAI_RDR4: 1071 case FSL_SAI_RDR5: 1072 case FSL_SAI_RDR6: 1073 case FSL_SAI_RDR7: 1074 return true; 1075 default: 1076 return false; 1077 } 1078 } 1079 1080 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) 1081 { 1082 struct fsl_sai *sai = dev_get_drvdata(dev); 1083 unsigned int ofs = sai->soc_data->reg_offset; 1084 1085 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs)) 1086 return true; 1087 1088 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs)) 1089 return true; 1090 1091 switch (reg) { 1092 case FSL_SAI_TDR0: 1093 case FSL_SAI_TDR1: 1094 case FSL_SAI_TDR2: 1095 case FSL_SAI_TDR3: 1096 case FSL_SAI_TDR4: 1097 case FSL_SAI_TDR5: 1098 case FSL_SAI_TDR6: 1099 case FSL_SAI_TDR7: 1100 case FSL_SAI_TMR: 1101 case FSL_SAI_RMR: 1102 case FSL_SAI_MCTL: 1103 case FSL_SAI_MDIV: 1104 case FSL_SAI_TTCTL: 1105 case FSL_SAI_RTCTL: 1106 return true; 1107 default: 1108 return false; 1109 } 1110 } 1111 1112 static struct regmap_config fsl_sai_regmap_config = { 1113 .reg_bits = 32, 1114 .reg_stride = 4, 1115 .val_bits = 32, 1116 .fast_io = true, 1117 1118 .max_register = FSL_SAI_RMR, 1119 .reg_defaults = fsl_sai_reg_defaults_ofs0, 1120 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0), 1121 .readable_reg = fsl_sai_readable_reg, 1122 .volatile_reg = fsl_sai_volatile_reg, 1123 .writeable_reg = fsl_sai_writeable_reg, 1124 .cache_type = REGCACHE_FLAT, 1125 }; 1126 1127 static int fsl_sai_check_version(struct device *dev) 1128 { 1129 struct fsl_sai *sai = dev_get_drvdata(dev); 1130 unsigned char ofs = sai->soc_data->reg_offset; 1131 unsigned int val; 1132 int ret; 1133 1134 if (FSL_SAI_TCSR(ofs) == FSL_SAI_VERID) 1135 return 0; 1136 1137 ret = regmap_read(sai->regmap, FSL_SAI_VERID, &val); 1138 if (ret < 0) 1139 return ret; 1140 1141 dev_dbg(dev, "VERID: 0x%016X\n", val); 1142 1143 sai->verid.version = val & 1144 (FSL_SAI_VERID_MAJOR_MASK | FSL_SAI_VERID_MINOR_MASK); 1145 sai->verid.version >>= FSL_SAI_VERID_MINOR_SHIFT; 1146 sai->verid.feature = val & FSL_SAI_VERID_FEATURE_MASK; 1147 1148 ret = regmap_read(sai->regmap, FSL_SAI_PARAM, &val); 1149 if (ret < 0) 1150 return ret; 1151 1152 dev_dbg(dev, "PARAM: 0x%016X\n", val); 1153 1154 /* Max slots per frame, power of 2 */ 1155 sai->param.slot_num = 1 << 1156 ((val & FSL_SAI_PARAM_SPF_MASK) >> FSL_SAI_PARAM_SPF_SHIFT); 1157 1158 /* Words per fifo, power of 2 */ 1159 sai->param.fifo_depth = 1 << 1160 ((val & FSL_SAI_PARAM_WPF_MASK) >> FSL_SAI_PARAM_WPF_SHIFT); 1161 1162 /* Number of datalines implemented */ 1163 sai->param.dataline = val & FSL_SAI_PARAM_DLN_MASK; 1164 1165 return 0; 1166 } 1167 1168 /* 1169 * Calculate the offset between first two datalines, don't 1170 * different offset in one case. 1171 */ 1172 static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) 1173 { 1174 int fbidx, nbidx, offset; 1175 1176 fbidx = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1177 nbidx = find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); 1178 offset = nbidx - fbidx - 1; 1179 1180 return (offset < 0 || offset >= (FSL_SAI_DL_NUM - 1) ? 0 : offset); 1181 } 1182 1183 /* 1184 * read the fsl,dataline property from dts file. 1185 * It has 3 value for each configuration, first one means the type: 1186 * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is 1187 * dataline mask for 'tx'. for example 1188 * 1189 * fsl,dataline = <1 0xff 0xff 2 0xff 0x11>, 1190 * 1191 * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type 1192 * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). 1193 * 1194 */ 1195 static int fsl_sai_read_dlcfg(struct fsl_sai *sai) 1196 { 1197 struct platform_device *pdev = sai->pdev; 1198 struct device_node *np = pdev->dev.of_node; 1199 struct device *dev = &pdev->dev; 1200 int ret, elems, i, index, num_cfg; 1201 char *propname = "fsl,dataline"; 1202 struct fsl_sai_dl_cfg *cfg; 1203 unsigned long dl_mask; 1204 unsigned int soc_dl; 1205 u32 rx, tx, type; 1206 1207 elems = of_property_count_u32_elems(np, propname); 1208 1209 if (elems <= 0) { 1210 elems = 0; 1211 } else if (elems % 3) { 1212 dev_err(dev, "Number of elements must be divisible to 3.\n"); 1213 return -EINVAL; 1214 } 1215 1216 num_cfg = elems / 3; 1217 /* Add one more for default value */ 1218 cfg = devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL); 1219 if (!cfg) 1220 return -ENOMEM; 1221 1222 /* Consider default value "0 0xFF 0xFF" if property is missing */ 1223 soc_dl = BIT(sai->soc_data->pins) - 1; 1224 cfg[0].type = FSL_SAI_DL_DEFAULT; 1225 cfg[0].pins[0] = sai->soc_data->pins; 1226 cfg[0].mask[0] = soc_dl; 1227 cfg[0].start_off[0] = 0; 1228 cfg[0].next_off[0] = 0; 1229 1230 cfg[0].pins[1] = sai->soc_data->pins; 1231 cfg[0].mask[1] = soc_dl; 1232 cfg[0].start_off[1] = 0; 1233 cfg[0].next_off[1] = 0; 1234 for (i = 1, index = 0; i < num_cfg + 1; i++) { 1235 /* 1236 * type of dataline 1237 * 0 means default mode 1238 * 1 means I2S mode 1239 * 2 means PDM mode 1240 */ 1241 ret = of_property_read_u32_index(np, propname, index++, &type); 1242 if (ret) 1243 return -EINVAL; 1244 1245 ret = of_property_read_u32_index(np, propname, index++, &rx); 1246 if (ret) 1247 return -EINVAL; 1248 1249 ret = of_property_read_u32_index(np, propname, index++, &tx); 1250 if (ret) 1251 return -EINVAL; 1252 1253 if ((rx & ~soc_dl) || (tx & ~soc_dl)) { 1254 dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_dl); 1255 return -EINVAL; 1256 } 1257 1258 rx = rx & soc_dl; 1259 tx = tx & soc_dl; 1260 1261 cfg[i].type = type; 1262 cfg[i].pins[0] = hweight8(rx); 1263 cfg[i].mask[0] = rx; 1264 dl_mask = rx; 1265 cfg[i].start_off[0] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1266 cfg[i].next_off[0] = fsl_sai_calc_dl_off(rx); 1267 1268 cfg[i].pins[1] = hweight8(tx); 1269 cfg[i].mask[1] = tx; 1270 dl_mask = tx; 1271 cfg[i].start_off[1] = find_first_bit(&dl_mask, FSL_SAI_DL_NUM); 1272 cfg[i].next_off[1] = fsl_sai_calc_dl_off(tx); 1273 } 1274 1275 sai->dl_cfg = cfg; 1276 sai->dl_cfg_cnt = num_cfg + 1; 1277 return 0; 1278 } 1279 1280 static int fsl_sai_runtime_suspend(struct device *dev); 1281 static int fsl_sai_runtime_resume(struct device *dev); 1282 1283 static int fsl_sai_probe(struct platform_device *pdev) 1284 { 1285 struct device_node *np = pdev->dev.of_node; 1286 struct device *dev = &pdev->dev; 1287 struct fsl_sai *sai; 1288 struct regmap *gpr; 1289 void __iomem *base; 1290 char tmp[8]; 1291 int irq, ret, i; 1292 int index; 1293 u32 dmas[4]; 1294 1295 sai = devm_kzalloc(dev, sizeof(*sai), GFP_KERNEL); 1296 if (!sai) 1297 return -ENOMEM; 1298 1299 sai->pdev = pdev; 1300 sai->soc_data = of_device_get_match_data(dev); 1301 1302 sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); 1303 1304 base = devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); 1305 if (IS_ERR(base)) 1306 return PTR_ERR(base); 1307 1308 if (sai->soc_data->reg_offset == 8) { 1309 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8; 1310 fsl_sai_regmap_config.max_register = FSL_SAI_MDIV; 1311 fsl_sai_regmap_config.num_reg_defaults = 1312 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8); 1313 } 1314 1315 sai->regmap = devm_regmap_init_mmio(dev, base, &fsl_sai_regmap_config); 1316 if (IS_ERR(sai->regmap)) { 1317 dev_err(dev, "regmap init failed\n"); 1318 return PTR_ERR(sai->regmap); 1319 } 1320 1321 sai->bus_clk = devm_clk_get(dev, "bus"); 1322 /* Compatible with old DTB cases */ 1323 if (IS_ERR(sai->bus_clk) && PTR_ERR(sai->bus_clk) != -EPROBE_DEFER) 1324 sai->bus_clk = devm_clk_get(dev, "sai"); 1325 if (IS_ERR(sai->bus_clk)) { 1326 dev_err(dev, "failed to get bus clock: %ld\n", 1327 PTR_ERR(sai->bus_clk)); 1328 /* -EPROBE_DEFER */ 1329 return PTR_ERR(sai->bus_clk); 1330 } 1331 1332 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { 1333 sprintf(tmp, "mclk%d", i); 1334 sai->mclk_clk[i] = devm_clk_get(dev, tmp); 1335 if (IS_ERR(sai->mclk_clk[i])) { 1336 dev_err(dev, "failed to get mclk%d clock: %ld\n", 1337 i, PTR_ERR(sai->mclk_clk[i])); 1338 sai->mclk_clk[i] = NULL; 1339 } 1340 } 1341 1342 if (sai->soc_data->mclk0_is_mclk1) 1343 sai->mclk_clk[0] = sai->mclk_clk[1]; 1344 else 1345 sai->mclk_clk[0] = sai->bus_clk; 1346 1347 fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, 1348 &sai->pll11k_clk); 1349 1350 /* Use Multi FIFO mode depending on the support from SDMA script */ 1351 ret = of_property_read_u32_array(np, "dmas", dmas, 4); 1352 if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) 1353 sai->is_multi_fifo_dma = true; 1354 1355 /* read dataline mask for rx and tx*/ 1356 ret = fsl_sai_read_dlcfg(sai); 1357 if (ret < 0) { 1358 dev_err(dev, "failed to read dlcfg %d\n", ret); 1359 return ret; 1360 } 1361 1362 irq = platform_get_irq(pdev, 0); 1363 if (irq < 0) 1364 return irq; 1365 1366 ret = devm_request_irq(dev, irq, fsl_sai_isr, IRQF_SHARED, 1367 np->name, sai); 1368 if (ret) { 1369 dev_err(dev, "failed to claim irq %u\n", irq); 1370 return ret; 1371 } 1372 1373 memcpy(&sai->cpu_dai_drv, &fsl_sai_dai_template, 1374 sizeof(fsl_sai_dai_template)); 1375 1376 /* Sync Tx with Rx as default by following old DT binding */ 1377 sai->synchronous[RX] = true; 1378 sai->synchronous[TX] = false; 1379 sai->cpu_dai_drv.symmetric_rate = 1; 1380 sai->cpu_dai_drv.symmetric_channels = 1; 1381 sai->cpu_dai_drv.symmetric_sample_bits = 1; 1382 1383 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && 1384 of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1385 /* error out if both synchronous and asynchronous are present */ 1386 dev_err(dev, "invalid binding for synchronous mode\n"); 1387 return -EINVAL; 1388 } 1389 1390 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { 1391 /* Sync Rx with Tx */ 1392 sai->synchronous[RX] = false; 1393 sai->synchronous[TX] = true; 1394 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { 1395 /* Discard all settings for asynchronous mode */ 1396 sai->synchronous[RX] = false; 1397 sai->synchronous[TX] = false; 1398 sai->cpu_dai_drv.symmetric_rate = 0; 1399 sai->cpu_dai_drv.symmetric_channels = 0; 1400 sai->cpu_dai_drv.symmetric_sample_bits = 0; 1401 } 1402 1403 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1404 of_device_is_compatible(np, "fsl,imx6ul-sai")) { 1405 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); 1406 if (IS_ERR(gpr)) { 1407 dev_err(dev, "cannot find iomuxc registers\n"); 1408 return PTR_ERR(gpr); 1409 } 1410 1411 index = of_alias_get_id(np, "sai"); 1412 if (index < 0) 1413 return index; 1414 1415 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), 1416 MCLK_DIR(index)); 1417 } 1418 1419 sai->dma_params_rx.addr = sai->res->start + FSL_SAI_RDR0; 1420 sai->dma_params_tx.addr = sai->res->start + FSL_SAI_TDR0; 1421 sai->dma_params_rx.maxburst = 1422 sai->soc_data->max_burst[RX] ? sai->soc_data->max_burst[RX] : FSL_SAI_MAXBURST_RX; 1423 sai->dma_params_tx.maxburst = 1424 sai->soc_data->max_burst[TX] ? sai->soc_data->max_burst[TX] : FSL_SAI_MAXBURST_TX; 1425 1426 sai->pinctrl = devm_pinctrl_get(&pdev->dev); 1427 1428 platform_set_drvdata(pdev, sai); 1429 pm_runtime_enable(dev); 1430 if (!pm_runtime_enabled(dev)) { 1431 ret = fsl_sai_runtime_resume(dev); 1432 if (ret) 1433 goto err_pm_disable; 1434 } 1435 1436 ret = pm_runtime_resume_and_get(dev); 1437 if (ret < 0) 1438 goto err_pm_get_sync; 1439 1440 /* Get sai version */ 1441 ret = fsl_sai_check_version(dev); 1442 if (ret < 0) 1443 dev_warn(dev, "Error reading SAI version: %d\n", ret); 1444 1445 /* Select MCLK direction */ 1446 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && 1447 sai->soc_data->max_register >= FSL_SAI_MCTL) { 1448 regmap_update_bits(sai->regmap, FSL_SAI_MCTL, 1449 FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN); 1450 } 1451 1452 ret = pm_runtime_put_sync(dev); 1453 if (ret < 0 && ret != -ENOSYS) 1454 goto err_pm_get_sync; 1455 1456 /* 1457 * Register platform component before registering cpu dai for there 1458 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1459 */ 1460 if (sai->soc_data->use_imx_pcm) { 1461 ret = imx_pcm_dma_init(pdev); 1462 if (ret) { 1463 dev_err_probe(dev, ret, "PCM DMA init failed\n"); 1464 if (!IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)) 1465 dev_err(dev, "Error: You must enable the imx-pcm-dma support!\n"); 1466 goto err_pm_get_sync; 1467 } 1468 } else { 1469 ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0); 1470 if (ret) { 1471 dev_err_probe(dev, ret, "Registering PCM dmaengine failed\n"); 1472 goto err_pm_get_sync; 1473 } 1474 } 1475 1476 ret = devm_snd_soc_register_component(dev, &fsl_component, 1477 &sai->cpu_dai_drv, 1); 1478 if (ret) 1479 goto err_pm_get_sync; 1480 1481 return ret; 1482 1483 err_pm_get_sync: 1484 if (!pm_runtime_status_suspended(dev)) 1485 fsl_sai_runtime_suspend(dev); 1486 err_pm_disable: 1487 pm_runtime_disable(dev); 1488 1489 return ret; 1490 } 1491 1492 static int fsl_sai_remove(struct platform_device *pdev) 1493 { 1494 pm_runtime_disable(&pdev->dev); 1495 if (!pm_runtime_status_suspended(&pdev->dev)) 1496 fsl_sai_runtime_suspend(&pdev->dev); 1497 1498 return 0; 1499 } 1500 1501 static const struct fsl_sai_soc_data fsl_sai_vf610_data = { 1502 .use_imx_pcm = false, 1503 .use_edma = false, 1504 .fifo_depth = 32, 1505 .pins = 1, 1506 .reg_offset = 0, 1507 .mclk0_is_mclk1 = false, 1508 .flags = 0, 1509 .max_register = FSL_SAI_RMR, 1510 }; 1511 1512 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = { 1513 .use_imx_pcm = true, 1514 .use_edma = false, 1515 .fifo_depth = 32, 1516 .pins = 1, 1517 .reg_offset = 0, 1518 .mclk0_is_mclk1 = true, 1519 .flags = 0, 1520 .max_register = FSL_SAI_RMR, 1521 }; 1522 1523 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = { 1524 .use_imx_pcm = true, 1525 .use_edma = false, 1526 .fifo_depth = 16, 1527 .pins = 2, 1528 .reg_offset = 8, 1529 .mclk0_is_mclk1 = false, 1530 .flags = PMQOS_CPU_LATENCY, 1531 .max_register = FSL_SAI_RMR, 1532 }; 1533 1534 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = { 1535 .use_imx_pcm = true, 1536 .use_edma = false, 1537 .fifo_depth = 128, 1538 .pins = 8, 1539 .reg_offset = 8, 1540 .mclk0_is_mclk1 = false, 1541 .flags = 0, 1542 .max_register = FSL_SAI_RMR, 1543 }; 1544 1545 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = { 1546 .use_imx_pcm = true, 1547 .use_edma = true, 1548 .fifo_depth = 64, 1549 .pins = 1, 1550 .reg_offset = 0, 1551 .mclk0_is_mclk1 = false, 1552 .flags = 0, 1553 .max_register = FSL_SAI_RMR, 1554 }; 1555 1556 static const struct fsl_sai_soc_data fsl_sai_imx8mm_data = { 1557 .use_imx_pcm = true, 1558 .use_edma = false, 1559 .fifo_depth = 128, 1560 .reg_offset = 8, 1561 .mclk0_is_mclk1 = false, 1562 .pins = 8, 1563 .flags = 0, 1564 .max_register = FSL_SAI_MCTL, 1565 }; 1566 1567 static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { 1568 .use_imx_pcm = true, 1569 .use_edma = false, 1570 .fifo_depth = 128, 1571 .reg_offset = 8, 1572 .mclk0_is_mclk1 = false, 1573 .pins = 8, 1574 .flags = 0, 1575 .max_register = FSL_SAI_MDIV, 1576 }; 1577 1578 static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { 1579 .use_imx_pcm = true, 1580 .use_edma = true, 1581 .fifo_depth = 16, 1582 .reg_offset = 8, 1583 .mclk0_is_mclk1 = false, 1584 .pins = 4, 1585 .flags = PMQOS_CPU_LATENCY, 1586 .max_register = FSL_SAI_RTCAP, 1587 }; 1588 1589 static const struct fsl_sai_soc_data fsl_sai_imx93_data = { 1590 .use_imx_pcm = true, 1591 .use_edma = true, 1592 .fifo_depth = 128, 1593 .reg_offset = 8, 1594 .mclk0_is_mclk1 = false, 1595 .pins = 4, 1596 .flags = 0, 1597 .max_register = FSL_SAI_MCTL, 1598 .max_burst = {8, 8}, 1599 }; 1600 1601 static const struct of_device_id fsl_sai_ids[] = { 1602 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data }, 1603 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data }, 1604 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data }, 1605 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data }, 1606 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data }, 1607 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data }, 1608 { .compatible = "fsl,imx8mm-sai", .data = &fsl_sai_imx8mm_data }, 1609 { .compatible = "fsl,imx8mp-sai", .data = &fsl_sai_imx8mp_data }, 1610 { .compatible = "fsl,imx8ulp-sai", .data = &fsl_sai_imx8ulp_data }, 1611 { .compatible = "fsl,imx8mn-sai", .data = &fsl_sai_imx8mp_data }, 1612 { .compatible = "fsl,imx93-sai", .data = &fsl_sai_imx93_data }, 1613 { /* sentinel */ } 1614 }; 1615 MODULE_DEVICE_TABLE(of, fsl_sai_ids); 1616 1617 static int fsl_sai_runtime_suspend(struct device *dev) 1618 { 1619 struct fsl_sai *sai = dev_get_drvdata(dev); 1620 1621 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1622 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1623 1624 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1625 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1626 1627 clk_disable_unprepare(sai->bus_clk); 1628 1629 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1630 cpu_latency_qos_remove_request(&sai->pm_qos_req); 1631 1632 regcache_cache_only(sai->regmap, true); 1633 1634 return 0; 1635 } 1636 1637 static int fsl_sai_runtime_resume(struct device *dev) 1638 { 1639 struct fsl_sai *sai = dev_get_drvdata(dev); 1640 unsigned int ofs = sai->soc_data->reg_offset; 1641 int ret; 1642 1643 ret = clk_prepare_enable(sai->bus_clk); 1644 if (ret) { 1645 dev_err(dev, "failed to enable bus clock: %d\n", ret); 1646 return ret; 1647 } 1648 1649 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) { 1650 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]); 1651 if (ret) 1652 goto disable_bus_clk; 1653 } 1654 1655 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) { 1656 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]); 1657 if (ret) 1658 goto disable_tx_clk; 1659 } 1660 1661 if (sai->soc_data->flags & PMQOS_CPU_LATENCY) 1662 cpu_latency_qos_add_request(&sai->pm_qos_req, 0); 1663 1664 regcache_cache_only(sai->regmap, false); 1665 regcache_mark_dirty(sai->regmap); 1666 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR); 1667 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR); 1668 usleep_range(1000, 2000); 1669 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0); 1670 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0); 1671 1672 ret = regcache_sync(sai->regmap); 1673 if (ret) 1674 goto disable_rx_clk; 1675 1676 return 0; 1677 1678 disable_rx_clk: 1679 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) 1680 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]); 1681 disable_tx_clk: 1682 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) 1683 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]); 1684 disable_bus_clk: 1685 clk_disable_unprepare(sai->bus_clk); 1686 1687 return ret; 1688 } 1689 1690 static const struct dev_pm_ops fsl_sai_pm_ops = { 1691 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, 1692 fsl_sai_runtime_resume, NULL) 1693 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1694 pm_runtime_force_resume) 1695 }; 1696 1697 static struct platform_driver fsl_sai_driver = { 1698 .probe = fsl_sai_probe, 1699 .remove = fsl_sai_remove, 1700 .driver = { 1701 .name = "fsl-sai", 1702 .pm = &fsl_sai_pm_ops, 1703 .of_match_table = fsl_sai_ids, 1704 }, 1705 }; 1706 module_platform_driver(fsl_sai_driver); 1707 1708 MODULE_DESCRIPTION("Freescale Soc SAI Interface"); 1709 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); 1710 MODULE_ALIAS("platform:fsl-sai"); 1711 MODULE_LICENSE("GPL"); 1712