1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // ALSA SoC IMX MQS driver 4 // 5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 6 // Copyright 2019 NXP 7 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/moduleparam.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/of.h> 15 #include <linux/pm.h> 16 #include <linux/slab.h> 17 #include <sound/soc.h> 18 #include <sound/pcm.h> 19 #include <sound/initval.h> 20 21 #define REG_MQS_CTRL 0x00 22 23 #define MQS_EN_MASK (0x1 << 28) 24 #define MQS_EN_SHIFT (28) 25 #define MQS_SW_RST_MASK (0x1 << 24) 26 #define MQS_SW_RST_SHIFT (24) 27 #define MQS_OVERSAMPLE_MASK (0x1 << 20) 28 #define MQS_OVERSAMPLE_SHIFT (20) 29 #define MQS_CLK_DIV_MASK (0xFF << 0) 30 #define MQS_CLK_DIV_SHIFT (0) 31 32 /* codec private data */ 33 struct fsl_mqs { 34 struct regmap *regmap; 35 struct clk *mclk; 36 struct clk *ipg; 37 38 unsigned int reg_iomuxc_gpr2; 39 unsigned int reg_mqs_ctrl; 40 bool use_gpr; 41 }; 42 43 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 44 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE 45 46 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream, 47 struct snd_pcm_hw_params *params, 48 struct snd_soc_dai *dai) 49 { 50 struct snd_soc_component *component = dai->component; 51 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 52 unsigned long mclk_rate; 53 int div, res; 54 int lrclk; 55 56 mclk_rate = clk_get_rate(mqs_priv->mclk); 57 lrclk = params_rate(params); 58 59 /* 60 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate; 61 * if repeat_rate is 8, mqs can achieve better quality. 62 * oversample rate is fix to 32 currently. 63 */ 64 div = mclk_rate / (32 * lrclk * 2 * 8); 65 res = mclk_rate % (32 * lrclk * 2 * 8); 66 67 if (res == 0 && div > 0 && div <= 256) { 68 if (mqs_priv->use_gpr) { 69 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 70 IMX6SX_GPR2_MQS_CLK_DIV_MASK, 71 (div - 1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT); 72 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 73 IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0); 74 } else { 75 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 76 MQS_CLK_DIV_MASK, 77 (div - 1) << MQS_CLK_DIV_SHIFT); 78 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 79 MQS_OVERSAMPLE_MASK, 0); 80 } 81 } else { 82 dev_err(component->dev, "can't get proper divider\n"); 83 } 84 85 return 0; 86 } 87 88 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 89 { 90 /* Only LEFT_J & SLAVE mode is supported. */ 91 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 92 case SND_SOC_DAIFMT_LEFT_J: 93 break; 94 default: 95 return -EINVAL; 96 } 97 98 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 99 case SND_SOC_DAIFMT_NB_NF: 100 break; 101 default: 102 return -EINVAL; 103 } 104 105 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 106 case SND_SOC_DAIFMT_CBC_CFC: 107 break; 108 default: 109 return -EINVAL; 110 } 111 112 return 0; 113 } 114 115 static int fsl_mqs_startup(struct snd_pcm_substream *substream, 116 struct snd_soc_dai *dai) 117 { 118 struct snd_soc_component *component = dai->component; 119 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 120 121 if (mqs_priv->use_gpr) 122 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 123 IMX6SX_GPR2_MQS_EN_MASK, 124 1 << IMX6SX_GPR2_MQS_EN_SHIFT); 125 else 126 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 127 MQS_EN_MASK, 128 1 << MQS_EN_SHIFT); 129 return 0; 130 } 131 132 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream, 133 struct snd_soc_dai *dai) 134 { 135 struct snd_soc_component *component = dai->component; 136 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component); 137 138 if (mqs_priv->use_gpr) 139 regmap_update_bits(mqs_priv->regmap, IOMUXC_GPR2, 140 IMX6SX_GPR2_MQS_EN_MASK, 0); 141 else 142 regmap_update_bits(mqs_priv->regmap, REG_MQS_CTRL, 143 MQS_EN_MASK, 0); 144 } 145 146 static const struct snd_soc_component_driver soc_codec_fsl_mqs = { 147 .idle_bias_on = 1, 148 .non_legacy_dai_naming = 1, 149 }; 150 151 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = { 152 .startup = fsl_mqs_startup, 153 .shutdown = fsl_mqs_shutdown, 154 .hw_params = fsl_mqs_hw_params, 155 .set_fmt = fsl_mqs_set_dai_fmt, 156 }; 157 158 static struct snd_soc_dai_driver fsl_mqs_dai = { 159 .name = "fsl-mqs-dai", 160 .playback = { 161 .stream_name = "Playback", 162 .channels_min = 2, 163 .channels_max = 2, 164 .rates = FSL_MQS_RATES, 165 .formats = FSL_MQS_FORMATS, 166 }, 167 .ops = &fsl_mqs_dai_ops, 168 }; 169 170 static const struct regmap_config fsl_mqs_regmap_config = { 171 .reg_bits = 32, 172 .reg_stride = 4, 173 .val_bits = 32, 174 .max_register = REG_MQS_CTRL, 175 .cache_type = REGCACHE_NONE, 176 }; 177 178 static int fsl_mqs_probe(struct platform_device *pdev) 179 { 180 struct device_node *np = pdev->dev.of_node; 181 struct device_node *gpr_np = NULL; 182 struct fsl_mqs *mqs_priv; 183 void __iomem *regs; 184 int ret; 185 186 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL); 187 if (!mqs_priv) 188 return -ENOMEM; 189 190 /* On i.MX6sx the MQS control register is in GPR domain 191 * But in i.MX8QM/i.MX8QXP the control register is moved 192 * to its own domain. 193 */ 194 if (of_device_is_compatible(np, "fsl,imx8qm-mqs")) 195 mqs_priv->use_gpr = false; 196 else 197 mqs_priv->use_gpr = true; 198 199 if (mqs_priv->use_gpr) { 200 gpr_np = of_parse_phandle(np, "gpr", 0); 201 if (!gpr_np) { 202 dev_err(&pdev->dev, "failed to get gpr node by phandle\n"); 203 return -EINVAL; 204 } 205 206 mqs_priv->regmap = syscon_node_to_regmap(gpr_np); 207 if (IS_ERR(mqs_priv->regmap)) { 208 dev_err(&pdev->dev, "failed to get gpr regmap\n"); 209 ret = PTR_ERR(mqs_priv->regmap); 210 goto err_free_gpr_np; 211 } 212 } else { 213 regs = devm_platform_ioremap_resource(pdev, 0); 214 if (IS_ERR(regs)) 215 return PTR_ERR(regs); 216 217 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 218 "core", 219 regs, 220 &fsl_mqs_regmap_config); 221 if (IS_ERR(mqs_priv->regmap)) { 222 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 223 PTR_ERR(mqs_priv->regmap)); 224 return PTR_ERR(mqs_priv->regmap); 225 } 226 227 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core"); 228 if (IS_ERR(mqs_priv->ipg)) { 229 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 230 PTR_ERR(mqs_priv->ipg)); 231 return PTR_ERR(mqs_priv->ipg); 232 } 233 } 234 235 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk"); 236 if (IS_ERR(mqs_priv->mclk)) { 237 dev_err(&pdev->dev, "failed to get the clock: %ld\n", 238 PTR_ERR(mqs_priv->mclk)); 239 ret = PTR_ERR(mqs_priv->mclk); 240 goto err_free_gpr_np; 241 } 242 243 dev_set_drvdata(&pdev->dev, mqs_priv); 244 pm_runtime_enable(&pdev->dev); 245 246 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs, 247 &fsl_mqs_dai, 1); 248 if (ret) 249 goto err_free_gpr_np; 250 return 0; 251 252 err_free_gpr_np: 253 of_node_put(gpr_np); 254 255 return ret; 256 } 257 258 static int fsl_mqs_remove(struct platform_device *pdev) 259 { 260 pm_runtime_disable(&pdev->dev); 261 return 0; 262 } 263 264 #ifdef CONFIG_PM 265 static int fsl_mqs_runtime_resume(struct device *dev) 266 { 267 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 268 int ret; 269 270 ret = clk_prepare_enable(mqs_priv->ipg); 271 if (ret) { 272 dev_err(dev, "failed to enable ipg clock\n"); 273 return ret; 274 } 275 276 ret = clk_prepare_enable(mqs_priv->mclk); 277 if (ret) { 278 dev_err(dev, "failed to enable mclk clock\n"); 279 clk_disable_unprepare(mqs_priv->ipg); 280 return ret; 281 } 282 283 if (mqs_priv->use_gpr) 284 regmap_write(mqs_priv->regmap, IOMUXC_GPR2, 285 mqs_priv->reg_iomuxc_gpr2); 286 else 287 regmap_write(mqs_priv->regmap, REG_MQS_CTRL, 288 mqs_priv->reg_mqs_ctrl); 289 return 0; 290 } 291 292 static int fsl_mqs_runtime_suspend(struct device *dev) 293 { 294 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev); 295 296 if (mqs_priv->use_gpr) 297 regmap_read(mqs_priv->regmap, IOMUXC_GPR2, 298 &mqs_priv->reg_iomuxc_gpr2); 299 else 300 regmap_read(mqs_priv->regmap, REG_MQS_CTRL, 301 &mqs_priv->reg_mqs_ctrl); 302 303 clk_disable_unprepare(mqs_priv->mclk); 304 clk_disable_unprepare(mqs_priv->ipg); 305 306 return 0; 307 } 308 #endif 309 310 static const struct dev_pm_ops fsl_mqs_pm_ops = { 311 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend, 312 fsl_mqs_runtime_resume, 313 NULL) 314 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 315 pm_runtime_force_resume) 316 }; 317 318 static const struct of_device_id fsl_mqs_dt_ids[] = { 319 { .compatible = "fsl,imx8qm-mqs", }, 320 { .compatible = "fsl,imx6sx-mqs", }, 321 {} 322 }; 323 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids); 324 325 static struct platform_driver fsl_mqs_driver = { 326 .probe = fsl_mqs_probe, 327 .remove = fsl_mqs_remove, 328 .driver = { 329 .name = "fsl-mqs", 330 .of_match_table = fsl_mqs_dt_ids, 331 .pm = &fsl_mqs_pm_ops, 332 }, 333 }; 334 335 module_platform_driver(fsl_mqs_driver); 336 337 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>"); 338 MODULE_DESCRIPTION("MQS codec driver"); 339 MODULE_LICENSE("GPL v2"); 340 MODULE_ALIAS("platform: fsl-mqs"); 341