1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // ALSA SoC IMX MQS driver
4 //
5 // Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
6 // Copyright 2019 NXP
7
8 #include <linux/clk.h>
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/of.h>
16 #include <linux/pm.h>
17 #include <linux/slab.h>
18 #include <sound/soc.h>
19 #include <sound/pcm.h>
20 #include <sound/initval.h>
21
22 #define REG_MQS_CTRL 0x00
23
24 #define MQS_EN_MASK (0x1 << 28)
25 #define MQS_EN_SHIFT (28)
26 #define MQS_SW_RST_MASK (0x1 << 24)
27 #define MQS_SW_RST_SHIFT (24)
28 #define MQS_OVERSAMPLE_MASK (0x1 << 20)
29 #define MQS_OVERSAMPLE_SHIFT (20)
30 #define MQS_CLK_DIV_MASK (0xFF << 0)
31 #define MQS_CLK_DIV_SHIFT (0)
32
33 /**
34 * struct fsl_mqs_soc_data - soc specific data
35 *
36 * @use_gpr: control register is in General Purpose Register group
37 * @ctrl_off: control register offset
38 * @en_mask: enable bit mask
39 * @en_shift: enable bit shift
40 * @rst_mask: reset bit mask
41 * @rst_shift: reset bit shift
42 * @osr_mask: oversample bit mask
43 * @osr_shift: oversample bit shift
44 * @div_mask: clock divider mask
45 * @div_shift: clock divider bit shift
46 */
47 struct fsl_mqs_soc_data {
48 bool use_gpr;
49 int ctrl_off;
50 int en_mask;
51 int en_shift;
52 int rst_mask;
53 int rst_shift;
54 int osr_mask;
55 int osr_shift;
56 int div_mask;
57 int div_shift;
58 };
59
60 /* codec private data */
61 struct fsl_mqs {
62 struct regmap *regmap;
63 struct clk *mclk;
64 struct clk *ipg;
65 const struct fsl_mqs_soc_data *soc;
66
67 unsigned int reg_mqs_ctrl;
68 };
69
70 #define FSL_MQS_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
71 #define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
72
fsl_mqs_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)73 static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
74 struct snd_pcm_hw_params *params,
75 struct snd_soc_dai *dai)
76 {
77 struct snd_soc_component *component = dai->component;
78 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
79 unsigned long mclk_rate;
80 int div, res;
81 int lrclk;
82
83 mclk_rate = clk_get_rate(mqs_priv->mclk);
84 lrclk = params_rate(params);
85
86 /*
87 * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
88 * if repeat_rate is 8, mqs can achieve better quality.
89 * oversample rate is fix to 32 currently.
90 */
91 div = mclk_rate / (32 * lrclk * 2 * 8);
92 res = mclk_rate % (32 * lrclk * 2 * 8);
93
94 if (res == 0 && div > 0 && div <= 256) {
95 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
96 mqs_priv->soc->div_mask,
97 (div - 1) << mqs_priv->soc->div_shift);
98 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
99 mqs_priv->soc->osr_mask, 0);
100 } else {
101 dev_err(component->dev, "can't get proper divider\n");
102 }
103
104 return 0;
105 }
106
fsl_mqs_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)107 static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
108 {
109 /* Only LEFT_J & SLAVE mode is supported. */
110 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
111 case SND_SOC_DAIFMT_LEFT_J:
112 break;
113 default:
114 return -EINVAL;
115 }
116
117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
118 case SND_SOC_DAIFMT_NB_NF:
119 break;
120 default:
121 return -EINVAL;
122 }
123
124 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
125 case SND_SOC_DAIFMT_CBC_CFC:
126 break;
127 default:
128 return -EINVAL;
129 }
130
131 return 0;
132 }
133
fsl_mqs_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)134 static int fsl_mqs_startup(struct snd_pcm_substream *substream,
135 struct snd_soc_dai *dai)
136 {
137 struct snd_soc_component *component = dai->component;
138 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
139
140 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
141 mqs_priv->soc->en_mask,
142 1 << mqs_priv->soc->en_shift);
143 return 0;
144 }
145
fsl_mqs_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)146 static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
147 struct snd_soc_dai *dai)
148 {
149 struct snd_soc_component *component = dai->component;
150 struct fsl_mqs *mqs_priv = snd_soc_component_get_drvdata(component);
151
152 regmap_update_bits(mqs_priv->regmap, mqs_priv->soc->ctrl_off,
153 mqs_priv->soc->en_mask, 0);
154 }
155
156 static const struct snd_soc_component_driver soc_codec_fsl_mqs = {
157 .idle_bias_on = 1,
158 };
159
160 static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
161 .startup = fsl_mqs_startup,
162 .shutdown = fsl_mqs_shutdown,
163 .hw_params = fsl_mqs_hw_params,
164 .set_fmt = fsl_mqs_set_dai_fmt,
165 };
166
167 static struct snd_soc_dai_driver fsl_mqs_dai = {
168 .name = "fsl-mqs-dai",
169 .playback = {
170 .stream_name = "Playback",
171 .channels_min = 2,
172 .channels_max = 2,
173 .rates = FSL_MQS_RATES,
174 .formats = FSL_MQS_FORMATS,
175 },
176 .ops = &fsl_mqs_dai_ops,
177 };
178
179 static const struct regmap_config fsl_mqs_regmap_config = {
180 .reg_bits = 32,
181 .reg_stride = 4,
182 .val_bits = 32,
183 .max_register = REG_MQS_CTRL,
184 .cache_type = REGCACHE_NONE,
185 };
186
fsl_mqs_probe(struct platform_device * pdev)187 static int fsl_mqs_probe(struct platform_device *pdev)
188 {
189 struct device_node *np = pdev->dev.of_node;
190 struct device_node *gpr_np = NULL;
191 struct fsl_mqs *mqs_priv;
192 void __iomem *regs;
193 int ret;
194
195 mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
196 if (!mqs_priv)
197 return -ENOMEM;
198
199 /* On i.MX6sx the MQS control register is in GPR domain
200 * But in i.MX8QM/i.MX8QXP the control register is moved
201 * to its own domain.
202 */
203 mqs_priv->soc = of_device_get_match_data(&pdev->dev);
204
205 if (mqs_priv->soc->use_gpr) {
206 gpr_np = of_parse_phandle(np, "gpr", 0);
207 if (!gpr_np) {
208 dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
209 return -EINVAL;
210 }
211
212 mqs_priv->regmap = syscon_node_to_regmap(gpr_np);
213 of_node_put(gpr_np);
214 if (IS_ERR(mqs_priv->regmap)) {
215 dev_err(&pdev->dev, "failed to get gpr regmap\n");
216 return PTR_ERR(mqs_priv->regmap);
217 }
218 } else {
219 regs = devm_platform_ioremap_resource(pdev, 0);
220 if (IS_ERR(regs))
221 return PTR_ERR(regs);
222
223 mqs_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
224 "core",
225 regs,
226 &fsl_mqs_regmap_config);
227 if (IS_ERR(mqs_priv->regmap)) {
228 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
229 PTR_ERR(mqs_priv->regmap));
230 return PTR_ERR(mqs_priv->regmap);
231 }
232
233 mqs_priv->ipg = devm_clk_get(&pdev->dev, "core");
234 if (IS_ERR(mqs_priv->ipg)) {
235 dev_err(&pdev->dev, "failed to get the clock: %ld\n",
236 PTR_ERR(mqs_priv->ipg));
237 return PTR_ERR(mqs_priv->ipg);
238 }
239 }
240
241 mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
242 if (IS_ERR(mqs_priv->mclk)) {
243 dev_err(&pdev->dev, "failed to get the clock: %ld\n",
244 PTR_ERR(mqs_priv->mclk));
245 return PTR_ERR(mqs_priv->mclk);
246 }
247
248 dev_set_drvdata(&pdev->dev, mqs_priv);
249 pm_runtime_enable(&pdev->dev);
250
251 ret = devm_snd_soc_register_component(&pdev->dev, &soc_codec_fsl_mqs,
252 &fsl_mqs_dai, 1);
253 if (ret)
254 return ret;
255
256 return 0;
257 }
258
fsl_mqs_remove(struct platform_device * pdev)259 static void fsl_mqs_remove(struct platform_device *pdev)
260 {
261 pm_runtime_disable(&pdev->dev);
262 }
263
264 #ifdef CONFIG_PM
fsl_mqs_runtime_resume(struct device * dev)265 static int fsl_mqs_runtime_resume(struct device *dev)
266 {
267 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
268 int ret;
269
270 ret = clk_prepare_enable(mqs_priv->ipg);
271 if (ret) {
272 dev_err(dev, "failed to enable ipg clock\n");
273 return ret;
274 }
275
276 ret = clk_prepare_enable(mqs_priv->mclk);
277 if (ret) {
278 dev_err(dev, "failed to enable mclk clock\n");
279 clk_disable_unprepare(mqs_priv->ipg);
280 return ret;
281 }
282
283 regmap_write(mqs_priv->regmap, mqs_priv->soc->ctrl_off, mqs_priv->reg_mqs_ctrl);
284 return 0;
285 }
286
fsl_mqs_runtime_suspend(struct device * dev)287 static int fsl_mqs_runtime_suspend(struct device *dev)
288 {
289 struct fsl_mqs *mqs_priv = dev_get_drvdata(dev);
290
291 regmap_read(mqs_priv->regmap, mqs_priv->soc->ctrl_off, &mqs_priv->reg_mqs_ctrl);
292
293 clk_disable_unprepare(mqs_priv->mclk);
294 clk_disable_unprepare(mqs_priv->ipg);
295
296 return 0;
297 }
298 #endif
299
300 static const struct dev_pm_ops fsl_mqs_pm_ops = {
301 SET_RUNTIME_PM_OPS(fsl_mqs_runtime_suspend,
302 fsl_mqs_runtime_resume,
303 NULL)
304 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
305 pm_runtime_force_resume)
306 };
307
308 static const struct fsl_mqs_soc_data fsl_mqs_imx8qm_data = {
309 .use_gpr = false,
310 .ctrl_off = REG_MQS_CTRL,
311 .en_mask = MQS_EN_MASK,
312 .en_shift = MQS_EN_SHIFT,
313 .rst_mask = MQS_SW_RST_MASK,
314 .rst_shift = MQS_SW_RST_SHIFT,
315 .osr_mask = MQS_OVERSAMPLE_MASK,
316 .osr_shift = MQS_OVERSAMPLE_SHIFT,
317 .div_mask = MQS_CLK_DIV_MASK,
318 .div_shift = MQS_CLK_DIV_SHIFT,
319 };
320
321 static const struct fsl_mqs_soc_data fsl_mqs_imx6sx_data = {
322 .use_gpr = true,
323 .ctrl_off = IOMUXC_GPR2,
324 .en_mask = IMX6SX_GPR2_MQS_EN_MASK,
325 .en_shift = IMX6SX_GPR2_MQS_EN_SHIFT,
326 .rst_mask = IMX6SX_GPR2_MQS_SW_RST_MASK,
327 .rst_shift = IMX6SX_GPR2_MQS_SW_RST_SHIFT,
328 .osr_mask = IMX6SX_GPR2_MQS_OVERSAMPLE_MASK,
329 .osr_shift = IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT,
330 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
331 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
332 };
333
334 static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
335 .use_gpr = true,
336 .ctrl_off = 0x20,
337 .en_mask = BIT(1),
338 .en_shift = 1,
339 .rst_mask = BIT(2),
340 .rst_shift = 2,
341 .osr_mask = BIT(3),
342 .osr_shift = 3,
343 .div_mask = GENMASK(15, 8),
344 .div_shift = 8,
345 };
346
347 static const struct of_device_id fsl_mqs_dt_ids[] = {
348 { .compatible = "fsl,imx8qm-mqs", .data = &fsl_mqs_imx8qm_data },
349 { .compatible = "fsl,imx6sx-mqs", .data = &fsl_mqs_imx6sx_data },
350 { .compatible = "fsl,imx93-mqs", .data = &fsl_mqs_imx93_data },
351 {}
352 };
353 MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
354
355 static struct platform_driver fsl_mqs_driver = {
356 .probe = fsl_mqs_probe,
357 .remove_new = fsl_mqs_remove,
358 .driver = {
359 .name = "fsl-mqs",
360 .of_match_table = fsl_mqs_dt_ids,
361 .pm = &fsl_mqs_pm_ops,
362 },
363 };
364
365 module_platform_driver(fsl_mqs_driver);
366
367 MODULE_AUTHOR("Shengjiu Wang <Shengjiu.Wang@nxp.com>");
368 MODULE_DESCRIPTION("MQS codec driver");
369 MODULE_LICENSE("GPL v2");
370 MODULE_ALIAS("platform:fsl-mqs");
371