1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PDM Microphone Interface for the NXP i.MX SoC 4 * Copyright 2018 NXP 5 */ 6 7 #ifndef _FSL_MICFIL_H 8 #define _FSL_MICFIL_H 9 10 /* MICFIL Register Map */ 11 #define REG_MICFIL_CTRL1 0x00 12 #define REG_MICFIL_CTRL2 0x04 13 #define REG_MICFIL_STAT 0x08 14 #define REG_MICFIL_FIFO_CTRL 0x10 15 #define REG_MICFIL_FIFO_STAT 0x14 16 #define REG_MICFIL_DATACH0 0x24 17 #define REG_MICFIL_DATACH1 0x28 18 #define REG_MICFIL_DATACH2 0x2C 19 #define REG_MICFIL_DATACH3 0x30 20 #define REG_MICFIL_DATACH4 0x34 21 #define REG_MICFIL_DATACH5 0x38 22 #define REG_MICFIL_DATACH6 0x3C 23 #define REG_MICFIL_DATACH7 0x40 24 #define REG_MICFIL_DC_CTRL 0x64 25 #define REG_MICFIL_OUT_CTRL 0x74 26 #define REG_MICFIL_OUT_STAT 0x7C 27 #define REG_MICFIL_VAD0_CTRL1 0x90 28 #define REG_MICFIL_VAD0_CTRL2 0x94 29 #define REG_MICFIL_VAD0_STAT 0x98 30 #define REG_MICFIL_VAD0_SCONFIG 0x9C 31 #define REG_MICFIL_VAD0_NCONFIG 0xA0 32 #define REG_MICFIL_VAD0_NDATA 0xA4 33 #define REG_MICFIL_VAD0_ZCD 0xA8 34 35 /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ 36 #define MICFIL_CTRL1_MDIS BIT(31) 37 #define MICFIL_CTRL1_DOZEN BIT(30) 38 #define MICFIL_CTRL1_PDMIEN BIT(29) 39 #define MICFIL_CTRL1_DBG BIT(28) 40 #define MICFIL_CTRL1_SRES BIT(27) 41 #define MICFIL_CTRL1_DBGE BIT(26) 42 #define MICFIL_CTRL1_DISEL_SHIFT 24 43 #define MICFIL_CTRL1_DISEL_WIDTH 2 44 #define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \ 45 << MICFIL_CTRL1_DISEL_SHIFT) 46 #define MICFIL_CTRL1_ERREN BIT(23) 47 #define MICFIL_CTRL1_CHEN_SHIFT 0 48 #define MICFIL_CTRL1_CHEN_WIDTH 8 49 #define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT) 50 #define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x)) 51 52 /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ 53 #define MICFIL_CTRL2_QSEL_SHIFT 25 54 #define MICFIL_CTRL2_QSEL_WIDTH 3 55 #define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \ 56 << MICFIL_CTRL2_QSEL_SHIFT) 57 #define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT) 58 #define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT) 59 #define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT) 60 #define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT) 61 #define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT) 62 #define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT) 63 64 #define MICFIL_CTRL2_CICOSR_SHIFT 16 65 #define MICFIL_CTRL2_CICOSR_WIDTH 4 66 #define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \ 67 << MICFIL_CTRL2_CICOSR_SHIFT) 68 #define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \ 69 & MICFIL_CTRL2_CICOSR_MASK) 70 #define MICFIL_CTRL2_CLKDIV_SHIFT 0 71 #define MICFIL_CTRL2_CLKDIV_WIDTH 8 72 #define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \ 73 << MICFIL_CTRL2_CLKDIV_SHIFT) 74 #define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \ 75 & MICFIL_CTRL2_CLKDIV_MASK) 76 77 /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ 78 #define MICFIL_STAT_BSY_FIL BIT(31) 79 #define MICFIL_STAT_FIR_RDY BIT(30) 80 #define MICFIL_STAT_LOWFREQF BIT(29) 81 #define MICFIL_STAT_CHXF_SHIFT(v) (v) 82 #define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) 83 #define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v)) 84 85 /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ 86 #define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0 87 #define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3 88 #define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \ 89 << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) 90 #define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \ 91 & MICFIL_FIFO_CTRL_FIFOWMK_MASK) 92 93 /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ 94 #define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v) 95 #define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v)) 96 #define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8) 97 #define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v)) 98 99 /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ 100 #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24 101 #define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3 102 #define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \ 103 << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) 104 #define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \ 105 & MICFIL_VAD0_CTRL1_CHSEL_MASK) 106 #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16 107 #define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4 108 #define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \ 109 << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) 110 #define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \ 111 & MICFIL_VAD0_CTRL1_CICOSR_MASK) 112 #define MICFIL_VAD0_CTRL1_INITT_SHIFT 8 113 #define MICFIL_VAD0_CTRL1_INITT_WIDTH 5 114 #define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \ 115 << MICFIL_VAD0_CTRL1_INITT_SHIFT) 116 #define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \ 117 & MICFIL_VAD0_CTRL1_INITT_MASK) 118 #define MICFIL_VAD0_CTRL1_ST10 BIT(4) 119 #define MICFIL_VAD0_CTRL1_ERIE BIT(3) 120 #define MICFIL_VAD0_CTRL1_IE BIT(2) 121 #define MICFIL_VAD0_CTRL1_RST BIT(1) 122 #define MICFIL_VAD0_CTRL1_EN BIT(0) 123 124 /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ 125 #define MICFIL_VAD0_CTRL2_FRENDIS BIT(31) 126 #define MICFIL_VAD0_CTRL2_PREFEN BIT(30) 127 #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28) 128 #define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16 129 #define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6 130 #define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \ 131 << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) 132 #define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \ 133 & MICFIL_VAD0_CTRL2_FRAMET_MASK) 134 #define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8 135 #define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4 136 #define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \ 137 << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) 138 #define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \ 139 & MICFIL_VAD0_CTRL2_INPGAIN_MASK) 140 #define MICFIL_VAD0_CTRL2_HPF_SHIFT 0 141 #define MICFIL_VAD0_CTRL2_HPF_WIDTH 2 142 #define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \ 143 << MICFIL_VAD0_CTRL2_HPF_SHIFT) 144 #define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \ 145 & MICFIL_VAD0_CTRL2_HPF_MASK) 146 147 /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ 148 #define MICFIL_VAD0_SCONFIG_SFILEN BIT(31) 149 #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30) 150 #define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0 151 #define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4 152 #define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \ 153 << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) 154 #define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \ 155 & MICFIL_VAD0_SCONFIG_SGAIN_MASK) 156 157 /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ 158 #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31) 159 #define MICFIL_VAD0_NCONFIG_NMINEN BIT(30) 160 #define MICFIL_VAD0_NCONFIG_NDECEN BIT(29) 161 #define MICFIL_VAD0_NCONFIG_NOREN BIT(28) 162 #define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8 163 #define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5 164 #define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \ 165 << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) 166 #define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \ 167 & MICFIL_VAD0_NCONFIG_NFILADJ_MASK) 168 #define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0 169 #define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4 170 #define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \ 171 << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) 172 #define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \ 173 & MICFIL_VAD0_NCONFIG_NGAIN_MASK) 174 175 /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ 176 #define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16 177 #define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10 178 #define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \ 179 << MICFIL_VAD0_ZCD_ZCDTH_SHIFT) 180 #define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\ 181 & MICFIL_VAD0_ZCD_ZCDTH_MASK) 182 #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8 183 #define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4 184 #define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\ 185 << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT) 186 #define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\ 187 & MICFIL_VAD0_ZCD_ZCDADJ_MASK) 188 #define MICFIL_VAD0_ZCD_ZCDAND BIT(4) 189 #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2) 190 #define MICFIL_VAD0_ZCD_ZCDEN BIT(0) 191 192 /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ 193 #define MICFIL_VAD0_STAT_INITF BIT(31) 194 #define MICFIL_VAD0_STAT_INSATF BIT(16) 195 #define MICFIL_VAD0_STAT_EF BIT(15) 196 #define MICFIL_VAD0_STAT_IF BIT(0) 197 198 /* MICFIL Output Control Register */ 199 #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) 200 201 /* Constants */ 202 #define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK) 203 #define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \ 204 == ((v) & MICFIL_CTRL1_DISEL_MASK)) 205 #define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \ 206 == ((v) & MICFIL_CTRL1_DISEL_MASK)) 207 #define MICFIL_OUTPUT_CHANNELS 8 208 #define MICFIL_FIFO_NUM 8 209 210 #define FIFO_PTRWID 3 211 #define FIFO_LEN BIT(FIFO_PTRWID) 212 213 #define MICFIL_IRQ_LINES 2 214 #define MICFIL_MAX_RETRY 25 215 #define MICFIL_SLEEP_MIN 90000 /* in us */ 216 #define MICFIL_SLEEP_MAX 100000 /* in us */ 217 #define MICFIL_DMA_MAXBURST_RX 6 218 #define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT) 219 220 #endif /* _FSL_MICFIL_H */ 221