147a70e6fSCosmin Samoila /* SPDX-License-Identifier: GPL-2.0 */ 247a70e6fSCosmin Samoila /* 347a70e6fSCosmin Samoila * PDM Microphone Interface for the NXP i.MX SoC 447a70e6fSCosmin Samoila * Copyright 2018 NXP 547a70e6fSCosmin Samoila */ 647a70e6fSCosmin Samoila 747a70e6fSCosmin Samoila #ifndef _FSL_MICFIL_H 847a70e6fSCosmin Samoila #define _FSL_MICFIL_H 947a70e6fSCosmin Samoila 1047a70e6fSCosmin Samoila /* MICFIL Register Map */ 1147a70e6fSCosmin Samoila #define REG_MICFIL_CTRL1 0x00 1247a70e6fSCosmin Samoila #define REG_MICFIL_CTRL2 0x04 1347a70e6fSCosmin Samoila #define REG_MICFIL_STAT 0x08 1447a70e6fSCosmin Samoila #define REG_MICFIL_FIFO_CTRL 0x10 1547a70e6fSCosmin Samoila #define REG_MICFIL_FIFO_STAT 0x14 1647a70e6fSCosmin Samoila #define REG_MICFIL_DATACH0 0x24 1747a70e6fSCosmin Samoila #define REG_MICFIL_DATACH1 0x28 1847a70e6fSCosmin Samoila #define REG_MICFIL_DATACH2 0x2C 1947a70e6fSCosmin Samoila #define REG_MICFIL_DATACH3 0x30 2047a70e6fSCosmin Samoila #define REG_MICFIL_DATACH4 0x34 2147a70e6fSCosmin Samoila #define REG_MICFIL_DATACH5 0x38 2247a70e6fSCosmin Samoila #define REG_MICFIL_DATACH6 0x3C 2347a70e6fSCosmin Samoila #define REG_MICFIL_DATACH7 0x40 2447a70e6fSCosmin Samoila #define REG_MICFIL_DC_CTRL 0x64 2547a70e6fSCosmin Samoila #define REG_MICFIL_OUT_CTRL 0x74 2647a70e6fSCosmin Samoila #define REG_MICFIL_OUT_STAT 0x7C 2747a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_CTRL1 0x90 2847a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_CTRL2 0x94 2947a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_STAT 0x98 3047a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_SCONFIG 0x9C 3147a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_NCONFIG 0xA0 3247a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_NDATA 0xA4 3347a70e6fSCosmin Samoila #define REG_MICFIL_VAD0_ZCD 0xA8 3447a70e6fSCosmin Samoila 3547a70e6fSCosmin Samoila /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ 36bd2cffd1SSascha Hauer #define MICFIL_CTRL1_MDIS BIT(31) 37bd2cffd1SSascha Hauer #define MICFIL_CTRL1_DOZEN BIT(30) 38bd2cffd1SSascha Hauer #define MICFIL_CTRL1_PDMIEN BIT(29) 39bd2cffd1SSascha Hauer #define MICFIL_CTRL1_DBG BIT(28) 40bd2cffd1SSascha Hauer #define MICFIL_CTRL1_SRES BIT(27) 41bd2cffd1SSascha Hauer #define MICFIL_CTRL1_DBGE BIT(26) 42*17f2142bSSascha Hauer 43*17f2142bSSascha Hauer #define MICFIL_CTRL1_DISEL_DISABLE 0 44*17f2142bSSascha Hauer #define MICFIL_CTRL1_DISEL_DMA 1 45*17f2142bSSascha Hauer #define MICFIL_CTRL1_DISEL_IRQ 2 46*17f2142bSSascha Hauer #define MICFIL_CTRL1_DISEL GENMASK(25, 24) 47bd2cffd1SSascha Hauer #define MICFIL_CTRL1_ERREN BIT(23) 48*17f2142bSSascha Hauer #define MICFIL_CTRL1_CHEN(ch) BIT(ch) 4947a70e6fSCosmin Samoila 5047a70e6fSCosmin Samoila /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ 5147a70e6fSCosmin Samoila #define MICFIL_CTRL2_QSEL_SHIFT 25 52*17f2142bSSascha Hauer #define MICFIL_CTRL2_QSEL GENMASK(27, 25) 53*17f2142bSSascha Hauer #define MICFIL_QSEL_MEDIUM_QUALITY 0 54*17f2142bSSascha Hauer #define MICFIL_QSEL_HIGH_QUALITY 1 55*17f2142bSSascha Hauer #define MICFIL_QSEL_LOW_QUALITY 7 56*17f2142bSSascha Hauer #define MICFIL_QSEL_VLOW0_QUALITY 6 57*17f2142bSSascha Hauer #define MICFIL_QSEL_VLOW1_QUALITY 5 58*17f2142bSSascha Hauer #define MICFIL_QSEL_VLOW2_QUALITY 4 5947a70e6fSCosmin Samoila 60*17f2142bSSascha Hauer #define MICFIL_CTRL2_CICOSR GENMASK(19, 16) 61*17f2142bSSascha Hauer #define MICFIL_CTRL2_CICOSR_DEFAULT 0 62*17f2142bSSascha Hauer #define MICFIL_CTRL2_CLKDIV GENMASK(7, 0) 6347a70e6fSCosmin Samoila 6447a70e6fSCosmin Samoila /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ 65bd2cffd1SSascha Hauer #define MICFIL_STAT_BSY_FIL BIT(31) 66bd2cffd1SSascha Hauer #define MICFIL_STAT_FIR_RDY BIT(30) 67bd2cffd1SSascha Hauer #define MICFIL_STAT_LOWFREQF BIT(29) 68*17f2142bSSascha Hauer #define MICFIL_STAT_CHXF(ch) BIT(ch) 6947a70e6fSCosmin Samoila 7047a70e6fSCosmin Samoila /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ 71*17f2142bSSascha Hauer #define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0) 7247a70e6fSCosmin Samoila 7347a70e6fSCosmin Samoila /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ 74*17f2142bSSascha Hauer #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch) 75*17f2142bSSascha Hauer #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) 7647a70e6fSCosmin Samoila 7747a70e6fSCosmin Samoila /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ 78*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24) 79*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16) 80*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8) 81bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL1_ST10 BIT(4) 82bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL1_ERIE BIT(3) 83bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL1_IE BIT(2) 84bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL1_RST BIT(1) 85bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL1_EN BIT(0) 8647a70e6fSCosmin Samoila 8747a70e6fSCosmin Samoila /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ 88bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL2_FRENDIS BIT(31) 89bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL2_PREFEN BIT(30) 90bd2cffd1SSascha Hauer #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28) 91*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16) 92*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8) 93*17f2142bSSascha Hauer #define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0) 9447a70e6fSCosmin Samoila 9547a70e6fSCosmin Samoila /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ 96bd2cffd1SSascha Hauer #define MICFIL_VAD0_SCONFIG_SFILEN BIT(31) 97bd2cffd1SSascha Hauer #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30) 98*17f2142bSSascha Hauer #define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0) 9947a70e6fSCosmin Samoila 10047a70e6fSCosmin Samoila /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ 101bd2cffd1SSascha Hauer #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31) 102bd2cffd1SSascha Hauer #define MICFIL_VAD0_NCONFIG_NMINEN BIT(30) 103bd2cffd1SSascha Hauer #define MICFIL_VAD0_NCONFIG_NDECEN BIT(29) 104bd2cffd1SSascha Hauer #define MICFIL_VAD0_NCONFIG_NOREN BIT(28) 105*17f2142bSSascha Hauer #define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8) 106*17f2142bSSascha Hauer #define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0) 10747a70e6fSCosmin Samoila 10847a70e6fSCosmin Samoila /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ 109*17f2142bSSascha Hauer #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16) 110*17f2142bSSascha Hauer #define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8) 111bd2cffd1SSascha Hauer #define MICFIL_VAD0_ZCD_ZCDAND BIT(4) 112bd2cffd1SSascha Hauer #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2) 113bd2cffd1SSascha Hauer #define MICFIL_VAD0_ZCD_ZCDEN BIT(0) 11447a70e6fSCosmin Samoila 11547a70e6fSCosmin Samoila /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ 116bd2cffd1SSascha Hauer #define MICFIL_VAD0_STAT_INITF BIT(31) 117bd2cffd1SSascha Hauer #define MICFIL_VAD0_STAT_INSATF BIT(16) 118bd2cffd1SSascha Hauer #define MICFIL_VAD0_STAT_EF BIT(15) 119bd2cffd1SSascha Hauer #define MICFIL_VAD0_STAT_IF BIT(0) 12047a70e6fSCosmin Samoila 12147a70e6fSCosmin Samoila /* MICFIL Output Control Register */ 12247a70e6fSCosmin Samoila #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) 12347a70e6fSCosmin Samoila 12447a70e6fSCosmin Samoila /* Constants */ 12547a70e6fSCosmin Samoila #define MICFIL_OUTPUT_CHANNELS 8 12647a70e6fSCosmin Samoila #define MICFIL_FIFO_NUM 8 12747a70e6fSCosmin Samoila 12847a70e6fSCosmin Samoila #define FIFO_PTRWID 3 12947a70e6fSCosmin Samoila #define FIFO_LEN BIT(FIFO_PTRWID) 13047a70e6fSCosmin Samoila 13147a70e6fSCosmin Samoila #define MICFIL_IRQ_LINES 2 13247a70e6fSCosmin Samoila #define MICFIL_MAX_RETRY 25 13347a70e6fSCosmin Samoila #define MICFIL_SLEEP_MIN 90000 /* in us */ 13447a70e6fSCosmin Samoila #define MICFIL_SLEEP_MAX 100000 /* in us */ 13547a70e6fSCosmin Samoila #define MICFIL_DMA_MAXBURST_RX 6 13647a70e6fSCosmin Samoila 13747a70e6fSCosmin Samoila #endif /* _FSL_MICFIL_H */ 138