1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 #include "fsl_utils.h" 28 29 #define MICFIL_OSR_DEFAULT 16 30 31 enum quality { 32 QUALITY_HIGH, 33 QUALITY_MEDIUM, 34 QUALITY_LOW, 35 QUALITY_VLOW0, 36 QUALITY_VLOW1, 37 QUALITY_VLOW2, 38 }; 39 40 struct fsl_micfil { 41 struct platform_device *pdev; 42 struct regmap *regmap; 43 const struct fsl_micfil_soc_data *soc; 44 struct clk *busclk; 45 struct clk *mclk; 46 struct clk *pll8k_clk; 47 struct clk *pll11k_clk; 48 struct snd_dmaengine_dai_dma_data dma_params_rx; 49 struct sdma_peripheral_config sdmacfg; 50 struct snd_soc_card *card; 51 unsigned int dataline; 52 char name[32]; 53 int irq[MICFIL_IRQ_LINES]; 54 enum quality quality; 55 int dc_remover; 56 int vad_init_mode; 57 int vad_enabled; 58 int vad_detected; 59 struct fsl_micfil_verid verid; 60 struct fsl_micfil_param param; 61 }; 62 63 struct fsl_micfil_soc_data { 64 unsigned int fifos; 65 unsigned int fifo_depth; 66 unsigned int dataline; 67 bool imx; 68 bool use_edma; 69 bool use_verid; 70 bool volume_sx; 71 u64 formats; 72 }; 73 74 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 75 .imx = true, 76 .fifos = 8, 77 .fifo_depth = 8, 78 .dataline = 0xf, 79 .formats = SNDRV_PCM_FMTBIT_S16_LE, 80 .volume_sx = true, 81 }; 82 83 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 84 .imx = true, 85 .fifos = 8, 86 .fifo_depth = 32, 87 .dataline = 0xf, 88 .formats = SNDRV_PCM_FMTBIT_S32_LE, 89 .volume_sx = false, 90 }; 91 92 static struct fsl_micfil_soc_data fsl_micfil_imx93 = { 93 .imx = true, 94 .fifos = 8, 95 .fifo_depth = 32, 96 .dataline = 0xf, 97 .formats = SNDRV_PCM_FMTBIT_S32_LE, 98 .use_edma = true, 99 .use_verid = true, 100 .volume_sx = false, 101 }; 102 103 static const struct of_device_id fsl_micfil_dt_ids[] = { 104 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 105 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 106 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 }, 107 {} 108 }; 109 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 110 111 static const char * const micfil_quality_select_texts[] = { 112 [QUALITY_HIGH] = "High", 113 [QUALITY_MEDIUM] = "Medium", 114 [QUALITY_LOW] = "Low", 115 [QUALITY_VLOW0] = "VLow0", 116 [QUALITY_VLOW1] = "Vlow1", 117 [QUALITY_VLOW2] = "Vlow2", 118 }; 119 120 static const struct soc_enum fsl_micfil_quality_enum = 121 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 122 micfil_quality_select_texts); 123 124 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 125 126 static int micfil_set_quality(struct fsl_micfil *micfil) 127 { 128 u32 qsel; 129 130 switch (micfil->quality) { 131 case QUALITY_HIGH: 132 qsel = MICFIL_QSEL_HIGH_QUALITY; 133 break; 134 case QUALITY_MEDIUM: 135 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 136 break; 137 case QUALITY_LOW: 138 qsel = MICFIL_QSEL_LOW_QUALITY; 139 break; 140 case QUALITY_VLOW0: 141 qsel = MICFIL_QSEL_VLOW0_QUALITY; 142 break; 143 case QUALITY_VLOW1: 144 qsel = MICFIL_QSEL_VLOW1_QUALITY; 145 break; 146 case QUALITY_VLOW2: 147 qsel = MICFIL_QSEL_VLOW2_QUALITY; 148 break; 149 } 150 151 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 152 MICFIL_CTRL2_QSEL, 153 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 154 } 155 156 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 157 struct snd_ctl_elem_value *ucontrol) 158 { 159 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 160 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 161 162 ucontrol->value.integer.value[0] = micfil->quality; 163 164 return 0; 165 } 166 167 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 168 struct snd_ctl_elem_value *ucontrol) 169 { 170 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 171 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 172 173 micfil->quality = ucontrol->value.integer.value[0]; 174 175 return micfil_set_quality(micfil); 176 } 177 178 static const char * const micfil_hwvad_enable[] = { 179 "Disable (Record only)", 180 "Enable (Record with Vad)", 181 }; 182 183 static const char * const micfil_hwvad_init_mode[] = { 184 "Envelope mode", "Energy mode", 185 }; 186 187 static const char * const micfil_hwvad_hpf_texts[] = { 188 "Filter bypass", 189 "Cut-off @1750Hz", 190 "Cut-off @215Hz", 191 "Cut-off @102Hz", 192 }; 193 194 /* 195 * DC Remover Control 196 * Filter Bypassed 1 1 197 * Cut-off @21Hz 0 0 198 * Cut-off @83Hz 0 1 199 * Cut-off @152HZ 1 0 200 */ 201 static const char * const micfil_dc_remover_texts[] = { 202 "Cut-off @21Hz", "Cut-off @83Hz", 203 "Cut-off @152Hz", "Bypass", 204 }; 205 206 static const struct soc_enum hwvad_enable_enum = 207 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 208 micfil_hwvad_enable); 209 static const struct soc_enum hwvad_init_mode_enum = 210 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 211 micfil_hwvad_init_mode); 212 static const struct soc_enum hwvad_hpf_enum = 213 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 214 ARRAY_SIZE(micfil_hwvad_hpf_texts), 215 micfil_hwvad_hpf_texts); 216 static const struct soc_enum fsl_micfil_dc_remover_enum = 217 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 218 micfil_dc_remover_texts); 219 220 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 221 struct snd_ctl_elem_value *ucontrol) 222 { 223 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 224 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 225 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 226 unsigned int *item = ucontrol->value.enumerated.item; 227 int val = snd_soc_enum_item_to_val(e, item[0]); 228 int i = 0, ret = 0; 229 u32 reg_val = 0; 230 231 if (val < 0 || val > 3) 232 return -EINVAL; 233 234 micfil->dc_remover = val; 235 236 /* Calculate total value for all channels */ 237 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 238 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 239 240 /* Update DC Remover mode for all channels */ 241 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 242 MICFIL_DC_CTRL_CONFIG, reg_val); 243 if (ret < 0) 244 return ret; 245 246 return 0; 247 } 248 249 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 250 struct snd_ctl_elem_value *ucontrol) 251 { 252 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 253 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 254 255 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 256 257 return 0; 258 } 259 260 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 261 struct snd_ctl_elem_value *ucontrol) 262 { 263 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 264 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 265 unsigned int *item = ucontrol->value.enumerated.item; 266 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 267 int val = snd_soc_enum_item_to_val(e, item[0]); 268 269 micfil->vad_enabled = val; 270 271 return 0; 272 } 273 274 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 275 struct snd_ctl_elem_value *ucontrol) 276 { 277 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 278 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 279 280 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 281 282 return 0; 283 } 284 285 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 286 struct snd_ctl_elem_value *ucontrol) 287 { 288 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 289 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 290 unsigned int *item = ucontrol->value.enumerated.item; 291 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 292 int val = snd_soc_enum_item_to_val(e, item[0]); 293 294 /* 0 - Envelope-based Mode 295 * 1 - Energy-based Mode 296 */ 297 micfil->vad_init_mode = val; 298 299 return 0; 300 } 301 302 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 303 struct snd_ctl_elem_value *ucontrol) 304 { 305 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 306 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 307 308 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 309 310 return 0; 311 } 312 313 static int hwvad_detected(struct snd_kcontrol *kcontrol, 314 struct snd_ctl_elem_value *ucontrol) 315 { 316 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 317 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 318 319 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 320 321 return 0; 322 } 323 324 static const struct snd_kcontrol_new fsl_micfil_volume_controls[] = { 325 SOC_SINGLE_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 326 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0, gain_tlv), 327 SOC_SINGLE_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 328 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0, gain_tlv), 329 SOC_SINGLE_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 330 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0, gain_tlv), 331 SOC_SINGLE_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 332 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0, gain_tlv), 333 SOC_SINGLE_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 334 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0, gain_tlv), 335 SOC_SINGLE_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 336 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0, gain_tlv), 337 SOC_SINGLE_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 338 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0, gain_tlv), 339 SOC_SINGLE_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 340 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0, gain_tlv), 341 }; 342 343 static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = { 344 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 345 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv), 346 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 347 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv), 348 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 349 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv), 350 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 351 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv), 352 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 353 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv), 354 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 355 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv), 356 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 357 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv), 358 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 359 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv), 360 }; 361 362 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 363 SOC_ENUM_EXT("MICFIL Quality Select", 364 fsl_micfil_quality_enum, 365 micfil_quality_get, micfil_quality_set), 366 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 367 hwvad_get_enable, hwvad_put_enable), 368 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 369 hwvad_get_init_mode, hwvad_put_init_mode), 370 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 371 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 372 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 373 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 374 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 375 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 376 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 377 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 378 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 379 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 380 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 381 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 382 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 383 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 384 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 385 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 386 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL), 387 }; 388 389 static int fsl_micfil_use_verid(struct device *dev) 390 { 391 struct fsl_micfil *micfil = dev_get_drvdata(dev); 392 unsigned int val; 393 int ret; 394 395 if (!micfil->soc->use_verid) 396 return 0; 397 398 ret = regmap_read(micfil->regmap, REG_MICFIL_VERID, &val); 399 if (ret < 0) 400 return ret; 401 402 dev_dbg(dev, "VERID: 0x%016X\n", val); 403 404 micfil->verid.version = val & 405 (MICFIL_VERID_MAJOR_MASK | MICFIL_VERID_MINOR_MASK); 406 micfil->verid.version >>= MICFIL_VERID_MINOR_SHIFT; 407 micfil->verid.feature = val & MICFIL_VERID_FEATURE_MASK; 408 409 ret = regmap_read(micfil->regmap, REG_MICFIL_PARAM, &val); 410 if (ret < 0) 411 return ret; 412 413 dev_dbg(dev, "PARAM: 0x%016X\n", val); 414 415 micfil->param.hwvad_num = (val & MICFIL_PARAM_NUM_HWVAD_MASK) >> 416 MICFIL_PARAM_NUM_HWVAD_SHIFT; 417 micfil->param.hwvad_zcd = val & MICFIL_PARAM_HWVAD_ZCD; 418 micfil->param.hwvad_energy_mode = val & MICFIL_PARAM_HWVAD_ENERGY_MODE; 419 micfil->param.hwvad = val & MICFIL_PARAM_HWVAD; 420 micfil->param.dc_out_bypass = val & MICFIL_PARAM_DC_OUT_BYPASS; 421 micfil->param.dc_in_bypass = val & MICFIL_PARAM_DC_IN_BYPASS; 422 micfil->param.low_power = val & MICFIL_PARAM_LOW_POWER; 423 micfil->param.fil_out_width = val & MICFIL_PARAM_FIL_OUT_WIDTH; 424 micfil->param.fifo_ptrwid = (val & MICFIL_PARAM_FIFO_PTRWID_MASK) >> 425 MICFIL_PARAM_FIFO_PTRWID_SHIFT; 426 micfil->param.npair = (val & MICFIL_PARAM_NPAIR_MASK) >> 427 MICFIL_PARAM_NPAIR_SHIFT; 428 429 return 0; 430 } 431 432 /* The SRES is a self-negated bit which provides the CPU with the 433 * capability to initialize the PDM Interface module through the 434 * slave-bus interface. This bit always reads as zero, and this 435 * bit is only effective when MDIS is cleared 436 */ 437 static int fsl_micfil_reset(struct device *dev) 438 { 439 struct fsl_micfil *micfil = dev_get_drvdata(dev); 440 int ret; 441 442 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 443 MICFIL_CTRL1_MDIS); 444 if (ret) 445 return ret; 446 447 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 448 MICFIL_CTRL1_SRES); 449 if (ret) 450 return ret; 451 452 /* 453 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 454 * as non-volatile register, so SRES still remain in regmap 455 * cache after set, that every update of REG_MICFIL_CTRL1, 456 * software reset happens. so clear it explicitly. 457 */ 458 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 459 MICFIL_CTRL1_SRES); 460 if (ret) 461 return ret; 462 463 /* 464 * Set SRES should clear CHnF flags, But even add delay here 465 * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 466 */ 467 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 468 if (ret) 469 return ret; 470 471 return 0; 472 } 473 474 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 475 struct snd_soc_dai *dai) 476 { 477 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 478 479 if (!micfil) { 480 dev_err(dai->dev, "micfil dai priv_data not set\n"); 481 return -EINVAL; 482 } 483 484 return 0; 485 } 486 487 /* Enable/disable hwvad interrupts */ 488 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 489 { 490 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 491 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 492 493 /* Voice Activity Detector Error Interruption */ 494 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 495 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 496 497 /* Voice Activity Detector Interruption */ 498 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 499 MICFIL_VAD0_CTRL1_IE, vadie_reg); 500 501 return 0; 502 } 503 504 /* Configuration done only in energy-based initialization mode */ 505 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 506 { 507 /* Keep the VADFRENDIS bitfield cleared. */ 508 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 509 MICFIL_VAD0_CTRL2_FRENDIS); 510 511 /* Keep the VADPREFEN bitfield cleared. */ 512 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 513 MICFIL_VAD0_CTRL2_PREFEN); 514 515 /* Keep the VADSFILEN bitfield cleared. */ 516 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 517 MICFIL_VAD0_SCONFIG_SFILEN); 518 519 /* Keep the VADSMAXEN bitfield cleared. */ 520 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 521 MICFIL_VAD0_SCONFIG_SMAXEN); 522 523 /* Keep the VADNFILAUTO bitfield asserted. */ 524 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 525 MICFIL_VAD0_NCONFIG_NFILAUT); 526 527 /* Keep the VADNMINEN bitfield cleared. */ 528 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 529 MICFIL_VAD0_NCONFIG_NMINEN); 530 531 /* Keep the VADNDECEN bitfield cleared. */ 532 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 533 MICFIL_VAD0_NCONFIG_NDECEN); 534 535 /* Keep the VADNOREN bitfield cleared. */ 536 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 537 MICFIL_VAD0_NCONFIG_NOREN); 538 539 return 0; 540 } 541 542 /* Configuration done only in envelope-based initialization mode */ 543 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 544 { 545 /* Assert the VADFRENDIS bitfield */ 546 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 547 MICFIL_VAD0_CTRL2_FRENDIS); 548 549 /* Assert the VADPREFEN bitfield. */ 550 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 551 MICFIL_VAD0_CTRL2_PREFEN); 552 553 /* Assert the VADSFILEN bitfield. */ 554 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 555 MICFIL_VAD0_SCONFIG_SFILEN); 556 557 /* Assert the VADSMAXEN bitfield. */ 558 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 559 MICFIL_VAD0_SCONFIG_SMAXEN); 560 561 /* Clear the VADNFILAUTO bitfield */ 562 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 563 MICFIL_VAD0_NCONFIG_NFILAUT); 564 565 /* Assert the VADNMINEN bitfield. */ 566 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 567 MICFIL_VAD0_NCONFIG_NMINEN); 568 569 /* Assert the VADNDECEN bitfield. */ 570 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 571 MICFIL_VAD0_NCONFIG_NDECEN); 572 573 /* Assert VADNOREN bitfield. */ 574 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 575 MICFIL_VAD0_NCONFIG_NOREN); 576 577 return 0; 578 } 579 580 /* 581 * Hardware Voice Active Detection: The HWVAD takes data from the input 582 * of a selected PDM microphone to detect if there is any 583 * voice activity. When a voice activity is detected, an interrupt could 584 * be delivered to the system. Initialization in section 8.4: 585 * Can work in two modes: 586 * -> Eneveope-based mode (section 8.4.1) 587 * -> Energy-based mode (section 8.4.2) 588 * 589 * It is important to remark that the HWVAD detector could be enabled 590 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 591 * bit in STAT register is cleared 592 */ 593 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 594 { 595 int ret; 596 597 micfil->vad_detected = 0; 598 599 /* envelope-based specific initialization */ 600 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 601 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 602 else 603 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 604 if (ret) 605 return ret; 606 607 /* Voice Activity Detector Internal Filters Initialization*/ 608 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 609 MICFIL_VAD0_CTRL1_ST10); 610 611 /* Voice Activity Detector Internal Filter */ 612 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 613 MICFIL_VAD0_CTRL1_ST10); 614 615 /* Enable Interrupts */ 616 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 617 if (ret) 618 return ret; 619 620 /* Voice Activity Detector Reset */ 621 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 622 MICFIL_VAD0_CTRL1_RST); 623 624 /* Voice Activity Detector Enabled */ 625 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 626 MICFIL_VAD0_CTRL1_EN); 627 628 return 0; 629 } 630 631 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 632 { 633 struct device *dev = &micfil->pdev->dev; 634 int ret = 0; 635 636 /* Disable HWVAD */ 637 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 638 MICFIL_VAD0_CTRL1_EN); 639 640 /* Disable hwvad interrupts */ 641 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 642 if (ret) 643 dev_err(dev, "Failed to disable interrupts\n"); 644 645 return ret; 646 } 647 648 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 649 struct snd_soc_dai *dai) 650 { 651 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 652 struct device *dev = &micfil->pdev->dev; 653 int ret; 654 655 switch (cmd) { 656 case SNDRV_PCM_TRIGGER_START: 657 case SNDRV_PCM_TRIGGER_RESUME: 658 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 659 ret = fsl_micfil_reset(dev); 660 if (ret) { 661 dev_err(dev, "failed to soft reset\n"); 662 return ret; 663 } 664 665 /* DMA Interrupt Selection - DISEL bits 666 * 00 - DMA and IRQ disabled 667 * 01 - DMA req enabled 668 * 10 - IRQ enabled 669 * 11 - reserved 670 */ 671 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 672 MICFIL_CTRL1_DISEL, 673 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 674 if (ret) 675 return ret; 676 677 /* Enable the module */ 678 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 679 MICFIL_CTRL1_PDMIEN); 680 if (ret) 681 return ret; 682 683 if (micfil->vad_enabled) 684 fsl_micfil_hwvad_enable(micfil); 685 686 break; 687 case SNDRV_PCM_TRIGGER_STOP: 688 case SNDRV_PCM_TRIGGER_SUSPEND: 689 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 690 if (micfil->vad_enabled) 691 fsl_micfil_hwvad_disable(micfil); 692 693 /* Disable the module */ 694 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 695 MICFIL_CTRL1_PDMIEN); 696 if (ret) 697 return ret; 698 699 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 700 MICFIL_CTRL1_DISEL, 701 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 702 if (ret) 703 return ret; 704 break; 705 default: 706 return -EINVAL; 707 } 708 return 0; 709 } 710 711 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 712 { 713 struct device *dev = &micfil->pdev->dev; 714 u64 ratio = sample_rate; 715 struct clk *clk; 716 int ret; 717 718 /* Get root clock */ 719 clk = micfil->mclk; 720 721 /* Disable clock first, for it was enabled by pm_runtime */ 722 clk_disable_unprepare(clk); 723 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 724 micfil->pll11k_clk, ratio); 725 ret = clk_prepare_enable(clk); 726 if (ret) 727 return ret; 728 729 return 0; 730 } 731 732 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 733 struct snd_pcm_hw_params *params, 734 struct snd_soc_dai *dai) 735 { 736 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 737 unsigned int channels = params_channels(params); 738 unsigned int rate = params_rate(params); 739 int clk_div = 8; 740 int osr = MICFIL_OSR_DEFAULT; 741 int ret; 742 743 /* 1. Disable the module */ 744 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 745 MICFIL_CTRL1_PDMIEN); 746 if (ret) 747 return ret; 748 749 /* enable channels */ 750 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 751 0xFF, ((1 << channels) - 1)); 752 if (ret) 753 return ret; 754 755 ret = fsl_micfil_reparent_rootclk(micfil, rate); 756 if (ret) 757 return ret; 758 759 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 760 if (ret) 761 return ret; 762 763 ret = micfil_set_quality(micfil); 764 if (ret) 765 return ret; 766 767 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 768 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 769 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 770 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr)); 771 772 /* Configure CIC OSR in VADCICOSR */ 773 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 774 MICFIL_VAD0_CTRL1_CICOSR, 775 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 776 777 /* Configure source channel in VADCHSEL */ 778 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 779 MICFIL_VAD0_CTRL1_CHSEL, 780 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 781 782 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 783 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 784 micfil->sdmacfg.n_fifos_src = channels; 785 micfil->sdmacfg.sw_done = true; 786 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 787 if (micfil->soc->use_edma) 788 micfil->dma_params_rx.maxburst = channels; 789 790 return 0; 791 } 792 793 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 794 { 795 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 796 struct device *dev = cpu_dai->dev; 797 unsigned int val = 0; 798 int ret, i; 799 800 micfil->quality = QUALITY_VLOW0; 801 micfil->card = cpu_dai->component->card; 802 803 /* set default gain to 2 */ 804 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 805 806 /* set DC Remover in bypass mode*/ 807 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 808 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 809 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 810 MICFIL_DC_CTRL_CONFIG, val); 811 if (ret) { 812 dev_err(dev, "failed to set DC Remover mode bits\n"); 813 return ret; 814 } 815 micfil->dc_remover = MICFIL_DC_BYPASS; 816 817 snd_soc_dai_init_dma_data(cpu_dai, NULL, 818 &micfil->dma_params_rx); 819 820 /* FIFO Watermark Control - FIFOWMK*/ 821 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 822 MICFIL_FIFO_CTRL_FIFOWMK, 823 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 824 if (ret) 825 return ret; 826 827 return 0; 828 } 829 830 static int fsl_micfil_component_probe(struct snd_soc_component *component) 831 { 832 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(component); 833 834 if (micfil->soc->volume_sx) 835 snd_soc_add_component_controls(component, fsl_micfil_volume_sx_controls, 836 ARRAY_SIZE(fsl_micfil_volume_sx_controls)); 837 else 838 snd_soc_add_component_controls(component, fsl_micfil_volume_controls, 839 ARRAY_SIZE(fsl_micfil_volume_controls)); 840 841 return 0; 842 } 843 844 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 845 .probe = fsl_micfil_dai_probe, 846 .startup = fsl_micfil_startup, 847 .trigger = fsl_micfil_trigger, 848 .hw_params = fsl_micfil_hw_params, 849 }; 850 851 static struct snd_soc_dai_driver fsl_micfil_dai = { 852 .capture = { 853 .stream_name = "CPU-Capture", 854 .channels_min = 1, 855 .channels_max = 8, 856 .rates = SNDRV_PCM_RATE_8000_48000, 857 .formats = SNDRV_PCM_FMTBIT_S16_LE, 858 }, 859 .ops = &fsl_micfil_dai_ops, 860 }; 861 862 static const struct snd_soc_component_driver fsl_micfil_component = { 863 .name = "fsl-micfil-dai", 864 .probe = fsl_micfil_component_probe, 865 .controls = fsl_micfil_snd_controls, 866 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 867 .legacy_dai_naming = 1, 868 }; 869 870 /* REGMAP */ 871 static const struct reg_default fsl_micfil_reg_defaults[] = { 872 {REG_MICFIL_CTRL1, 0x00000000}, 873 {REG_MICFIL_CTRL2, 0x00000000}, 874 {REG_MICFIL_STAT, 0x00000000}, 875 {REG_MICFIL_FIFO_CTRL, 0x00000007}, 876 {REG_MICFIL_FIFO_STAT, 0x00000000}, 877 {REG_MICFIL_DATACH0, 0x00000000}, 878 {REG_MICFIL_DATACH1, 0x00000000}, 879 {REG_MICFIL_DATACH2, 0x00000000}, 880 {REG_MICFIL_DATACH3, 0x00000000}, 881 {REG_MICFIL_DATACH4, 0x00000000}, 882 {REG_MICFIL_DATACH5, 0x00000000}, 883 {REG_MICFIL_DATACH6, 0x00000000}, 884 {REG_MICFIL_DATACH7, 0x00000000}, 885 {REG_MICFIL_DC_CTRL, 0x00000000}, 886 {REG_MICFIL_OUT_CTRL, 0x00000000}, 887 {REG_MICFIL_OUT_STAT, 0x00000000}, 888 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 889 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 890 {REG_MICFIL_VAD0_STAT, 0x00000000}, 891 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 892 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 893 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 894 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 895 }; 896 897 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 898 { 899 switch (reg) { 900 case REG_MICFIL_CTRL1: 901 case REG_MICFIL_CTRL2: 902 case REG_MICFIL_STAT: 903 case REG_MICFIL_FIFO_CTRL: 904 case REG_MICFIL_FIFO_STAT: 905 case REG_MICFIL_DATACH0: 906 case REG_MICFIL_DATACH1: 907 case REG_MICFIL_DATACH2: 908 case REG_MICFIL_DATACH3: 909 case REG_MICFIL_DATACH4: 910 case REG_MICFIL_DATACH5: 911 case REG_MICFIL_DATACH6: 912 case REG_MICFIL_DATACH7: 913 case REG_MICFIL_DC_CTRL: 914 case REG_MICFIL_OUT_CTRL: 915 case REG_MICFIL_OUT_STAT: 916 case REG_MICFIL_FSYNC_CTRL: 917 case REG_MICFIL_VERID: 918 case REG_MICFIL_PARAM: 919 case REG_MICFIL_VAD0_CTRL1: 920 case REG_MICFIL_VAD0_CTRL2: 921 case REG_MICFIL_VAD0_STAT: 922 case REG_MICFIL_VAD0_SCONFIG: 923 case REG_MICFIL_VAD0_NCONFIG: 924 case REG_MICFIL_VAD0_NDATA: 925 case REG_MICFIL_VAD0_ZCD: 926 return true; 927 default: 928 return false; 929 } 930 } 931 932 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 933 { 934 switch (reg) { 935 case REG_MICFIL_CTRL1: 936 case REG_MICFIL_CTRL2: 937 case REG_MICFIL_STAT: /* Write 1 to Clear */ 938 case REG_MICFIL_FIFO_CTRL: 939 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 940 case REG_MICFIL_DC_CTRL: 941 case REG_MICFIL_OUT_CTRL: 942 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 943 case REG_MICFIL_FSYNC_CTRL: 944 case REG_MICFIL_VAD0_CTRL1: 945 case REG_MICFIL_VAD0_CTRL2: 946 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 947 case REG_MICFIL_VAD0_SCONFIG: 948 case REG_MICFIL_VAD0_NCONFIG: 949 case REG_MICFIL_VAD0_ZCD: 950 return true; 951 default: 952 return false; 953 } 954 } 955 956 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 957 { 958 switch (reg) { 959 case REG_MICFIL_STAT: 960 case REG_MICFIL_DATACH0: 961 case REG_MICFIL_DATACH1: 962 case REG_MICFIL_DATACH2: 963 case REG_MICFIL_DATACH3: 964 case REG_MICFIL_DATACH4: 965 case REG_MICFIL_DATACH5: 966 case REG_MICFIL_DATACH6: 967 case REG_MICFIL_DATACH7: 968 case REG_MICFIL_VERID: 969 case REG_MICFIL_PARAM: 970 case REG_MICFIL_VAD0_STAT: 971 case REG_MICFIL_VAD0_NDATA: 972 return true; 973 default: 974 return false; 975 } 976 } 977 978 static const struct regmap_config fsl_micfil_regmap_config = { 979 .reg_bits = 32, 980 .reg_stride = 4, 981 .val_bits = 32, 982 983 .max_register = REG_MICFIL_VAD0_ZCD, 984 .reg_defaults = fsl_micfil_reg_defaults, 985 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 986 .readable_reg = fsl_micfil_readable_reg, 987 .volatile_reg = fsl_micfil_volatile_reg, 988 .writeable_reg = fsl_micfil_writeable_reg, 989 .cache_type = REGCACHE_RBTREE, 990 }; 991 992 /* END OF REGMAP */ 993 994 static irqreturn_t micfil_isr(int irq, void *devid) 995 { 996 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 997 struct platform_device *pdev = micfil->pdev; 998 u32 stat_reg; 999 u32 fifo_stat_reg; 1000 u32 ctrl1_reg; 1001 bool dma_enabled; 1002 int i; 1003 1004 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1005 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 1006 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 1007 1008 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 1009 1010 /* Channel 0-7 Output Data Flags */ 1011 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 1012 if (stat_reg & MICFIL_STAT_CHXF(i)) 1013 dev_dbg(&pdev->dev, 1014 "Data available in Data Channel %d\n", i); 1015 /* if DMA is not enabled, field must be written with 1 1016 * to clear 1017 */ 1018 if (!dma_enabled) 1019 regmap_write_bits(micfil->regmap, 1020 REG_MICFIL_STAT, 1021 MICFIL_STAT_CHXF(i), 1022 1); 1023 } 1024 1025 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 1026 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 1027 dev_dbg(&pdev->dev, 1028 "FIFO Overflow Exception flag for channel %d\n", 1029 i); 1030 1031 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 1032 dev_dbg(&pdev->dev, 1033 "FIFO Underflow Exception flag for channel %d\n", 1034 i); 1035 } 1036 1037 return IRQ_HANDLED; 1038 } 1039 1040 static irqreturn_t micfil_err_isr(int irq, void *devid) 1041 { 1042 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1043 struct platform_device *pdev = micfil->pdev; 1044 u32 stat_reg; 1045 1046 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 1047 1048 if (stat_reg & MICFIL_STAT_BSY_FIL) 1049 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 1050 1051 if (stat_reg & MICFIL_STAT_FIR_RDY) 1052 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 1053 1054 if (stat_reg & MICFIL_STAT_LOWFREQF) { 1055 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 1056 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 1057 MICFIL_STAT_LOWFREQF, 1); 1058 } 1059 1060 return IRQ_HANDLED; 1061 } 1062 1063 static irqreturn_t voice_detected_fn(int irq, void *devid) 1064 { 1065 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1066 struct snd_kcontrol *kctl; 1067 1068 if (!micfil->card) 1069 return IRQ_HANDLED; 1070 1071 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 1072 if (!kctl) 1073 return IRQ_HANDLED; 1074 1075 if (micfil->vad_detected) 1076 snd_ctl_notify(micfil->card->snd_card, 1077 SNDRV_CTL_EVENT_MASK_VALUE, 1078 &kctl->id); 1079 1080 return IRQ_HANDLED; 1081 } 1082 1083 static irqreturn_t hwvad_isr(int irq, void *devid) 1084 { 1085 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1086 struct device *dev = &micfil->pdev->dev; 1087 u32 vad0_reg; 1088 int ret; 1089 1090 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1091 1092 /* 1093 * The only difference between MICFIL_VAD0_STAT_EF and 1094 * MICFIL_VAD0_STAT_IF is that the former requires Write 1095 * 1 to Clear. Since both flags are set, it is enough 1096 * to only read one of them 1097 */ 1098 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 1099 /* Write 1 to clear */ 1100 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 1101 MICFIL_VAD0_STAT_IF, 1102 MICFIL_VAD0_STAT_IF); 1103 1104 micfil->vad_detected = 1; 1105 } 1106 1107 ret = fsl_micfil_hwvad_disable(micfil); 1108 if (ret) 1109 dev_err(dev, "Failed to disable hwvad\n"); 1110 1111 return IRQ_WAKE_THREAD; 1112 } 1113 1114 static irqreturn_t hwvad_err_isr(int irq, void *devid) 1115 { 1116 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1117 struct device *dev = &micfil->pdev->dev; 1118 u32 vad0_reg; 1119 1120 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1121 1122 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 1123 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 1124 1125 return IRQ_HANDLED; 1126 } 1127 1128 static int fsl_micfil_runtime_suspend(struct device *dev); 1129 static int fsl_micfil_runtime_resume(struct device *dev); 1130 1131 static int fsl_micfil_probe(struct platform_device *pdev) 1132 { 1133 struct device_node *np = pdev->dev.of_node; 1134 struct fsl_micfil *micfil; 1135 struct resource *res; 1136 void __iomem *regs; 1137 int ret, i; 1138 1139 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1140 if (!micfil) 1141 return -ENOMEM; 1142 1143 micfil->pdev = pdev; 1144 strscpy(micfil->name, np->name, sizeof(micfil->name)); 1145 1146 micfil->soc = of_device_get_match_data(&pdev->dev); 1147 1148 /* ipg_clk is used to control the registers 1149 * ipg_clk_app is used to operate the filter 1150 */ 1151 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1152 if (IS_ERR(micfil->mclk)) { 1153 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1154 PTR_ERR(micfil->mclk)); 1155 return PTR_ERR(micfil->mclk); 1156 } 1157 1158 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1159 if (IS_ERR(micfil->busclk)) { 1160 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1161 PTR_ERR(micfil->busclk)); 1162 return PTR_ERR(micfil->busclk); 1163 } 1164 1165 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1166 &micfil->pll11k_clk); 1167 1168 /* init regmap */ 1169 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1170 if (IS_ERR(regs)) 1171 return PTR_ERR(regs); 1172 1173 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1174 regs, 1175 &fsl_micfil_regmap_config); 1176 if (IS_ERR(micfil->regmap)) { 1177 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1178 PTR_ERR(micfil->regmap)); 1179 return PTR_ERR(micfil->regmap); 1180 } 1181 1182 /* dataline mask for RX */ 1183 ret = of_property_read_u32_index(np, 1184 "fsl,dataline", 1185 0, 1186 &micfil->dataline); 1187 if (ret) 1188 micfil->dataline = 1; 1189 1190 if (micfil->dataline & ~micfil->soc->dataline) { 1191 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1192 micfil->soc->dataline); 1193 return -EINVAL; 1194 } 1195 1196 /* get IRQs */ 1197 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1198 micfil->irq[i] = platform_get_irq(pdev, i); 1199 if (micfil->irq[i] < 0) 1200 return micfil->irq[i]; 1201 } 1202 1203 /* Digital Microphone interface interrupt */ 1204 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1205 micfil_isr, IRQF_SHARED, 1206 micfil->name, micfil); 1207 if (ret) { 1208 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1209 micfil->irq[0]); 1210 return ret; 1211 } 1212 1213 /* Digital Microphone interface error interrupt */ 1214 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1215 micfil_err_isr, IRQF_SHARED, 1216 micfil->name, micfil); 1217 if (ret) { 1218 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1219 micfil->irq[1]); 1220 return ret; 1221 } 1222 1223 /* Digital Microphone interface voice activity detector event */ 1224 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1225 hwvad_isr, voice_detected_fn, 1226 IRQF_SHARED, micfil->name, micfil); 1227 if (ret) { 1228 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1229 micfil->irq[0]); 1230 return ret; 1231 } 1232 1233 /* Digital Microphone interface voice activity detector error */ 1234 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1235 hwvad_err_isr, IRQF_SHARED, 1236 micfil->name, micfil); 1237 if (ret) { 1238 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1239 micfil->irq[1]); 1240 return ret; 1241 } 1242 1243 micfil->dma_params_rx.chan_name = "rx"; 1244 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; 1245 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1246 1247 platform_set_drvdata(pdev, micfil); 1248 1249 pm_runtime_enable(&pdev->dev); 1250 if (!pm_runtime_enabled(&pdev->dev)) { 1251 ret = fsl_micfil_runtime_resume(&pdev->dev); 1252 if (ret) 1253 goto err_pm_disable; 1254 } 1255 1256 ret = pm_runtime_resume_and_get(&pdev->dev); 1257 if (ret < 0) 1258 goto err_pm_get_sync; 1259 1260 /* Get micfil version */ 1261 ret = fsl_micfil_use_verid(&pdev->dev); 1262 if (ret < 0) 1263 dev_warn(&pdev->dev, "Error reading MICFIL version: %d\n", ret); 1264 1265 ret = pm_runtime_put_sync(&pdev->dev); 1266 if (ret < 0 && ret != -ENOSYS) 1267 goto err_pm_get_sync; 1268 1269 regcache_cache_only(micfil->regmap, true); 1270 1271 /* 1272 * Register platform component before registering cpu dai for there 1273 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1274 */ 1275 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1276 if (ret) { 1277 dev_err(&pdev->dev, "failed to pcm register\n"); 1278 goto err_pm_disable; 1279 } 1280 1281 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1282 1283 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1284 &fsl_micfil_dai, 1); 1285 if (ret) { 1286 dev_err(&pdev->dev, "failed to register component %s\n", 1287 fsl_micfil_component.name); 1288 goto err_pm_disable; 1289 } 1290 1291 return ret; 1292 1293 err_pm_get_sync: 1294 if (!pm_runtime_status_suspended(&pdev->dev)) 1295 fsl_micfil_runtime_suspend(&pdev->dev); 1296 err_pm_disable: 1297 pm_runtime_disable(&pdev->dev); 1298 1299 return ret; 1300 } 1301 1302 static void fsl_micfil_remove(struct platform_device *pdev) 1303 { 1304 pm_runtime_disable(&pdev->dev); 1305 } 1306 1307 static int fsl_micfil_runtime_suspend(struct device *dev) 1308 { 1309 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1310 1311 regcache_cache_only(micfil->regmap, true); 1312 1313 clk_disable_unprepare(micfil->mclk); 1314 clk_disable_unprepare(micfil->busclk); 1315 1316 return 0; 1317 } 1318 1319 static int fsl_micfil_runtime_resume(struct device *dev) 1320 { 1321 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1322 int ret; 1323 1324 ret = clk_prepare_enable(micfil->busclk); 1325 if (ret < 0) 1326 return ret; 1327 1328 ret = clk_prepare_enable(micfil->mclk); 1329 if (ret < 0) { 1330 clk_disable_unprepare(micfil->busclk); 1331 return ret; 1332 } 1333 1334 regcache_cache_only(micfil->regmap, false); 1335 regcache_mark_dirty(micfil->regmap); 1336 regcache_sync(micfil->regmap); 1337 1338 return 0; 1339 } 1340 1341 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1342 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 1343 fsl_micfil_runtime_resume, 1344 NULL) 1345 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1346 pm_runtime_force_resume) 1347 }; 1348 1349 static struct platform_driver fsl_micfil_driver = { 1350 .probe = fsl_micfil_probe, 1351 .remove_new = fsl_micfil_remove, 1352 .driver = { 1353 .name = "fsl-micfil-dai", 1354 .pm = &fsl_micfil_pm_ops, 1355 .of_match_table = fsl_micfil_dt_ids, 1356 }, 1357 }; 1358 module_platform_driver(fsl_micfil_driver); 1359 1360 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1361 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1362 MODULE_LICENSE("Dual BSD/GPL"); 1363