1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 #include "fsl_utils.h" 28 29 #define MICFIL_OSR_DEFAULT 16 30 31 enum quality { 32 QUALITY_HIGH, 33 QUALITY_MEDIUM, 34 QUALITY_LOW, 35 QUALITY_VLOW0, 36 QUALITY_VLOW1, 37 QUALITY_VLOW2, 38 }; 39 40 struct fsl_micfil { 41 struct platform_device *pdev; 42 struct regmap *regmap; 43 const struct fsl_micfil_soc_data *soc; 44 struct clk *busclk; 45 struct clk *mclk; 46 struct clk *pll8k_clk; 47 struct clk *pll11k_clk; 48 struct snd_dmaengine_dai_dma_data dma_params_rx; 49 struct sdma_peripheral_config sdmacfg; 50 struct snd_soc_card *card; 51 unsigned int dataline; 52 char name[32]; 53 int irq[MICFIL_IRQ_LINES]; 54 enum quality quality; 55 int dc_remover; 56 int vad_init_mode; 57 int vad_enabled; 58 int vad_detected; 59 }; 60 61 struct fsl_micfil_soc_data { 62 unsigned int fifos; 63 unsigned int fifo_depth; 64 unsigned int dataline; 65 bool imx; 66 bool use_edma; 67 u64 formats; 68 }; 69 70 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 71 .imx = true, 72 .fifos = 8, 73 .fifo_depth = 8, 74 .dataline = 0xf, 75 .formats = SNDRV_PCM_FMTBIT_S16_LE, 76 }; 77 78 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 79 .imx = true, 80 .fifos = 8, 81 .fifo_depth = 32, 82 .dataline = 0xf, 83 .formats = SNDRV_PCM_FMTBIT_S32_LE, 84 }; 85 86 static struct fsl_micfil_soc_data fsl_micfil_imx93 = { 87 .imx = true, 88 .fifos = 8, 89 .fifo_depth = 32, 90 .dataline = 0xf, 91 .formats = SNDRV_PCM_FMTBIT_S32_LE, 92 .use_edma = true, 93 }; 94 95 static const struct of_device_id fsl_micfil_dt_ids[] = { 96 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 97 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 98 { .compatible = "fsl,imx93-micfil", .data = &fsl_micfil_imx93 }, 99 {} 100 }; 101 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 102 103 static const char * const micfil_quality_select_texts[] = { 104 [QUALITY_HIGH] = "High", 105 [QUALITY_MEDIUM] = "Medium", 106 [QUALITY_LOW] = "Low", 107 [QUALITY_VLOW0] = "VLow0", 108 [QUALITY_VLOW1] = "Vlow1", 109 [QUALITY_VLOW2] = "Vlow2", 110 }; 111 112 static const struct soc_enum fsl_micfil_quality_enum = 113 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 114 micfil_quality_select_texts); 115 116 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 117 118 static int micfil_set_quality(struct fsl_micfil *micfil) 119 { 120 u32 qsel; 121 122 switch (micfil->quality) { 123 case QUALITY_HIGH: 124 qsel = MICFIL_QSEL_HIGH_QUALITY; 125 break; 126 case QUALITY_MEDIUM: 127 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 128 break; 129 case QUALITY_LOW: 130 qsel = MICFIL_QSEL_LOW_QUALITY; 131 break; 132 case QUALITY_VLOW0: 133 qsel = MICFIL_QSEL_VLOW0_QUALITY; 134 break; 135 case QUALITY_VLOW1: 136 qsel = MICFIL_QSEL_VLOW1_QUALITY; 137 break; 138 case QUALITY_VLOW2: 139 qsel = MICFIL_QSEL_VLOW2_QUALITY; 140 break; 141 } 142 143 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 144 MICFIL_CTRL2_QSEL, 145 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 146 } 147 148 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 149 struct snd_ctl_elem_value *ucontrol) 150 { 151 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 152 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 153 154 ucontrol->value.integer.value[0] = micfil->quality; 155 156 return 0; 157 } 158 159 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 160 struct snd_ctl_elem_value *ucontrol) 161 { 162 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 163 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 164 165 micfil->quality = ucontrol->value.integer.value[0]; 166 167 return micfil_set_quality(micfil); 168 } 169 170 static const char * const micfil_hwvad_enable[] = { 171 "Disable (Record only)", 172 "Enable (Record with Vad)", 173 }; 174 175 static const char * const micfil_hwvad_init_mode[] = { 176 "Envelope mode", "Energy mode", 177 }; 178 179 static const char * const micfil_hwvad_hpf_texts[] = { 180 "Filter bypass", 181 "Cut-off @1750Hz", 182 "Cut-off @215Hz", 183 "Cut-off @102Hz", 184 }; 185 186 /* 187 * DC Remover Control 188 * Filter Bypassed 1 1 189 * Cut-off @21Hz 0 0 190 * Cut-off @83Hz 0 1 191 * Cut-off @152HZ 1 0 192 */ 193 static const char * const micfil_dc_remover_texts[] = { 194 "Cut-off @21Hz", "Cut-off @83Hz", 195 "Cut-off @152Hz", "Bypass", 196 }; 197 198 static const struct soc_enum hwvad_enable_enum = 199 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable), 200 micfil_hwvad_enable); 201 static const struct soc_enum hwvad_init_mode_enum = 202 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_init_mode), 203 micfil_hwvad_init_mode); 204 static const struct soc_enum hwvad_hpf_enum = 205 SOC_ENUM_SINGLE(REG_MICFIL_VAD0_CTRL2, 0, 206 ARRAY_SIZE(micfil_hwvad_hpf_texts), 207 micfil_hwvad_hpf_texts); 208 static const struct soc_enum fsl_micfil_dc_remover_enum = 209 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts), 210 micfil_dc_remover_texts); 211 212 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol, 213 struct snd_ctl_elem_value *ucontrol) 214 { 215 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 216 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 217 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 218 unsigned int *item = ucontrol->value.enumerated.item; 219 int val = snd_soc_enum_item_to_val(e, item[0]); 220 int i = 0, ret = 0; 221 u32 reg_val = 0; 222 223 if (val < 0 || val > 3) 224 return -EINVAL; 225 226 micfil->dc_remover = val; 227 228 /* Calculate total value for all channels */ 229 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 230 reg_val |= val << MICFIL_DC_CHX_SHIFT(i); 231 232 /* Update DC Remover mode for all channels */ 233 ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_CTRL, 234 MICFIL_DC_CTRL_CONFIG, reg_val); 235 if (ret < 0) 236 return ret; 237 238 return 0; 239 } 240 241 static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol, 242 struct snd_ctl_elem_value *ucontrol) 243 { 244 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 245 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 246 247 ucontrol->value.enumerated.item[0] = micfil->dc_remover; 248 249 return 0; 250 } 251 252 static int hwvad_put_enable(struct snd_kcontrol *kcontrol, 253 struct snd_ctl_elem_value *ucontrol) 254 { 255 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 256 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 257 unsigned int *item = ucontrol->value.enumerated.item; 258 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 259 int val = snd_soc_enum_item_to_val(e, item[0]); 260 261 micfil->vad_enabled = val; 262 263 return 0; 264 } 265 266 static int hwvad_get_enable(struct snd_kcontrol *kcontrol, 267 struct snd_ctl_elem_value *ucontrol) 268 { 269 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 270 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 271 272 ucontrol->value.enumerated.item[0] = micfil->vad_enabled; 273 274 return 0; 275 } 276 277 static int hwvad_put_init_mode(struct snd_kcontrol *kcontrol, 278 struct snd_ctl_elem_value *ucontrol) 279 { 280 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 281 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 282 unsigned int *item = ucontrol->value.enumerated.item; 283 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 284 int val = snd_soc_enum_item_to_val(e, item[0]); 285 286 /* 0 - Envelope-based Mode 287 * 1 - Energy-based Mode 288 */ 289 micfil->vad_init_mode = val; 290 291 return 0; 292 } 293 294 static int hwvad_get_init_mode(struct snd_kcontrol *kcontrol, 295 struct snd_ctl_elem_value *ucontrol) 296 { 297 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 298 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 299 300 ucontrol->value.enumerated.item[0] = micfil->vad_init_mode; 301 302 return 0; 303 } 304 305 static int hwvad_detected(struct snd_kcontrol *kcontrol, 306 struct snd_ctl_elem_value *ucontrol) 307 { 308 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 309 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp); 310 311 ucontrol->value.enumerated.item[0] = micfil->vad_detected; 312 313 return 0; 314 } 315 316 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 317 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 318 MICFIL_OUTGAIN_CHX_SHIFT(0), 0x8, 0xF, gain_tlv), 319 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 320 MICFIL_OUTGAIN_CHX_SHIFT(1), 0x8, 0xF, gain_tlv), 321 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 322 MICFIL_OUTGAIN_CHX_SHIFT(2), 0x8, 0xF, gain_tlv), 323 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 324 MICFIL_OUTGAIN_CHX_SHIFT(3), 0x8, 0xF, gain_tlv), 325 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 326 MICFIL_OUTGAIN_CHX_SHIFT(4), 0x8, 0xF, gain_tlv), 327 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 328 MICFIL_OUTGAIN_CHX_SHIFT(5), 0x8, 0xF, gain_tlv), 329 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 330 MICFIL_OUTGAIN_CHX_SHIFT(6), 0x8, 0xF, gain_tlv), 331 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 332 MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv), 333 SOC_ENUM_EXT("MICFIL Quality Select", 334 fsl_micfil_quality_enum, 335 micfil_quality_get, micfil_quality_set), 336 SOC_ENUM_EXT("HWVAD Enablement Switch", hwvad_enable_enum, 337 hwvad_get_enable, hwvad_put_enable), 338 SOC_ENUM_EXT("HWVAD Initialization Mode", hwvad_init_mode_enum, 339 hwvad_get_init_mode, hwvad_put_init_mode), 340 SOC_ENUM("HWVAD High-Pass Filter", hwvad_hpf_enum), 341 SOC_SINGLE("HWVAD ZCD Switch", REG_MICFIL_VAD0_ZCD, 0, 1, 0), 342 SOC_SINGLE("HWVAD ZCD Auto Threshold Switch", 343 REG_MICFIL_VAD0_ZCD, 2, 1, 0), 344 SOC_ENUM_EXT("MICFIL DC Remover Control", fsl_micfil_dc_remover_enum, 345 micfil_get_dc_remover_state, micfil_put_dc_remover_state), 346 SOC_SINGLE("HWVAD Input Gain", REG_MICFIL_VAD0_CTRL2, 8, 15, 0), 347 SOC_SINGLE("HWVAD Sound Gain", REG_MICFIL_VAD0_SCONFIG, 0, 15, 0), 348 SOC_SINGLE("HWVAD Noise Gain", REG_MICFIL_VAD0_NCONFIG, 0, 15, 0), 349 SOC_SINGLE_RANGE("HWVAD Detector Frame Time", REG_MICFIL_VAD0_CTRL2, 16, 0, 63, 0), 350 SOC_SINGLE("HWVAD Detector Initialization Time", REG_MICFIL_VAD0_CTRL1, 8, 31, 0), 351 SOC_SINGLE("HWVAD Noise Filter Adjustment", REG_MICFIL_VAD0_NCONFIG, 8, 31, 0), 352 SOC_SINGLE("HWVAD ZCD Threshold", REG_MICFIL_VAD0_ZCD, 16, 1023, 0), 353 SOC_SINGLE("HWVAD ZCD Adjustment", REG_MICFIL_VAD0_ZCD, 8, 15, 0), 354 SOC_SINGLE("HWVAD ZCD And Behavior Switch", 355 REG_MICFIL_VAD0_ZCD, 4, 1, 0), 356 SOC_SINGLE_BOOL_EXT("VAD Detected", 0, hwvad_detected, NULL), 357 }; 358 359 /* The SRES is a self-negated bit which provides the CPU with the 360 * capability to initialize the PDM Interface module through the 361 * slave-bus interface. This bit always reads as zero, and this 362 * bit is only effective when MDIS is cleared 363 */ 364 static int fsl_micfil_reset(struct device *dev) 365 { 366 struct fsl_micfil *micfil = dev_get_drvdata(dev); 367 int ret; 368 369 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 370 MICFIL_CTRL1_MDIS); 371 if (ret) 372 return ret; 373 374 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 375 MICFIL_CTRL1_SRES); 376 if (ret) 377 return ret; 378 379 /* 380 * SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined 381 * as non-volatile register, so SRES still remain in regmap 382 * cache after set, that every update of REG_MICFIL_CTRL1, 383 * software reset happens. so clear it explicitly. 384 */ 385 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 386 MICFIL_CTRL1_SRES); 387 if (ret) 388 return ret; 389 390 /* 391 * Set SRES should clear CHnF flags, But even add delay here 392 * the CHnF may not be cleared sometimes, so clear CHnF explicitly. 393 */ 394 ret = regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 0xFF, 0xFF); 395 if (ret) 396 return ret; 397 398 return 0; 399 } 400 401 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 402 struct snd_soc_dai *dai) 403 { 404 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 405 406 if (!micfil) { 407 dev_err(dai->dev, "micfil dai priv_data not set\n"); 408 return -EINVAL; 409 } 410 411 return 0; 412 } 413 414 /* Enable/disable hwvad interrupts */ 415 static int fsl_micfil_configure_hwvad_interrupts(struct fsl_micfil *micfil, int enable) 416 { 417 u32 vadie_reg = enable ? MICFIL_VAD0_CTRL1_IE : 0; 418 u32 vaderie_reg = enable ? MICFIL_VAD0_CTRL1_ERIE : 0; 419 420 /* Voice Activity Detector Error Interruption */ 421 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 422 MICFIL_VAD0_CTRL1_ERIE, vaderie_reg); 423 424 /* Voice Activity Detector Interruption */ 425 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 426 MICFIL_VAD0_CTRL1_IE, vadie_reg); 427 428 return 0; 429 } 430 431 /* Configuration done only in energy-based initialization mode */ 432 static int fsl_micfil_init_hwvad_energy_mode(struct fsl_micfil *micfil) 433 { 434 /* Keep the VADFRENDIS bitfield cleared. */ 435 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 436 MICFIL_VAD0_CTRL2_FRENDIS); 437 438 /* Keep the VADPREFEN bitfield cleared. */ 439 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 440 MICFIL_VAD0_CTRL2_PREFEN); 441 442 /* Keep the VADSFILEN bitfield cleared. */ 443 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 444 MICFIL_VAD0_SCONFIG_SFILEN); 445 446 /* Keep the VADSMAXEN bitfield cleared. */ 447 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 448 MICFIL_VAD0_SCONFIG_SMAXEN); 449 450 /* Keep the VADNFILAUTO bitfield asserted. */ 451 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 452 MICFIL_VAD0_NCONFIG_NFILAUT); 453 454 /* Keep the VADNMINEN bitfield cleared. */ 455 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 456 MICFIL_VAD0_NCONFIG_NMINEN); 457 458 /* Keep the VADNDECEN bitfield cleared. */ 459 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 460 MICFIL_VAD0_NCONFIG_NDECEN); 461 462 /* Keep the VADNOREN bitfield cleared. */ 463 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 464 MICFIL_VAD0_NCONFIG_NOREN); 465 466 return 0; 467 } 468 469 /* Configuration done only in envelope-based initialization mode */ 470 static int fsl_micfil_init_hwvad_envelope_mode(struct fsl_micfil *micfil) 471 { 472 /* Assert the VADFRENDIS bitfield */ 473 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 474 MICFIL_VAD0_CTRL2_FRENDIS); 475 476 /* Assert the VADPREFEN bitfield. */ 477 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, 478 MICFIL_VAD0_CTRL2_PREFEN); 479 480 /* Assert the VADSFILEN bitfield. */ 481 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 482 MICFIL_VAD0_SCONFIG_SFILEN); 483 484 /* Assert the VADSMAXEN bitfield. */ 485 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, 486 MICFIL_VAD0_SCONFIG_SMAXEN); 487 488 /* Clear the VADNFILAUTO bitfield */ 489 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 490 MICFIL_VAD0_NCONFIG_NFILAUT); 491 492 /* Assert the VADNMINEN bitfield. */ 493 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 494 MICFIL_VAD0_NCONFIG_NMINEN); 495 496 /* Assert the VADNDECEN bitfield. */ 497 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 498 MICFIL_VAD0_NCONFIG_NDECEN); 499 500 /* Assert VADNOREN bitfield. */ 501 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, 502 MICFIL_VAD0_NCONFIG_NOREN); 503 504 return 0; 505 } 506 507 /* 508 * Hardware Voice Active Detection: The HWVAD takes data from the input 509 * of a selected PDM microphone to detect if there is any 510 * voice activity. When a voice activity is detected, an interrupt could 511 * be delivered to the system. Initialization in section 8.4: 512 * Can work in two modes: 513 * -> Eneveope-based mode (section 8.4.1) 514 * -> Energy-based mode (section 8.4.2) 515 * 516 * It is important to remark that the HWVAD detector could be enabled 517 * or reset only when the MICFIL isn't running i.e. when the BSY_FIL 518 * bit in STAT register is cleared 519 */ 520 static int fsl_micfil_hwvad_enable(struct fsl_micfil *micfil) 521 { 522 int ret; 523 524 micfil->vad_detected = 0; 525 526 /* envelope-based specific initialization */ 527 if (micfil->vad_init_mode == MICFIL_HWVAD_ENVELOPE_MODE) 528 ret = fsl_micfil_init_hwvad_envelope_mode(micfil); 529 else 530 ret = fsl_micfil_init_hwvad_energy_mode(micfil); 531 if (ret) 532 return ret; 533 534 /* Voice Activity Detector Internal Filters Initialization*/ 535 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 536 MICFIL_VAD0_CTRL1_ST10); 537 538 /* Voice Activity Detector Internal Filter */ 539 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 540 MICFIL_VAD0_CTRL1_ST10); 541 542 /* Enable Interrupts */ 543 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 1); 544 if (ret) 545 return ret; 546 547 /* Voice Activity Detector Reset */ 548 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 549 MICFIL_VAD0_CTRL1_RST); 550 551 /* Voice Activity Detector Enabled */ 552 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 553 MICFIL_VAD0_CTRL1_EN); 554 555 return 0; 556 } 557 558 static int fsl_micfil_hwvad_disable(struct fsl_micfil *micfil) 559 { 560 struct device *dev = &micfil->pdev->dev; 561 int ret = 0; 562 563 /* Disable HWVAD */ 564 regmap_clear_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 565 MICFIL_VAD0_CTRL1_EN); 566 567 /* Disable hwvad interrupts */ 568 ret = fsl_micfil_configure_hwvad_interrupts(micfil, 0); 569 if (ret) 570 dev_err(dev, "Failed to disable interrupts\n"); 571 572 return ret; 573 } 574 575 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 576 struct snd_soc_dai *dai) 577 { 578 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 579 struct device *dev = &micfil->pdev->dev; 580 int ret; 581 582 switch (cmd) { 583 case SNDRV_PCM_TRIGGER_START: 584 case SNDRV_PCM_TRIGGER_RESUME: 585 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 586 ret = fsl_micfil_reset(dev); 587 if (ret) { 588 dev_err(dev, "failed to soft reset\n"); 589 return ret; 590 } 591 592 /* DMA Interrupt Selection - DISEL bits 593 * 00 - DMA and IRQ disabled 594 * 01 - DMA req enabled 595 * 10 - IRQ enabled 596 * 11 - reserved 597 */ 598 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 599 MICFIL_CTRL1_DISEL, 600 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 601 if (ret) 602 return ret; 603 604 /* Enable the module */ 605 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 606 MICFIL_CTRL1_PDMIEN); 607 if (ret) 608 return ret; 609 610 if (micfil->vad_enabled) 611 fsl_micfil_hwvad_enable(micfil); 612 613 break; 614 case SNDRV_PCM_TRIGGER_STOP: 615 case SNDRV_PCM_TRIGGER_SUSPEND: 616 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 617 if (micfil->vad_enabled) 618 fsl_micfil_hwvad_disable(micfil); 619 620 /* Disable the module */ 621 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 622 MICFIL_CTRL1_PDMIEN); 623 if (ret) 624 return ret; 625 626 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 627 MICFIL_CTRL1_DISEL, 628 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 629 if (ret) 630 return ret; 631 break; 632 default: 633 return -EINVAL; 634 } 635 return 0; 636 } 637 638 static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned int sample_rate) 639 { 640 struct device *dev = &micfil->pdev->dev; 641 u64 ratio = sample_rate; 642 struct clk *clk; 643 int ret; 644 645 /* Get root clock */ 646 clk = micfil->mclk; 647 648 /* Disable clock first, for it was enabled by pm_runtime */ 649 clk_disable_unprepare(clk); 650 fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, 651 micfil->pll11k_clk, ratio); 652 ret = clk_prepare_enable(clk); 653 if (ret) 654 return ret; 655 656 return 0; 657 } 658 659 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 660 struct snd_pcm_hw_params *params, 661 struct snd_soc_dai *dai) 662 { 663 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 664 unsigned int channels = params_channels(params); 665 unsigned int rate = params_rate(params); 666 int clk_div = 8; 667 int osr = MICFIL_OSR_DEFAULT; 668 int ret; 669 670 /* 1. Disable the module */ 671 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 672 MICFIL_CTRL1_PDMIEN); 673 if (ret) 674 return ret; 675 676 /* enable channels */ 677 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 678 0xFF, ((1 << channels) - 1)); 679 if (ret) 680 return ret; 681 682 ret = fsl_micfil_reparent_rootclk(micfil, rate); 683 if (ret) 684 return ret; 685 686 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 687 if (ret) 688 return ret; 689 690 ret = micfil_set_quality(micfil); 691 if (ret) 692 return ret; 693 694 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 695 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 696 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 697 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr)); 698 699 /* Configure CIC OSR in VADCICOSR */ 700 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 701 MICFIL_VAD0_CTRL1_CICOSR, 702 FIELD_PREP(MICFIL_VAD0_CTRL1_CICOSR, 16 - osr)); 703 704 /* Configure source channel in VADCHSEL */ 705 regmap_update_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, 706 MICFIL_VAD0_CTRL1_CHSEL, 707 FIELD_PREP(MICFIL_VAD0_CTRL1_CHSEL, (channels - 1))); 708 709 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 710 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 711 micfil->sdmacfg.n_fifos_src = channels; 712 micfil->sdmacfg.sw_done = true; 713 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 714 if (micfil->soc->use_edma) 715 micfil->dma_params_rx.maxburst = channels; 716 717 return 0; 718 } 719 720 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 721 .startup = fsl_micfil_startup, 722 .trigger = fsl_micfil_trigger, 723 .hw_params = fsl_micfil_hw_params, 724 }; 725 726 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 727 { 728 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 729 struct device *dev = cpu_dai->dev; 730 unsigned int val = 0; 731 int ret, i; 732 733 micfil->quality = QUALITY_VLOW0; 734 micfil->card = cpu_dai->component->card; 735 736 /* set default gain to 2 */ 737 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); 738 739 /* set DC Remover in bypass mode*/ 740 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) 741 val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); 742 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, 743 MICFIL_DC_CTRL_CONFIG, val); 744 if (ret) { 745 dev_err(dev, "failed to set DC Remover mode bits\n"); 746 return ret; 747 } 748 micfil->dc_remover = MICFIL_DC_BYPASS; 749 750 snd_soc_dai_init_dma_data(cpu_dai, NULL, 751 &micfil->dma_params_rx); 752 753 /* FIFO Watermark Control - FIFOWMK*/ 754 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 755 MICFIL_FIFO_CTRL_FIFOWMK, 756 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 757 if (ret) 758 return ret; 759 760 return 0; 761 } 762 763 static struct snd_soc_dai_driver fsl_micfil_dai = { 764 .probe = fsl_micfil_dai_probe, 765 .capture = { 766 .stream_name = "CPU-Capture", 767 .channels_min = 1, 768 .channels_max = 8, 769 .rates = SNDRV_PCM_RATE_8000_48000, 770 .formats = SNDRV_PCM_FMTBIT_S16_LE, 771 }, 772 .ops = &fsl_micfil_dai_ops, 773 }; 774 775 static const struct snd_soc_component_driver fsl_micfil_component = { 776 .name = "fsl-micfil-dai", 777 .controls = fsl_micfil_snd_controls, 778 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 779 .legacy_dai_naming = 1, 780 }; 781 782 /* REGMAP */ 783 static const struct reg_default fsl_micfil_reg_defaults[] = { 784 {REG_MICFIL_CTRL1, 0x00000000}, 785 {REG_MICFIL_CTRL2, 0x00000000}, 786 {REG_MICFIL_STAT, 0x00000000}, 787 {REG_MICFIL_FIFO_CTRL, 0x00000007}, 788 {REG_MICFIL_FIFO_STAT, 0x00000000}, 789 {REG_MICFIL_DATACH0, 0x00000000}, 790 {REG_MICFIL_DATACH1, 0x00000000}, 791 {REG_MICFIL_DATACH2, 0x00000000}, 792 {REG_MICFIL_DATACH3, 0x00000000}, 793 {REG_MICFIL_DATACH4, 0x00000000}, 794 {REG_MICFIL_DATACH5, 0x00000000}, 795 {REG_MICFIL_DATACH6, 0x00000000}, 796 {REG_MICFIL_DATACH7, 0x00000000}, 797 {REG_MICFIL_DC_CTRL, 0x00000000}, 798 {REG_MICFIL_OUT_CTRL, 0x00000000}, 799 {REG_MICFIL_OUT_STAT, 0x00000000}, 800 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 801 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 802 {REG_MICFIL_VAD0_STAT, 0x00000000}, 803 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 804 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 805 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 806 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 807 }; 808 809 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 810 { 811 switch (reg) { 812 case REG_MICFIL_CTRL1: 813 case REG_MICFIL_CTRL2: 814 case REG_MICFIL_STAT: 815 case REG_MICFIL_FIFO_CTRL: 816 case REG_MICFIL_FIFO_STAT: 817 case REG_MICFIL_DATACH0: 818 case REG_MICFIL_DATACH1: 819 case REG_MICFIL_DATACH2: 820 case REG_MICFIL_DATACH3: 821 case REG_MICFIL_DATACH4: 822 case REG_MICFIL_DATACH5: 823 case REG_MICFIL_DATACH6: 824 case REG_MICFIL_DATACH7: 825 case REG_MICFIL_DC_CTRL: 826 case REG_MICFIL_OUT_CTRL: 827 case REG_MICFIL_OUT_STAT: 828 case REG_MICFIL_VAD0_CTRL1: 829 case REG_MICFIL_VAD0_CTRL2: 830 case REG_MICFIL_VAD0_STAT: 831 case REG_MICFIL_VAD0_SCONFIG: 832 case REG_MICFIL_VAD0_NCONFIG: 833 case REG_MICFIL_VAD0_NDATA: 834 case REG_MICFIL_VAD0_ZCD: 835 return true; 836 default: 837 return false; 838 } 839 } 840 841 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 842 { 843 switch (reg) { 844 case REG_MICFIL_CTRL1: 845 case REG_MICFIL_CTRL2: 846 case REG_MICFIL_STAT: /* Write 1 to Clear */ 847 case REG_MICFIL_FIFO_CTRL: 848 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 849 case REG_MICFIL_DC_CTRL: 850 case REG_MICFIL_OUT_CTRL: 851 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 852 case REG_MICFIL_VAD0_CTRL1: 853 case REG_MICFIL_VAD0_CTRL2: 854 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 855 case REG_MICFIL_VAD0_SCONFIG: 856 case REG_MICFIL_VAD0_NCONFIG: 857 case REG_MICFIL_VAD0_ZCD: 858 return true; 859 default: 860 return false; 861 } 862 } 863 864 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 865 { 866 switch (reg) { 867 case REG_MICFIL_STAT: 868 case REG_MICFIL_DATACH0: 869 case REG_MICFIL_DATACH1: 870 case REG_MICFIL_DATACH2: 871 case REG_MICFIL_DATACH3: 872 case REG_MICFIL_DATACH4: 873 case REG_MICFIL_DATACH5: 874 case REG_MICFIL_DATACH6: 875 case REG_MICFIL_DATACH7: 876 case REG_MICFIL_VAD0_STAT: 877 case REG_MICFIL_VAD0_NDATA: 878 return true; 879 default: 880 return false; 881 } 882 } 883 884 static const struct regmap_config fsl_micfil_regmap_config = { 885 .reg_bits = 32, 886 .reg_stride = 4, 887 .val_bits = 32, 888 889 .max_register = REG_MICFIL_VAD0_ZCD, 890 .reg_defaults = fsl_micfil_reg_defaults, 891 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 892 .readable_reg = fsl_micfil_readable_reg, 893 .volatile_reg = fsl_micfil_volatile_reg, 894 .writeable_reg = fsl_micfil_writeable_reg, 895 .cache_type = REGCACHE_RBTREE, 896 }; 897 898 /* END OF REGMAP */ 899 900 static irqreturn_t micfil_isr(int irq, void *devid) 901 { 902 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 903 struct platform_device *pdev = micfil->pdev; 904 u32 stat_reg; 905 u32 fifo_stat_reg; 906 u32 ctrl1_reg; 907 bool dma_enabled; 908 int i; 909 910 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 911 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 912 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 913 914 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 915 916 /* Channel 0-7 Output Data Flags */ 917 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 918 if (stat_reg & MICFIL_STAT_CHXF(i)) 919 dev_dbg(&pdev->dev, 920 "Data available in Data Channel %d\n", i); 921 /* if DMA is not enabled, field must be written with 1 922 * to clear 923 */ 924 if (!dma_enabled) 925 regmap_write_bits(micfil->regmap, 926 REG_MICFIL_STAT, 927 MICFIL_STAT_CHXF(i), 928 1); 929 } 930 931 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 932 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 933 dev_dbg(&pdev->dev, 934 "FIFO Overflow Exception flag for channel %d\n", 935 i); 936 937 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 938 dev_dbg(&pdev->dev, 939 "FIFO Underflow Exception flag for channel %d\n", 940 i); 941 } 942 943 return IRQ_HANDLED; 944 } 945 946 static irqreturn_t micfil_err_isr(int irq, void *devid) 947 { 948 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 949 struct platform_device *pdev = micfil->pdev; 950 u32 stat_reg; 951 952 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 953 954 if (stat_reg & MICFIL_STAT_BSY_FIL) 955 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 956 957 if (stat_reg & MICFIL_STAT_FIR_RDY) 958 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 959 960 if (stat_reg & MICFIL_STAT_LOWFREQF) { 961 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 962 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 963 MICFIL_STAT_LOWFREQF, 1); 964 } 965 966 return IRQ_HANDLED; 967 } 968 969 static irqreturn_t voice_detected_fn(int irq, void *devid) 970 { 971 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 972 struct snd_kcontrol *kctl; 973 974 if (!micfil->card) 975 return IRQ_HANDLED; 976 977 kctl = snd_soc_card_get_kcontrol(micfil->card, "VAD Detected"); 978 if (!kctl) 979 return IRQ_HANDLED; 980 981 if (micfil->vad_detected) 982 snd_ctl_notify(micfil->card->snd_card, 983 SNDRV_CTL_EVENT_MASK_VALUE, 984 &kctl->id); 985 986 return IRQ_HANDLED; 987 } 988 989 static irqreturn_t hwvad_isr(int irq, void *devid) 990 { 991 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 992 struct device *dev = &micfil->pdev->dev; 993 u32 vad0_reg; 994 int ret; 995 996 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 997 998 /* 999 * The only difference between MICFIL_VAD0_STAT_EF and 1000 * MICFIL_VAD0_STAT_IF is that the former requires Write 1001 * 1 to Clear. Since both flags are set, it is enough 1002 * to only read one of them 1003 */ 1004 if (vad0_reg & MICFIL_VAD0_STAT_IF) { 1005 /* Write 1 to clear */ 1006 regmap_write_bits(micfil->regmap, REG_MICFIL_VAD0_STAT, 1007 MICFIL_VAD0_STAT_IF, 1008 MICFIL_VAD0_STAT_IF); 1009 1010 micfil->vad_detected = 1; 1011 } 1012 1013 ret = fsl_micfil_hwvad_disable(micfil); 1014 if (ret) 1015 dev_err(dev, "Failed to disable hwvad\n"); 1016 1017 return IRQ_WAKE_THREAD; 1018 } 1019 1020 static irqreturn_t hwvad_err_isr(int irq, void *devid) 1021 { 1022 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 1023 struct device *dev = &micfil->pdev->dev; 1024 u32 vad0_reg; 1025 1026 regmap_read(micfil->regmap, REG_MICFIL_VAD0_STAT, &vad0_reg); 1027 1028 if (vad0_reg & MICFIL_VAD0_STAT_INSATF) 1029 dev_dbg(dev, "voice activity input overflow/underflow detected\n"); 1030 1031 return IRQ_HANDLED; 1032 } 1033 1034 static int fsl_micfil_probe(struct platform_device *pdev) 1035 { 1036 struct device_node *np = pdev->dev.of_node; 1037 struct fsl_micfil *micfil; 1038 struct resource *res; 1039 void __iomem *regs; 1040 int ret, i; 1041 1042 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 1043 if (!micfil) 1044 return -ENOMEM; 1045 1046 micfil->pdev = pdev; 1047 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); 1048 1049 micfil->soc = of_device_get_match_data(&pdev->dev); 1050 1051 /* ipg_clk is used to control the registers 1052 * ipg_clk_app is used to operate the filter 1053 */ 1054 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 1055 if (IS_ERR(micfil->mclk)) { 1056 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 1057 PTR_ERR(micfil->mclk)); 1058 return PTR_ERR(micfil->mclk); 1059 } 1060 1061 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 1062 if (IS_ERR(micfil->busclk)) { 1063 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 1064 PTR_ERR(micfil->busclk)); 1065 return PTR_ERR(micfil->busclk); 1066 } 1067 1068 fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, 1069 &micfil->pll11k_clk); 1070 1071 /* init regmap */ 1072 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1073 if (IS_ERR(regs)) 1074 return PTR_ERR(regs); 1075 1076 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 1077 regs, 1078 &fsl_micfil_regmap_config); 1079 if (IS_ERR(micfil->regmap)) { 1080 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 1081 PTR_ERR(micfil->regmap)); 1082 return PTR_ERR(micfil->regmap); 1083 } 1084 1085 /* dataline mask for RX */ 1086 ret = of_property_read_u32_index(np, 1087 "fsl,dataline", 1088 0, 1089 &micfil->dataline); 1090 if (ret) 1091 micfil->dataline = 1; 1092 1093 if (micfil->dataline & ~micfil->soc->dataline) { 1094 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 1095 micfil->soc->dataline); 1096 return -EINVAL; 1097 } 1098 1099 /* get IRQs */ 1100 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 1101 micfil->irq[i] = platform_get_irq(pdev, i); 1102 if (micfil->irq[i] < 0) 1103 return micfil->irq[i]; 1104 } 1105 1106 /* Digital Microphone interface interrupt */ 1107 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 1108 micfil_isr, IRQF_SHARED, 1109 micfil->name, micfil); 1110 if (ret) { 1111 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 1112 micfil->irq[0]); 1113 return ret; 1114 } 1115 1116 /* Digital Microphone interface error interrupt */ 1117 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 1118 micfil_err_isr, IRQF_SHARED, 1119 micfil->name, micfil); 1120 if (ret) { 1121 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 1122 micfil->irq[1]); 1123 return ret; 1124 } 1125 1126 /* Digital Microphone interface voice activity detector event */ 1127 ret = devm_request_threaded_irq(&pdev->dev, micfil->irq[2], 1128 hwvad_isr, voice_detected_fn, 1129 IRQF_SHARED, micfil->name, micfil); 1130 if (ret) { 1131 dev_err(&pdev->dev, "failed to claim hwvad event irq %u\n", 1132 micfil->irq[0]); 1133 return ret; 1134 } 1135 1136 /* Digital Microphone interface voice activity detector error */ 1137 ret = devm_request_irq(&pdev->dev, micfil->irq[3], 1138 hwvad_err_isr, IRQF_SHARED, 1139 micfil->name, micfil); 1140 if (ret) { 1141 dev_err(&pdev->dev, "failed to claim hwvad error irq %u\n", 1142 micfil->irq[1]); 1143 return ret; 1144 } 1145 1146 micfil->dma_params_rx.chan_name = "rx"; 1147 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; 1148 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 1149 1150 platform_set_drvdata(pdev, micfil); 1151 1152 pm_runtime_enable(&pdev->dev); 1153 regcache_cache_only(micfil->regmap, true); 1154 1155 /* 1156 * Register platform component before registering cpu dai for there 1157 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 1158 */ 1159 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1160 if (ret) { 1161 dev_err(&pdev->dev, "failed to pcm register\n"); 1162 goto err_pm_disable; 1163 } 1164 1165 fsl_micfil_dai.capture.formats = micfil->soc->formats; 1166 1167 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 1168 &fsl_micfil_dai, 1); 1169 if (ret) { 1170 dev_err(&pdev->dev, "failed to register component %s\n", 1171 fsl_micfil_component.name); 1172 goto err_pm_disable; 1173 } 1174 1175 return ret; 1176 1177 err_pm_disable: 1178 pm_runtime_disable(&pdev->dev); 1179 1180 return ret; 1181 } 1182 1183 static void fsl_micfil_remove(struct platform_device *pdev) 1184 { 1185 pm_runtime_disable(&pdev->dev); 1186 } 1187 1188 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev) 1189 { 1190 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1191 1192 regcache_cache_only(micfil->regmap, true); 1193 1194 clk_disable_unprepare(micfil->mclk); 1195 clk_disable_unprepare(micfil->busclk); 1196 1197 return 0; 1198 } 1199 1200 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev) 1201 { 1202 struct fsl_micfil *micfil = dev_get_drvdata(dev); 1203 int ret; 1204 1205 ret = clk_prepare_enable(micfil->busclk); 1206 if (ret < 0) 1207 return ret; 1208 1209 ret = clk_prepare_enable(micfil->mclk); 1210 if (ret < 0) { 1211 clk_disable_unprepare(micfil->busclk); 1212 return ret; 1213 } 1214 1215 regcache_cache_only(micfil->regmap, false); 1216 regcache_mark_dirty(micfil->regmap); 1217 regcache_sync(micfil->regmap); 1218 1219 return 0; 1220 } 1221 1222 static int __maybe_unused fsl_micfil_suspend(struct device *dev) 1223 { 1224 pm_runtime_force_suspend(dev); 1225 1226 return 0; 1227 } 1228 1229 static int __maybe_unused fsl_micfil_resume(struct device *dev) 1230 { 1231 pm_runtime_force_resume(dev); 1232 1233 return 0; 1234 } 1235 1236 static const struct dev_pm_ops fsl_micfil_pm_ops = { 1237 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 1238 fsl_micfil_runtime_resume, 1239 NULL) 1240 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend, 1241 fsl_micfil_resume) 1242 }; 1243 1244 static struct platform_driver fsl_micfil_driver = { 1245 .probe = fsl_micfil_probe, 1246 .remove_new = fsl_micfil_remove, 1247 .driver = { 1248 .name = "fsl-micfil-dai", 1249 .pm = &fsl_micfil_pm_ops, 1250 .of_match_table = fsl_micfil_dt_ids, 1251 }, 1252 }; 1253 module_platform_driver(fsl_micfil_driver); 1254 1255 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 1256 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 1257 MODULE_LICENSE("GPL v2"); 1258