1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2018 NXP 3 4 #include <linux/bitfield.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/interrupt.h> 8 #include <linux/kobject.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/sysfs.h> 18 #include <linux/types.h> 19 #include <linux/dma/imx-dma.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm.h> 22 #include <sound/soc.h> 23 #include <sound/tlv.h> 24 #include <sound/core.h> 25 26 #include "fsl_micfil.h" 27 28 #define MICFIL_OSR_DEFAULT 16 29 30 enum quality { 31 QUALITY_HIGH, 32 QUALITY_MEDIUM, 33 QUALITY_LOW, 34 QUALITY_VLOW0, 35 QUALITY_VLOW1, 36 QUALITY_VLOW2, 37 }; 38 39 struct fsl_micfil { 40 struct platform_device *pdev; 41 struct regmap *regmap; 42 const struct fsl_micfil_soc_data *soc; 43 struct clk *busclk; 44 struct clk *mclk; 45 struct snd_dmaengine_dai_dma_data dma_params_rx; 46 struct sdma_peripheral_config sdmacfg; 47 unsigned int dataline; 48 char name[32]; 49 int irq[MICFIL_IRQ_LINES]; 50 enum quality quality; 51 }; 52 53 struct fsl_micfil_soc_data { 54 unsigned int fifos; 55 unsigned int fifo_depth; 56 unsigned int dataline; 57 bool imx; 58 u64 formats; 59 }; 60 61 static struct fsl_micfil_soc_data fsl_micfil_imx8mm = { 62 .imx = true, 63 .fifos = 8, 64 .fifo_depth = 8, 65 .dataline = 0xf, 66 .formats = SNDRV_PCM_FMTBIT_S16_LE, 67 }; 68 69 static struct fsl_micfil_soc_data fsl_micfil_imx8mp = { 70 .imx = true, 71 .fifos = 8, 72 .fifo_depth = 32, 73 .dataline = 0xf, 74 .formats = SNDRV_PCM_FMTBIT_S32_LE, 75 }; 76 77 static const struct of_device_id fsl_micfil_dt_ids[] = { 78 { .compatible = "fsl,imx8mm-micfil", .data = &fsl_micfil_imx8mm }, 79 { .compatible = "fsl,imx8mp-micfil", .data = &fsl_micfil_imx8mp }, 80 {} 81 }; 82 MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids); 83 84 static const char * const micfil_quality_select_texts[] = { 85 [QUALITY_HIGH] = "High", 86 [QUALITY_MEDIUM] = "Medium", 87 [QUALITY_LOW] = "Low", 88 [QUALITY_VLOW0] = "VLow0", 89 [QUALITY_VLOW1] = "Vlow1", 90 [QUALITY_VLOW2] = "Vlow2", 91 }; 92 93 static const struct soc_enum fsl_micfil_quality_enum = 94 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts), 95 micfil_quality_select_texts); 96 97 static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0); 98 99 static int micfil_set_quality(struct fsl_micfil *micfil) 100 { 101 u32 qsel; 102 103 switch (micfil->quality) { 104 case QUALITY_HIGH: 105 qsel = MICFIL_QSEL_HIGH_QUALITY; 106 break; 107 case QUALITY_MEDIUM: 108 qsel = MICFIL_QSEL_MEDIUM_QUALITY; 109 break; 110 case QUALITY_LOW: 111 qsel = MICFIL_QSEL_LOW_QUALITY; 112 break; 113 case QUALITY_VLOW0: 114 qsel = MICFIL_QSEL_VLOW0_QUALITY; 115 break; 116 case QUALITY_VLOW1: 117 qsel = MICFIL_QSEL_VLOW1_QUALITY; 118 break; 119 case QUALITY_VLOW2: 120 qsel = MICFIL_QSEL_VLOW2_QUALITY; 121 break; 122 } 123 124 return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 125 MICFIL_CTRL2_QSEL, 126 FIELD_PREP(MICFIL_CTRL2_QSEL, qsel)); 127 } 128 129 static int micfil_quality_get(struct snd_kcontrol *kcontrol, 130 struct snd_ctl_elem_value *ucontrol) 131 { 132 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 133 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 134 135 ucontrol->value.integer.value[0] = micfil->quality; 136 137 return 0; 138 } 139 140 static int micfil_quality_set(struct snd_kcontrol *kcontrol, 141 struct snd_ctl_elem_value *ucontrol) 142 { 143 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 144 struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt); 145 146 micfil->quality = ucontrol->value.integer.value[0]; 147 148 return micfil_set_quality(micfil); 149 } 150 151 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = { 152 SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL, 153 MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv), 154 SOC_SINGLE_SX_TLV("CH1 Volume", REG_MICFIL_OUT_CTRL, 155 MICFIL_OUTGAIN_CHX_SHIFT(1), 0xF, 0x7, gain_tlv), 156 SOC_SINGLE_SX_TLV("CH2 Volume", REG_MICFIL_OUT_CTRL, 157 MICFIL_OUTGAIN_CHX_SHIFT(2), 0xF, 0x7, gain_tlv), 158 SOC_SINGLE_SX_TLV("CH3 Volume", REG_MICFIL_OUT_CTRL, 159 MICFIL_OUTGAIN_CHX_SHIFT(3), 0xF, 0x7, gain_tlv), 160 SOC_SINGLE_SX_TLV("CH4 Volume", REG_MICFIL_OUT_CTRL, 161 MICFIL_OUTGAIN_CHX_SHIFT(4), 0xF, 0x7, gain_tlv), 162 SOC_SINGLE_SX_TLV("CH5 Volume", REG_MICFIL_OUT_CTRL, 163 MICFIL_OUTGAIN_CHX_SHIFT(5), 0xF, 0x7, gain_tlv), 164 SOC_SINGLE_SX_TLV("CH6 Volume", REG_MICFIL_OUT_CTRL, 165 MICFIL_OUTGAIN_CHX_SHIFT(6), 0xF, 0x7, gain_tlv), 166 SOC_SINGLE_SX_TLV("CH7 Volume", REG_MICFIL_OUT_CTRL, 167 MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv), 168 SOC_ENUM_EXT("MICFIL Quality Select", 169 fsl_micfil_quality_enum, 170 micfil_quality_get, micfil_quality_set), 171 }; 172 173 /* The SRES is a self-negated bit which provides the CPU with the 174 * capability to initialize the PDM Interface module through the 175 * slave-bus interface. This bit always reads as zero, and this 176 * bit is only effective when MDIS is cleared 177 */ 178 static int fsl_micfil_reset(struct device *dev) 179 { 180 struct fsl_micfil *micfil = dev_get_drvdata(dev); 181 int ret; 182 183 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 184 MICFIL_CTRL1_MDIS); 185 if (ret) 186 return ret; 187 188 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 189 MICFIL_CTRL1_SRES); 190 if (ret) 191 return ret; 192 193 return 0; 194 } 195 196 static int fsl_micfil_startup(struct snd_pcm_substream *substream, 197 struct snd_soc_dai *dai) 198 { 199 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 200 201 if (!micfil) { 202 dev_err(dai->dev, "micfil dai priv_data not set\n"); 203 return -EINVAL; 204 } 205 206 return 0; 207 } 208 209 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd, 210 struct snd_soc_dai *dai) 211 { 212 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 213 struct device *dev = &micfil->pdev->dev; 214 int ret; 215 216 switch (cmd) { 217 case SNDRV_PCM_TRIGGER_START: 218 case SNDRV_PCM_TRIGGER_RESUME: 219 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 220 ret = fsl_micfil_reset(dev); 221 if (ret) { 222 dev_err(dev, "failed to soft reset\n"); 223 return ret; 224 } 225 226 /* DMA Interrupt Selection - DISEL bits 227 * 00 - DMA and IRQ disabled 228 * 01 - DMA req enabled 229 * 10 - IRQ enabled 230 * 11 - reserved 231 */ 232 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 233 MICFIL_CTRL1_DISEL, 234 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA)); 235 if (ret) 236 return ret; 237 238 /* Enable the module */ 239 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, 240 MICFIL_CTRL1_PDMIEN); 241 if (ret) 242 return ret; 243 244 break; 245 case SNDRV_PCM_TRIGGER_STOP: 246 case SNDRV_PCM_TRIGGER_SUSPEND: 247 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 248 /* Disable the module */ 249 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 250 MICFIL_CTRL1_PDMIEN); 251 if (ret) 252 return ret; 253 254 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 255 MICFIL_CTRL1_DISEL, 256 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE)); 257 if (ret) 258 return ret; 259 break; 260 default: 261 return -EINVAL; 262 } 263 return 0; 264 } 265 266 static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, 267 struct snd_pcm_hw_params *params, 268 struct snd_soc_dai *dai) 269 { 270 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai); 271 unsigned int channels = params_channels(params); 272 unsigned int rate = params_rate(params); 273 int clk_div = 8; 274 int osr = MICFIL_OSR_DEFAULT; 275 int ret; 276 277 /* 1. Disable the module */ 278 ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1, 279 MICFIL_CTRL1_PDMIEN); 280 if (ret) 281 return ret; 282 283 /* enable channels */ 284 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1, 285 0xFF, ((1 << channels) - 1)); 286 if (ret) 287 return ret; 288 289 ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); 290 if (ret) 291 return ret; 292 293 ret = micfil_set_quality(micfil); 294 if (ret) 295 return ret; 296 297 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2, 298 MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR, 299 FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) | 300 FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr)); 301 302 micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg; 303 micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg); 304 micfil->sdmacfg.n_fifos_src = channels; 305 micfil->sdmacfg.sw_done = true; 306 micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX; 307 308 return 0; 309 } 310 311 static const struct snd_soc_dai_ops fsl_micfil_dai_ops = { 312 .startup = fsl_micfil_startup, 313 .trigger = fsl_micfil_trigger, 314 .hw_params = fsl_micfil_hw_params, 315 }; 316 317 static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) 318 { 319 struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev); 320 int ret; 321 322 micfil->quality = QUALITY_MEDIUM; 323 324 /* set default gain to max_gain */ 325 regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); 326 327 snd_soc_dai_init_dma_data(cpu_dai, NULL, 328 &micfil->dma_params_rx); 329 330 /* FIFO Watermark Control - FIFOWMK*/ 331 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL, 332 MICFIL_FIFO_CTRL_FIFOWMK, 333 FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1)); 334 if (ret) 335 return ret; 336 337 return 0; 338 } 339 340 static struct snd_soc_dai_driver fsl_micfil_dai = { 341 .probe = fsl_micfil_dai_probe, 342 .capture = { 343 .stream_name = "CPU-Capture", 344 .channels_min = 1, 345 .channels_max = 8, 346 .rates = SNDRV_PCM_RATE_8000_48000, 347 .formats = SNDRV_PCM_FMTBIT_S16_LE, 348 }, 349 .ops = &fsl_micfil_dai_ops, 350 }; 351 352 static const struct snd_soc_component_driver fsl_micfil_component = { 353 .name = "fsl-micfil-dai", 354 .controls = fsl_micfil_snd_controls, 355 .num_controls = ARRAY_SIZE(fsl_micfil_snd_controls), 356 357 }; 358 359 /* REGMAP */ 360 static const struct reg_default fsl_micfil_reg_defaults[] = { 361 {REG_MICFIL_CTRL1, 0x00000000}, 362 {REG_MICFIL_CTRL2, 0x00000000}, 363 {REG_MICFIL_STAT, 0x00000000}, 364 {REG_MICFIL_FIFO_CTRL, 0x00000007}, 365 {REG_MICFIL_FIFO_STAT, 0x00000000}, 366 {REG_MICFIL_DATACH0, 0x00000000}, 367 {REG_MICFIL_DATACH1, 0x00000000}, 368 {REG_MICFIL_DATACH2, 0x00000000}, 369 {REG_MICFIL_DATACH3, 0x00000000}, 370 {REG_MICFIL_DATACH4, 0x00000000}, 371 {REG_MICFIL_DATACH5, 0x00000000}, 372 {REG_MICFIL_DATACH6, 0x00000000}, 373 {REG_MICFIL_DATACH7, 0x00000000}, 374 {REG_MICFIL_DC_CTRL, 0x00000000}, 375 {REG_MICFIL_OUT_CTRL, 0x00000000}, 376 {REG_MICFIL_OUT_STAT, 0x00000000}, 377 {REG_MICFIL_VAD0_CTRL1, 0x00000000}, 378 {REG_MICFIL_VAD0_CTRL2, 0x000A0000}, 379 {REG_MICFIL_VAD0_STAT, 0x00000000}, 380 {REG_MICFIL_VAD0_SCONFIG, 0x00000000}, 381 {REG_MICFIL_VAD0_NCONFIG, 0x80000000}, 382 {REG_MICFIL_VAD0_NDATA, 0x00000000}, 383 {REG_MICFIL_VAD0_ZCD, 0x00000004}, 384 }; 385 386 static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg) 387 { 388 switch (reg) { 389 case REG_MICFIL_CTRL1: 390 case REG_MICFIL_CTRL2: 391 case REG_MICFIL_STAT: 392 case REG_MICFIL_FIFO_CTRL: 393 case REG_MICFIL_FIFO_STAT: 394 case REG_MICFIL_DATACH0: 395 case REG_MICFIL_DATACH1: 396 case REG_MICFIL_DATACH2: 397 case REG_MICFIL_DATACH3: 398 case REG_MICFIL_DATACH4: 399 case REG_MICFIL_DATACH5: 400 case REG_MICFIL_DATACH6: 401 case REG_MICFIL_DATACH7: 402 case REG_MICFIL_DC_CTRL: 403 case REG_MICFIL_OUT_CTRL: 404 case REG_MICFIL_OUT_STAT: 405 case REG_MICFIL_VAD0_CTRL1: 406 case REG_MICFIL_VAD0_CTRL2: 407 case REG_MICFIL_VAD0_STAT: 408 case REG_MICFIL_VAD0_SCONFIG: 409 case REG_MICFIL_VAD0_NCONFIG: 410 case REG_MICFIL_VAD0_NDATA: 411 case REG_MICFIL_VAD0_ZCD: 412 return true; 413 default: 414 return false; 415 } 416 } 417 418 static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg) 419 { 420 switch (reg) { 421 case REG_MICFIL_CTRL1: 422 case REG_MICFIL_CTRL2: 423 case REG_MICFIL_STAT: /* Write 1 to Clear */ 424 case REG_MICFIL_FIFO_CTRL: 425 case REG_MICFIL_FIFO_STAT: /* Write 1 to Clear */ 426 case REG_MICFIL_DC_CTRL: 427 case REG_MICFIL_OUT_CTRL: 428 case REG_MICFIL_OUT_STAT: /* Write 1 to Clear */ 429 case REG_MICFIL_VAD0_CTRL1: 430 case REG_MICFIL_VAD0_CTRL2: 431 case REG_MICFIL_VAD0_STAT: /* Write 1 to Clear */ 432 case REG_MICFIL_VAD0_SCONFIG: 433 case REG_MICFIL_VAD0_NCONFIG: 434 case REG_MICFIL_VAD0_ZCD: 435 return true; 436 default: 437 return false; 438 } 439 } 440 441 static bool fsl_micfil_volatile_reg(struct device *dev, unsigned int reg) 442 { 443 switch (reg) { 444 case REG_MICFIL_STAT: 445 case REG_MICFIL_DATACH0: 446 case REG_MICFIL_DATACH1: 447 case REG_MICFIL_DATACH2: 448 case REG_MICFIL_DATACH3: 449 case REG_MICFIL_DATACH4: 450 case REG_MICFIL_DATACH5: 451 case REG_MICFIL_DATACH6: 452 case REG_MICFIL_DATACH7: 453 case REG_MICFIL_VAD0_STAT: 454 case REG_MICFIL_VAD0_NDATA: 455 return true; 456 default: 457 return false; 458 } 459 } 460 461 static const struct regmap_config fsl_micfil_regmap_config = { 462 .reg_bits = 32, 463 .reg_stride = 4, 464 .val_bits = 32, 465 466 .max_register = REG_MICFIL_VAD0_ZCD, 467 .reg_defaults = fsl_micfil_reg_defaults, 468 .num_reg_defaults = ARRAY_SIZE(fsl_micfil_reg_defaults), 469 .readable_reg = fsl_micfil_readable_reg, 470 .volatile_reg = fsl_micfil_volatile_reg, 471 .writeable_reg = fsl_micfil_writeable_reg, 472 .cache_type = REGCACHE_RBTREE, 473 }; 474 475 /* END OF REGMAP */ 476 477 static irqreturn_t micfil_isr(int irq, void *devid) 478 { 479 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 480 struct platform_device *pdev = micfil->pdev; 481 u32 stat_reg; 482 u32 fifo_stat_reg; 483 u32 ctrl1_reg; 484 bool dma_enabled; 485 int i; 486 487 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 488 regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg); 489 regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg); 490 491 dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA; 492 493 /* Channel 0-7 Output Data Flags */ 494 for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) { 495 if (stat_reg & MICFIL_STAT_CHXF(i)) 496 dev_dbg(&pdev->dev, 497 "Data available in Data Channel %d\n", i); 498 /* if DMA is not enabled, field must be written with 1 499 * to clear 500 */ 501 if (!dma_enabled) 502 regmap_write_bits(micfil->regmap, 503 REG_MICFIL_STAT, 504 MICFIL_STAT_CHXF(i), 505 1); 506 } 507 508 for (i = 0; i < MICFIL_FIFO_NUM; i++) { 509 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i)) 510 dev_dbg(&pdev->dev, 511 "FIFO Overflow Exception flag for channel %d\n", 512 i); 513 514 if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i)) 515 dev_dbg(&pdev->dev, 516 "FIFO Underflow Exception flag for channel %d\n", 517 i); 518 } 519 520 return IRQ_HANDLED; 521 } 522 523 static irqreturn_t micfil_err_isr(int irq, void *devid) 524 { 525 struct fsl_micfil *micfil = (struct fsl_micfil *)devid; 526 struct platform_device *pdev = micfil->pdev; 527 u32 stat_reg; 528 529 regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg); 530 531 if (stat_reg & MICFIL_STAT_BSY_FIL) 532 dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n"); 533 534 if (stat_reg & MICFIL_STAT_FIR_RDY) 535 dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n"); 536 537 if (stat_reg & MICFIL_STAT_LOWFREQF) { 538 dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n"); 539 regmap_write_bits(micfil->regmap, REG_MICFIL_STAT, 540 MICFIL_STAT_LOWFREQF, 1); 541 } 542 543 return IRQ_HANDLED; 544 } 545 546 static int fsl_micfil_probe(struct platform_device *pdev) 547 { 548 struct device_node *np = pdev->dev.of_node; 549 struct fsl_micfil *micfil; 550 struct resource *res; 551 void __iomem *regs; 552 int ret, i; 553 554 micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL); 555 if (!micfil) 556 return -ENOMEM; 557 558 micfil->pdev = pdev; 559 strncpy(micfil->name, np->name, sizeof(micfil->name) - 1); 560 561 micfil->soc = of_device_get_match_data(&pdev->dev); 562 563 /* ipg_clk is used to control the registers 564 * ipg_clk_app is used to operate the filter 565 */ 566 micfil->mclk = devm_clk_get(&pdev->dev, "ipg_clk_app"); 567 if (IS_ERR(micfil->mclk)) { 568 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 569 PTR_ERR(micfil->mclk)); 570 return PTR_ERR(micfil->mclk); 571 } 572 573 micfil->busclk = devm_clk_get(&pdev->dev, "ipg_clk"); 574 if (IS_ERR(micfil->busclk)) { 575 dev_err(&pdev->dev, "failed to get ipg clock: %ld\n", 576 PTR_ERR(micfil->busclk)); 577 return PTR_ERR(micfil->busclk); 578 } 579 580 /* init regmap */ 581 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 582 if (IS_ERR(regs)) 583 return PTR_ERR(regs); 584 585 micfil->regmap = devm_regmap_init_mmio(&pdev->dev, 586 regs, 587 &fsl_micfil_regmap_config); 588 if (IS_ERR(micfil->regmap)) { 589 dev_err(&pdev->dev, "failed to init MICFIL regmap: %ld\n", 590 PTR_ERR(micfil->regmap)); 591 return PTR_ERR(micfil->regmap); 592 } 593 594 /* dataline mask for RX */ 595 ret = of_property_read_u32_index(np, 596 "fsl,dataline", 597 0, 598 &micfil->dataline); 599 if (ret) 600 micfil->dataline = 1; 601 602 if (micfil->dataline & ~micfil->soc->dataline) { 603 dev_err(&pdev->dev, "dataline setting error, Mask is 0x%X\n", 604 micfil->soc->dataline); 605 return -EINVAL; 606 } 607 608 /* get IRQs */ 609 for (i = 0; i < MICFIL_IRQ_LINES; i++) { 610 micfil->irq[i] = platform_get_irq(pdev, i); 611 if (micfil->irq[i] < 0) 612 return micfil->irq[i]; 613 } 614 615 /* Digital Microphone interface interrupt */ 616 ret = devm_request_irq(&pdev->dev, micfil->irq[0], 617 micfil_isr, IRQF_SHARED, 618 micfil->name, micfil); 619 if (ret) { 620 dev_err(&pdev->dev, "failed to claim mic interface irq %u\n", 621 micfil->irq[0]); 622 return ret; 623 } 624 625 /* Digital Microphone interface error interrupt */ 626 ret = devm_request_irq(&pdev->dev, micfil->irq[1], 627 micfil_err_isr, IRQF_SHARED, 628 micfil->name, micfil); 629 if (ret) { 630 dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n", 631 micfil->irq[1]); 632 return ret; 633 } 634 635 micfil->dma_params_rx.chan_name = "rx"; 636 micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0; 637 micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX; 638 639 platform_set_drvdata(pdev, micfil); 640 641 pm_runtime_enable(&pdev->dev); 642 regcache_cache_only(micfil->regmap, true); 643 644 /* 645 * Register platform component before registering cpu dai for there 646 * is not defer probe for platform component in snd_soc_add_pcm_runtime(). 647 */ 648 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 649 if (ret) { 650 dev_err(&pdev->dev, "failed to pcm register\n"); 651 return ret; 652 } 653 654 fsl_micfil_dai.capture.formats = micfil->soc->formats; 655 656 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_micfil_component, 657 &fsl_micfil_dai, 1); 658 if (ret) { 659 dev_err(&pdev->dev, "failed to register component %s\n", 660 fsl_micfil_component.name); 661 } 662 663 return ret; 664 } 665 666 static int __maybe_unused fsl_micfil_runtime_suspend(struct device *dev) 667 { 668 struct fsl_micfil *micfil = dev_get_drvdata(dev); 669 670 regcache_cache_only(micfil->regmap, true); 671 672 clk_disable_unprepare(micfil->mclk); 673 clk_disable_unprepare(micfil->busclk); 674 675 return 0; 676 } 677 678 static int __maybe_unused fsl_micfil_runtime_resume(struct device *dev) 679 { 680 struct fsl_micfil *micfil = dev_get_drvdata(dev); 681 int ret; 682 683 ret = clk_prepare_enable(micfil->busclk); 684 if (ret < 0) 685 return ret; 686 687 ret = clk_prepare_enable(micfil->mclk); 688 if (ret < 0) { 689 clk_disable_unprepare(micfil->busclk); 690 return ret; 691 } 692 693 regcache_cache_only(micfil->regmap, false); 694 regcache_mark_dirty(micfil->regmap); 695 regcache_sync(micfil->regmap); 696 697 return 0; 698 } 699 700 static int __maybe_unused fsl_micfil_suspend(struct device *dev) 701 { 702 pm_runtime_force_suspend(dev); 703 704 return 0; 705 } 706 707 static int __maybe_unused fsl_micfil_resume(struct device *dev) 708 { 709 pm_runtime_force_resume(dev); 710 711 return 0; 712 } 713 714 static const struct dev_pm_ops fsl_micfil_pm_ops = { 715 SET_RUNTIME_PM_OPS(fsl_micfil_runtime_suspend, 716 fsl_micfil_runtime_resume, 717 NULL) 718 SET_SYSTEM_SLEEP_PM_OPS(fsl_micfil_suspend, 719 fsl_micfil_resume) 720 }; 721 722 static struct platform_driver fsl_micfil_driver = { 723 .probe = fsl_micfil_probe, 724 .driver = { 725 .name = "fsl-micfil-dai", 726 .pm = &fsl_micfil_pm_ops, 727 .of_match_table = fsl_micfil_dt_ids, 728 }, 729 }; 730 module_platform_driver(fsl_micfil_driver); 731 732 MODULE_AUTHOR("Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>"); 733 MODULE_DESCRIPTION("NXP PDM Microphone Interface (MICFIL) driver"); 734 MODULE_LICENSE("GPL v2"); 735