1 /* 2 * fsl_esai.h - ALSA ESAI interface for the Freescale i.MX SoC 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * 6 * Author: Nicolin Chen <Guangyu.Chen@freescale.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13 #ifndef _FSL_ESAI_DAI_H 14 #define _FSL_ESAI_DAI_H 15 16 /* ESAI Register Map */ 17 #define REG_ESAI_ETDR 0x00 18 #define REG_ESAI_ERDR 0x04 19 #define REG_ESAI_ECR 0x08 20 #define REG_ESAI_ESR 0x0C 21 #define REG_ESAI_TFCR 0x10 22 #define REG_ESAI_TFSR 0x14 23 #define REG_ESAI_RFCR 0x18 24 #define REG_ESAI_RFSR 0x1C 25 #define REG_ESAI_xFCR(tx) (tx ? REG_ESAI_TFCR : REG_ESAI_RFCR) 26 #define REG_ESAI_xFSR(tx) (tx ? REG_ESAI_TFSR : REG_ESAI_RFSR) 27 #define REG_ESAI_TX0 0x80 28 #define REG_ESAI_TX1 0x84 29 #define REG_ESAI_TX2 0x88 30 #define REG_ESAI_TX3 0x8C 31 #define REG_ESAI_TX4 0x90 32 #define REG_ESAI_TX5 0x94 33 #define REG_ESAI_TSR 0x98 34 #define REG_ESAI_RX0 0xA0 35 #define REG_ESAI_RX1 0xA4 36 #define REG_ESAI_RX2 0xA8 37 #define REG_ESAI_RX3 0xAC 38 #define REG_ESAI_SAISR 0xCC 39 #define REG_ESAI_SAICR 0xD0 40 #define REG_ESAI_TCR 0xD4 41 #define REG_ESAI_TCCR 0xD8 42 #define REG_ESAI_RCR 0xDC 43 #define REG_ESAI_RCCR 0xE0 44 #define REG_ESAI_xCR(tx) (tx ? REG_ESAI_TCR : REG_ESAI_RCR) 45 #define REG_ESAI_xCCR(tx) (tx ? REG_ESAI_TCCR : REG_ESAI_RCCR) 46 #define REG_ESAI_TSMA 0xE4 47 #define REG_ESAI_TSMB 0xE8 48 #define REG_ESAI_RSMA 0xEC 49 #define REG_ESAI_RSMB 0xF0 50 #define REG_ESAI_xSMA(tx) (tx ? REG_ESAI_TSMA : REG_ESAI_RSMA) 51 #define REG_ESAI_xSMB(tx) (tx ? REG_ESAI_TSMB : REG_ESAI_RSMB) 52 #define REG_ESAI_PRRC 0xF8 53 #define REG_ESAI_PCRC 0xFC 54 55 /* ESAI Control Register -- REG_ESAI_ECR 0x8 */ 56 #define ESAI_ECR_ETI_SHIFT 19 57 #define ESAI_ECR_ETI_MASK (1 << ESAI_ECR_ETI_SHIFT) 58 #define ESAI_ECR_ETI (1 << ESAI_ECR_ETI_SHIFT) 59 #define ESAI_ECR_ETO_SHIFT 18 60 #define ESAI_ECR_ETO_MASK (1 << ESAI_ECR_ETO_SHIFT) 61 #define ESAI_ECR_ETO (1 << ESAI_ECR_ETO_SHIFT) 62 #define ESAI_ECR_ERI_SHIFT 17 63 #define ESAI_ECR_ERI_MASK (1 << ESAI_ECR_ERI_SHIFT) 64 #define ESAI_ECR_ERI (1 << ESAI_ECR_ERI_SHIFT) 65 #define ESAI_ECR_ERO_SHIFT 16 66 #define ESAI_ECR_ERO_MASK (1 << ESAI_ECR_ERO_SHIFT) 67 #define ESAI_ECR_ERO (1 << ESAI_ECR_ERO_SHIFT) 68 #define ESAI_ECR_ERST_SHIFT 1 69 #define ESAI_ECR_ERST_MASK (1 << ESAI_ECR_ERST_SHIFT) 70 #define ESAI_ECR_ERST (1 << ESAI_ECR_ERST_SHIFT) 71 #define ESAI_ECR_ESAIEN_SHIFT 0 72 #define ESAI_ECR_ESAIEN_MASK (1 << ESAI_ECR_ESAIEN_SHIFT) 73 #define ESAI_ECR_ESAIEN (1 << ESAI_ECR_ESAIEN_SHIFT) 74 75 /* ESAI Status Register -- REG_ESAI_ESR 0xC */ 76 #define ESAI_ESR_TINIT_SHIFT 10 77 #define ESAI_ESR_TINIT_MASK (1 << ESAI_ESR_TINIT_SHIFT) 78 #define ESAI_ESR_TINIT (1 << ESAI_ESR_TINIT_SHIFT) 79 #define ESAI_ESR_RFF_SHIFT 9 80 #define ESAI_ESR_RFF_MASK (1 << ESAI_ESR_RFF_SHIFT) 81 #define ESAI_ESR_RFF (1 << ESAI_ESR_RFF_SHIFT) 82 #define ESAI_ESR_TFE_SHIFT 8 83 #define ESAI_ESR_TFE_MASK (1 << ESAI_ESR_TFE_SHIFT) 84 #define ESAI_ESR_TFE (1 << ESAI_ESR_TFE_SHIFT) 85 #define ESAI_ESR_TLS_SHIFT 7 86 #define ESAI_ESR_TLS_MASK (1 << ESAI_ESR_TLS_SHIFT) 87 #define ESAI_ESR_TLS (1 << ESAI_ESR_TLS_SHIFT) 88 #define ESAI_ESR_TDE_SHIFT 6 89 #define ESAI_ESR_TDE_MASK (1 << ESAI_ESR_TDE_SHIFT) 90 #define ESAI_ESR_TDE (1 << ESAI_ESR_TDE_SHIFT) 91 #define ESAI_ESR_TED_SHIFT 5 92 #define ESAI_ESR_TED_MASK (1 << ESAI_ESR_TED_SHIFT) 93 #define ESAI_ESR_TED (1 << ESAI_ESR_TED_SHIFT) 94 #define ESAI_ESR_TD_SHIFT 4 95 #define ESAI_ESR_TD_MASK (1 << ESAI_ESR_TD_SHIFT) 96 #define ESAI_ESR_TD (1 << ESAI_ESR_TD_SHIFT) 97 #define ESAI_ESR_RLS_SHIFT 3 98 #define ESAI_ESR_RLS_MASK (1 << ESAI_ESR_RLS_SHIFT) 99 #define ESAI_ESR_RLS (1 << ESAI_ESR_RLS_SHIFT) 100 #define ESAI_ESR_RDE_SHIFT 2 101 #define ESAI_ESR_RDE_MASK (1 << ESAI_ESR_RDE_SHIFT) 102 #define ESAI_ESR_RDE (1 << ESAI_ESR_RDE_SHIFT) 103 #define ESAI_ESR_RED_SHIFT 1 104 #define ESAI_ESR_RED_MASK (1 << ESAI_ESR_RED_SHIFT) 105 #define ESAI_ESR_RED (1 << ESAI_ESR_RED_SHIFT) 106 #define ESAI_ESR_RD_SHIFT 0 107 #define ESAI_ESR_RD_MASK (1 << ESAI_ESR_RD_SHIFT) 108 #define ESAI_ESR_RD (1 << ESAI_ESR_RD_SHIFT) 109 110 /* 111 * Transmit FIFO Configuration Register -- REG_ESAI_TFCR 0x10 112 * Receive FIFO Configuration Register -- REG_ESAI_RFCR 0x18 113 */ 114 #define ESAI_xFCR_TIEN_SHIFT 19 115 #define ESAI_xFCR_TIEN_MASK (1 << ESAI_xFCR_TIEN_SHIFT) 116 #define ESAI_xFCR_TIEN (1 << ESAI_xFCR_TIEN_SHIFT) 117 #define ESAI_xFCR_REXT_SHIFT 19 118 #define ESAI_xFCR_REXT_MASK (1 << ESAI_xFCR_REXT_SHIFT) 119 #define ESAI_xFCR_REXT (1 << ESAI_xFCR_REXT_SHIFT) 120 #define ESAI_xFCR_xWA_SHIFT 16 121 #define ESAI_xFCR_xWA_WIDTH 3 122 #define ESAI_xFCR_xWA_MASK (((1 << ESAI_xFCR_xWA_WIDTH) - 1) << ESAI_xFCR_xWA_SHIFT) 123 #define ESAI_xFCR_xWA(v) (((8 - ((v) >> 2)) << ESAI_xFCR_xWA_SHIFT) & ESAI_xFCR_xWA_MASK) 124 #define ESAI_xFCR_xFWM_SHIFT 8 125 #define ESAI_xFCR_xFWM_WIDTH 8 126 #define ESAI_xFCR_xFWM_MASK (((1 << ESAI_xFCR_xFWM_WIDTH) - 1) << ESAI_xFCR_xFWM_SHIFT) 127 #define ESAI_xFCR_xFWM(v) ((((v) - 1) << ESAI_xFCR_xFWM_SHIFT) & ESAI_xFCR_xFWM_MASK) 128 #define ESAI_xFCR_xE_SHIFT 2 129 #define ESAI_xFCR_TE_WIDTH 6 130 #define ESAI_xFCR_RE_WIDTH 4 131 #define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) 132 #define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT) 133 #define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK) 134 #define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK) 135 #define ESAI_xFCR_xFR_SHIFT 1 136 #define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT) 137 #define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT) 138 #define ESAI_xFCR_xFEN_SHIFT 0 139 #define ESAI_xFCR_xFEN_MASK (1 << ESAI_xFCR_xFEN_SHIFT) 140 #define ESAI_xFCR_xFEN (1 << ESAI_xFCR_xFEN_SHIFT) 141 142 /* 143 * Transmit FIFO Status Register -- REG_ESAI_TFSR 0x14 144 * Receive FIFO Status Register --REG_ESAI_RFSR 0x1C 145 */ 146 #define ESAI_xFSR_NTFO_SHIFT 12 147 #define ESAI_xFSR_NRFI_SHIFT 12 148 #define ESAI_xFSR_NTFI_SHIFT 8 149 #define ESAI_xFSR_NRFO_SHIFT 8 150 #define ESAI_xFSR_NTFx_WIDTH 3 151 #define ESAI_xFSR_NRFx_WIDTH 2 152 #define ESAI_xFSR_NTFO_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFO_SHIFT) 153 #define ESAI_xFSR_NTFI_MASK (((1 << ESAI_xFSR_NTFx_WIDTH) - 1) << ESAI_xFSR_NTFI_SHIFT) 154 #define ESAI_xFSR_NRFO_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFO_SHIFT) 155 #define ESAI_xFSR_NRFI_MASK (((1 << ESAI_xFSR_NRFx_WIDTH) - 1) << ESAI_xFSR_NRFI_SHIFT) 156 #define ESAI_xFSR_xFCNT_SHIFT 0 157 #define ESAI_xFSR_xFCNT_WIDTH 8 158 #define ESAI_xFSR_xFCNT_MASK (((1 << ESAI_xFSR_xFCNT_WIDTH) - 1) << ESAI_xFSR_xFCNT_SHIFT) 159 160 /* ESAI Transmit Slot Register -- REG_ESAI_TSR 0x98 */ 161 #define ESAI_TSR_SHIFT 0 162 #define ESAI_TSR_WIDTH 24 163 #define ESAI_TSR_MASK (((1 << ESAI_TSR_WIDTH) - 1) << ESAI_TSR_SHIFT) 164 165 /* Serial Audio Interface Status Register -- REG_ESAI_SAISR 0xCC */ 166 #define ESAI_SAISR_TODFE_SHIFT 17 167 #define ESAI_SAISR_TODFE_MASK (1 << ESAI_SAISR_TODFE_SHIFT) 168 #define ESAI_SAISR_TODFE (1 << ESAI_SAISR_TODFE_SHIFT) 169 #define ESAI_SAISR_TEDE_SHIFT 16 170 #define ESAI_SAISR_TEDE_MASK (1 << ESAI_SAISR_TEDE_SHIFT) 171 #define ESAI_SAISR_TEDE (1 << ESAI_SAISR_TEDE_SHIFT) 172 #define ESAI_SAISR_TDE_SHIFT 15 173 #define ESAI_SAISR_TDE_MASK (1 << ESAI_SAISR_TDE_SHIFT) 174 #define ESAI_SAISR_TDE (1 << ESAI_SAISR_TDE_SHIFT) 175 #define ESAI_SAISR_TUE_SHIFT 14 176 #define ESAI_SAISR_TUE_MASK (1 << ESAI_SAISR_TUE_SHIFT) 177 #define ESAI_SAISR_TUE (1 << ESAI_SAISR_TUE_SHIFT) 178 #define ESAI_SAISR_TFS_SHIFT 13 179 #define ESAI_SAISR_TFS_MASK (1 << ESAI_SAISR_TFS_SHIFT) 180 #define ESAI_SAISR_TFS (1 << ESAI_SAISR_TFS_SHIFT) 181 #define ESAI_SAISR_RODF_SHIFT 10 182 #define ESAI_SAISR_RODF_MASK (1 << ESAI_SAISR_RODF_SHIFT) 183 #define ESAI_SAISR_RODF (1 << ESAI_SAISR_RODF_SHIFT) 184 #define ESAI_SAISR_REDF_SHIFT 9 185 #define ESAI_SAISR_REDF_MASK (1 << ESAI_SAISR_REDF_SHIFT) 186 #define ESAI_SAISR_REDF (1 << ESAI_SAISR_REDF_SHIFT) 187 #define ESAI_SAISR_RDF_SHIFT 8 188 #define ESAI_SAISR_RDF_MASK (1 << ESAI_SAISR_RDF_SHIFT) 189 #define ESAI_SAISR_RDF (1 << ESAI_SAISR_RDF_SHIFT) 190 #define ESAI_SAISR_ROE_SHIFT 7 191 #define ESAI_SAISR_ROE_MASK (1 << ESAI_SAISR_ROE_SHIFT) 192 #define ESAI_SAISR_ROE (1 << ESAI_SAISR_ROE_SHIFT) 193 #define ESAI_SAISR_RFS_SHIFT 6 194 #define ESAI_SAISR_RFS_MASK (1 << ESAI_SAISR_RFS_SHIFT) 195 #define ESAI_SAISR_RFS (1 << ESAI_SAISR_RFS_SHIFT) 196 #define ESAI_SAISR_IF2_SHIFT 2 197 #define ESAI_SAISR_IF2_MASK (1 << ESAI_SAISR_IF2_SHIFT) 198 #define ESAI_SAISR_IF2 (1 << ESAI_SAISR_IF2_SHIFT) 199 #define ESAI_SAISR_IF1_SHIFT 1 200 #define ESAI_SAISR_IF1_MASK (1 << ESAI_SAISR_IF1_SHIFT) 201 #define ESAI_SAISR_IF1 (1 << ESAI_SAISR_IF1_SHIFT) 202 #define ESAI_SAISR_IF0_SHIFT 0 203 #define ESAI_SAISR_IF0_MASK (1 << ESAI_SAISR_IF0_SHIFT) 204 #define ESAI_SAISR_IF0 (1 << ESAI_SAISR_IF0_SHIFT) 205 206 /* Serial Audio Interface Control Register -- REG_ESAI_SAICR 0xD0 */ 207 #define ESAI_SAICR_ALC_SHIFT 8 208 #define ESAI_SAICR_ALC_MASK (1 << ESAI_SAICR_ALC_SHIFT) 209 #define ESAI_SAICR_ALC (1 << ESAI_SAICR_ALC_SHIFT) 210 #define ESAI_SAICR_TEBE_SHIFT 7 211 #define ESAI_SAICR_TEBE_MASK (1 << ESAI_SAICR_TEBE_SHIFT) 212 #define ESAI_SAICR_TEBE (1 << ESAI_SAICR_TEBE_SHIFT) 213 #define ESAI_SAICR_SYNC_SHIFT 6 214 #define ESAI_SAICR_SYNC_MASK (1 << ESAI_SAICR_SYNC_SHIFT) 215 #define ESAI_SAICR_SYNC (1 << ESAI_SAICR_SYNC_SHIFT) 216 #define ESAI_SAICR_OF2_SHIFT 2 217 #define ESAI_SAICR_OF2_MASK (1 << ESAI_SAICR_OF2_SHIFT) 218 #define ESAI_SAICR_OF2 (1 << ESAI_SAICR_OF2_SHIFT) 219 #define ESAI_SAICR_OF1_SHIFT 1 220 #define ESAI_SAICR_OF1_MASK (1 << ESAI_SAICR_OF1_SHIFT) 221 #define ESAI_SAICR_OF1 (1 << ESAI_SAICR_OF1_SHIFT) 222 #define ESAI_SAICR_OF0_SHIFT 0 223 #define ESAI_SAICR_OF0_MASK (1 << ESAI_SAICR_OF0_SHIFT) 224 #define ESAI_SAICR_OF0 (1 << ESAI_SAICR_OF0_SHIFT) 225 226 /* 227 * Transmit Control Register -- REG_ESAI_TCR 0xD4 228 * Receive Control Register -- REG_ESAI_RCR 0xDC 229 */ 230 #define ESAI_xCR_xLIE_SHIFT 23 231 #define ESAI_xCR_xLIE_MASK (1 << ESAI_xCR_xLIE_SHIFT) 232 #define ESAI_xCR_xLIE (1 << ESAI_xCR_xLIE_SHIFT) 233 #define ESAI_xCR_xIE_SHIFT 22 234 #define ESAI_xCR_xIE_MASK (1 << ESAI_xCR_xIE_SHIFT) 235 #define ESAI_xCR_xIE (1 << ESAI_xCR_xIE_SHIFT) 236 #define ESAI_xCR_xEDIE_SHIFT 21 237 #define ESAI_xCR_xEDIE_MASK (1 << ESAI_xCR_xEDIE_SHIFT) 238 #define ESAI_xCR_xEDIE (1 << ESAI_xCR_xEDIE_SHIFT) 239 #define ESAI_xCR_xEIE_SHIFT 20 240 #define ESAI_xCR_xEIE_MASK (1 << ESAI_xCR_xEIE_SHIFT) 241 #define ESAI_xCR_xEIE (1 << ESAI_xCR_xEIE_SHIFT) 242 #define ESAI_xCR_xPR_SHIFT 19 243 #define ESAI_xCR_xPR_MASK (1 << ESAI_xCR_xPR_SHIFT) 244 #define ESAI_xCR_xPR (1 << ESAI_xCR_xPR_SHIFT) 245 #define ESAI_xCR_PADC_SHIFT 17 246 #define ESAI_xCR_PADC_MASK (1 << ESAI_xCR_PADC_SHIFT) 247 #define ESAI_xCR_PADC (1 << ESAI_xCR_PADC_SHIFT) 248 #define ESAI_xCR_xFSR_SHIFT 16 249 #define ESAI_xCR_xFSR_MASK (1 << ESAI_xCR_xFSR_SHIFT) 250 #define ESAI_xCR_xFSR (1 << ESAI_xCR_xFSR_SHIFT) 251 #define ESAI_xCR_xFSL_SHIFT 15 252 #define ESAI_xCR_xFSL_MASK (1 << ESAI_xCR_xFSL_SHIFT) 253 #define ESAI_xCR_xFSL (1 << ESAI_xCR_xFSL_SHIFT) 254 #define ESAI_xCR_xSWS_SHIFT 10 255 #define ESAI_xCR_xSWS_WIDTH 5 256 #define ESAI_xCR_xSWS_MASK (((1 << ESAI_xCR_xSWS_WIDTH) - 1) << ESAI_xCR_xSWS_SHIFT) 257 #define ESAI_xCR_xSWS(s, w) ((w < 24 ? (s - w + ((w - 8) >> 2)) : (s < 32 ? 0x1e : 0x1f)) << ESAI_xCR_xSWS_SHIFT) 258 #define ESAI_xCR_xMOD_SHIFT 8 259 #define ESAI_xCR_xMOD_WIDTH 2 260 #define ESAI_xCR_xMOD_MASK (((1 << ESAI_xCR_xMOD_WIDTH) - 1) << ESAI_xCR_xMOD_SHIFT) 261 #define ESAI_xCR_xMOD_ONDEMAND (0x1 << ESAI_xCR_xMOD_SHIFT) 262 #define ESAI_xCR_xMOD_NETWORK (0x1 << ESAI_xCR_xMOD_SHIFT) 263 #define ESAI_xCR_xMOD_AC97 (0x3 << ESAI_xCR_xMOD_SHIFT) 264 #define ESAI_xCR_xWA_SHIFT 7 265 #define ESAI_xCR_xWA_MASK (1 << ESAI_xCR_xWA_SHIFT) 266 #define ESAI_xCR_xWA (1 << ESAI_xCR_xWA_SHIFT) 267 #define ESAI_xCR_xSHFD_SHIFT 6 268 #define ESAI_xCR_xSHFD_MASK (1 << ESAI_xCR_xSHFD_SHIFT) 269 #define ESAI_xCR_xSHFD (1 << ESAI_xCR_xSHFD_SHIFT) 270 #define ESAI_xCR_xE_SHIFT 0 271 #define ESAI_xCR_TE_WIDTH 6 272 #define ESAI_xCR_RE_WIDTH 4 273 #define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) 274 #define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT) 275 #define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK) 276 #define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK) 277 278 /* 279 * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8 280 * Receive Clock Control Register -- REG_ESAI_RCCR 0xE0 281 */ 282 #define ESAI_xCCR_xHCKD_SHIFT 23 283 #define ESAI_xCCR_xHCKD_MASK (1 << ESAI_xCCR_xHCKD_SHIFT) 284 #define ESAI_xCCR_xHCKD (1 << ESAI_xCCR_xHCKD_SHIFT) 285 #define ESAI_xCCR_xFSD_SHIFT 22 286 #define ESAI_xCCR_xFSD_MASK (1 << ESAI_xCCR_xFSD_SHIFT) 287 #define ESAI_xCCR_xFSD (1 << ESAI_xCCR_xFSD_SHIFT) 288 #define ESAI_xCCR_xCKD_SHIFT 21 289 #define ESAI_xCCR_xCKD_MASK (1 << ESAI_xCCR_xCKD_SHIFT) 290 #define ESAI_xCCR_xCKD (1 << ESAI_xCCR_xCKD_SHIFT) 291 #define ESAI_xCCR_xHCKP_SHIFT 20 292 #define ESAI_xCCR_xHCKP_MASK (1 << ESAI_xCCR_xHCKP_SHIFT) 293 #define ESAI_xCCR_xHCKP (1 << ESAI_xCCR_xHCKP_SHIFT) 294 #define ESAI_xCCR_xFSP_SHIFT 19 295 #define ESAI_xCCR_xFSP_MASK (1 << ESAI_xCCR_xFSP_SHIFT) 296 #define ESAI_xCCR_xFSP (1 << ESAI_xCCR_xFSP_SHIFT) 297 #define ESAI_xCCR_xCKP_SHIFT 18 298 #define ESAI_xCCR_xCKP_MASK (1 << ESAI_xCCR_xCKP_SHIFT) 299 #define ESAI_xCCR_xCKP (1 << ESAI_xCCR_xCKP_SHIFT) 300 #define ESAI_xCCR_xFP_SHIFT 14 301 #define ESAI_xCCR_xFP_WIDTH 4 302 #define ESAI_xCCR_xFP_MASK (((1 << ESAI_xCCR_xFP_WIDTH) - 1) << ESAI_xCCR_xFP_SHIFT) 303 #define ESAI_xCCR_xFP(v) ((((v) - 1) << ESAI_xCCR_xFP_SHIFT) & ESAI_xCCR_xFP_MASK) 304 #define ESAI_xCCR_xDC_SHIFT 9 305 #define ESAI_xCCR_xDC_WIDTH 5 306 #define ESAI_xCCR_xDC_MASK (((1 << ESAI_xCCR_xDC_WIDTH) - 1) << ESAI_xCCR_xDC_SHIFT) 307 #define ESAI_xCCR_xDC(v) ((((v) - 1) << ESAI_xCCR_xDC_SHIFT) & ESAI_xCCR_xDC_MASK) 308 #define ESAI_xCCR_xPSR_SHIFT 8 309 #define ESAI_xCCR_xPSR_MASK (1 << ESAI_xCCR_xPSR_SHIFT) 310 #define ESAI_xCCR_xPSR_BYPASS (1 << ESAI_xCCR_xPSR_SHIFT) 311 #define ESAI_xCCR_xPSR_DIV8 (0 << ESAI_xCCR_xPSR_SHIFT) 312 #define ESAI_xCCR_xPM_SHIFT 0 313 #define ESAI_xCCR_xPM_WIDTH 8 314 #define ESAI_xCCR_xPM_MASK (((1 << ESAI_xCCR_xPM_WIDTH) - 1) << ESAI_xCCR_xPM_SHIFT) 315 #define ESAI_xCCR_xPM(v) ((((v) - 1) << ESAI_xCCR_xPM_SHIFT) & ESAI_xCCR_xPM_MASK) 316 317 /* Transmit Slot Mask Register A/B -- REG_ESAI_TSMA/B 0xE4 ~ 0xF0 */ 318 #define ESAI_xSMA_xS_SHIFT 0 319 #define ESAI_xSMA_xS_WIDTH 16 320 #define ESAI_xSMA_xS_MASK (((1 << ESAI_xSMA_xS_WIDTH) - 1) << ESAI_xSMA_xS_SHIFT) 321 #define ESAI_xSMA_xS(v) ((v) & ESAI_xSMA_xS_MASK) 322 #define ESAI_xSMB_xS_SHIFT 0 323 #define ESAI_xSMB_xS_WIDTH 16 324 #define ESAI_xSMB_xS_MASK (((1 << ESAI_xSMB_xS_WIDTH) - 1) << ESAI_xSMB_xS_SHIFT) 325 #define ESAI_xSMB_xS(v) (((v) >> ESAI_xSMA_xS_WIDTH) & ESAI_xSMB_xS_MASK) 326 327 /* Port C Direction Register -- REG_ESAI_PRRC 0xF8 */ 328 #define ESAI_PRRC_PDC_SHIFT 0 329 #define ESAI_PRRC_PDC_WIDTH 12 330 #define ESAI_PRRC_PDC_MASK (((1 << ESAI_PRRC_PDC_WIDTH) - 1) << ESAI_PRRC_PDC_SHIFT) 331 #define ESAI_PRRC_PDC(v) ((v) & ESAI_PRRC_PDC_MASK) 332 333 /* Port C Control Register -- REG_ESAI_PCRC 0xFC */ 334 #define ESAI_PCRC_PC_SHIFT 0 335 #define ESAI_PCRC_PC_WIDTH 12 336 #define ESAI_PCRC_PC_MASK (((1 << ESAI_PCRC_PC_WIDTH) - 1) << ESAI_PCRC_PC_SHIFT) 337 #define ESAI_PCRC_PC(v) ((v) & ESAI_PCRC_PC_MASK) 338 339 #define ESAI_GPIO 0xfff 340 341 /* ESAI clock source */ 342 #define ESAI_HCKT_FSYS 0 343 #define ESAI_HCKT_EXTAL 1 344 #define ESAI_HCKR_FSYS 2 345 #define ESAI_HCKR_EXTAL 3 346 347 /* ESAI clock divider */ 348 #define ESAI_TX_DIV_PSR 0 349 #define ESAI_TX_DIV_PM 1 350 #define ESAI_TX_DIV_FP 2 351 #define ESAI_RX_DIV_PSR 3 352 #define ESAI_RX_DIV_PM 4 353 #define ESAI_RX_DIV_FP 5 354 #endif /* _FSL_ESAI_DAI_H */ 355