1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/module.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_params.h> 15 16 #include "fsl_esai.h" 17 #include "imx-pcm.h" 18 19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 20 SNDRV_PCM_FMTBIT_S16_LE | \ 21 SNDRV_PCM_FMTBIT_S20_3LE | \ 22 SNDRV_PCM_FMTBIT_S24_LE) 23 24 /** 25 * struct fsl_esai_soc_data - soc specific data 26 * @reset_at_xrun: flags for enable reset operaton 27 */ 28 struct fsl_esai_soc_data { 29 bool reset_at_xrun; 30 }; 31 32 /** 33 * struct fsl_esai - ESAI private data 34 * @dma_params_rx: DMA parameters for receive channel 35 * @dma_params_tx: DMA parameters for transmit channel 36 * @pdev: platform device pointer 37 * @regmap: regmap handler 38 * @coreclk: clock source to access register 39 * @extalclk: esai clock source to derive HCK, SCK and FS 40 * @fsysclk: system clock source to derive HCK, SCK and FS 41 * @spbaclk: SPBA clock (optional, depending on SoC design) 42 * @work: work to handle the reset operation 43 * @soc: soc specific data 44 * @lock: spin lock between hw_reset() and trigger() 45 * @fifo_depth: depth of tx/rx FIFO 46 * @slot_width: width of each DAI slot 47 * @slots: number of slots 48 * @tx_mask: slot mask for TX 49 * @rx_mask: slot mask for RX 50 * @channels: channel num for tx or rx 51 * @hck_rate: clock rate of desired HCKx clock 52 * @sck_rate: clock rate of desired SCKx clock 53 * @hck_dir: the direction of HCKx pads 54 * @sck_div: if using PSR/PM dividers for SCKx clock 55 * @slave_mode: if fully using DAI slave mode 56 * @synchronous: if using tx/rx synchronous mode 57 * @name: driver name 58 */ 59 struct fsl_esai { 60 struct snd_dmaengine_dai_dma_data dma_params_rx; 61 struct snd_dmaengine_dai_dma_data dma_params_tx; 62 struct platform_device *pdev; 63 struct regmap *regmap; 64 struct clk *coreclk; 65 struct clk *extalclk; 66 struct clk *fsysclk; 67 struct clk *spbaclk; 68 struct work_struct work; 69 const struct fsl_esai_soc_data *soc; 70 spinlock_t lock; /* Protect hw_reset and trigger */ 71 u32 fifo_depth; 72 u32 slot_width; 73 u32 slots; 74 u32 tx_mask; 75 u32 rx_mask; 76 u32 channels[2]; 77 u32 hck_rate[2]; 78 u32 sck_rate[2]; 79 bool hck_dir[2]; 80 bool sck_div[2]; 81 bool slave_mode; 82 bool synchronous; 83 char name[32]; 84 }; 85 86 static struct fsl_esai_soc_data fsl_esai_vf610 = { 87 .reset_at_xrun = true, 88 }; 89 90 static struct fsl_esai_soc_data fsl_esai_imx35 = { 91 .reset_at_xrun = true, 92 }; 93 94 static struct fsl_esai_soc_data fsl_esai_imx6ull = { 95 .reset_at_xrun = false, 96 }; 97 98 static irqreturn_t esai_isr(int irq, void *devid) 99 { 100 struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 101 struct platform_device *pdev = esai_priv->pdev; 102 u32 esr; 103 u32 saisr; 104 105 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 106 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr); 107 108 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) && 109 esai_priv->soc->reset_at_xrun) { 110 dev_dbg(&pdev->dev, "reset module for xrun\n"); 111 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 112 ESAI_xCR_xEIE_MASK, 0); 113 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 114 ESAI_xCR_xEIE_MASK, 0); 115 schedule_work(&esai_priv->work); 116 } 117 118 if (esr & ESAI_ESR_TINIT_MASK) 119 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 120 121 if (esr & ESAI_ESR_RFF_MASK) 122 dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 123 124 if (esr & ESAI_ESR_TFE_MASK) 125 dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 126 127 if (esr & ESAI_ESR_TLS_MASK) 128 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 129 130 if (esr & ESAI_ESR_TDE_MASK) 131 dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 132 133 if (esr & ESAI_ESR_TED_MASK) 134 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 135 136 if (esr & ESAI_ESR_TD_MASK) 137 dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 138 139 if (esr & ESAI_ESR_RLS_MASK) 140 dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 141 142 if (esr & ESAI_ESR_RDE_MASK) 143 dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 144 145 if (esr & ESAI_ESR_RED_MASK) 146 dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 147 148 if (esr & ESAI_ESR_RD_MASK) 149 dev_dbg(&pdev->dev, "isr: Receiving data\n"); 150 151 return IRQ_HANDLED; 152 } 153 154 /** 155 * fsl_esai_divisor_cal - This function is used to calculate the 156 * divisors of psr, pm, fp and it is supposed to be called in 157 * set_dai_sysclk() and set_bclk(). 158 * 159 * @dai: pointer to DAI 160 * @tx: current setting is for playback or capture 161 * @ratio: desired overall ratio for the paticipating dividers 162 * @usefp: for HCK setting, there is no need to set fp divider 163 * @fp: bypass other dividers by setting fp directly if fp != 0 164 */ 165 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 166 bool usefp, u32 fp) 167 { 168 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 169 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 170 171 maxfp = usefp ? 16 : 1; 172 173 if (usefp && fp) 174 goto out_fp; 175 176 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 177 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 178 2 * 8 * 256 * maxfp); 179 return -EINVAL; 180 } else if (ratio % 2) { 181 dev_err(dai->dev, "the raio must be even if using upper divider\n"); 182 return -EINVAL; 183 } 184 185 ratio /= 2; 186 187 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 188 189 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 190 if (ratio <= 256) { 191 pm = ratio; 192 fp = 1; 193 goto out; 194 } 195 196 /* Set the max fluctuation -- 0.1% of the max devisor */ 197 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 198 199 /* Find the best value for PM */ 200 for (i = 1; i <= 256; i++) { 201 for (j = 1; j <= maxfp; j++) { 202 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 203 prod = (psr ? 1 : 8) * i * j; 204 205 if (prod == ratio) 206 sub = 0; 207 else if (prod / ratio == 1) 208 sub = prod - ratio; 209 else if (ratio / prod == 1) 210 sub = ratio - prod; 211 else 212 continue; 213 214 /* Calculate the fraction */ 215 sub = sub * 1000 / ratio; 216 if (sub < savesub) { 217 savesub = sub; 218 pm = i; 219 fp = j; 220 } 221 222 /* We are lucky */ 223 if (savesub == 0) 224 goto out; 225 } 226 } 227 228 if (pm == 999) { 229 dev_err(dai->dev, "failed to calculate proper divisors\n"); 230 return -EINVAL; 231 } 232 233 out: 234 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 235 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 236 psr | ESAI_xCCR_xPM(pm)); 237 238 out_fp: 239 /* Bypass fp if not being required */ 240 if (maxfp <= 1) 241 return 0; 242 243 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 244 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 245 246 return 0; 247 } 248 249 /** 250 * fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR) 251 * @dai: pointer to DAI 252 * @clk_id: The clock source of HCKT/HCKR 253 * (Input from outside; output from inside, FSYS or EXTAL) 254 * @freq: The required clock rate of HCKT/HCKR 255 * @dir: The clock direction of HCKT/HCKR 256 * 257 * Note: If the direction is input, we do not care about clk_id. 258 */ 259 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 260 unsigned int freq, int dir) 261 { 262 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 263 struct clk *clksrc = esai_priv->extalclk; 264 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous); 265 bool in = dir == SND_SOC_CLOCK_IN; 266 u32 ratio, ecr = 0; 267 unsigned long clk_rate; 268 int ret; 269 270 if (freq == 0) { 271 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 272 in ? "in" : "out", tx ? 'T' : 'R'); 273 return -EINVAL; 274 } 275 276 /* Bypass divider settings if the requirement doesn't change */ 277 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 278 return 0; 279 280 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 281 esai_priv->sck_div[tx] = true; 282 283 /* Set the direction of HCKT/HCKR pins */ 284 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 285 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 286 287 if (in) 288 goto out; 289 290 switch (clk_id) { 291 case ESAI_HCKT_FSYS: 292 case ESAI_HCKR_FSYS: 293 clksrc = esai_priv->fsysclk; 294 break; 295 case ESAI_HCKT_EXTAL: 296 ecr |= ESAI_ECR_ETI; 297 break; 298 case ESAI_HCKR_EXTAL: 299 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI; 300 break; 301 default: 302 return -EINVAL; 303 } 304 305 if (IS_ERR(clksrc)) { 306 dev_err(dai->dev, "no assigned %s clock\n", 307 clk_id % 2 ? "extal" : "fsys"); 308 return PTR_ERR(clksrc); 309 } 310 clk_rate = clk_get_rate(clksrc); 311 312 ratio = clk_rate / freq; 313 if (ratio * freq > clk_rate) 314 ret = ratio * freq - clk_rate; 315 else if (ratio * freq < clk_rate) 316 ret = clk_rate - ratio * freq; 317 else 318 ret = 0; 319 320 /* Block if clock source can not be divided into the required rate */ 321 if (ret != 0 && clk_rate / ret < 1000) { 322 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 323 tx ? 'T' : 'R'); 324 return -EINVAL; 325 } 326 327 /* Only EXTAL source can be output directly without using PSR and PM */ 328 if (ratio == 1 && clksrc == esai_priv->extalclk) { 329 /* Bypass all the dividers if not being needed */ 330 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 331 goto out; 332 } else if (ratio < 2) { 333 /* The ratio should be no less than 2 if using other sources */ 334 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 335 tx ? 'T' : 'R'); 336 return -EINVAL; 337 } 338 339 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 340 if (ret) 341 return ret; 342 343 esai_priv->sck_div[tx] = false; 344 345 out: 346 esai_priv->hck_dir[tx] = dir; 347 esai_priv->hck_rate[tx] = freq; 348 349 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 350 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 351 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 352 353 return 0; 354 } 355 356 /** 357 * fsl_esai_set_bclk - configure the related dividers according to the bclk rate 358 * @dai: pointer to DAI 359 * @tx: direction boolean 360 * @freq: bclk freq 361 */ 362 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 363 { 364 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 365 u32 hck_rate = esai_priv->hck_rate[tx]; 366 u32 sub, ratio = hck_rate / freq; 367 int ret; 368 369 /* Don't apply for fully slave mode or unchanged bclk */ 370 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 371 return 0; 372 373 if (ratio * freq > hck_rate) 374 sub = ratio * freq - hck_rate; 375 else if (ratio * freq < hck_rate) 376 sub = hck_rate - ratio * freq; 377 else 378 sub = 0; 379 380 /* Block if clock source can not be divided into the required rate */ 381 if (sub != 0 && hck_rate / sub < 1000) { 382 dev_err(dai->dev, "failed to derive required SCK%c rate\n", 383 tx ? 'T' : 'R'); 384 return -EINVAL; 385 } 386 387 /* The ratio should be contented by FP alone if bypassing PM and PSR */ 388 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 389 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 390 return -EINVAL; 391 } 392 393 ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 394 esai_priv->sck_div[tx] ? 0 : ratio); 395 if (ret) 396 return ret; 397 398 /* Save current bclk rate */ 399 esai_priv->sck_rate[tx] = freq; 400 401 return 0; 402 } 403 404 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 405 u32 rx_mask, int slots, int slot_width) 406 { 407 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 408 409 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 410 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 411 412 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 413 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 414 415 esai_priv->slot_width = slot_width; 416 esai_priv->slots = slots; 417 esai_priv->tx_mask = tx_mask; 418 esai_priv->rx_mask = rx_mask; 419 420 return 0; 421 } 422 423 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 424 { 425 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 426 u32 xcr = 0, xccr = 0, mask; 427 428 /* DAI mode */ 429 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 430 case SND_SOC_DAIFMT_I2S: 431 /* Data on rising edge of bclk, frame low, 1clk before data */ 432 xcr |= ESAI_xCR_xFSR; 433 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 434 break; 435 case SND_SOC_DAIFMT_LEFT_J: 436 /* Data on rising edge of bclk, frame high */ 437 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 438 break; 439 case SND_SOC_DAIFMT_RIGHT_J: 440 /* Data on rising edge of bclk, frame high, right aligned */ 441 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 442 xcr |= ESAI_xCR_xWA; 443 break; 444 case SND_SOC_DAIFMT_DSP_A: 445 /* Data on rising edge of bclk, frame high, 1clk before data */ 446 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 447 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 448 break; 449 case SND_SOC_DAIFMT_DSP_B: 450 /* Data on rising edge of bclk, frame high */ 451 xcr |= ESAI_xCR_xFSL; 452 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 453 break; 454 default: 455 return -EINVAL; 456 } 457 458 /* DAI clock inversion */ 459 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 460 case SND_SOC_DAIFMT_NB_NF: 461 /* Nothing to do for both normal cases */ 462 break; 463 case SND_SOC_DAIFMT_IB_NF: 464 /* Invert bit clock */ 465 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 466 break; 467 case SND_SOC_DAIFMT_NB_IF: 468 /* Invert frame clock */ 469 xccr ^= ESAI_xCCR_xFSP; 470 break; 471 case SND_SOC_DAIFMT_IB_IF: 472 /* Invert both clocks */ 473 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 474 break; 475 default: 476 return -EINVAL; 477 } 478 479 esai_priv->slave_mode = false; 480 481 /* DAI clock master masks */ 482 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 483 case SND_SOC_DAIFMT_CBM_CFM: 484 esai_priv->slave_mode = true; 485 break; 486 case SND_SOC_DAIFMT_CBS_CFM: 487 xccr |= ESAI_xCCR_xCKD; 488 break; 489 case SND_SOC_DAIFMT_CBM_CFS: 490 xccr |= ESAI_xCCR_xFSD; 491 break; 492 case SND_SOC_DAIFMT_CBS_CFS: 493 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 494 break; 495 default: 496 return -EINVAL; 497 } 498 499 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; 500 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 501 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 502 503 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 504 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 505 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 506 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 507 508 return 0; 509 } 510 511 static int fsl_esai_startup(struct snd_pcm_substream *substream, 512 struct snd_soc_dai *dai) 513 { 514 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 515 516 if (!snd_soc_dai_active(dai)) { 517 /* Set synchronous mode */ 518 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 519 ESAI_SAICR_SYNC, esai_priv->synchronous ? 520 ESAI_SAICR_SYNC : 0); 521 522 /* Set a default slot number -- 2 */ 523 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 524 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 525 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 526 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 527 } 528 529 return 0; 530 531 } 532 533 static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 534 struct snd_pcm_hw_params *params, 535 struct snd_soc_dai *dai) 536 { 537 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 538 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 539 u32 width = params_width(params); 540 u32 channels = params_channels(params); 541 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 542 u32 slot_width = width; 543 u32 bclk, mask, val; 544 int ret; 545 546 /* Override slot_width if being specifically set */ 547 if (esai_priv->slot_width) 548 slot_width = esai_priv->slot_width; 549 550 bclk = params_rate(params) * slot_width * esai_priv->slots; 551 552 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk); 553 if (ret) 554 return ret; 555 556 mask = ESAI_xCR_xSWS_MASK; 557 val = ESAI_xCR_xSWS(slot_width, width); 558 559 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 560 /* Recording in synchronous mode needs to set TCR also */ 561 if (!tx && esai_priv->synchronous) 562 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); 563 564 /* Use Normal mode to support monaural audio */ 565 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 566 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 567 ESAI_xCR_xMOD_NETWORK : 0); 568 569 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 570 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 571 572 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 573 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 574 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 575 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 576 577 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 578 579 if (tx) 580 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 581 ESAI_xCR_PADC, ESAI_xCR_PADC); 582 583 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 584 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 585 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 586 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 587 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 588 return 0; 589 } 590 591 static int fsl_esai_hw_init(struct fsl_esai *esai_priv) 592 { 593 struct platform_device *pdev = esai_priv->pdev; 594 int ret; 595 596 /* Reset ESAI unit */ 597 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 598 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 599 ESAI_ECR_ESAIEN | ESAI_ECR_ERST); 600 if (ret) { 601 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 602 return ret; 603 } 604 605 /* 606 * We need to enable ESAI so as to access some of its registers. 607 * Otherwise, we would fail to dump regmap from user space. 608 */ 609 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 610 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 611 ESAI_ECR_ESAIEN); 612 if (ret) { 613 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 614 return ret; 615 } 616 617 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 618 ESAI_PRRC_PDC_MASK, 0); 619 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 620 ESAI_PCRC_PC_MASK, 0); 621 622 return 0; 623 } 624 625 static int fsl_esai_register_restore(struct fsl_esai *esai_priv) 626 { 627 int ret; 628 629 /* FIFO reset for safety */ 630 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, 631 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 632 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, 633 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 634 635 regcache_mark_dirty(esai_priv->regmap); 636 ret = regcache_sync(esai_priv->regmap); 637 if (ret) 638 return ret; 639 640 /* FIFO reset done */ 641 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 642 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 643 644 return 0; 645 } 646 647 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx) 648 { 649 u8 i, channels = esai_priv->channels[tx]; 650 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 651 u32 mask; 652 653 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 654 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 655 656 /* Write initial words reqiured by ESAI as normal procedure */ 657 for (i = 0; tx && i < channels; i++) 658 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 659 660 /* 661 * When set the TE/RE in the end of enablement flow, there 662 * will be channel swap issue for multi data line case. 663 * In order to workaround this issue, we switch the bit 664 * enablement sequence to below sequence 665 * 1) clear the xSMB & xSMA: which is done in probe and 666 * stop state. 667 * 2) set TE/RE 668 * 3) set xSMB 669 * 4) set xSMA: xSMA is the last one in this flow, which 670 * will trigger esai to start. 671 */ 672 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 673 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 674 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 675 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; 676 677 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 678 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); 679 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 680 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); 681 682 /* Enable Exception interrupt */ 683 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 684 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE); 685 } 686 687 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx) 688 { 689 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 690 ESAI_xCR_xEIE_MASK, 0); 691 692 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 693 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 694 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 695 ESAI_xSMA_xS_MASK, 0); 696 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 697 ESAI_xSMB_xS_MASK, 0); 698 699 /* Disable and reset FIFO */ 700 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 701 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 702 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 703 ESAI_xFCR_xFR, 0); 704 } 705 706 static void fsl_esai_hw_reset(struct work_struct *work) 707 { 708 struct fsl_esai *esai_priv = container_of(work, struct fsl_esai, work); 709 bool tx = true, rx = false, enabled[2]; 710 unsigned long lock_flags; 711 u32 tfcr, rfcr; 712 713 spin_lock_irqsave(&esai_priv->lock, lock_flags); 714 /* Save the registers */ 715 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr); 716 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr); 717 enabled[tx] = tfcr & ESAI_xFCR_xFEN; 718 enabled[rx] = rfcr & ESAI_xFCR_xFEN; 719 720 /* Stop the tx & rx */ 721 fsl_esai_trigger_stop(esai_priv, tx); 722 fsl_esai_trigger_stop(esai_priv, rx); 723 724 /* Reset the esai, and ignore return value */ 725 fsl_esai_hw_init(esai_priv); 726 727 /* Enforce ESAI personal resets for both TX and RX */ 728 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 729 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 730 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 731 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 732 733 /* Restore registers by regcache_sync, and ignore return value */ 734 fsl_esai_register_restore(esai_priv); 735 736 /* Remove ESAI personal resets by configuring PCRC and PRRC also */ 737 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 738 ESAI_xCR_xPR_MASK, 0); 739 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 740 ESAI_xCR_xPR_MASK, 0); 741 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 742 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 743 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 744 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 745 746 /* Restart tx / rx, if they already enabled */ 747 if (enabled[tx]) 748 fsl_esai_trigger_start(esai_priv, tx); 749 if (enabled[rx]) 750 fsl_esai_trigger_start(esai_priv, rx); 751 752 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 753 } 754 755 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 756 struct snd_soc_dai *dai) 757 { 758 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 759 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 760 unsigned long lock_flags; 761 762 esai_priv->channels[tx] = substream->runtime->channels; 763 764 switch (cmd) { 765 case SNDRV_PCM_TRIGGER_START: 766 case SNDRV_PCM_TRIGGER_RESUME: 767 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 768 spin_lock_irqsave(&esai_priv->lock, lock_flags); 769 fsl_esai_trigger_start(esai_priv, tx); 770 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 771 break; 772 case SNDRV_PCM_TRIGGER_SUSPEND: 773 case SNDRV_PCM_TRIGGER_STOP: 774 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 775 spin_lock_irqsave(&esai_priv->lock, lock_flags); 776 fsl_esai_trigger_stop(esai_priv, tx); 777 spin_unlock_irqrestore(&esai_priv->lock, lock_flags); 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 return 0; 784 } 785 786 static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 787 .startup = fsl_esai_startup, 788 .trigger = fsl_esai_trigger, 789 .hw_params = fsl_esai_hw_params, 790 .set_sysclk = fsl_esai_set_dai_sysclk, 791 .set_fmt = fsl_esai_set_dai_fmt, 792 .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 793 }; 794 795 static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 796 { 797 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 798 799 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 800 &esai_priv->dma_params_rx); 801 802 return 0; 803 } 804 805 static struct snd_soc_dai_driver fsl_esai_dai = { 806 .probe = fsl_esai_dai_probe, 807 .playback = { 808 .stream_name = "CPU-Playback", 809 .channels_min = 1, 810 .channels_max = 12, 811 .rates = SNDRV_PCM_RATE_8000_192000, 812 .formats = FSL_ESAI_FORMATS, 813 }, 814 .capture = { 815 .stream_name = "CPU-Capture", 816 .channels_min = 1, 817 .channels_max = 8, 818 .rates = SNDRV_PCM_RATE_8000_192000, 819 .formats = FSL_ESAI_FORMATS, 820 }, 821 .ops = &fsl_esai_dai_ops, 822 }; 823 824 static const struct snd_soc_component_driver fsl_esai_component = { 825 .name = "fsl-esai", 826 }; 827 828 static const struct reg_default fsl_esai_reg_defaults[] = { 829 {REG_ESAI_ETDR, 0x00000000}, 830 {REG_ESAI_ECR, 0x00000000}, 831 {REG_ESAI_TFCR, 0x00000000}, 832 {REG_ESAI_RFCR, 0x00000000}, 833 {REG_ESAI_TX0, 0x00000000}, 834 {REG_ESAI_TX1, 0x00000000}, 835 {REG_ESAI_TX2, 0x00000000}, 836 {REG_ESAI_TX3, 0x00000000}, 837 {REG_ESAI_TX4, 0x00000000}, 838 {REG_ESAI_TX5, 0x00000000}, 839 {REG_ESAI_TSR, 0x00000000}, 840 {REG_ESAI_SAICR, 0x00000000}, 841 {REG_ESAI_TCR, 0x00000000}, 842 {REG_ESAI_TCCR, 0x00000000}, 843 {REG_ESAI_RCR, 0x00000000}, 844 {REG_ESAI_RCCR, 0x00000000}, 845 {REG_ESAI_TSMA, 0x0000ffff}, 846 {REG_ESAI_TSMB, 0x0000ffff}, 847 {REG_ESAI_RSMA, 0x0000ffff}, 848 {REG_ESAI_RSMB, 0x0000ffff}, 849 {REG_ESAI_PRRC, 0x00000000}, 850 {REG_ESAI_PCRC, 0x00000000}, 851 }; 852 853 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 854 { 855 switch (reg) { 856 case REG_ESAI_ERDR: 857 case REG_ESAI_ECR: 858 case REG_ESAI_ESR: 859 case REG_ESAI_TFCR: 860 case REG_ESAI_TFSR: 861 case REG_ESAI_RFCR: 862 case REG_ESAI_RFSR: 863 case REG_ESAI_RX0: 864 case REG_ESAI_RX1: 865 case REG_ESAI_RX2: 866 case REG_ESAI_RX3: 867 case REG_ESAI_SAISR: 868 case REG_ESAI_SAICR: 869 case REG_ESAI_TCR: 870 case REG_ESAI_TCCR: 871 case REG_ESAI_RCR: 872 case REG_ESAI_RCCR: 873 case REG_ESAI_TSMA: 874 case REG_ESAI_TSMB: 875 case REG_ESAI_RSMA: 876 case REG_ESAI_RSMB: 877 case REG_ESAI_PRRC: 878 case REG_ESAI_PCRC: 879 return true; 880 default: 881 return false; 882 } 883 } 884 885 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 886 { 887 switch (reg) { 888 case REG_ESAI_ERDR: 889 case REG_ESAI_ESR: 890 case REG_ESAI_TFSR: 891 case REG_ESAI_RFSR: 892 case REG_ESAI_RX0: 893 case REG_ESAI_RX1: 894 case REG_ESAI_RX2: 895 case REG_ESAI_RX3: 896 case REG_ESAI_SAISR: 897 return true; 898 default: 899 return false; 900 } 901 } 902 903 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 904 { 905 switch (reg) { 906 case REG_ESAI_ETDR: 907 case REG_ESAI_ECR: 908 case REG_ESAI_TFCR: 909 case REG_ESAI_RFCR: 910 case REG_ESAI_TX0: 911 case REG_ESAI_TX1: 912 case REG_ESAI_TX2: 913 case REG_ESAI_TX3: 914 case REG_ESAI_TX4: 915 case REG_ESAI_TX5: 916 case REG_ESAI_TSR: 917 case REG_ESAI_SAICR: 918 case REG_ESAI_TCR: 919 case REG_ESAI_TCCR: 920 case REG_ESAI_RCR: 921 case REG_ESAI_RCCR: 922 case REG_ESAI_TSMA: 923 case REG_ESAI_TSMB: 924 case REG_ESAI_RSMA: 925 case REG_ESAI_RSMB: 926 case REG_ESAI_PRRC: 927 case REG_ESAI_PCRC: 928 return true; 929 default: 930 return false; 931 } 932 } 933 934 static const struct regmap_config fsl_esai_regmap_config = { 935 .reg_bits = 32, 936 .reg_stride = 4, 937 .val_bits = 32, 938 939 .max_register = REG_ESAI_PCRC, 940 .reg_defaults = fsl_esai_reg_defaults, 941 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 942 .readable_reg = fsl_esai_readable_reg, 943 .volatile_reg = fsl_esai_volatile_reg, 944 .writeable_reg = fsl_esai_writeable_reg, 945 .cache_type = REGCACHE_FLAT, 946 }; 947 948 static int fsl_esai_probe(struct platform_device *pdev) 949 { 950 struct device_node *np = pdev->dev.of_node; 951 struct fsl_esai *esai_priv; 952 struct resource *res; 953 const __be32 *iprop; 954 void __iomem *regs; 955 int irq, ret; 956 957 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 958 if (!esai_priv) 959 return -ENOMEM; 960 961 esai_priv->pdev = pdev; 962 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 963 964 esai_priv->soc = of_device_get_match_data(&pdev->dev); 965 966 /* Get the addresses and IRQ */ 967 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 968 regs = devm_ioremap_resource(&pdev->dev, res); 969 if (IS_ERR(regs)) 970 return PTR_ERR(regs); 971 972 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 973 "core", regs, &fsl_esai_regmap_config); 974 if (IS_ERR(esai_priv->regmap)) { 975 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 976 PTR_ERR(esai_priv->regmap)); 977 return PTR_ERR(esai_priv->regmap); 978 } 979 980 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 981 if (IS_ERR(esai_priv->coreclk)) { 982 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 983 PTR_ERR(esai_priv->coreclk)); 984 return PTR_ERR(esai_priv->coreclk); 985 } 986 987 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 988 if (IS_ERR(esai_priv->extalclk)) 989 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 990 PTR_ERR(esai_priv->extalclk)); 991 992 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 993 if (IS_ERR(esai_priv->fsysclk)) 994 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 995 PTR_ERR(esai_priv->fsysclk)); 996 997 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 998 if (IS_ERR(esai_priv->spbaclk)) 999 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 1000 PTR_ERR(esai_priv->spbaclk)); 1001 1002 irq = platform_get_irq(pdev, 0); 1003 if (irq < 0) 1004 return irq; 1005 1006 ret = devm_request_irq(&pdev->dev, irq, esai_isr, IRQF_SHARED, 1007 esai_priv->name, esai_priv); 1008 if (ret) { 1009 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 1010 return ret; 1011 } 1012 1013 /* Set a default slot number */ 1014 esai_priv->slots = 2; 1015 1016 /* Set a default master/slave state */ 1017 esai_priv->slave_mode = true; 1018 1019 /* Determine the FIFO depth */ 1020 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 1021 if (iprop) 1022 esai_priv->fifo_depth = be32_to_cpup(iprop); 1023 else 1024 esai_priv->fifo_depth = 64; 1025 1026 esai_priv->dma_params_tx.maxburst = 16; 1027 esai_priv->dma_params_rx.maxburst = 16; 1028 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 1029 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 1030 1031 esai_priv->synchronous = 1032 of_property_read_bool(np, "fsl,esai-synchronous"); 1033 1034 /* Implement full symmetry for synchronous mode */ 1035 if (esai_priv->synchronous) { 1036 fsl_esai_dai.symmetric_rate = 1; 1037 fsl_esai_dai.symmetric_channels = 1; 1038 fsl_esai_dai.symmetric_sample_bits = 1; 1039 } 1040 1041 dev_set_drvdata(&pdev->dev, esai_priv); 1042 1043 spin_lock_init(&esai_priv->lock); 1044 ret = fsl_esai_hw_init(esai_priv); 1045 if (ret) 1046 return ret; 1047 1048 esai_priv->tx_mask = 0xFFFFFFFF; 1049 esai_priv->rx_mask = 0xFFFFFFFF; 1050 1051 /* Clear the TSMA, TSMB, RSMA, RSMB */ 1052 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0); 1053 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0); 1054 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0); 1055 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0); 1056 1057 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 1058 &fsl_esai_dai, 1); 1059 if (ret) { 1060 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1061 return ret; 1062 } 1063 1064 INIT_WORK(&esai_priv->work, fsl_esai_hw_reset); 1065 1066 pm_runtime_enable(&pdev->dev); 1067 1068 regcache_cache_only(esai_priv->regmap, true); 1069 1070 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 1071 if (ret) 1072 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 1073 1074 return ret; 1075 } 1076 1077 static int fsl_esai_remove(struct platform_device *pdev) 1078 { 1079 struct fsl_esai *esai_priv = platform_get_drvdata(pdev); 1080 1081 pm_runtime_disable(&pdev->dev); 1082 cancel_work_sync(&esai_priv->work); 1083 1084 return 0; 1085 } 1086 1087 static const struct of_device_id fsl_esai_dt_ids[] = { 1088 { .compatible = "fsl,imx35-esai", .data = &fsl_esai_imx35 }, 1089 { .compatible = "fsl,vf610-esai", .data = &fsl_esai_vf610 }, 1090 { .compatible = "fsl,imx6ull-esai", .data = &fsl_esai_imx6ull }, 1091 {} 1092 }; 1093 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 1094 1095 #ifdef CONFIG_PM 1096 static int fsl_esai_runtime_resume(struct device *dev) 1097 { 1098 struct fsl_esai *esai = dev_get_drvdata(dev); 1099 int ret; 1100 1101 /* 1102 * Some platforms might use the same bit to gate all three or two of 1103 * clocks, so keep all clocks open/close at the same time for safety 1104 */ 1105 ret = clk_prepare_enable(esai->coreclk); 1106 if (ret) 1107 return ret; 1108 if (!IS_ERR(esai->spbaclk)) { 1109 ret = clk_prepare_enable(esai->spbaclk); 1110 if (ret) 1111 goto err_spbaclk; 1112 } 1113 if (!IS_ERR(esai->extalclk)) { 1114 ret = clk_prepare_enable(esai->extalclk); 1115 if (ret) 1116 goto err_extalclk; 1117 } 1118 if (!IS_ERR(esai->fsysclk)) { 1119 ret = clk_prepare_enable(esai->fsysclk); 1120 if (ret) 1121 goto err_fsysclk; 1122 } 1123 1124 regcache_cache_only(esai->regmap, false); 1125 1126 ret = fsl_esai_register_restore(esai); 1127 if (ret) 1128 goto err_regcache_sync; 1129 1130 return 0; 1131 1132 err_regcache_sync: 1133 if (!IS_ERR(esai->fsysclk)) 1134 clk_disable_unprepare(esai->fsysclk); 1135 err_fsysclk: 1136 if (!IS_ERR(esai->extalclk)) 1137 clk_disable_unprepare(esai->extalclk); 1138 err_extalclk: 1139 if (!IS_ERR(esai->spbaclk)) 1140 clk_disable_unprepare(esai->spbaclk); 1141 err_spbaclk: 1142 clk_disable_unprepare(esai->coreclk); 1143 1144 return ret; 1145 } 1146 1147 static int fsl_esai_runtime_suspend(struct device *dev) 1148 { 1149 struct fsl_esai *esai = dev_get_drvdata(dev); 1150 1151 regcache_cache_only(esai->regmap, true); 1152 1153 if (!IS_ERR(esai->fsysclk)) 1154 clk_disable_unprepare(esai->fsysclk); 1155 if (!IS_ERR(esai->extalclk)) 1156 clk_disable_unprepare(esai->extalclk); 1157 if (!IS_ERR(esai->spbaclk)) 1158 clk_disable_unprepare(esai->spbaclk); 1159 clk_disable_unprepare(esai->coreclk); 1160 1161 return 0; 1162 } 1163 #endif /* CONFIG_PM */ 1164 1165 static const struct dev_pm_ops fsl_esai_pm_ops = { 1166 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend, 1167 fsl_esai_runtime_resume, 1168 NULL) 1169 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1170 pm_runtime_force_resume) 1171 }; 1172 1173 static struct platform_driver fsl_esai_driver = { 1174 .probe = fsl_esai_probe, 1175 .remove = fsl_esai_remove, 1176 .driver = { 1177 .name = "fsl-esai-dai", 1178 .pm = &fsl_esai_pm_ops, 1179 .of_match_table = fsl_esai_dt_ids, 1180 }, 1181 }; 1182 1183 module_platform_driver(fsl_esai_driver); 1184 1185 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1186 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 1187 MODULE_LICENSE("GPL v2"); 1188 MODULE_ALIAS("platform:fsl-esai-dai"); 1189