1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/module.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <sound/dmaengine_pcm.h> 14 #include <sound/pcm_params.h> 15 16 #include "fsl_esai.h" 17 #include "imx-pcm.h" 18 19 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 20 SNDRV_PCM_FMTBIT_S16_LE | \ 21 SNDRV_PCM_FMTBIT_S20_3LE | \ 22 SNDRV_PCM_FMTBIT_S24_LE) 23 24 /** 25 * fsl_esai: ESAI private data 26 * 27 * @dma_params_rx: DMA parameters for receive channel 28 * @dma_params_tx: DMA parameters for transmit channel 29 * @pdev: platform device pointer 30 * @regmap: regmap handler 31 * @coreclk: clock source to access register 32 * @extalclk: esai clock source to derive HCK, SCK and FS 33 * @fsysclk: system clock source to derive HCK, SCK and FS 34 * @spbaclk: SPBA clock (optional, depending on SoC design) 35 * @task: tasklet to handle the reset operation 36 * @fifo_depth: depth of tx/rx FIFO 37 * @slot_width: width of each DAI slot 38 * @slots: number of slots 39 * @channels: channel num for tx or rx 40 * @hck_rate: clock rate of desired HCKx clock 41 * @sck_rate: clock rate of desired SCKx clock 42 * @hck_dir: the direction of HCKx pads 43 * @sck_div: if using PSR/PM dividers for SCKx clock 44 * @slave_mode: if fully using DAI slave mode 45 * @synchronous: if using tx/rx synchronous mode 46 * @reset_at_xrun: flags for enable reset operaton 47 * @name: driver name 48 */ 49 struct fsl_esai { 50 struct snd_dmaengine_dai_dma_data dma_params_rx; 51 struct snd_dmaengine_dai_dma_data dma_params_tx; 52 struct platform_device *pdev; 53 struct regmap *regmap; 54 struct clk *coreclk; 55 struct clk *extalclk; 56 struct clk *fsysclk; 57 struct clk *spbaclk; 58 struct tasklet_struct task; 59 u32 fifo_depth; 60 u32 slot_width; 61 u32 slots; 62 u32 tx_mask; 63 u32 rx_mask; 64 u32 channels[2]; 65 u32 hck_rate[2]; 66 u32 sck_rate[2]; 67 bool hck_dir[2]; 68 bool sck_div[2]; 69 bool slave_mode; 70 bool synchronous; 71 bool reset_at_xrun; 72 char name[32]; 73 }; 74 75 static irqreturn_t esai_isr(int irq, void *devid) 76 { 77 struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 78 struct platform_device *pdev = esai_priv->pdev; 79 u32 esr; 80 u32 saisr; 81 82 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 83 regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr); 84 85 if ((saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE)) && 86 esai_priv->reset_at_xrun) { 87 dev_dbg(&pdev->dev, "reset module for xrun\n"); 88 tasklet_schedule(&esai_priv->task); 89 } 90 91 if (esr & ESAI_ESR_TINIT_MASK) 92 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 93 94 if (esr & ESAI_ESR_RFF_MASK) 95 dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 96 97 if (esr & ESAI_ESR_TFE_MASK) 98 dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 99 100 if (esr & ESAI_ESR_TLS_MASK) 101 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 102 103 if (esr & ESAI_ESR_TDE_MASK) 104 dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 105 106 if (esr & ESAI_ESR_TED_MASK) 107 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 108 109 if (esr & ESAI_ESR_TD_MASK) 110 dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 111 112 if (esr & ESAI_ESR_RLS_MASK) 113 dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 114 115 if (esr & ESAI_ESR_RDE_MASK) 116 dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 117 118 if (esr & ESAI_ESR_RED_MASK) 119 dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 120 121 if (esr & ESAI_ESR_RD_MASK) 122 dev_dbg(&pdev->dev, "isr: Receiving data\n"); 123 124 return IRQ_HANDLED; 125 } 126 127 /** 128 * This function is used to calculate the divisors of psr, pm, fp and it is 129 * supposed to be called in set_dai_sysclk() and set_bclk(). 130 * 131 * @ratio: desired overall ratio for the paticipating dividers 132 * @usefp: for HCK setting, there is no need to set fp divider 133 * @fp: bypass other dividers by setting fp directly if fp != 0 134 * @tx: current setting is for playback or capture 135 */ 136 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 137 bool usefp, u32 fp) 138 { 139 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 140 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 141 142 maxfp = usefp ? 16 : 1; 143 144 if (usefp && fp) 145 goto out_fp; 146 147 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 148 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 149 2 * 8 * 256 * maxfp); 150 return -EINVAL; 151 } else if (ratio % 2) { 152 dev_err(dai->dev, "the raio must be even if using upper divider\n"); 153 return -EINVAL; 154 } 155 156 ratio /= 2; 157 158 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 159 160 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 161 if (ratio <= 256) { 162 pm = ratio; 163 fp = 1; 164 goto out; 165 } 166 167 /* Set the max fluctuation -- 0.1% of the max devisor */ 168 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 169 170 /* Find the best value for PM */ 171 for (i = 1; i <= 256; i++) { 172 for (j = 1; j <= maxfp; j++) { 173 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 174 prod = (psr ? 1 : 8) * i * j; 175 176 if (prod == ratio) 177 sub = 0; 178 else if (prod / ratio == 1) 179 sub = prod - ratio; 180 else if (ratio / prod == 1) 181 sub = ratio - prod; 182 else 183 continue; 184 185 /* Calculate the fraction */ 186 sub = sub * 1000 / ratio; 187 if (sub < savesub) { 188 savesub = sub; 189 pm = i; 190 fp = j; 191 } 192 193 /* We are lucky */ 194 if (savesub == 0) 195 goto out; 196 } 197 } 198 199 if (pm == 999) { 200 dev_err(dai->dev, "failed to calculate proper divisors\n"); 201 return -EINVAL; 202 } 203 204 out: 205 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 206 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 207 psr | ESAI_xCCR_xPM(pm)); 208 209 out_fp: 210 /* Bypass fp if not being required */ 211 if (maxfp <= 1) 212 return 0; 213 214 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 215 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 216 217 return 0; 218 } 219 220 /** 221 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) 222 * 223 * @Parameters: 224 * clk_id: The clock source of HCKT/HCKR 225 * (Input from outside; output from inside, FSYS or EXTAL) 226 * freq: The required clock rate of HCKT/HCKR 227 * dir: The clock direction of HCKT/HCKR 228 * 229 * Note: If the direction is input, we do not care about clk_id. 230 */ 231 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 232 unsigned int freq, int dir) 233 { 234 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 235 struct clk *clksrc = esai_priv->extalclk; 236 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous); 237 bool in = dir == SND_SOC_CLOCK_IN; 238 u32 ratio, ecr = 0; 239 unsigned long clk_rate; 240 int ret; 241 242 if (freq == 0) { 243 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 244 in ? "in" : "out", tx ? 'T' : 'R'); 245 return -EINVAL; 246 } 247 248 /* Bypass divider settings if the requirement doesn't change */ 249 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 250 return 0; 251 252 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 253 esai_priv->sck_div[tx] = true; 254 255 /* Set the direction of HCKT/HCKR pins */ 256 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 257 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 258 259 if (in) 260 goto out; 261 262 switch (clk_id) { 263 case ESAI_HCKT_FSYS: 264 case ESAI_HCKR_FSYS: 265 clksrc = esai_priv->fsysclk; 266 break; 267 case ESAI_HCKT_EXTAL: 268 ecr |= ESAI_ECR_ETI; 269 break; 270 case ESAI_HCKR_EXTAL: 271 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI; 272 break; 273 default: 274 return -EINVAL; 275 } 276 277 if (IS_ERR(clksrc)) { 278 dev_err(dai->dev, "no assigned %s clock\n", 279 clk_id % 2 ? "extal" : "fsys"); 280 return PTR_ERR(clksrc); 281 } 282 clk_rate = clk_get_rate(clksrc); 283 284 ratio = clk_rate / freq; 285 if (ratio * freq > clk_rate) 286 ret = ratio * freq - clk_rate; 287 else if (ratio * freq < clk_rate) 288 ret = clk_rate - ratio * freq; 289 else 290 ret = 0; 291 292 /* Block if clock source can not be divided into the required rate */ 293 if (ret != 0 && clk_rate / ret < 1000) { 294 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 295 tx ? 'T' : 'R'); 296 return -EINVAL; 297 } 298 299 /* Only EXTAL source can be output directly without using PSR and PM */ 300 if (ratio == 1 && clksrc == esai_priv->extalclk) { 301 /* Bypass all the dividers if not being needed */ 302 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 303 goto out; 304 } else if (ratio < 2) { 305 /* The ratio should be no less than 2 if using other sources */ 306 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 307 tx ? 'T' : 'R'); 308 return -EINVAL; 309 } 310 311 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 312 if (ret) 313 return ret; 314 315 esai_priv->sck_div[tx] = false; 316 317 out: 318 esai_priv->hck_dir[tx] = dir; 319 esai_priv->hck_rate[tx] = freq; 320 321 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 322 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 323 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 324 325 return 0; 326 } 327 328 /** 329 * This function configures the related dividers according to the bclk rate 330 */ 331 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 332 { 333 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 334 u32 hck_rate = esai_priv->hck_rate[tx]; 335 u32 sub, ratio = hck_rate / freq; 336 int ret; 337 338 /* Don't apply for fully slave mode or unchanged bclk */ 339 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 340 return 0; 341 342 if (ratio * freq > hck_rate) 343 sub = ratio * freq - hck_rate; 344 else if (ratio * freq < hck_rate) 345 sub = hck_rate - ratio * freq; 346 else 347 sub = 0; 348 349 /* Block if clock source can not be divided into the required rate */ 350 if (sub != 0 && hck_rate / sub < 1000) { 351 dev_err(dai->dev, "failed to derive required SCK%c rate\n", 352 tx ? 'T' : 'R'); 353 return -EINVAL; 354 } 355 356 /* The ratio should be contented by FP alone if bypassing PM and PSR */ 357 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 358 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 359 return -EINVAL; 360 } 361 362 ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 363 esai_priv->sck_div[tx] ? 0 : ratio); 364 if (ret) 365 return ret; 366 367 /* Save current bclk rate */ 368 esai_priv->sck_rate[tx] = freq; 369 370 return 0; 371 } 372 373 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 374 u32 rx_mask, int slots, int slot_width) 375 { 376 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 377 378 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 379 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 380 381 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 382 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 383 384 esai_priv->slot_width = slot_width; 385 esai_priv->slots = slots; 386 esai_priv->tx_mask = tx_mask; 387 esai_priv->rx_mask = rx_mask; 388 389 return 0; 390 } 391 392 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 393 { 394 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 395 u32 xcr = 0, xccr = 0, mask; 396 397 /* DAI mode */ 398 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 399 case SND_SOC_DAIFMT_I2S: 400 /* Data on rising edge of bclk, frame low, 1clk before data */ 401 xcr |= ESAI_xCR_xFSR; 402 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 403 break; 404 case SND_SOC_DAIFMT_LEFT_J: 405 /* Data on rising edge of bclk, frame high */ 406 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 407 break; 408 case SND_SOC_DAIFMT_RIGHT_J: 409 /* Data on rising edge of bclk, frame high, right aligned */ 410 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 411 xcr |= ESAI_xCR_xWA; 412 break; 413 case SND_SOC_DAIFMT_DSP_A: 414 /* Data on rising edge of bclk, frame high, 1clk before data */ 415 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 416 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 417 break; 418 case SND_SOC_DAIFMT_DSP_B: 419 /* Data on rising edge of bclk, frame high */ 420 xcr |= ESAI_xCR_xFSL; 421 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 422 break; 423 default: 424 return -EINVAL; 425 } 426 427 /* DAI clock inversion */ 428 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 429 case SND_SOC_DAIFMT_NB_NF: 430 /* Nothing to do for both normal cases */ 431 break; 432 case SND_SOC_DAIFMT_IB_NF: 433 /* Invert bit clock */ 434 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 435 break; 436 case SND_SOC_DAIFMT_NB_IF: 437 /* Invert frame clock */ 438 xccr ^= ESAI_xCCR_xFSP; 439 break; 440 case SND_SOC_DAIFMT_IB_IF: 441 /* Invert both clocks */ 442 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 443 break; 444 default: 445 return -EINVAL; 446 } 447 448 esai_priv->slave_mode = false; 449 450 /* DAI clock master masks */ 451 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 452 case SND_SOC_DAIFMT_CBM_CFM: 453 esai_priv->slave_mode = true; 454 break; 455 case SND_SOC_DAIFMT_CBS_CFM: 456 xccr |= ESAI_xCCR_xCKD; 457 break; 458 case SND_SOC_DAIFMT_CBM_CFS: 459 xccr |= ESAI_xCCR_xFSD; 460 break; 461 case SND_SOC_DAIFMT_CBS_CFS: 462 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 463 break; 464 default: 465 return -EINVAL; 466 } 467 468 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; 469 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 470 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 471 472 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 473 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 474 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 475 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 476 477 return 0; 478 } 479 480 static int fsl_esai_startup(struct snd_pcm_substream *substream, 481 struct snd_soc_dai *dai) 482 { 483 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 484 485 if (!dai->active) { 486 /* Set synchronous mode */ 487 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 488 ESAI_SAICR_SYNC, esai_priv->synchronous ? 489 ESAI_SAICR_SYNC : 0); 490 491 /* Set a default slot number -- 2 */ 492 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 493 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 494 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 495 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 496 } 497 498 return 0; 499 500 } 501 502 static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 503 struct snd_pcm_hw_params *params, 504 struct snd_soc_dai *dai) 505 { 506 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 507 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 508 u32 width = params_width(params); 509 u32 channels = params_channels(params); 510 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 511 u32 slot_width = width; 512 u32 bclk, mask, val; 513 int ret; 514 515 /* Override slot_width if being specifically set */ 516 if (esai_priv->slot_width) 517 slot_width = esai_priv->slot_width; 518 519 bclk = params_rate(params) * slot_width * esai_priv->slots; 520 521 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk); 522 if (ret) 523 return ret; 524 525 mask = ESAI_xCR_xSWS_MASK; 526 val = ESAI_xCR_xSWS(slot_width, width); 527 528 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 529 /* Recording in synchronous mode needs to set TCR also */ 530 if (!tx && esai_priv->synchronous) 531 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); 532 533 /* Use Normal mode to support monaural audio */ 534 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 535 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 536 ESAI_xCR_xMOD_NETWORK : 0); 537 538 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 539 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 540 541 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 542 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 543 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 544 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 545 546 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 547 548 if (tx) 549 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 550 ESAI_xCR_PADC, ESAI_xCR_PADC); 551 552 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 553 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 554 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 555 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 556 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 557 return 0; 558 } 559 560 static int fsl_esai_hw_init(struct fsl_esai *esai_priv) 561 { 562 struct platform_device *pdev = esai_priv->pdev; 563 int ret; 564 565 /* Reset ESAI unit */ 566 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 567 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 568 ESAI_ECR_ESAIEN | ESAI_ECR_ERST); 569 if (ret) { 570 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 571 return ret; 572 } 573 574 /* 575 * We need to enable ESAI so as to access some of its registers. 576 * Otherwise, we would fail to dump regmap from user space. 577 */ 578 ret = regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 579 ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK, 580 ESAI_ECR_ESAIEN); 581 if (ret) { 582 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 583 return ret; 584 } 585 586 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 587 ESAI_PRRC_PDC_MASK, 0); 588 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 589 ESAI_PCRC_PC_MASK, 0); 590 591 return 0; 592 } 593 594 static int fsl_esai_register_restore(struct fsl_esai *esai_priv) 595 { 596 int ret; 597 598 /* FIFO reset for safety */ 599 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, 600 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 601 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, 602 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 603 604 regcache_mark_dirty(esai_priv->regmap); 605 ret = regcache_sync(esai_priv->regmap); 606 if (ret) 607 return ret; 608 609 /* FIFO reset done */ 610 regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 611 regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 612 613 return 0; 614 } 615 616 static void fsl_esai_trigger_start(struct fsl_esai *esai_priv, bool tx) 617 { 618 u8 i, channels = esai_priv->channels[tx]; 619 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 620 u32 mask; 621 622 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 623 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 624 625 /* Write initial words reqiured by ESAI as normal procedure */ 626 for (i = 0; tx && i < channels; i++) 627 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 628 629 /* 630 * When set the TE/RE in the end of enablement flow, there 631 * will be channel swap issue for multi data line case. 632 * In order to workaround this issue, we switch the bit 633 * enablement sequence to below sequence 634 * 1) clear the xSMB & xSMA: which is done in probe and 635 * stop state. 636 * 2) set TE/RE 637 * 3) set xSMB 638 * 4) set xSMA: xSMA is the last one in this flow, which 639 * will trigger esai to start. 640 */ 641 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 642 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 643 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 644 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; 645 646 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 647 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); 648 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 649 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); 650 651 /* Enable Exception interrupt */ 652 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 653 ESAI_xCR_xEIE_MASK, ESAI_xCR_xEIE); 654 } 655 656 static void fsl_esai_trigger_stop(struct fsl_esai *esai_priv, bool tx) 657 { 658 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 659 ESAI_xCR_xEIE_MASK, 0); 660 661 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 662 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 663 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 664 ESAI_xSMA_xS_MASK, 0); 665 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 666 ESAI_xSMB_xS_MASK, 0); 667 668 /* Disable and reset FIFO */ 669 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 670 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 671 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 672 ESAI_xFCR_xFR, 0); 673 } 674 675 static void fsl_esai_hw_reset(unsigned long arg) 676 { 677 struct fsl_esai *esai_priv = (struct fsl_esai *)arg; 678 bool tx = true, rx = false, enabled[2]; 679 u32 tfcr, rfcr; 680 681 /* Save the registers */ 682 regmap_read(esai_priv->regmap, REG_ESAI_TFCR, &tfcr); 683 regmap_read(esai_priv->regmap, REG_ESAI_RFCR, &rfcr); 684 enabled[tx] = tfcr & ESAI_xFCR_xFEN; 685 enabled[rx] = rfcr & ESAI_xFCR_xFEN; 686 687 /* Stop the tx & rx */ 688 fsl_esai_trigger_stop(esai_priv, tx); 689 fsl_esai_trigger_stop(esai_priv, rx); 690 691 /* Reset the esai, and ignore return value */ 692 fsl_esai_hw_init(esai_priv); 693 694 /* Enforce ESAI personal resets for both TX and RX */ 695 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 696 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 697 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 698 ESAI_xCR_xPR_MASK, ESAI_xCR_xPR); 699 700 /* Restore registers by regcache_sync, and ignore return value */ 701 fsl_esai_register_restore(esai_priv); 702 703 /* Remove ESAI personal resets by configuring PCRC and PRRC also */ 704 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 705 ESAI_xCR_xPR_MASK, 0); 706 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, 707 ESAI_xCR_xPR_MASK, 0); 708 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 709 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 710 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 711 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 712 713 /* Restart tx / rx, if they already enabled */ 714 if (enabled[tx]) 715 fsl_esai_trigger_start(esai_priv, tx); 716 if (enabled[rx]) 717 fsl_esai_trigger_start(esai_priv, rx); 718 } 719 720 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 721 struct snd_soc_dai *dai) 722 { 723 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 724 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 725 726 esai_priv->channels[tx] = substream->runtime->channels; 727 728 switch (cmd) { 729 case SNDRV_PCM_TRIGGER_START: 730 case SNDRV_PCM_TRIGGER_RESUME: 731 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 732 fsl_esai_trigger_start(esai_priv, tx); 733 break; 734 case SNDRV_PCM_TRIGGER_SUSPEND: 735 case SNDRV_PCM_TRIGGER_STOP: 736 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 737 fsl_esai_trigger_stop(esai_priv, tx); 738 break; 739 default: 740 return -EINVAL; 741 } 742 743 return 0; 744 } 745 746 static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 747 .startup = fsl_esai_startup, 748 .trigger = fsl_esai_trigger, 749 .hw_params = fsl_esai_hw_params, 750 .set_sysclk = fsl_esai_set_dai_sysclk, 751 .set_fmt = fsl_esai_set_dai_fmt, 752 .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 753 }; 754 755 static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 756 { 757 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 758 759 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 760 &esai_priv->dma_params_rx); 761 762 return 0; 763 } 764 765 static struct snd_soc_dai_driver fsl_esai_dai = { 766 .probe = fsl_esai_dai_probe, 767 .playback = { 768 .stream_name = "CPU-Playback", 769 .channels_min = 1, 770 .channels_max = 12, 771 .rates = SNDRV_PCM_RATE_8000_192000, 772 .formats = FSL_ESAI_FORMATS, 773 }, 774 .capture = { 775 .stream_name = "CPU-Capture", 776 .channels_min = 1, 777 .channels_max = 8, 778 .rates = SNDRV_PCM_RATE_8000_192000, 779 .formats = FSL_ESAI_FORMATS, 780 }, 781 .ops = &fsl_esai_dai_ops, 782 }; 783 784 static const struct snd_soc_component_driver fsl_esai_component = { 785 .name = "fsl-esai", 786 }; 787 788 static const struct reg_default fsl_esai_reg_defaults[] = { 789 {REG_ESAI_ETDR, 0x00000000}, 790 {REG_ESAI_ECR, 0x00000000}, 791 {REG_ESAI_TFCR, 0x00000000}, 792 {REG_ESAI_RFCR, 0x00000000}, 793 {REG_ESAI_TX0, 0x00000000}, 794 {REG_ESAI_TX1, 0x00000000}, 795 {REG_ESAI_TX2, 0x00000000}, 796 {REG_ESAI_TX3, 0x00000000}, 797 {REG_ESAI_TX4, 0x00000000}, 798 {REG_ESAI_TX5, 0x00000000}, 799 {REG_ESAI_TSR, 0x00000000}, 800 {REG_ESAI_SAICR, 0x00000000}, 801 {REG_ESAI_TCR, 0x00000000}, 802 {REG_ESAI_TCCR, 0x00000000}, 803 {REG_ESAI_RCR, 0x00000000}, 804 {REG_ESAI_RCCR, 0x00000000}, 805 {REG_ESAI_TSMA, 0x0000ffff}, 806 {REG_ESAI_TSMB, 0x0000ffff}, 807 {REG_ESAI_RSMA, 0x0000ffff}, 808 {REG_ESAI_RSMB, 0x0000ffff}, 809 {REG_ESAI_PRRC, 0x00000000}, 810 {REG_ESAI_PCRC, 0x00000000}, 811 }; 812 813 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 814 { 815 switch (reg) { 816 case REG_ESAI_ERDR: 817 case REG_ESAI_ECR: 818 case REG_ESAI_ESR: 819 case REG_ESAI_TFCR: 820 case REG_ESAI_TFSR: 821 case REG_ESAI_RFCR: 822 case REG_ESAI_RFSR: 823 case REG_ESAI_RX0: 824 case REG_ESAI_RX1: 825 case REG_ESAI_RX2: 826 case REG_ESAI_RX3: 827 case REG_ESAI_SAISR: 828 case REG_ESAI_SAICR: 829 case REG_ESAI_TCR: 830 case REG_ESAI_TCCR: 831 case REG_ESAI_RCR: 832 case REG_ESAI_RCCR: 833 case REG_ESAI_TSMA: 834 case REG_ESAI_TSMB: 835 case REG_ESAI_RSMA: 836 case REG_ESAI_RSMB: 837 case REG_ESAI_PRRC: 838 case REG_ESAI_PCRC: 839 return true; 840 default: 841 return false; 842 } 843 } 844 845 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 846 { 847 switch (reg) { 848 case REG_ESAI_ERDR: 849 case REG_ESAI_ESR: 850 case REG_ESAI_TFSR: 851 case REG_ESAI_RFSR: 852 case REG_ESAI_RX0: 853 case REG_ESAI_RX1: 854 case REG_ESAI_RX2: 855 case REG_ESAI_RX3: 856 case REG_ESAI_SAISR: 857 return true; 858 default: 859 return false; 860 } 861 } 862 863 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 864 { 865 switch (reg) { 866 case REG_ESAI_ETDR: 867 case REG_ESAI_ECR: 868 case REG_ESAI_TFCR: 869 case REG_ESAI_RFCR: 870 case REG_ESAI_TX0: 871 case REG_ESAI_TX1: 872 case REG_ESAI_TX2: 873 case REG_ESAI_TX3: 874 case REG_ESAI_TX4: 875 case REG_ESAI_TX5: 876 case REG_ESAI_TSR: 877 case REG_ESAI_SAICR: 878 case REG_ESAI_TCR: 879 case REG_ESAI_TCCR: 880 case REG_ESAI_RCR: 881 case REG_ESAI_RCCR: 882 case REG_ESAI_TSMA: 883 case REG_ESAI_TSMB: 884 case REG_ESAI_RSMA: 885 case REG_ESAI_RSMB: 886 case REG_ESAI_PRRC: 887 case REG_ESAI_PCRC: 888 return true; 889 default: 890 return false; 891 } 892 } 893 894 static const struct regmap_config fsl_esai_regmap_config = { 895 .reg_bits = 32, 896 .reg_stride = 4, 897 .val_bits = 32, 898 899 .max_register = REG_ESAI_PCRC, 900 .reg_defaults = fsl_esai_reg_defaults, 901 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 902 .readable_reg = fsl_esai_readable_reg, 903 .volatile_reg = fsl_esai_volatile_reg, 904 .writeable_reg = fsl_esai_writeable_reg, 905 .cache_type = REGCACHE_FLAT, 906 }; 907 908 static int fsl_esai_probe(struct platform_device *pdev) 909 { 910 struct device_node *np = pdev->dev.of_node; 911 struct fsl_esai *esai_priv; 912 struct resource *res; 913 const __be32 *iprop; 914 void __iomem *regs; 915 int irq, ret; 916 917 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 918 if (!esai_priv) 919 return -ENOMEM; 920 921 esai_priv->pdev = pdev; 922 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 923 924 if (of_device_is_compatible(np, "fsl,vf610-esai") || 925 of_device_is_compatible(np, "fsl,imx35-esai")) 926 esai_priv->reset_at_xrun = true; 927 928 /* Get the addresses and IRQ */ 929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 930 regs = devm_ioremap_resource(&pdev->dev, res); 931 if (IS_ERR(regs)) 932 return PTR_ERR(regs); 933 934 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 935 "core", regs, &fsl_esai_regmap_config); 936 if (IS_ERR(esai_priv->regmap)) { 937 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 938 PTR_ERR(esai_priv->regmap)); 939 return PTR_ERR(esai_priv->regmap); 940 } 941 942 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 943 if (IS_ERR(esai_priv->coreclk)) { 944 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 945 PTR_ERR(esai_priv->coreclk)); 946 return PTR_ERR(esai_priv->coreclk); 947 } 948 949 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 950 if (IS_ERR(esai_priv->extalclk)) 951 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 952 PTR_ERR(esai_priv->extalclk)); 953 954 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 955 if (IS_ERR(esai_priv->fsysclk)) 956 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 957 PTR_ERR(esai_priv->fsysclk)); 958 959 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 960 if (IS_ERR(esai_priv->spbaclk)) 961 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 962 PTR_ERR(esai_priv->spbaclk)); 963 964 irq = platform_get_irq(pdev, 0); 965 if (irq < 0) 966 return irq; 967 968 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, 969 esai_priv->name, esai_priv); 970 if (ret) { 971 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 972 return ret; 973 } 974 975 /* Set a default slot number */ 976 esai_priv->slots = 2; 977 978 /* Set a default master/slave state */ 979 esai_priv->slave_mode = true; 980 981 /* Determine the FIFO depth */ 982 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 983 if (iprop) 984 esai_priv->fifo_depth = be32_to_cpup(iprop); 985 else 986 esai_priv->fifo_depth = 64; 987 988 esai_priv->dma_params_tx.maxburst = 16; 989 esai_priv->dma_params_rx.maxburst = 16; 990 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 991 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 992 993 esai_priv->synchronous = 994 of_property_read_bool(np, "fsl,esai-synchronous"); 995 996 /* Implement full symmetry for synchronous mode */ 997 if (esai_priv->synchronous) { 998 fsl_esai_dai.symmetric_rates = 1; 999 fsl_esai_dai.symmetric_channels = 1; 1000 fsl_esai_dai.symmetric_samplebits = 1; 1001 } 1002 1003 dev_set_drvdata(&pdev->dev, esai_priv); 1004 1005 ret = fsl_esai_hw_init(esai_priv); 1006 if (ret) 1007 return ret; 1008 1009 esai_priv->tx_mask = 0xFFFFFFFF; 1010 esai_priv->rx_mask = 0xFFFFFFFF; 1011 1012 /* Clear the TSMA, TSMB, RSMA, RSMB */ 1013 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0); 1014 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0); 1015 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0); 1016 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0); 1017 1018 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 1019 &fsl_esai_dai, 1); 1020 if (ret) { 1021 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 1022 return ret; 1023 } 1024 1025 tasklet_init(&esai_priv->task, fsl_esai_hw_reset, 1026 (unsigned long)esai_priv); 1027 1028 pm_runtime_enable(&pdev->dev); 1029 1030 regcache_cache_only(esai_priv->regmap, true); 1031 1032 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 1033 if (ret) 1034 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 1035 1036 return ret; 1037 } 1038 1039 static int fsl_esai_remove(struct platform_device *pdev) 1040 { 1041 struct fsl_esai *esai_priv = platform_get_drvdata(pdev); 1042 1043 pm_runtime_disable(&pdev->dev); 1044 tasklet_kill(&esai_priv->task); 1045 1046 return 0; 1047 } 1048 1049 static const struct of_device_id fsl_esai_dt_ids[] = { 1050 { .compatible = "fsl,imx35-esai", }, 1051 { .compatible = "fsl,vf610-esai", }, 1052 {} 1053 }; 1054 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 1055 1056 #ifdef CONFIG_PM 1057 static int fsl_esai_runtime_resume(struct device *dev) 1058 { 1059 struct fsl_esai *esai = dev_get_drvdata(dev); 1060 int ret; 1061 1062 /* 1063 * Some platforms might use the same bit to gate all three or two of 1064 * clocks, so keep all clocks open/close at the same time for safety 1065 */ 1066 ret = clk_prepare_enable(esai->coreclk); 1067 if (ret) 1068 return ret; 1069 if (!IS_ERR(esai->spbaclk)) { 1070 ret = clk_prepare_enable(esai->spbaclk); 1071 if (ret) 1072 goto err_spbaclk; 1073 } 1074 if (!IS_ERR(esai->extalclk)) { 1075 ret = clk_prepare_enable(esai->extalclk); 1076 if (ret) 1077 goto err_extalclk; 1078 } 1079 if (!IS_ERR(esai->fsysclk)) { 1080 ret = clk_prepare_enable(esai->fsysclk); 1081 if (ret) 1082 goto err_fsysclk; 1083 } 1084 1085 regcache_cache_only(esai->regmap, false); 1086 1087 ret = fsl_esai_register_restore(esai); 1088 if (ret) 1089 goto err_regcache_sync; 1090 1091 return 0; 1092 1093 err_regcache_sync: 1094 if (!IS_ERR(esai->fsysclk)) 1095 clk_disable_unprepare(esai->fsysclk); 1096 err_fsysclk: 1097 if (!IS_ERR(esai->extalclk)) 1098 clk_disable_unprepare(esai->extalclk); 1099 err_extalclk: 1100 if (!IS_ERR(esai->spbaclk)) 1101 clk_disable_unprepare(esai->spbaclk); 1102 err_spbaclk: 1103 clk_disable_unprepare(esai->coreclk); 1104 1105 return ret; 1106 } 1107 1108 static int fsl_esai_runtime_suspend(struct device *dev) 1109 { 1110 struct fsl_esai *esai = dev_get_drvdata(dev); 1111 1112 regcache_cache_only(esai->regmap, true); 1113 1114 if (!IS_ERR(esai->fsysclk)) 1115 clk_disable_unprepare(esai->fsysclk); 1116 if (!IS_ERR(esai->extalclk)) 1117 clk_disable_unprepare(esai->extalclk); 1118 if (!IS_ERR(esai->spbaclk)) 1119 clk_disable_unprepare(esai->spbaclk); 1120 clk_disable_unprepare(esai->coreclk); 1121 1122 return 0; 1123 } 1124 #endif /* CONFIG_PM */ 1125 1126 static const struct dev_pm_ops fsl_esai_pm_ops = { 1127 SET_RUNTIME_PM_OPS(fsl_esai_runtime_suspend, 1128 fsl_esai_runtime_resume, 1129 NULL) 1130 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1131 pm_runtime_force_resume) 1132 }; 1133 1134 static struct platform_driver fsl_esai_driver = { 1135 .probe = fsl_esai_probe, 1136 .remove = fsl_esai_remove, 1137 .driver = { 1138 .name = "fsl-esai-dai", 1139 .pm = &fsl_esai_pm_ops, 1140 .of_match_table = fsl_esai_dt_ids, 1141 }, 1142 }; 1143 1144 module_platform_driver(fsl_esai_driver); 1145 1146 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1147 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 1148 MODULE_LICENSE("GPL v2"); 1149 MODULE_ALIAS("platform:fsl-esai-dai"); 1150