1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/module.h> 10 #include <linux/of_irq.h> 11 #include <linux/of_platform.h> 12 #include <sound/dmaengine_pcm.h> 13 #include <sound/pcm_params.h> 14 15 #include "fsl_esai.h" 16 #include "imx-pcm.h" 17 18 #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 19 SNDRV_PCM_FMTBIT_S16_LE | \ 20 SNDRV_PCM_FMTBIT_S20_3LE | \ 21 SNDRV_PCM_FMTBIT_S24_LE) 22 23 /** 24 * fsl_esai: ESAI private data 25 * 26 * @dma_params_rx: DMA parameters for receive channel 27 * @dma_params_tx: DMA parameters for transmit channel 28 * @pdev: platform device pointer 29 * @regmap: regmap handler 30 * @coreclk: clock source to access register 31 * @extalclk: esai clock source to derive HCK, SCK and FS 32 * @fsysclk: system clock source to derive HCK, SCK and FS 33 * @spbaclk: SPBA clock (optional, depending on SoC design) 34 * @fifo_depth: depth of tx/rx FIFO 35 * @slot_width: width of each DAI slot 36 * @slots: number of slots 37 * @hck_rate: clock rate of desired HCKx clock 38 * @sck_rate: clock rate of desired SCKx clock 39 * @hck_dir: the direction of HCKx pads 40 * @sck_div: if using PSR/PM dividers for SCKx clock 41 * @slave_mode: if fully using DAI slave mode 42 * @synchronous: if using tx/rx synchronous mode 43 * @name: driver name 44 */ 45 struct fsl_esai { 46 struct snd_dmaengine_dai_dma_data dma_params_rx; 47 struct snd_dmaengine_dai_dma_data dma_params_tx; 48 struct platform_device *pdev; 49 struct regmap *regmap; 50 struct clk *coreclk; 51 struct clk *extalclk; 52 struct clk *fsysclk; 53 struct clk *spbaclk; 54 u32 fifo_depth; 55 u32 slot_width; 56 u32 slots; 57 u32 tx_mask; 58 u32 rx_mask; 59 u32 hck_rate[2]; 60 u32 sck_rate[2]; 61 bool hck_dir[2]; 62 bool sck_div[2]; 63 bool slave_mode; 64 bool synchronous; 65 char name[32]; 66 }; 67 68 static irqreturn_t esai_isr(int irq, void *devid) 69 { 70 struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 71 struct platform_device *pdev = esai_priv->pdev; 72 u32 esr; 73 74 regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 75 76 if (esr & ESAI_ESR_TINIT_MASK) 77 dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 78 79 if (esr & ESAI_ESR_RFF_MASK) 80 dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 81 82 if (esr & ESAI_ESR_TFE_MASK) 83 dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 84 85 if (esr & ESAI_ESR_TLS_MASK) 86 dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 87 88 if (esr & ESAI_ESR_TDE_MASK) 89 dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 90 91 if (esr & ESAI_ESR_TED_MASK) 92 dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 93 94 if (esr & ESAI_ESR_TD_MASK) 95 dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 96 97 if (esr & ESAI_ESR_RLS_MASK) 98 dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 99 100 if (esr & ESAI_ESR_RDE_MASK) 101 dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 102 103 if (esr & ESAI_ESR_RED_MASK) 104 dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 105 106 if (esr & ESAI_ESR_RD_MASK) 107 dev_dbg(&pdev->dev, "isr: Receiving data\n"); 108 109 return IRQ_HANDLED; 110 } 111 112 /** 113 * This function is used to calculate the divisors of psr, pm, fp and it is 114 * supposed to be called in set_dai_sysclk() and set_bclk(). 115 * 116 * @ratio: desired overall ratio for the paticipating dividers 117 * @usefp: for HCK setting, there is no need to set fp divider 118 * @fp: bypass other dividers by setting fp directly if fp != 0 119 * @tx: current setting is for playback or capture 120 */ 121 static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 122 bool usefp, u32 fp) 123 { 124 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 125 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 126 127 maxfp = usefp ? 16 : 1; 128 129 if (usefp && fp) 130 goto out_fp; 131 132 if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 133 dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 134 2 * 8 * 256 * maxfp); 135 return -EINVAL; 136 } else if (ratio % 2) { 137 dev_err(dai->dev, "the raio must be even if using upper divider\n"); 138 return -EINVAL; 139 } 140 141 ratio /= 2; 142 143 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 144 145 /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 146 if (ratio <= 256) { 147 pm = ratio; 148 fp = 1; 149 goto out; 150 } 151 152 /* Set the max fluctuation -- 0.1% of the max devisor */ 153 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 154 155 /* Find the best value for PM */ 156 for (i = 1; i <= 256; i++) { 157 for (j = 1; j <= maxfp; j++) { 158 /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 159 prod = (psr ? 1 : 8) * i * j; 160 161 if (prod == ratio) 162 sub = 0; 163 else if (prod / ratio == 1) 164 sub = prod - ratio; 165 else if (ratio / prod == 1) 166 sub = ratio - prod; 167 else 168 continue; 169 170 /* Calculate the fraction */ 171 sub = sub * 1000 / ratio; 172 if (sub < savesub) { 173 savesub = sub; 174 pm = i; 175 fp = j; 176 } 177 178 /* We are lucky */ 179 if (savesub == 0) 180 goto out; 181 } 182 } 183 184 if (pm == 999) { 185 dev_err(dai->dev, "failed to calculate proper divisors\n"); 186 return -EINVAL; 187 } 188 189 out: 190 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 191 ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 192 psr | ESAI_xCCR_xPM(pm)); 193 194 out_fp: 195 /* Bypass fp if not being required */ 196 if (maxfp <= 1) 197 return 0; 198 199 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 200 ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 201 202 return 0; 203 } 204 205 /** 206 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) 207 * 208 * @Parameters: 209 * clk_id: The clock source of HCKT/HCKR 210 * (Input from outside; output from inside, FSYS or EXTAL) 211 * freq: The required clock rate of HCKT/HCKR 212 * dir: The clock direction of HCKT/HCKR 213 * 214 * Note: If the direction is input, we do not care about clk_id. 215 */ 216 static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 217 unsigned int freq, int dir) 218 { 219 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 220 struct clk *clksrc = esai_priv->extalclk; 221 bool tx = (clk_id <= ESAI_HCKT_EXTAL || esai_priv->synchronous); 222 bool in = dir == SND_SOC_CLOCK_IN; 223 u32 ratio, ecr = 0; 224 unsigned long clk_rate; 225 int ret; 226 227 if (freq == 0) { 228 dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 229 in ? "in" : "out", tx ? 'T' : 'R'); 230 return -EINVAL; 231 } 232 233 /* Bypass divider settings if the requirement doesn't change */ 234 if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 235 return 0; 236 237 /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 238 esai_priv->sck_div[tx] = true; 239 240 /* Set the direction of HCKT/HCKR pins */ 241 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 242 ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 243 244 if (in) 245 goto out; 246 247 switch (clk_id) { 248 case ESAI_HCKT_FSYS: 249 case ESAI_HCKR_FSYS: 250 clksrc = esai_priv->fsysclk; 251 break; 252 case ESAI_HCKT_EXTAL: 253 ecr |= ESAI_ECR_ETI; 254 break; 255 case ESAI_HCKR_EXTAL: 256 ecr |= esai_priv->synchronous ? ESAI_ECR_ETI : ESAI_ECR_ERI; 257 break; 258 default: 259 return -EINVAL; 260 } 261 262 if (IS_ERR(clksrc)) { 263 dev_err(dai->dev, "no assigned %s clock\n", 264 clk_id % 2 ? "extal" : "fsys"); 265 return PTR_ERR(clksrc); 266 } 267 clk_rate = clk_get_rate(clksrc); 268 269 ratio = clk_rate / freq; 270 if (ratio * freq > clk_rate) 271 ret = ratio * freq - clk_rate; 272 else if (ratio * freq < clk_rate) 273 ret = clk_rate - ratio * freq; 274 else 275 ret = 0; 276 277 /* Block if clock source can not be divided into the required rate */ 278 if (ret != 0 && clk_rate / ret < 1000) { 279 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 280 tx ? 'T' : 'R'); 281 return -EINVAL; 282 } 283 284 /* Only EXTAL source can be output directly without using PSR and PM */ 285 if (ratio == 1 && clksrc == esai_priv->extalclk) { 286 /* Bypass all the dividers if not being needed */ 287 ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 288 goto out; 289 } else if (ratio < 2) { 290 /* The ratio should be no less than 2 if using other sources */ 291 dev_err(dai->dev, "failed to derive required HCK%c rate\n", 292 tx ? 'T' : 'R'); 293 return -EINVAL; 294 } 295 296 ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 297 if (ret) 298 return ret; 299 300 esai_priv->sck_div[tx] = false; 301 302 out: 303 esai_priv->hck_dir[tx] = dir; 304 esai_priv->hck_rate[tx] = freq; 305 306 regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 307 tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 308 ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 309 310 return 0; 311 } 312 313 /** 314 * This function configures the related dividers according to the bclk rate 315 */ 316 static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 317 { 318 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 319 u32 hck_rate = esai_priv->hck_rate[tx]; 320 u32 sub, ratio = hck_rate / freq; 321 int ret; 322 323 /* Don't apply for fully slave mode or unchanged bclk */ 324 if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 325 return 0; 326 327 if (ratio * freq > hck_rate) 328 sub = ratio * freq - hck_rate; 329 else if (ratio * freq < hck_rate) 330 sub = hck_rate - ratio * freq; 331 else 332 sub = 0; 333 334 /* Block if clock source can not be divided into the required rate */ 335 if (sub != 0 && hck_rate / sub < 1000) { 336 dev_err(dai->dev, "failed to derive required SCK%c rate\n", 337 tx ? 'T' : 'R'); 338 return -EINVAL; 339 } 340 341 /* The ratio should be contented by FP alone if bypassing PM and PSR */ 342 if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 343 dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 344 return -EINVAL; 345 } 346 347 ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 348 esai_priv->sck_div[tx] ? 0 : ratio); 349 if (ret) 350 return ret; 351 352 /* Save current bclk rate */ 353 esai_priv->sck_rate[tx] = freq; 354 355 return 0; 356 } 357 358 static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 359 u32 rx_mask, int slots, int slot_width) 360 { 361 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 362 363 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 364 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 365 366 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 367 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 368 369 esai_priv->slot_width = slot_width; 370 esai_priv->slots = slots; 371 esai_priv->tx_mask = tx_mask; 372 esai_priv->rx_mask = rx_mask; 373 374 return 0; 375 } 376 377 static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 378 { 379 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 380 u32 xcr = 0, xccr = 0, mask; 381 382 /* DAI mode */ 383 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 384 case SND_SOC_DAIFMT_I2S: 385 /* Data on rising edge of bclk, frame low, 1clk before data */ 386 xcr |= ESAI_xCR_xFSR; 387 xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 388 break; 389 case SND_SOC_DAIFMT_LEFT_J: 390 /* Data on rising edge of bclk, frame high */ 391 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 392 break; 393 case SND_SOC_DAIFMT_RIGHT_J: 394 /* Data on rising edge of bclk, frame high, right aligned */ 395 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 396 xcr |= ESAI_xCR_xWA; 397 break; 398 case SND_SOC_DAIFMT_DSP_A: 399 /* Data on rising edge of bclk, frame high, 1clk before data */ 400 xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 401 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 402 break; 403 case SND_SOC_DAIFMT_DSP_B: 404 /* Data on rising edge of bclk, frame high */ 405 xcr |= ESAI_xCR_xFSL; 406 xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 407 break; 408 default: 409 return -EINVAL; 410 } 411 412 /* DAI clock inversion */ 413 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 414 case SND_SOC_DAIFMT_NB_NF: 415 /* Nothing to do for both normal cases */ 416 break; 417 case SND_SOC_DAIFMT_IB_NF: 418 /* Invert bit clock */ 419 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 420 break; 421 case SND_SOC_DAIFMT_NB_IF: 422 /* Invert frame clock */ 423 xccr ^= ESAI_xCCR_xFSP; 424 break; 425 case SND_SOC_DAIFMT_IB_IF: 426 /* Invert both clocks */ 427 xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 428 break; 429 default: 430 return -EINVAL; 431 } 432 433 esai_priv->slave_mode = false; 434 435 /* DAI clock master masks */ 436 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 437 case SND_SOC_DAIFMT_CBM_CFM: 438 esai_priv->slave_mode = true; 439 break; 440 case SND_SOC_DAIFMT_CBS_CFM: 441 xccr |= ESAI_xCCR_xCKD; 442 break; 443 case SND_SOC_DAIFMT_CBM_CFS: 444 xccr |= ESAI_xCCR_xFSD; 445 break; 446 case SND_SOC_DAIFMT_CBS_CFS: 447 xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 448 break; 449 default: 450 return -EINVAL; 451 } 452 453 mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR | ESAI_xCR_xWA; 454 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 455 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 456 457 mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 458 ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 459 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 460 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 461 462 return 0; 463 } 464 465 static int fsl_esai_startup(struct snd_pcm_substream *substream, 466 struct snd_soc_dai *dai) 467 { 468 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 469 int ret; 470 471 /* 472 * Some platforms might use the same bit to gate all three or two of 473 * clocks, so keep all clocks open/close at the same time for safety 474 */ 475 ret = clk_prepare_enable(esai_priv->coreclk); 476 if (ret) 477 return ret; 478 if (!IS_ERR(esai_priv->spbaclk)) { 479 ret = clk_prepare_enable(esai_priv->spbaclk); 480 if (ret) 481 goto err_spbaclk; 482 } 483 if (!IS_ERR(esai_priv->extalclk)) { 484 ret = clk_prepare_enable(esai_priv->extalclk); 485 if (ret) 486 goto err_extalck; 487 } 488 if (!IS_ERR(esai_priv->fsysclk)) { 489 ret = clk_prepare_enable(esai_priv->fsysclk); 490 if (ret) 491 goto err_fsysclk; 492 } 493 494 if (!dai->active) { 495 /* Set synchronous mode */ 496 regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 497 ESAI_SAICR_SYNC, esai_priv->synchronous ? 498 ESAI_SAICR_SYNC : 0); 499 500 /* Set a default slot number -- 2 */ 501 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 502 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 503 regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 504 ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 505 } 506 507 return 0; 508 509 err_fsysclk: 510 if (!IS_ERR(esai_priv->extalclk)) 511 clk_disable_unprepare(esai_priv->extalclk); 512 err_extalck: 513 if (!IS_ERR(esai_priv->spbaclk)) 514 clk_disable_unprepare(esai_priv->spbaclk); 515 err_spbaclk: 516 clk_disable_unprepare(esai_priv->coreclk); 517 518 return ret; 519 } 520 521 static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 522 struct snd_pcm_hw_params *params, 523 struct snd_soc_dai *dai) 524 { 525 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 526 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 527 u32 width = params_width(params); 528 u32 channels = params_channels(params); 529 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 530 u32 slot_width = width; 531 u32 bclk, mask, val; 532 int ret; 533 534 /* Override slot_width if being specifically set */ 535 if (esai_priv->slot_width) 536 slot_width = esai_priv->slot_width; 537 538 bclk = params_rate(params) * slot_width * esai_priv->slots; 539 540 ret = fsl_esai_set_bclk(dai, esai_priv->synchronous || tx, bclk); 541 if (ret) 542 return ret; 543 544 mask = ESAI_xCR_xSWS_MASK; 545 val = ESAI_xCR_xSWS(slot_width, width); 546 547 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 548 /* Recording in synchronous mode needs to set TCR also */ 549 if (!tx && esai_priv->synchronous) 550 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val); 551 552 /* Use Normal mode to support monaural audio */ 553 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 554 ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 555 ESAI_xCR_xMOD_NETWORK : 0); 556 557 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 558 ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 559 560 mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 561 (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 562 val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 563 (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 564 565 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 566 567 if (tx) 568 regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, 569 ESAI_xCR_PADC, ESAI_xCR_PADC); 570 571 /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 572 regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 573 ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 574 regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 575 ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 576 return 0; 577 } 578 579 static void fsl_esai_shutdown(struct snd_pcm_substream *substream, 580 struct snd_soc_dai *dai) 581 { 582 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 583 584 if (!IS_ERR(esai_priv->fsysclk)) 585 clk_disable_unprepare(esai_priv->fsysclk); 586 if (!IS_ERR(esai_priv->extalclk)) 587 clk_disable_unprepare(esai_priv->extalclk); 588 if (!IS_ERR(esai_priv->spbaclk)) 589 clk_disable_unprepare(esai_priv->spbaclk); 590 clk_disable_unprepare(esai_priv->coreclk); 591 } 592 593 static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 594 struct snd_soc_dai *dai) 595 { 596 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 597 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 598 u8 i, channels = substream->runtime->channels; 599 u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 600 u32 mask; 601 602 switch (cmd) { 603 case SNDRV_PCM_TRIGGER_START: 604 case SNDRV_PCM_TRIGGER_RESUME: 605 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 606 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 607 ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 608 609 /* Write initial words reqiured by ESAI as normal procedure */ 610 for (i = 0; tx && i < channels; i++) 611 regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 612 613 /* 614 * When set the TE/RE in the end of enablement flow, there 615 * will be channel swap issue for multi data line case. 616 * In order to workaround this issue, we switch the bit 617 * enablement sequence to below sequence 618 * 1) clear the xSMB & xSMA: which is done in probe and 619 * stop state. 620 * 2) set TE/RE 621 * 3) set xSMB 622 * 4) set xSMA: xSMA is the last one in this flow, which 623 * will trigger esai to start. 624 */ 625 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 626 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 627 tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 628 mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask; 629 630 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 631 ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask)); 632 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 633 ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask)); 634 635 break; 636 case SNDRV_PCM_TRIGGER_SUSPEND: 637 case SNDRV_PCM_TRIGGER_STOP: 638 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 639 regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 640 tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 641 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx), 642 ESAI_xSMA_xS_MASK, 0); 643 regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx), 644 ESAI_xSMB_xS_MASK, 0); 645 646 /* Disable and reset FIFO */ 647 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 648 ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 649 regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 650 ESAI_xFCR_xFR, 0); 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return 0; 657 } 658 659 static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 660 .startup = fsl_esai_startup, 661 .shutdown = fsl_esai_shutdown, 662 .trigger = fsl_esai_trigger, 663 .hw_params = fsl_esai_hw_params, 664 .set_sysclk = fsl_esai_set_dai_sysclk, 665 .set_fmt = fsl_esai_set_dai_fmt, 666 .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 667 }; 668 669 static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 670 { 671 struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 672 673 snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 674 &esai_priv->dma_params_rx); 675 676 return 0; 677 } 678 679 static struct snd_soc_dai_driver fsl_esai_dai = { 680 .probe = fsl_esai_dai_probe, 681 .playback = { 682 .stream_name = "CPU-Playback", 683 .channels_min = 1, 684 .channels_max = 12, 685 .rates = SNDRV_PCM_RATE_8000_192000, 686 .formats = FSL_ESAI_FORMATS, 687 }, 688 .capture = { 689 .stream_name = "CPU-Capture", 690 .channels_min = 1, 691 .channels_max = 8, 692 .rates = SNDRV_PCM_RATE_8000_192000, 693 .formats = FSL_ESAI_FORMATS, 694 }, 695 .ops = &fsl_esai_dai_ops, 696 }; 697 698 static const struct snd_soc_component_driver fsl_esai_component = { 699 .name = "fsl-esai", 700 }; 701 702 static const struct reg_default fsl_esai_reg_defaults[] = { 703 {REG_ESAI_ETDR, 0x00000000}, 704 {REG_ESAI_ECR, 0x00000000}, 705 {REG_ESAI_TFCR, 0x00000000}, 706 {REG_ESAI_RFCR, 0x00000000}, 707 {REG_ESAI_TX0, 0x00000000}, 708 {REG_ESAI_TX1, 0x00000000}, 709 {REG_ESAI_TX2, 0x00000000}, 710 {REG_ESAI_TX3, 0x00000000}, 711 {REG_ESAI_TX4, 0x00000000}, 712 {REG_ESAI_TX5, 0x00000000}, 713 {REG_ESAI_TSR, 0x00000000}, 714 {REG_ESAI_SAICR, 0x00000000}, 715 {REG_ESAI_TCR, 0x00000000}, 716 {REG_ESAI_TCCR, 0x00000000}, 717 {REG_ESAI_RCR, 0x00000000}, 718 {REG_ESAI_RCCR, 0x00000000}, 719 {REG_ESAI_TSMA, 0x0000ffff}, 720 {REG_ESAI_TSMB, 0x0000ffff}, 721 {REG_ESAI_RSMA, 0x0000ffff}, 722 {REG_ESAI_RSMB, 0x0000ffff}, 723 {REG_ESAI_PRRC, 0x00000000}, 724 {REG_ESAI_PCRC, 0x00000000}, 725 }; 726 727 static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 728 { 729 switch (reg) { 730 case REG_ESAI_ERDR: 731 case REG_ESAI_ECR: 732 case REG_ESAI_ESR: 733 case REG_ESAI_TFCR: 734 case REG_ESAI_TFSR: 735 case REG_ESAI_RFCR: 736 case REG_ESAI_RFSR: 737 case REG_ESAI_RX0: 738 case REG_ESAI_RX1: 739 case REG_ESAI_RX2: 740 case REG_ESAI_RX3: 741 case REG_ESAI_SAISR: 742 case REG_ESAI_SAICR: 743 case REG_ESAI_TCR: 744 case REG_ESAI_TCCR: 745 case REG_ESAI_RCR: 746 case REG_ESAI_RCCR: 747 case REG_ESAI_TSMA: 748 case REG_ESAI_TSMB: 749 case REG_ESAI_RSMA: 750 case REG_ESAI_RSMB: 751 case REG_ESAI_PRRC: 752 case REG_ESAI_PCRC: 753 return true; 754 default: 755 return false; 756 } 757 } 758 759 static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 760 { 761 switch (reg) { 762 case REG_ESAI_ERDR: 763 case REG_ESAI_ESR: 764 case REG_ESAI_TFSR: 765 case REG_ESAI_RFSR: 766 case REG_ESAI_RX0: 767 case REG_ESAI_RX1: 768 case REG_ESAI_RX2: 769 case REG_ESAI_RX3: 770 case REG_ESAI_SAISR: 771 return true; 772 default: 773 return false; 774 } 775 } 776 777 static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 778 { 779 switch (reg) { 780 case REG_ESAI_ETDR: 781 case REG_ESAI_ECR: 782 case REG_ESAI_TFCR: 783 case REG_ESAI_RFCR: 784 case REG_ESAI_TX0: 785 case REG_ESAI_TX1: 786 case REG_ESAI_TX2: 787 case REG_ESAI_TX3: 788 case REG_ESAI_TX4: 789 case REG_ESAI_TX5: 790 case REG_ESAI_TSR: 791 case REG_ESAI_SAICR: 792 case REG_ESAI_TCR: 793 case REG_ESAI_TCCR: 794 case REG_ESAI_RCR: 795 case REG_ESAI_RCCR: 796 case REG_ESAI_TSMA: 797 case REG_ESAI_TSMB: 798 case REG_ESAI_RSMA: 799 case REG_ESAI_RSMB: 800 case REG_ESAI_PRRC: 801 case REG_ESAI_PCRC: 802 return true; 803 default: 804 return false; 805 } 806 } 807 808 static const struct regmap_config fsl_esai_regmap_config = { 809 .reg_bits = 32, 810 .reg_stride = 4, 811 .val_bits = 32, 812 813 .max_register = REG_ESAI_PCRC, 814 .reg_defaults = fsl_esai_reg_defaults, 815 .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 816 .readable_reg = fsl_esai_readable_reg, 817 .volatile_reg = fsl_esai_volatile_reg, 818 .writeable_reg = fsl_esai_writeable_reg, 819 .cache_type = REGCACHE_FLAT, 820 }; 821 822 static int fsl_esai_probe(struct platform_device *pdev) 823 { 824 struct device_node *np = pdev->dev.of_node; 825 struct fsl_esai *esai_priv; 826 struct resource *res; 827 const __be32 *iprop; 828 void __iomem *regs; 829 int irq, ret; 830 831 esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 832 if (!esai_priv) 833 return -ENOMEM; 834 835 esai_priv->pdev = pdev; 836 snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 837 838 /* Get the addresses and IRQ */ 839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 840 regs = devm_ioremap_resource(&pdev->dev, res); 841 if (IS_ERR(regs)) 842 return PTR_ERR(regs); 843 844 esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 845 "core", regs, &fsl_esai_regmap_config); 846 if (IS_ERR(esai_priv->regmap)) { 847 dev_err(&pdev->dev, "failed to init regmap: %ld\n", 848 PTR_ERR(esai_priv->regmap)); 849 return PTR_ERR(esai_priv->regmap); 850 } 851 852 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 853 if (IS_ERR(esai_priv->coreclk)) { 854 dev_err(&pdev->dev, "failed to get core clock: %ld\n", 855 PTR_ERR(esai_priv->coreclk)); 856 return PTR_ERR(esai_priv->coreclk); 857 } 858 859 esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 860 if (IS_ERR(esai_priv->extalclk)) 861 dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 862 PTR_ERR(esai_priv->extalclk)); 863 864 esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 865 if (IS_ERR(esai_priv->fsysclk)) 866 dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 867 PTR_ERR(esai_priv->fsysclk)); 868 869 esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 870 if (IS_ERR(esai_priv->spbaclk)) 871 dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 872 PTR_ERR(esai_priv->spbaclk)); 873 874 irq = platform_get_irq(pdev, 0); 875 if (irq < 0) { 876 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 877 return irq; 878 } 879 880 ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, 881 esai_priv->name, esai_priv); 882 if (ret) { 883 dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 884 return ret; 885 } 886 887 /* Set a default slot number */ 888 esai_priv->slots = 2; 889 890 /* Set a default master/slave state */ 891 esai_priv->slave_mode = true; 892 893 /* Determine the FIFO depth */ 894 iprop = of_get_property(np, "fsl,fifo-depth", NULL); 895 if (iprop) 896 esai_priv->fifo_depth = be32_to_cpup(iprop); 897 else 898 esai_priv->fifo_depth = 64; 899 900 esai_priv->dma_params_tx.maxburst = 16; 901 esai_priv->dma_params_rx.maxburst = 16; 902 esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 903 esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 904 905 esai_priv->synchronous = 906 of_property_read_bool(np, "fsl,esai-synchronous"); 907 908 /* Implement full symmetry for synchronous mode */ 909 if (esai_priv->synchronous) { 910 fsl_esai_dai.symmetric_rates = 1; 911 fsl_esai_dai.symmetric_channels = 1; 912 fsl_esai_dai.symmetric_samplebits = 1; 913 } 914 915 dev_set_drvdata(&pdev->dev, esai_priv); 916 917 /* Reset ESAI unit */ 918 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST); 919 if (ret) { 920 dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 921 return ret; 922 } 923 924 /* 925 * We need to enable ESAI so as to access some of its registers. 926 * Otherwise, we would fail to dump regmap from user space. 927 */ 928 ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN); 929 if (ret) { 930 dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 931 return ret; 932 } 933 934 esai_priv->tx_mask = 0xFFFFFFFF; 935 esai_priv->rx_mask = 0xFFFFFFFF; 936 937 /* Clear the TSMA, TSMB, RSMA, RSMB */ 938 regmap_write(esai_priv->regmap, REG_ESAI_TSMA, 0); 939 regmap_write(esai_priv->regmap, REG_ESAI_TSMB, 0); 940 regmap_write(esai_priv->regmap, REG_ESAI_RSMA, 0); 941 regmap_write(esai_priv->regmap, REG_ESAI_RSMB, 0); 942 943 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 944 &fsl_esai_dai, 1); 945 if (ret) { 946 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 947 return ret; 948 } 949 950 ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 951 if (ret) 952 dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 953 954 return ret; 955 } 956 957 static const struct of_device_id fsl_esai_dt_ids[] = { 958 { .compatible = "fsl,imx35-esai", }, 959 { .compatible = "fsl,vf610-esai", }, 960 {} 961 }; 962 MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 963 964 #ifdef CONFIG_PM_SLEEP 965 static int fsl_esai_suspend(struct device *dev) 966 { 967 struct fsl_esai *esai = dev_get_drvdata(dev); 968 969 regcache_cache_only(esai->regmap, true); 970 regcache_mark_dirty(esai->regmap); 971 972 return 0; 973 } 974 975 static int fsl_esai_resume(struct device *dev) 976 { 977 struct fsl_esai *esai = dev_get_drvdata(dev); 978 int ret; 979 980 regcache_cache_only(esai->regmap, false); 981 982 /* FIFO reset for safety */ 983 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, 984 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 985 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, 986 ESAI_xFCR_xFR, ESAI_xFCR_xFR); 987 988 ret = regcache_sync(esai->regmap); 989 if (ret) 990 return ret; 991 992 /* FIFO reset done */ 993 regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 994 regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 995 996 return 0; 997 } 998 #endif /* CONFIG_PM_SLEEP */ 999 1000 static const struct dev_pm_ops fsl_esai_pm_ops = { 1001 SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume) 1002 }; 1003 1004 static struct platform_driver fsl_esai_driver = { 1005 .probe = fsl_esai_probe, 1006 .driver = { 1007 .name = "fsl-esai-dai", 1008 .pm = &fsl_esai_pm_ops, 1009 .of_match_table = fsl_esai_dt_ids, 1010 }, 1011 }; 1012 1013 module_platform_driver(fsl_esai_driver); 1014 1015 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 1016 MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 1017 MODULE_LICENSE("GPL v2"); 1018 MODULE_ALIAS("platform:fsl-esai-dai"); 1019