13b5af9f1SFabio Estevam // SPDX-License-Identifier: GPL-2.0 23b5af9f1SFabio Estevam // 33b5af9f1SFabio Estevam // Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 43b5af9f1SFabio Estevam // 53b5af9f1SFabio Estevam // Copyright (C) 2014 Freescale Semiconductor, Inc. 643d24e76SNicolin Chen 743d24e76SNicolin Chen #include <linux/clk.h> 843d24e76SNicolin Chen #include <linux/dmaengine.h> 943d24e76SNicolin Chen #include <linux/module.h> 1043d24e76SNicolin Chen #include <linux/of_irq.h> 1143d24e76SNicolin Chen #include <linux/of_platform.h> 1243d24e76SNicolin Chen #include <sound/dmaengine_pcm.h> 1343d24e76SNicolin Chen #include <sound/pcm_params.h> 1443d24e76SNicolin Chen 1543d24e76SNicolin Chen #include "fsl_esai.h" 1643d24e76SNicolin Chen #include "imx-pcm.h" 1743d24e76SNicolin Chen 1843d24e76SNicolin Chen #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 1943d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S16_LE | \ 2043d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S20_3LE | \ 2143d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S24_LE) 2243d24e76SNicolin Chen 2343d24e76SNicolin Chen /** 2443d24e76SNicolin Chen * fsl_esai: ESAI private data 2543d24e76SNicolin Chen * 2643d24e76SNicolin Chen * @dma_params_rx: DMA parameters for receive channel 2743d24e76SNicolin Chen * @dma_params_tx: DMA parameters for transmit channel 2843d24e76SNicolin Chen * @pdev: platform device pointer 2943d24e76SNicolin Chen * @regmap: regmap handler 3043d24e76SNicolin Chen * @coreclk: clock source to access register 3143d24e76SNicolin Chen * @extalclk: esai clock source to derive HCK, SCK and FS 3243d24e76SNicolin Chen * @fsysclk: system clock source to derive HCK, SCK and FS 33a2a4d604SShengjiu Wang * @spbaclk: SPBA clock (optional, depending on SoC design) 3443d24e76SNicolin Chen * @fifo_depth: depth of tx/rx FIFO 3543d24e76SNicolin Chen * @slot_width: width of each DAI slot 36de0d712aSShengjiu Wang * @slots: number of slots 3743d24e76SNicolin Chen * @hck_rate: clock rate of desired HCKx clock 38f975ca46SNicolin Chen * @sck_rate: clock rate of desired SCKx clock 39f975ca46SNicolin Chen * @hck_dir: the direction of HCKx pads 4043d24e76SNicolin Chen * @sck_div: if using PSR/PM dividers for SCKx clock 4143d24e76SNicolin Chen * @slave_mode: if fully using DAI slave mode 4243d24e76SNicolin Chen * @synchronous: if using tx/rx synchronous mode 4343d24e76SNicolin Chen * @name: driver name 4443d24e76SNicolin Chen */ 4543d24e76SNicolin Chen struct fsl_esai { 4643d24e76SNicolin Chen struct snd_dmaengine_dai_dma_data dma_params_rx; 4743d24e76SNicolin Chen struct snd_dmaengine_dai_dma_data dma_params_tx; 4843d24e76SNicolin Chen struct platform_device *pdev; 4943d24e76SNicolin Chen struct regmap *regmap; 5043d24e76SNicolin Chen struct clk *coreclk; 5143d24e76SNicolin Chen struct clk *extalclk; 5243d24e76SNicolin Chen struct clk *fsysclk; 53a2a4d604SShengjiu Wang struct clk *spbaclk; 5443d24e76SNicolin Chen u32 fifo_depth; 5543d24e76SNicolin Chen u32 slot_width; 56de0d712aSShengjiu Wang u32 slots; 5743d24e76SNicolin Chen u32 hck_rate[2]; 58f975ca46SNicolin Chen u32 sck_rate[2]; 59f975ca46SNicolin Chen bool hck_dir[2]; 6043d24e76SNicolin Chen bool sck_div[2]; 6143d24e76SNicolin Chen bool slave_mode; 6243d24e76SNicolin Chen bool synchronous; 6343d24e76SNicolin Chen char name[32]; 6443d24e76SNicolin Chen }; 6543d24e76SNicolin Chen 6643d24e76SNicolin Chen static irqreturn_t esai_isr(int irq, void *devid) 6743d24e76SNicolin Chen { 6843d24e76SNicolin Chen struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 6943d24e76SNicolin Chen struct platform_device *pdev = esai_priv->pdev; 7043d24e76SNicolin Chen u32 esr; 7143d24e76SNicolin Chen 7243d24e76SNicolin Chen regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 7343d24e76SNicolin Chen 7443d24e76SNicolin Chen if (esr & ESAI_ESR_TINIT_MASK) 753bcc8656SColin Ian King dev_dbg(&pdev->dev, "isr: Transmission Initialized\n"); 7643d24e76SNicolin Chen 7743d24e76SNicolin Chen if (esr & ESAI_ESR_RFF_MASK) 7843d24e76SNicolin Chen dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 7943d24e76SNicolin Chen 8043d24e76SNicolin Chen if (esr & ESAI_ESR_TFE_MASK) 813bcc8656SColin Ian King dev_warn(&pdev->dev, "isr: Transmission underrun\n"); 8243d24e76SNicolin Chen 8343d24e76SNicolin Chen if (esr & ESAI_ESR_TLS_MASK) 8443d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 8543d24e76SNicolin Chen 8643d24e76SNicolin Chen if (esr & ESAI_ESR_TDE_MASK) 873bcc8656SColin Ian King dev_dbg(&pdev->dev, "isr: Transmission data exception\n"); 8843d24e76SNicolin Chen 8943d24e76SNicolin Chen if (esr & ESAI_ESR_TED_MASK) 9043d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 9143d24e76SNicolin Chen 9243d24e76SNicolin Chen if (esr & ESAI_ESR_TD_MASK) 9343d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 9443d24e76SNicolin Chen 9543d24e76SNicolin Chen if (esr & ESAI_ESR_RLS_MASK) 9643d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 9743d24e76SNicolin Chen 9843d24e76SNicolin Chen if (esr & ESAI_ESR_RDE_MASK) 9943d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 10043d24e76SNicolin Chen 10143d24e76SNicolin Chen if (esr & ESAI_ESR_RED_MASK) 10243d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 10343d24e76SNicolin Chen 10443d24e76SNicolin Chen if (esr & ESAI_ESR_RD_MASK) 10543d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving data\n"); 10643d24e76SNicolin Chen 10743d24e76SNicolin Chen return IRQ_HANDLED; 10843d24e76SNicolin Chen } 10943d24e76SNicolin Chen 11043d24e76SNicolin Chen /** 11143d24e76SNicolin Chen * This function is used to calculate the divisors of psr, pm, fp and it is 11243d24e76SNicolin Chen * supposed to be called in set_dai_sysclk() and set_bclk(). 11343d24e76SNicolin Chen * 11443d24e76SNicolin Chen * @ratio: desired overall ratio for the paticipating dividers 11543d24e76SNicolin Chen * @usefp: for HCK setting, there is no need to set fp divider 11643d24e76SNicolin Chen * @fp: bypass other dividers by setting fp directly if fp != 0 11743d24e76SNicolin Chen * @tx: current setting is for playback or capture 11843d24e76SNicolin Chen */ 11943d24e76SNicolin Chen static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 12043d24e76SNicolin Chen bool usefp, u32 fp) 12143d24e76SNicolin Chen { 12243d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 12343d24e76SNicolin Chen u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 12443d24e76SNicolin Chen 12543d24e76SNicolin Chen maxfp = usefp ? 16 : 1; 12643d24e76SNicolin Chen 12743d24e76SNicolin Chen if (usefp && fp) 12843d24e76SNicolin Chen goto out_fp; 12943d24e76SNicolin Chen 13043d24e76SNicolin Chen if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 13143d24e76SNicolin Chen dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 13243d24e76SNicolin Chen 2 * 8 * 256 * maxfp); 13343d24e76SNicolin Chen return -EINVAL; 13443d24e76SNicolin Chen } else if (ratio % 2) { 13543d24e76SNicolin Chen dev_err(dai->dev, "the raio must be even if using upper divider\n"); 13643d24e76SNicolin Chen return -EINVAL; 13743d24e76SNicolin Chen } 13843d24e76SNicolin Chen 13943d24e76SNicolin Chen ratio /= 2; 14043d24e76SNicolin Chen 14143d24e76SNicolin Chen psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 14243d24e76SNicolin Chen 143c656941dSNicolin Chen /* Do not loop-search if PM (1 ~ 256) alone can serve the ratio */ 144c656941dSNicolin Chen if (ratio <= 256) { 145c656941dSNicolin Chen pm = ratio; 146c656941dSNicolin Chen fp = 1; 147c656941dSNicolin Chen goto out; 148c656941dSNicolin Chen } 149c656941dSNicolin Chen 15043d24e76SNicolin Chen /* Set the max fluctuation -- 0.1% of the max devisor */ 15143d24e76SNicolin Chen savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 15243d24e76SNicolin Chen 15343d24e76SNicolin Chen /* Find the best value for PM */ 15443d24e76SNicolin Chen for (i = 1; i <= 256; i++) { 15543d24e76SNicolin Chen for (j = 1; j <= maxfp; j++) { 15643d24e76SNicolin Chen /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 15743d24e76SNicolin Chen prod = (psr ? 1 : 8) * i * j; 15843d24e76SNicolin Chen 15943d24e76SNicolin Chen if (prod == ratio) 16043d24e76SNicolin Chen sub = 0; 16143d24e76SNicolin Chen else if (prod / ratio == 1) 16243d24e76SNicolin Chen sub = prod - ratio; 16343d24e76SNicolin Chen else if (ratio / prod == 1) 16443d24e76SNicolin Chen sub = ratio - prod; 16543d24e76SNicolin Chen else 16643d24e76SNicolin Chen continue; 16743d24e76SNicolin Chen 16843d24e76SNicolin Chen /* Calculate the fraction */ 16943d24e76SNicolin Chen sub = sub * 1000 / ratio; 17043d24e76SNicolin Chen if (sub < savesub) { 17143d24e76SNicolin Chen savesub = sub; 17243d24e76SNicolin Chen pm = i; 17343d24e76SNicolin Chen fp = j; 17443d24e76SNicolin Chen } 17543d24e76SNicolin Chen 17643d24e76SNicolin Chen /* We are lucky */ 17743d24e76SNicolin Chen if (savesub == 0) 17843d24e76SNicolin Chen goto out; 17943d24e76SNicolin Chen } 18043d24e76SNicolin Chen } 18143d24e76SNicolin Chen 18243d24e76SNicolin Chen if (pm == 999) { 18343d24e76SNicolin Chen dev_err(dai->dev, "failed to calculate proper divisors\n"); 18443d24e76SNicolin Chen return -EINVAL; 18543d24e76SNicolin Chen } 18643d24e76SNicolin Chen 18743d24e76SNicolin Chen out: 18843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 18943d24e76SNicolin Chen ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 19043d24e76SNicolin Chen psr | ESAI_xCCR_xPM(pm)); 19143d24e76SNicolin Chen 19243d24e76SNicolin Chen out_fp: 19343d24e76SNicolin Chen /* Bypass fp if not being required */ 19443d24e76SNicolin Chen if (maxfp <= 1) 19543d24e76SNicolin Chen return 0; 19643d24e76SNicolin Chen 19743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 19843d24e76SNicolin Chen ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 19943d24e76SNicolin Chen 20043d24e76SNicolin Chen return 0; 20143d24e76SNicolin Chen } 20243d24e76SNicolin Chen 20343d24e76SNicolin Chen /** 20443d24e76SNicolin Chen * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) 20543d24e76SNicolin Chen * 20643d24e76SNicolin Chen * @Parameters: 20743d24e76SNicolin Chen * clk_id: The clock source of HCKT/HCKR 20843d24e76SNicolin Chen * (Input from outside; output from inside, FSYS or EXTAL) 20943d24e76SNicolin Chen * freq: The required clock rate of HCKT/HCKR 21043d24e76SNicolin Chen * dir: The clock direction of HCKT/HCKR 21143d24e76SNicolin Chen * 21243d24e76SNicolin Chen * Note: If the direction is input, we do not care about clk_id. 21343d24e76SNicolin Chen */ 21443d24e76SNicolin Chen static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 21543d24e76SNicolin Chen unsigned int freq, int dir) 21643d24e76SNicolin Chen { 21743d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 21843d24e76SNicolin Chen struct clk *clksrc = esai_priv->extalclk; 21943d24e76SNicolin Chen bool tx = clk_id <= ESAI_HCKT_EXTAL; 22043d24e76SNicolin Chen bool in = dir == SND_SOC_CLOCK_IN; 2213e185238SXiubo Li u32 ratio, ecr = 0; 22243d24e76SNicolin Chen unsigned long clk_rate; 2233e185238SXiubo Li int ret; 22443d24e76SNicolin Chen 2258a2278b7SNicolin Chen if (freq == 0) { 2268a2278b7SNicolin Chen dev_err(dai->dev, "%sput freq of HCK%c should not be 0Hz\n", 2278a2278b7SNicolin Chen in ? "in" : "out", tx ? 'T' : 'R'); 2288a2278b7SNicolin Chen return -EINVAL; 2298a2278b7SNicolin Chen } 2308a2278b7SNicolin Chen 231f975ca46SNicolin Chen /* Bypass divider settings if the requirement doesn't change */ 232f975ca46SNicolin Chen if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx]) 233f975ca46SNicolin Chen return 0; 23443d24e76SNicolin Chen 23543d24e76SNicolin Chen /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 23643d24e76SNicolin Chen esai_priv->sck_div[tx] = true; 23743d24e76SNicolin Chen 23843d24e76SNicolin Chen /* Set the direction of HCKT/HCKR pins */ 23943d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 24043d24e76SNicolin Chen ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 24143d24e76SNicolin Chen 24243d24e76SNicolin Chen if (in) 24343d24e76SNicolin Chen goto out; 24443d24e76SNicolin Chen 24543d24e76SNicolin Chen switch (clk_id) { 24643d24e76SNicolin Chen case ESAI_HCKT_FSYS: 24743d24e76SNicolin Chen case ESAI_HCKR_FSYS: 24843d24e76SNicolin Chen clksrc = esai_priv->fsysclk; 24943d24e76SNicolin Chen break; 25043d24e76SNicolin Chen case ESAI_HCKT_EXTAL: 25143d24e76SNicolin Chen ecr |= ESAI_ECR_ETI; 25216bbeb2bSGustavo A. R. Silva /* fall through */ 25343d24e76SNicolin Chen case ESAI_HCKR_EXTAL: 25443d24e76SNicolin Chen ecr |= ESAI_ECR_ERI; 25543d24e76SNicolin Chen break; 25643d24e76SNicolin Chen default: 25743d24e76SNicolin Chen return -EINVAL; 25843d24e76SNicolin Chen } 25943d24e76SNicolin Chen 26043d24e76SNicolin Chen if (IS_ERR(clksrc)) { 26143d24e76SNicolin Chen dev_err(dai->dev, "no assigned %s clock\n", 26243d24e76SNicolin Chen clk_id % 2 ? "extal" : "fsys"); 26343d24e76SNicolin Chen return PTR_ERR(clksrc); 26443d24e76SNicolin Chen } 26543d24e76SNicolin Chen clk_rate = clk_get_rate(clksrc); 26643d24e76SNicolin Chen 26743d24e76SNicolin Chen ratio = clk_rate / freq; 26843d24e76SNicolin Chen if (ratio * freq > clk_rate) 26943d24e76SNicolin Chen ret = ratio * freq - clk_rate; 27043d24e76SNicolin Chen else if (ratio * freq < clk_rate) 27143d24e76SNicolin Chen ret = clk_rate - ratio * freq; 27243d24e76SNicolin Chen else 27343d24e76SNicolin Chen ret = 0; 27443d24e76SNicolin Chen 27543d24e76SNicolin Chen /* Block if clock source can not be divided into the required rate */ 27643d24e76SNicolin Chen if (ret != 0 && clk_rate / ret < 1000) { 27743d24e76SNicolin Chen dev_err(dai->dev, "failed to derive required HCK%c rate\n", 27843d24e76SNicolin Chen tx ? 'T' : 'R'); 27943d24e76SNicolin Chen return -EINVAL; 28043d24e76SNicolin Chen } 28143d24e76SNicolin Chen 28257ebbcafSNicolin Chen /* Only EXTAL source can be output directly without using PSR and PM */ 28357ebbcafSNicolin Chen if (ratio == 1 && clksrc == esai_priv->extalclk) { 28443d24e76SNicolin Chen /* Bypass all the dividers if not being needed */ 28543d24e76SNicolin Chen ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 28643d24e76SNicolin Chen goto out; 28757ebbcafSNicolin Chen } else if (ratio < 2) { 28857ebbcafSNicolin Chen /* The ratio should be no less than 2 if using other sources */ 28957ebbcafSNicolin Chen dev_err(dai->dev, "failed to derive required HCK%c rate\n", 29057ebbcafSNicolin Chen tx ? 'T' : 'R'); 29157ebbcafSNicolin Chen return -EINVAL; 29243d24e76SNicolin Chen } 29343d24e76SNicolin Chen 29443d24e76SNicolin Chen ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 29543d24e76SNicolin Chen if (ret) 29643d24e76SNicolin Chen return ret; 29743d24e76SNicolin Chen 29843d24e76SNicolin Chen esai_priv->sck_div[tx] = false; 29943d24e76SNicolin Chen 30043d24e76SNicolin Chen out: 301f975ca46SNicolin Chen esai_priv->hck_dir[tx] = dir; 30243d24e76SNicolin Chen esai_priv->hck_rate[tx] = freq; 30343d24e76SNicolin Chen 30443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 30543d24e76SNicolin Chen tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 30643d24e76SNicolin Chen ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 30743d24e76SNicolin Chen 30843d24e76SNicolin Chen return 0; 30943d24e76SNicolin Chen } 31043d24e76SNicolin Chen 31143d24e76SNicolin Chen /** 31243d24e76SNicolin Chen * This function configures the related dividers according to the bclk rate 31343d24e76SNicolin Chen */ 31443d24e76SNicolin Chen static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 31543d24e76SNicolin Chen { 31643d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 31743d24e76SNicolin Chen u32 hck_rate = esai_priv->hck_rate[tx]; 31843d24e76SNicolin Chen u32 sub, ratio = hck_rate / freq; 319f975ca46SNicolin Chen int ret; 32043d24e76SNicolin Chen 321f975ca46SNicolin Chen /* Don't apply for fully slave mode or unchanged bclk */ 322f975ca46SNicolin Chen if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq) 32343d24e76SNicolin Chen return 0; 32443d24e76SNicolin Chen 32543d24e76SNicolin Chen if (ratio * freq > hck_rate) 32643d24e76SNicolin Chen sub = ratio * freq - hck_rate; 32743d24e76SNicolin Chen else if (ratio * freq < hck_rate) 32843d24e76SNicolin Chen sub = hck_rate - ratio * freq; 32943d24e76SNicolin Chen else 33043d24e76SNicolin Chen sub = 0; 33143d24e76SNicolin Chen 33243d24e76SNicolin Chen /* Block if clock source can not be divided into the required rate */ 33343d24e76SNicolin Chen if (sub != 0 && hck_rate / sub < 1000) { 33443d24e76SNicolin Chen dev_err(dai->dev, "failed to derive required SCK%c rate\n", 33543d24e76SNicolin Chen tx ? 'T' : 'R'); 33643d24e76SNicolin Chen return -EINVAL; 33743d24e76SNicolin Chen } 33843d24e76SNicolin Chen 33989e47f62SNicolin Chen /* The ratio should be contented by FP alone if bypassing PM and PSR */ 34089e47f62SNicolin Chen if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 34143d24e76SNicolin Chen dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 34243d24e76SNicolin Chen return -EINVAL; 34343d24e76SNicolin Chen } 34443d24e76SNicolin Chen 345f975ca46SNicolin Chen ret = fsl_esai_divisor_cal(dai, tx, ratio, true, 34643d24e76SNicolin Chen esai_priv->sck_div[tx] ? 0 : ratio); 347f975ca46SNicolin Chen if (ret) 348f975ca46SNicolin Chen return ret; 349f975ca46SNicolin Chen 350f975ca46SNicolin Chen /* Save current bclk rate */ 351f975ca46SNicolin Chen esai_priv->sck_rate[tx] = freq; 352f975ca46SNicolin Chen 353f975ca46SNicolin Chen return 0; 35443d24e76SNicolin Chen } 35543d24e76SNicolin Chen 35643d24e76SNicolin Chen static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 35743d24e76SNicolin Chen u32 rx_mask, int slots, int slot_width) 35843d24e76SNicolin Chen { 35943d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 36043d24e76SNicolin Chen 36143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 36243d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 36343d24e76SNicolin Chen 36443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA, 36543d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask)); 36643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB, 367236014acSXiubo Li ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask)); 36843d24e76SNicolin Chen 36943d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 37043d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 37143d24e76SNicolin Chen 37243d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA, 37343d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask)); 37443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB, 375236014acSXiubo Li ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask)); 37643d24e76SNicolin Chen 37743d24e76SNicolin Chen esai_priv->slot_width = slot_width; 378de0d712aSShengjiu Wang esai_priv->slots = slots; 37943d24e76SNicolin Chen 38043d24e76SNicolin Chen return 0; 38143d24e76SNicolin Chen } 38243d24e76SNicolin Chen 38343d24e76SNicolin Chen static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 38443d24e76SNicolin Chen { 38543d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 38643d24e76SNicolin Chen u32 xcr = 0, xccr = 0, mask; 38743d24e76SNicolin Chen 38843d24e76SNicolin Chen /* DAI mode */ 38943d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 39043d24e76SNicolin Chen case SND_SOC_DAIFMT_I2S: 39143d24e76SNicolin Chen /* Data on rising edge of bclk, frame low, 1clk before data */ 39243d24e76SNicolin Chen xcr |= ESAI_xCR_xFSR; 39343d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 39443d24e76SNicolin Chen break; 39543d24e76SNicolin Chen case SND_SOC_DAIFMT_LEFT_J: 39643d24e76SNicolin Chen /* Data on rising edge of bclk, frame high */ 39743d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 39843d24e76SNicolin Chen break; 39943d24e76SNicolin Chen case SND_SOC_DAIFMT_RIGHT_J: 40043d24e76SNicolin Chen /* Data on rising edge of bclk, frame high, right aligned */ 40143d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA; 40243d24e76SNicolin Chen break; 40343d24e76SNicolin Chen case SND_SOC_DAIFMT_DSP_A: 40443d24e76SNicolin Chen /* Data on rising edge of bclk, frame high, 1clk before data */ 40543d24e76SNicolin Chen xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 40643d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 40743d24e76SNicolin Chen break; 40843d24e76SNicolin Chen case SND_SOC_DAIFMT_DSP_B: 40943d24e76SNicolin Chen /* Data on rising edge of bclk, frame high */ 41043d24e76SNicolin Chen xcr |= ESAI_xCR_xFSL; 41143d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 41243d24e76SNicolin Chen break; 41343d24e76SNicolin Chen default: 41443d24e76SNicolin Chen return -EINVAL; 41543d24e76SNicolin Chen } 41643d24e76SNicolin Chen 41743d24e76SNicolin Chen /* DAI clock inversion */ 41843d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 41943d24e76SNicolin Chen case SND_SOC_DAIFMT_NB_NF: 42043d24e76SNicolin Chen /* Nothing to do for both normal cases */ 42143d24e76SNicolin Chen break; 42243d24e76SNicolin Chen case SND_SOC_DAIFMT_IB_NF: 42343d24e76SNicolin Chen /* Invert bit clock */ 42443d24e76SNicolin Chen xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 42543d24e76SNicolin Chen break; 42643d24e76SNicolin Chen case SND_SOC_DAIFMT_NB_IF: 42743d24e76SNicolin Chen /* Invert frame clock */ 42843d24e76SNicolin Chen xccr ^= ESAI_xCCR_xFSP; 42943d24e76SNicolin Chen break; 43043d24e76SNicolin Chen case SND_SOC_DAIFMT_IB_IF: 43143d24e76SNicolin Chen /* Invert both clocks */ 43243d24e76SNicolin Chen xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 43343d24e76SNicolin Chen break; 43443d24e76SNicolin Chen default: 43543d24e76SNicolin Chen return -EINVAL; 43643d24e76SNicolin Chen } 43743d24e76SNicolin Chen 43843d24e76SNicolin Chen esai_priv->slave_mode = false; 43943d24e76SNicolin Chen 44043d24e76SNicolin Chen /* DAI clock master masks */ 44143d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 44243d24e76SNicolin Chen case SND_SOC_DAIFMT_CBM_CFM: 44343d24e76SNicolin Chen esai_priv->slave_mode = true; 44443d24e76SNicolin Chen break; 44543d24e76SNicolin Chen case SND_SOC_DAIFMT_CBS_CFM: 44643d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKD; 44743d24e76SNicolin Chen break; 44843d24e76SNicolin Chen case SND_SOC_DAIFMT_CBM_CFS: 44943d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSD; 45043d24e76SNicolin Chen break; 45143d24e76SNicolin Chen case SND_SOC_DAIFMT_CBS_CFS: 45243d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 45343d24e76SNicolin Chen break; 45443d24e76SNicolin Chen default: 45543d24e76SNicolin Chen return -EINVAL; 45643d24e76SNicolin Chen } 45743d24e76SNicolin Chen 45843d24e76SNicolin Chen mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR; 45943d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 46043d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 46143d24e76SNicolin Chen 46243d24e76SNicolin Chen mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 46343d24e76SNicolin Chen ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA; 46443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 46543d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 46643d24e76SNicolin Chen 46743d24e76SNicolin Chen return 0; 46843d24e76SNicolin Chen } 46943d24e76SNicolin Chen 47043d24e76SNicolin Chen static int fsl_esai_startup(struct snd_pcm_substream *substream, 47143d24e76SNicolin Chen struct snd_soc_dai *dai) 47243d24e76SNicolin Chen { 47343d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 4743e185238SXiubo Li int ret; 47543d24e76SNicolin Chen 47643d24e76SNicolin Chen /* 47743d24e76SNicolin Chen * Some platforms might use the same bit to gate all three or two of 47843d24e76SNicolin Chen * clocks, so keep all clocks open/close at the same time for safety 47943d24e76SNicolin Chen */ 48033529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->coreclk); 48133529ec9SFabio Estevam if (ret) 48233529ec9SFabio Estevam return ret; 483a2a4d604SShengjiu Wang if (!IS_ERR(esai_priv->spbaclk)) { 484a2a4d604SShengjiu Wang ret = clk_prepare_enable(esai_priv->spbaclk); 485a2a4d604SShengjiu Wang if (ret) 486a2a4d604SShengjiu Wang goto err_spbaclk; 487a2a4d604SShengjiu Wang } 48833529ec9SFabio Estevam if (!IS_ERR(esai_priv->extalclk)) { 48933529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->extalclk); 49033529ec9SFabio Estevam if (ret) 49133529ec9SFabio Estevam goto err_extalck; 49233529ec9SFabio Estevam } 49333529ec9SFabio Estevam if (!IS_ERR(esai_priv->fsysclk)) { 49433529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->fsysclk); 49533529ec9SFabio Estevam if (ret) 49633529ec9SFabio Estevam goto err_fsysclk; 49733529ec9SFabio Estevam } 49843d24e76SNicolin Chen 49943d24e76SNicolin Chen if (!dai->active) { 50043d24e76SNicolin Chen /* Set synchronous mode */ 50143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 50243d24e76SNicolin Chen ESAI_SAICR_SYNC, esai_priv->synchronous ? 50343d24e76SNicolin Chen ESAI_SAICR_SYNC : 0); 50443d24e76SNicolin Chen 50543d24e76SNicolin Chen /* Set a default slot number -- 2 */ 50643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 50743d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 50843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 50943d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 51043d24e76SNicolin Chen } 51143d24e76SNicolin Chen 51243d24e76SNicolin Chen return 0; 51333529ec9SFabio Estevam 51433529ec9SFabio Estevam err_fsysclk: 51533529ec9SFabio Estevam if (!IS_ERR(esai_priv->extalclk)) 51633529ec9SFabio Estevam clk_disable_unprepare(esai_priv->extalclk); 51733529ec9SFabio Estevam err_extalck: 518a2a4d604SShengjiu Wang if (!IS_ERR(esai_priv->spbaclk)) 519a2a4d604SShengjiu Wang clk_disable_unprepare(esai_priv->spbaclk); 520a2a4d604SShengjiu Wang err_spbaclk: 52133529ec9SFabio Estevam clk_disable_unprepare(esai_priv->coreclk); 52233529ec9SFabio Estevam 52333529ec9SFabio Estevam return ret; 52443d24e76SNicolin Chen } 52543d24e76SNicolin Chen 52643d24e76SNicolin Chen static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 52743d24e76SNicolin Chen struct snd_pcm_hw_params *params, 52843d24e76SNicolin Chen struct snd_soc_dai *dai) 52943d24e76SNicolin Chen { 53043d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 53143d24e76SNicolin Chen bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 5324ca73043SZidan Wang u32 width = params_width(params); 53343d24e76SNicolin Chen u32 channels = params_channels(params); 534de0d712aSShengjiu Wang u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 53586ea522bSNicolin Chen u32 slot_width = width; 5363e185238SXiubo Li u32 bclk, mask, val; 5373e185238SXiubo Li int ret; 53843d24e76SNicolin Chen 539d8ffcf71SGeert Uytterhoeven /* Override slot_width if being specifically set */ 54086ea522bSNicolin Chen if (esai_priv->slot_width) 54186ea522bSNicolin Chen slot_width = esai_priv->slot_width; 54286ea522bSNicolin Chen 54386ea522bSNicolin Chen bclk = params_rate(params) * slot_width * esai_priv->slots; 54443d24e76SNicolin Chen 54543d24e76SNicolin Chen ret = fsl_esai_set_bclk(dai, tx, bclk); 54643d24e76SNicolin Chen if (ret) 54743d24e76SNicolin Chen return ret; 54843d24e76SNicolin Chen 54943d24e76SNicolin Chen /* Use Normal mode to support monaural audio */ 55043d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 55143d24e76SNicolin Chen ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 55243d24e76SNicolin Chen ESAI_xCR_xMOD_NETWORK : 0); 55343d24e76SNicolin Chen 55443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 55543d24e76SNicolin Chen ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 55643d24e76SNicolin Chen 55743d24e76SNicolin Chen mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 55843d24e76SNicolin Chen (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 55943d24e76SNicolin Chen val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 560de0d712aSShengjiu Wang (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins)); 56143d24e76SNicolin Chen 56243d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 56343d24e76SNicolin Chen 56443d24e76SNicolin Chen mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0); 56586ea522bSNicolin Chen val = ESAI_xCR_xSWS(slot_width, width) | (tx ? ESAI_xCR_PADC : 0); 56643d24e76SNicolin Chen 56743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 56843d24e76SNicolin Chen 5694f8210f6SNicolin Chen /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */ 5704f8210f6SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 5714f8210f6SNicolin Chen ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 5724f8210f6SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 5734f8210f6SNicolin Chen ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 57443d24e76SNicolin Chen return 0; 57543d24e76SNicolin Chen } 57643d24e76SNicolin Chen 57743d24e76SNicolin Chen static void fsl_esai_shutdown(struct snd_pcm_substream *substream, 57843d24e76SNicolin Chen struct snd_soc_dai *dai) 57943d24e76SNicolin Chen { 58043d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 58143d24e76SNicolin Chen 58243d24e76SNicolin Chen if (!IS_ERR(esai_priv->fsysclk)) 58343d24e76SNicolin Chen clk_disable_unprepare(esai_priv->fsysclk); 58443d24e76SNicolin Chen if (!IS_ERR(esai_priv->extalclk)) 58543d24e76SNicolin Chen clk_disable_unprepare(esai_priv->extalclk); 586a2a4d604SShengjiu Wang if (!IS_ERR(esai_priv->spbaclk)) 587a2a4d604SShengjiu Wang clk_disable_unprepare(esai_priv->spbaclk); 58843d24e76SNicolin Chen clk_disable_unprepare(esai_priv->coreclk); 58943d24e76SNicolin Chen } 59043d24e76SNicolin Chen 59143d24e76SNicolin Chen static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 59243d24e76SNicolin Chen struct snd_soc_dai *dai) 59343d24e76SNicolin Chen { 59443d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 59543d24e76SNicolin Chen bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 59643d24e76SNicolin Chen u8 i, channels = substream->runtime->channels; 597de0d712aSShengjiu Wang u32 pins = DIV_ROUND_UP(channels, esai_priv->slots); 59843d24e76SNicolin Chen 59943d24e76SNicolin Chen switch (cmd) { 60043d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_START: 60143d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_RESUME: 60243d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 60343d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 60443d24e76SNicolin Chen ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 60543d24e76SNicolin Chen 60643d24e76SNicolin Chen /* Write initial words reqiured by ESAI as normal procedure */ 60743d24e76SNicolin Chen for (i = 0; tx && i < channels; i++) 60843d24e76SNicolin Chen regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 60943d24e76SNicolin Chen 61043d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 61143d24e76SNicolin Chen tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 612de0d712aSShengjiu Wang tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins)); 61343d24e76SNicolin Chen break; 61443d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_SUSPEND: 61543d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_STOP: 61643d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 61743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 61843d24e76SNicolin Chen tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 61943d24e76SNicolin Chen 62043d24e76SNicolin Chen /* Disable and reset FIFO */ 62143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 62243d24e76SNicolin Chen ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 62343d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 62443d24e76SNicolin Chen ESAI_xFCR_xFR, 0); 62543d24e76SNicolin Chen break; 62643d24e76SNicolin Chen default: 62743d24e76SNicolin Chen return -EINVAL; 62843d24e76SNicolin Chen } 62943d24e76SNicolin Chen 63043d24e76SNicolin Chen return 0; 63143d24e76SNicolin Chen } 63243d24e76SNicolin Chen 6335d29e95eSGustavo A. R. Silva static const struct snd_soc_dai_ops fsl_esai_dai_ops = { 63443d24e76SNicolin Chen .startup = fsl_esai_startup, 63543d24e76SNicolin Chen .shutdown = fsl_esai_shutdown, 63643d24e76SNicolin Chen .trigger = fsl_esai_trigger, 63743d24e76SNicolin Chen .hw_params = fsl_esai_hw_params, 63843d24e76SNicolin Chen .set_sysclk = fsl_esai_set_dai_sysclk, 63943d24e76SNicolin Chen .set_fmt = fsl_esai_set_dai_fmt, 64043d24e76SNicolin Chen .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 64143d24e76SNicolin Chen }; 64243d24e76SNicolin Chen 64343d24e76SNicolin Chen static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 64443d24e76SNicolin Chen { 64543d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 64643d24e76SNicolin Chen 64743d24e76SNicolin Chen snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 64843d24e76SNicolin Chen &esai_priv->dma_params_rx); 64943d24e76SNicolin Chen 65043d24e76SNicolin Chen return 0; 65143d24e76SNicolin Chen } 65243d24e76SNicolin Chen 65343d24e76SNicolin Chen static struct snd_soc_dai_driver fsl_esai_dai = { 65443d24e76SNicolin Chen .probe = fsl_esai_dai_probe, 65543d24e76SNicolin Chen .playback = { 65674ccb27cSNicolin Chen .stream_name = "CPU-Playback", 65743d24e76SNicolin Chen .channels_min = 1, 65843d24e76SNicolin Chen .channels_max = 12, 659f2a3ee01SFabio Estevam .rates = SNDRV_PCM_RATE_8000_192000, 66043d24e76SNicolin Chen .formats = FSL_ESAI_FORMATS, 66143d24e76SNicolin Chen }, 66243d24e76SNicolin Chen .capture = { 66374ccb27cSNicolin Chen .stream_name = "CPU-Capture", 66443d24e76SNicolin Chen .channels_min = 1, 66543d24e76SNicolin Chen .channels_max = 8, 666f2a3ee01SFabio Estevam .rates = SNDRV_PCM_RATE_8000_192000, 66743d24e76SNicolin Chen .formats = FSL_ESAI_FORMATS, 66843d24e76SNicolin Chen }, 66943d24e76SNicolin Chen .ops = &fsl_esai_dai_ops, 67043d24e76SNicolin Chen }; 67143d24e76SNicolin Chen 67243d24e76SNicolin Chen static const struct snd_soc_component_driver fsl_esai_component = { 67343d24e76SNicolin Chen .name = "fsl-esai", 67443d24e76SNicolin Chen }; 67543d24e76SNicolin Chen 676c64c6076SZidan Wang static const struct reg_default fsl_esai_reg_defaults[] = { 6778973112aSZidan Wang {REG_ESAI_ETDR, 0x00000000}, 6788973112aSZidan Wang {REG_ESAI_ECR, 0x00000000}, 6798973112aSZidan Wang {REG_ESAI_TFCR, 0x00000000}, 6808973112aSZidan Wang {REG_ESAI_RFCR, 0x00000000}, 6818973112aSZidan Wang {REG_ESAI_TX0, 0x00000000}, 6828973112aSZidan Wang {REG_ESAI_TX1, 0x00000000}, 6838973112aSZidan Wang {REG_ESAI_TX2, 0x00000000}, 6848973112aSZidan Wang {REG_ESAI_TX3, 0x00000000}, 6858973112aSZidan Wang {REG_ESAI_TX4, 0x00000000}, 6868973112aSZidan Wang {REG_ESAI_TX5, 0x00000000}, 6878973112aSZidan Wang {REG_ESAI_TSR, 0x00000000}, 6888973112aSZidan Wang {REG_ESAI_SAICR, 0x00000000}, 6898973112aSZidan Wang {REG_ESAI_TCR, 0x00000000}, 6908973112aSZidan Wang {REG_ESAI_TCCR, 0x00000000}, 6918973112aSZidan Wang {REG_ESAI_RCR, 0x00000000}, 6928973112aSZidan Wang {REG_ESAI_RCCR, 0x00000000}, 6938973112aSZidan Wang {REG_ESAI_TSMA, 0x0000ffff}, 6948973112aSZidan Wang {REG_ESAI_TSMB, 0x0000ffff}, 6958973112aSZidan Wang {REG_ESAI_RSMA, 0x0000ffff}, 6968973112aSZidan Wang {REG_ESAI_RSMB, 0x0000ffff}, 6978973112aSZidan Wang {REG_ESAI_PRRC, 0x00000000}, 6988973112aSZidan Wang {REG_ESAI_PCRC, 0x00000000}, 699c64c6076SZidan Wang }; 700c64c6076SZidan Wang 70143d24e76SNicolin Chen static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 70243d24e76SNicolin Chen { 70343d24e76SNicolin Chen switch (reg) { 70443d24e76SNicolin Chen case REG_ESAI_ERDR: 70543d24e76SNicolin Chen case REG_ESAI_ECR: 70643d24e76SNicolin Chen case REG_ESAI_ESR: 70743d24e76SNicolin Chen case REG_ESAI_TFCR: 70843d24e76SNicolin Chen case REG_ESAI_TFSR: 70943d24e76SNicolin Chen case REG_ESAI_RFCR: 71043d24e76SNicolin Chen case REG_ESAI_RFSR: 71143d24e76SNicolin Chen case REG_ESAI_RX0: 71243d24e76SNicolin Chen case REG_ESAI_RX1: 71343d24e76SNicolin Chen case REG_ESAI_RX2: 71443d24e76SNicolin Chen case REG_ESAI_RX3: 71543d24e76SNicolin Chen case REG_ESAI_SAISR: 71643d24e76SNicolin Chen case REG_ESAI_SAICR: 71743d24e76SNicolin Chen case REG_ESAI_TCR: 71843d24e76SNicolin Chen case REG_ESAI_TCCR: 71943d24e76SNicolin Chen case REG_ESAI_RCR: 72043d24e76SNicolin Chen case REG_ESAI_RCCR: 72143d24e76SNicolin Chen case REG_ESAI_TSMA: 72243d24e76SNicolin Chen case REG_ESAI_TSMB: 72343d24e76SNicolin Chen case REG_ESAI_RSMA: 72443d24e76SNicolin Chen case REG_ESAI_RSMB: 72543d24e76SNicolin Chen case REG_ESAI_PRRC: 72643d24e76SNicolin Chen case REG_ESAI_PCRC: 72743d24e76SNicolin Chen return true; 72843d24e76SNicolin Chen default: 72943d24e76SNicolin Chen return false; 73043d24e76SNicolin Chen } 73143d24e76SNicolin Chen } 73243d24e76SNicolin Chen 733c64c6076SZidan Wang static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg) 734c64c6076SZidan Wang { 735c64c6076SZidan Wang switch (reg) { 736c64c6076SZidan Wang case REG_ESAI_ERDR: 737c64c6076SZidan Wang case REG_ESAI_ESR: 738c64c6076SZidan Wang case REG_ESAI_TFSR: 739c64c6076SZidan Wang case REG_ESAI_RFSR: 740c64c6076SZidan Wang case REG_ESAI_RX0: 741c64c6076SZidan Wang case REG_ESAI_RX1: 742c64c6076SZidan Wang case REG_ESAI_RX2: 743c64c6076SZidan Wang case REG_ESAI_RX3: 744c64c6076SZidan Wang case REG_ESAI_SAISR: 745c64c6076SZidan Wang return true; 746c64c6076SZidan Wang default: 747c64c6076SZidan Wang return false; 748c64c6076SZidan Wang } 749c64c6076SZidan Wang } 750c64c6076SZidan Wang 75143d24e76SNicolin Chen static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 75243d24e76SNicolin Chen { 75343d24e76SNicolin Chen switch (reg) { 75443d24e76SNicolin Chen case REG_ESAI_ETDR: 75543d24e76SNicolin Chen case REG_ESAI_ECR: 75643d24e76SNicolin Chen case REG_ESAI_TFCR: 75743d24e76SNicolin Chen case REG_ESAI_RFCR: 75843d24e76SNicolin Chen case REG_ESAI_TX0: 75943d24e76SNicolin Chen case REG_ESAI_TX1: 76043d24e76SNicolin Chen case REG_ESAI_TX2: 76143d24e76SNicolin Chen case REG_ESAI_TX3: 76243d24e76SNicolin Chen case REG_ESAI_TX4: 76343d24e76SNicolin Chen case REG_ESAI_TX5: 76443d24e76SNicolin Chen case REG_ESAI_TSR: 76543d24e76SNicolin Chen case REG_ESAI_SAICR: 76643d24e76SNicolin Chen case REG_ESAI_TCR: 76743d24e76SNicolin Chen case REG_ESAI_TCCR: 76843d24e76SNicolin Chen case REG_ESAI_RCR: 76943d24e76SNicolin Chen case REG_ESAI_RCCR: 77043d24e76SNicolin Chen case REG_ESAI_TSMA: 77143d24e76SNicolin Chen case REG_ESAI_TSMB: 77243d24e76SNicolin Chen case REG_ESAI_RSMA: 77343d24e76SNicolin Chen case REG_ESAI_RSMB: 77443d24e76SNicolin Chen case REG_ESAI_PRRC: 77543d24e76SNicolin Chen case REG_ESAI_PCRC: 77643d24e76SNicolin Chen return true; 77743d24e76SNicolin Chen default: 77843d24e76SNicolin Chen return false; 77943d24e76SNicolin Chen } 78043d24e76SNicolin Chen } 78143d24e76SNicolin Chen 78292bd0334SXiubo Li static const struct regmap_config fsl_esai_regmap_config = { 78343d24e76SNicolin Chen .reg_bits = 32, 78443d24e76SNicolin Chen .reg_stride = 4, 78543d24e76SNicolin Chen .val_bits = 32, 78643d24e76SNicolin Chen 78743d24e76SNicolin Chen .max_register = REG_ESAI_PCRC, 788c64c6076SZidan Wang .reg_defaults = fsl_esai_reg_defaults, 789c64c6076SZidan Wang .num_reg_defaults = ARRAY_SIZE(fsl_esai_reg_defaults), 79043d24e76SNicolin Chen .readable_reg = fsl_esai_readable_reg, 791c64c6076SZidan Wang .volatile_reg = fsl_esai_volatile_reg, 79243d24e76SNicolin Chen .writeable_reg = fsl_esai_writeable_reg, 7930effb865SMarek Vasut .cache_type = REGCACHE_FLAT, 79443d24e76SNicolin Chen }; 79543d24e76SNicolin Chen 79643d24e76SNicolin Chen static int fsl_esai_probe(struct platform_device *pdev) 79743d24e76SNicolin Chen { 79843d24e76SNicolin Chen struct device_node *np = pdev->dev.of_node; 79943d24e76SNicolin Chen struct fsl_esai *esai_priv; 80043d24e76SNicolin Chen struct resource *res; 8010600b3e1SFabio Estevam const __be32 *iprop; 80243d24e76SNicolin Chen void __iomem *regs; 80343d24e76SNicolin Chen int irq, ret; 80443d24e76SNicolin Chen 80543d24e76SNicolin Chen esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 80643d24e76SNicolin Chen if (!esai_priv) 80743d24e76SNicolin Chen return -ENOMEM; 80843d24e76SNicolin Chen 80943d24e76SNicolin Chen esai_priv->pdev = pdev; 8105d585e1eSRob Herring snprintf(esai_priv->name, sizeof(esai_priv->name), "%pOFn", np); 81143d24e76SNicolin Chen 81243d24e76SNicolin Chen /* Get the addresses and IRQ */ 81343d24e76SNicolin Chen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 81443d24e76SNicolin Chen regs = devm_ioremap_resource(&pdev->dev, res); 81543d24e76SNicolin Chen if (IS_ERR(regs)) 81643d24e76SNicolin Chen return PTR_ERR(regs); 81743d24e76SNicolin Chen 81843d24e76SNicolin Chen esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 81943d24e76SNicolin Chen "core", regs, &fsl_esai_regmap_config); 82043d24e76SNicolin Chen if (IS_ERR(esai_priv->regmap)) { 82143d24e76SNicolin Chen dev_err(&pdev->dev, "failed to init regmap: %ld\n", 82243d24e76SNicolin Chen PTR_ERR(esai_priv->regmap)); 82343d24e76SNicolin Chen return PTR_ERR(esai_priv->regmap); 82443d24e76SNicolin Chen } 82543d24e76SNicolin Chen 82643d24e76SNicolin Chen esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 82743d24e76SNicolin Chen if (IS_ERR(esai_priv->coreclk)) { 82843d24e76SNicolin Chen dev_err(&pdev->dev, "failed to get core clock: %ld\n", 82943d24e76SNicolin Chen PTR_ERR(esai_priv->coreclk)); 83043d24e76SNicolin Chen return PTR_ERR(esai_priv->coreclk); 83143d24e76SNicolin Chen } 83243d24e76SNicolin Chen 83343d24e76SNicolin Chen esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 83443d24e76SNicolin Chen if (IS_ERR(esai_priv->extalclk)) 83543d24e76SNicolin Chen dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 83643d24e76SNicolin Chen PTR_ERR(esai_priv->extalclk)); 83743d24e76SNicolin Chen 83843d24e76SNicolin Chen esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 83943d24e76SNicolin Chen if (IS_ERR(esai_priv->fsysclk)) 84043d24e76SNicolin Chen dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 84143d24e76SNicolin Chen PTR_ERR(esai_priv->fsysclk)); 84243d24e76SNicolin Chen 843a2a4d604SShengjiu Wang esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba"); 844a2a4d604SShengjiu Wang if (IS_ERR(esai_priv->spbaclk)) 845a2a4d604SShengjiu Wang dev_warn(&pdev->dev, "failed to get spba clock: %ld\n", 846a2a4d604SShengjiu Wang PTR_ERR(esai_priv->spbaclk)); 847a2a4d604SShengjiu Wang 84843d24e76SNicolin Chen irq = platform_get_irq(pdev, 0); 84943d24e76SNicolin Chen if (irq < 0) { 850da2d4524SFabio Estevam dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 85143d24e76SNicolin Chen return irq; 85243d24e76SNicolin Chen } 85343d24e76SNicolin Chen 85443d24e76SNicolin Chen ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, 85543d24e76SNicolin Chen esai_priv->name, esai_priv); 85643d24e76SNicolin Chen if (ret) { 85743d24e76SNicolin Chen dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 85843d24e76SNicolin Chen return ret; 85943d24e76SNicolin Chen } 86043d24e76SNicolin Chen 861de0d712aSShengjiu Wang /* Set a default slot number */ 862de0d712aSShengjiu Wang esai_priv->slots = 2; 863de0d712aSShengjiu Wang 86443d24e76SNicolin Chen /* Set a default master/slave state */ 86543d24e76SNicolin Chen esai_priv->slave_mode = true; 86643d24e76SNicolin Chen 86743d24e76SNicolin Chen /* Determine the FIFO depth */ 86843d24e76SNicolin Chen iprop = of_get_property(np, "fsl,fifo-depth", NULL); 86943d24e76SNicolin Chen if (iprop) 87043d24e76SNicolin Chen esai_priv->fifo_depth = be32_to_cpup(iprop); 87143d24e76SNicolin Chen else 87243d24e76SNicolin Chen esai_priv->fifo_depth = 64; 87343d24e76SNicolin Chen 87443d24e76SNicolin Chen esai_priv->dma_params_tx.maxburst = 16; 87543d24e76SNicolin Chen esai_priv->dma_params_rx.maxburst = 16; 87643d24e76SNicolin Chen esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 87743d24e76SNicolin Chen esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 87843d24e76SNicolin Chen 87943d24e76SNicolin Chen esai_priv->synchronous = 88043d24e76SNicolin Chen of_property_read_bool(np, "fsl,esai-synchronous"); 88143d24e76SNicolin Chen 88243d24e76SNicolin Chen /* Implement full symmetry for synchronous mode */ 88343d24e76SNicolin Chen if (esai_priv->synchronous) { 88443d24e76SNicolin Chen fsl_esai_dai.symmetric_rates = 1; 88543d24e76SNicolin Chen fsl_esai_dai.symmetric_channels = 1; 88643d24e76SNicolin Chen fsl_esai_dai.symmetric_samplebits = 1; 88743d24e76SNicolin Chen } 88843d24e76SNicolin Chen 88943d24e76SNicolin Chen dev_set_drvdata(&pdev->dev, esai_priv); 89043d24e76SNicolin Chen 89143d24e76SNicolin Chen /* Reset ESAI unit */ 89243d24e76SNicolin Chen ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST); 89343d24e76SNicolin Chen if (ret) { 89443d24e76SNicolin Chen dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 89543d24e76SNicolin Chen return ret; 89643d24e76SNicolin Chen } 89743d24e76SNicolin Chen 89843d24e76SNicolin Chen /* 89943d24e76SNicolin Chen * We need to enable ESAI so as to access some of its registers. 90043d24e76SNicolin Chen * Otherwise, we would fail to dump regmap from user space. 90143d24e76SNicolin Chen */ 90243d24e76SNicolin Chen ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN); 90343d24e76SNicolin Chen if (ret) { 90443d24e76SNicolin Chen dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 90543d24e76SNicolin Chen return ret; 90643d24e76SNicolin Chen } 90743d24e76SNicolin Chen 90843d24e76SNicolin Chen ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 90943d24e76SNicolin Chen &fsl_esai_dai, 1); 91043d24e76SNicolin Chen if (ret) { 91143d24e76SNicolin Chen dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 91243d24e76SNicolin Chen return ret; 91343d24e76SNicolin Chen } 91443d24e76SNicolin Chen 9150d69e0ddSShengjiu Wang ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE); 91643d24e76SNicolin Chen if (ret) 91743d24e76SNicolin Chen dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 91843d24e76SNicolin Chen 91943d24e76SNicolin Chen return ret; 92043d24e76SNicolin Chen } 92143d24e76SNicolin Chen 92243d24e76SNicolin Chen static const struct of_device_id fsl_esai_dt_ids[] = { 92343d24e76SNicolin Chen { .compatible = "fsl,imx35-esai", }, 924b21cc2f5SXiubo Li { .compatible = "fsl,vf610-esai", }, 92543d24e76SNicolin Chen {} 92643d24e76SNicolin Chen }; 92743d24e76SNicolin Chen MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 92843d24e76SNicolin Chen 929739146b6SNicolin Chen #ifdef CONFIG_PM_SLEEP 930c64c6076SZidan Wang static int fsl_esai_suspend(struct device *dev) 931c64c6076SZidan Wang { 932c64c6076SZidan Wang struct fsl_esai *esai = dev_get_drvdata(dev); 933c64c6076SZidan Wang 934c64c6076SZidan Wang regcache_cache_only(esai->regmap, true); 935c64c6076SZidan Wang regcache_mark_dirty(esai->regmap); 936c64c6076SZidan Wang 937c64c6076SZidan Wang return 0; 938c64c6076SZidan Wang } 939c64c6076SZidan Wang 940c64c6076SZidan Wang static int fsl_esai_resume(struct device *dev) 941c64c6076SZidan Wang { 942c64c6076SZidan Wang struct fsl_esai *esai = dev_get_drvdata(dev); 943c64c6076SZidan Wang int ret; 944c64c6076SZidan Wang 945c64c6076SZidan Wang regcache_cache_only(esai->regmap, false); 946c64c6076SZidan Wang 947c64c6076SZidan Wang /* FIFO reset for safety */ 948c64c6076SZidan Wang regmap_update_bits(esai->regmap, REG_ESAI_TFCR, 949c64c6076SZidan Wang ESAI_xFCR_xFR, ESAI_xFCR_xFR); 950c64c6076SZidan Wang regmap_update_bits(esai->regmap, REG_ESAI_RFCR, 951c64c6076SZidan Wang ESAI_xFCR_xFR, ESAI_xFCR_xFR); 952c64c6076SZidan Wang 953c64c6076SZidan Wang ret = regcache_sync(esai->regmap); 954c64c6076SZidan Wang if (ret) 955c64c6076SZidan Wang return ret; 956c64c6076SZidan Wang 957c64c6076SZidan Wang /* FIFO reset done */ 958c64c6076SZidan Wang regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0); 959c64c6076SZidan Wang regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0); 960c64c6076SZidan Wang 961c64c6076SZidan Wang return 0; 962c64c6076SZidan Wang } 963c64c6076SZidan Wang #endif /* CONFIG_PM_SLEEP */ 964c64c6076SZidan Wang 965c64c6076SZidan Wang static const struct dev_pm_ops fsl_esai_pm_ops = { 966c64c6076SZidan Wang SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume) 967c64c6076SZidan Wang }; 968c64c6076SZidan Wang 96943d24e76SNicolin Chen static struct platform_driver fsl_esai_driver = { 97043d24e76SNicolin Chen .probe = fsl_esai_probe, 97143d24e76SNicolin Chen .driver = { 97243d24e76SNicolin Chen .name = "fsl-esai-dai", 973c64c6076SZidan Wang .pm = &fsl_esai_pm_ops, 97443d24e76SNicolin Chen .of_match_table = fsl_esai_dt_ids, 97543d24e76SNicolin Chen }, 97643d24e76SNicolin Chen }; 97743d24e76SNicolin Chen 97843d24e76SNicolin Chen module_platform_driver(fsl_esai_driver); 97943d24e76SNicolin Chen 98043d24e76SNicolin Chen MODULE_AUTHOR("Freescale Semiconductor, Inc."); 98143d24e76SNicolin Chen MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 98243d24e76SNicolin Chen MODULE_LICENSE("GPL v2"); 98343d24e76SNicolin Chen MODULE_ALIAS("platform:fsl-esai-dai"); 984