143d24e76SNicolin Chen /* 243d24e76SNicolin Chen * Freescale ESAI ALSA SoC Digital Audio Interface (DAI) driver 343d24e76SNicolin Chen * 443d24e76SNicolin Chen * Copyright (C) 2014 Freescale Semiconductor, Inc. 543d24e76SNicolin Chen * 643d24e76SNicolin Chen * This file is licensed under the terms of the GNU General Public License 743d24e76SNicolin Chen * version 2. This program is licensed "as is" without any warranty of any 843d24e76SNicolin Chen * kind, whether express or implied. 943d24e76SNicolin Chen */ 1043d24e76SNicolin Chen 1143d24e76SNicolin Chen #include <linux/clk.h> 1243d24e76SNicolin Chen #include <linux/dmaengine.h> 1343d24e76SNicolin Chen #include <linux/module.h> 1443d24e76SNicolin Chen #include <linux/of_irq.h> 1543d24e76SNicolin Chen #include <linux/of_platform.h> 1643d24e76SNicolin Chen #include <sound/dmaengine_pcm.h> 1743d24e76SNicolin Chen #include <sound/pcm_params.h> 1843d24e76SNicolin Chen 1943d24e76SNicolin Chen #include "fsl_esai.h" 2043d24e76SNicolin Chen #include "imx-pcm.h" 2143d24e76SNicolin Chen 2243d24e76SNicolin Chen #define FSL_ESAI_RATES SNDRV_PCM_RATE_8000_192000 2343d24e76SNicolin Chen #define FSL_ESAI_FORMATS (SNDRV_PCM_FMTBIT_S8 | \ 2443d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S16_LE | \ 2543d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S20_3LE | \ 2643d24e76SNicolin Chen SNDRV_PCM_FMTBIT_S24_LE) 2743d24e76SNicolin Chen 2843d24e76SNicolin Chen /** 2943d24e76SNicolin Chen * fsl_esai: ESAI private data 3043d24e76SNicolin Chen * 3143d24e76SNicolin Chen * @dma_params_rx: DMA parameters for receive channel 3243d24e76SNicolin Chen * @dma_params_tx: DMA parameters for transmit channel 3343d24e76SNicolin Chen * @pdev: platform device pointer 3443d24e76SNicolin Chen * @regmap: regmap handler 3543d24e76SNicolin Chen * @coreclk: clock source to access register 3643d24e76SNicolin Chen * @extalclk: esai clock source to derive HCK, SCK and FS 3743d24e76SNicolin Chen * @fsysclk: system clock source to derive HCK, SCK and FS 3843d24e76SNicolin Chen * @fifo_depth: depth of tx/rx FIFO 3943d24e76SNicolin Chen * @slot_width: width of each DAI slot 4043d24e76SNicolin Chen * @hck_rate: clock rate of desired HCKx clock 4143d24e76SNicolin Chen * @sck_div: if using PSR/PM dividers for SCKx clock 4243d24e76SNicolin Chen * @slave_mode: if fully using DAI slave mode 4343d24e76SNicolin Chen * @synchronous: if using tx/rx synchronous mode 4443d24e76SNicolin Chen * @name: driver name 4543d24e76SNicolin Chen */ 4643d24e76SNicolin Chen struct fsl_esai { 4743d24e76SNicolin Chen struct snd_dmaengine_dai_dma_data dma_params_rx; 4843d24e76SNicolin Chen struct snd_dmaengine_dai_dma_data dma_params_tx; 4943d24e76SNicolin Chen struct platform_device *pdev; 5043d24e76SNicolin Chen struct regmap *regmap; 5143d24e76SNicolin Chen struct clk *coreclk; 5243d24e76SNicolin Chen struct clk *extalclk; 5343d24e76SNicolin Chen struct clk *fsysclk; 5443d24e76SNicolin Chen u32 fifo_depth; 5543d24e76SNicolin Chen u32 slot_width; 5643d24e76SNicolin Chen u32 hck_rate[2]; 5743d24e76SNicolin Chen bool sck_div[2]; 5843d24e76SNicolin Chen bool slave_mode; 5943d24e76SNicolin Chen bool synchronous; 6043d24e76SNicolin Chen char name[32]; 6143d24e76SNicolin Chen }; 6243d24e76SNicolin Chen 6343d24e76SNicolin Chen static irqreturn_t esai_isr(int irq, void *devid) 6443d24e76SNicolin Chen { 6543d24e76SNicolin Chen struct fsl_esai *esai_priv = (struct fsl_esai *)devid; 6643d24e76SNicolin Chen struct platform_device *pdev = esai_priv->pdev; 6743d24e76SNicolin Chen u32 esr; 6843d24e76SNicolin Chen 6943d24e76SNicolin Chen regmap_read(esai_priv->regmap, REG_ESAI_ESR, &esr); 7043d24e76SNicolin Chen 7143d24e76SNicolin Chen if (esr & ESAI_ESR_TINIT_MASK) 7243d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmition Initialized\n"); 7343d24e76SNicolin Chen 7443d24e76SNicolin Chen if (esr & ESAI_ESR_RFF_MASK) 7543d24e76SNicolin Chen dev_warn(&pdev->dev, "isr: Receiving overrun\n"); 7643d24e76SNicolin Chen 7743d24e76SNicolin Chen if (esr & ESAI_ESR_TFE_MASK) 7843d24e76SNicolin Chen dev_warn(&pdev->dev, "isr: Transmition underrun\n"); 7943d24e76SNicolin Chen 8043d24e76SNicolin Chen if (esr & ESAI_ESR_TLS_MASK) 8143d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Just transmitted the last slot\n"); 8243d24e76SNicolin Chen 8343d24e76SNicolin Chen if (esr & ESAI_ESR_TDE_MASK) 8443d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmition data exception\n"); 8543d24e76SNicolin Chen 8643d24e76SNicolin Chen if (esr & ESAI_ESR_TED_MASK) 8743d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmitting even slots\n"); 8843d24e76SNicolin Chen 8943d24e76SNicolin Chen if (esr & ESAI_ESR_TD_MASK) 9043d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Transmitting data\n"); 9143d24e76SNicolin Chen 9243d24e76SNicolin Chen if (esr & ESAI_ESR_RLS_MASK) 9343d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Just received the last slot\n"); 9443d24e76SNicolin Chen 9543d24e76SNicolin Chen if (esr & ESAI_ESR_RDE_MASK) 9643d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving data exception\n"); 9743d24e76SNicolin Chen 9843d24e76SNicolin Chen if (esr & ESAI_ESR_RED_MASK) 9943d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving even slots\n"); 10043d24e76SNicolin Chen 10143d24e76SNicolin Chen if (esr & ESAI_ESR_RD_MASK) 10243d24e76SNicolin Chen dev_dbg(&pdev->dev, "isr: Receiving data\n"); 10343d24e76SNicolin Chen 10443d24e76SNicolin Chen return IRQ_HANDLED; 10543d24e76SNicolin Chen } 10643d24e76SNicolin Chen 10743d24e76SNicolin Chen /** 10843d24e76SNicolin Chen * This function is used to calculate the divisors of psr, pm, fp and it is 10943d24e76SNicolin Chen * supposed to be called in set_dai_sysclk() and set_bclk(). 11043d24e76SNicolin Chen * 11143d24e76SNicolin Chen * @ratio: desired overall ratio for the paticipating dividers 11243d24e76SNicolin Chen * @usefp: for HCK setting, there is no need to set fp divider 11343d24e76SNicolin Chen * @fp: bypass other dividers by setting fp directly if fp != 0 11443d24e76SNicolin Chen * @tx: current setting is for playback or capture 11543d24e76SNicolin Chen */ 11643d24e76SNicolin Chen static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 11743d24e76SNicolin Chen bool usefp, u32 fp) 11843d24e76SNicolin Chen { 11943d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 12043d24e76SNicolin Chen u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; 12143d24e76SNicolin Chen 12243d24e76SNicolin Chen maxfp = usefp ? 16 : 1; 12343d24e76SNicolin Chen 12443d24e76SNicolin Chen if (usefp && fp) 12543d24e76SNicolin Chen goto out_fp; 12643d24e76SNicolin Chen 12743d24e76SNicolin Chen if (ratio > 2 * 8 * 256 * maxfp || ratio < 2) { 12843d24e76SNicolin Chen dev_err(dai->dev, "the ratio is out of range (2 ~ %d)\n", 12943d24e76SNicolin Chen 2 * 8 * 256 * maxfp); 13043d24e76SNicolin Chen return -EINVAL; 13143d24e76SNicolin Chen } else if (ratio % 2) { 13243d24e76SNicolin Chen dev_err(dai->dev, "the raio must be even if using upper divider\n"); 13343d24e76SNicolin Chen return -EINVAL; 13443d24e76SNicolin Chen } 13543d24e76SNicolin Chen 13643d24e76SNicolin Chen ratio /= 2; 13743d24e76SNicolin Chen 13843d24e76SNicolin Chen psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; 13943d24e76SNicolin Chen 14043d24e76SNicolin Chen /* Set the max fluctuation -- 0.1% of the max devisor */ 14143d24e76SNicolin Chen savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; 14243d24e76SNicolin Chen 14343d24e76SNicolin Chen /* Find the best value for PM */ 14443d24e76SNicolin Chen for (i = 1; i <= 256; i++) { 14543d24e76SNicolin Chen for (j = 1; j <= maxfp; j++) { 14643d24e76SNicolin Chen /* PSR (1 or 8) * PM (1 ~ 256) * FP (1 ~ 16) */ 14743d24e76SNicolin Chen prod = (psr ? 1 : 8) * i * j; 14843d24e76SNicolin Chen 14943d24e76SNicolin Chen if (prod == ratio) 15043d24e76SNicolin Chen sub = 0; 15143d24e76SNicolin Chen else if (prod / ratio == 1) 15243d24e76SNicolin Chen sub = prod - ratio; 15343d24e76SNicolin Chen else if (ratio / prod == 1) 15443d24e76SNicolin Chen sub = ratio - prod; 15543d24e76SNicolin Chen else 15643d24e76SNicolin Chen continue; 15743d24e76SNicolin Chen 15843d24e76SNicolin Chen /* Calculate the fraction */ 15943d24e76SNicolin Chen sub = sub * 1000 / ratio; 16043d24e76SNicolin Chen if (sub < savesub) { 16143d24e76SNicolin Chen savesub = sub; 16243d24e76SNicolin Chen pm = i; 16343d24e76SNicolin Chen fp = j; 16443d24e76SNicolin Chen } 16543d24e76SNicolin Chen 16643d24e76SNicolin Chen /* We are lucky */ 16743d24e76SNicolin Chen if (savesub == 0) 16843d24e76SNicolin Chen goto out; 16943d24e76SNicolin Chen } 17043d24e76SNicolin Chen } 17143d24e76SNicolin Chen 17243d24e76SNicolin Chen if (pm == 999) { 17343d24e76SNicolin Chen dev_err(dai->dev, "failed to calculate proper divisors\n"); 17443d24e76SNicolin Chen return -EINVAL; 17543d24e76SNicolin Chen } 17643d24e76SNicolin Chen 17743d24e76SNicolin Chen out: 17843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 17943d24e76SNicolin Chen ESAI_xCCR_xPSR_MASK | ESAI_xCCR_xPM_MASK, 18043d24e76SNicolin Chen psr | ESAI_xCCR_xPM(pm)); 18143d24e76SNicolin Chen 18243d24e76SNicolin Chen out_fp: 18343d24e76SNicolin Chen /* Bypass fp if not being required */ 18443d24e76SNicolin Chen if (maxfp <= 1) 18543d24e76SNicolin Chen return 0; 18643d24e76SNicolin Chen 18743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 18843d24e76SNicolin Chen ESAI_xCCR_xFP_MASK, ESAI_xCCR_xFP(fp)); 18943d24e76SNicolin Chen 19043d24e76SNicolin Chen return 0; 19143d24e76SNicolin Chen } 19243d24e76SNicolin Chen 19343d24e76SNicolin Chen /** 19443d24e76SNicolin Chen * This function mainly configures the clock frequency of MCLK (HCKT/HCKR) 19543d24e76SNicolin Chen * 19643d24e76SNicolin Chen * @Parameters: 19743d24e76SNicolin Chen * clk_id: The clock source of HCKT/HCKR 19843d24e76SNicolin Chen * (Input from outside; output from inside, FSYS or EXTAL) 19943d24e76SNicolin Chen * freq: The required clock rate of HCKT/HCKR 20043d24e76SNicolin Chen * dir: The clock direction of HCKT/HCKR 20143d24e76SNicolin Chen * 20243d24e76SNicolin Chen * Note: If the direction is input, we do not care about clk_id. 20343d24e76SNicolin Chen */ 20443d24e76SNicolin Chen static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 20543d24e76SNicolin Chen unsigned int freq, int dir) 20643d24e76SNicolin Chen { 20743d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 20843d24e76SNicolin Chen struct clk *clksrc = esai_priv->extalclk; 20943d24e76SNicolin Chen bool tx = clk_id <= ESAI_HCKT_EXTAL; 21043d24e76SNicolin Chen bool in = dir == SND_SOC_CLOCK_IN; 21143d24e76SNicolin Chen u32 ret, ratio, ecr = 0; 21243d24e76SNicolin Chen unsigned long clk_rate; 21343d24e76SNicolin Chen 21443d24e76SNicolin Chen /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */ 21543d24e76SNicolin Chen esai_priv->sck_div[tx] = true; 21643d24e76SNicolin Chen 21743d24e76SNicolin Chen /* Set the direction of HCKT/HCKR pins */ 21843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCCR(tx), 21943d24e76SNicolin Chen ESAI_xCCR_xHCKD, in ? 0 : ESAI_xCCR_xHCKD); 22043d24e76SNicolin Chen 22143d24e76SNicolin Chen if (in) 22243d24e76SNicolin Chen goto out; 22343d24e76SNicolin Chen 22443d24e76SNicolin Chen switch (clk_id) { 22543d24e76SNicolin Chen case ESAI_HCKT_FSYS: 22643d24e76SNicolin Chen case ESAI_HCKR_FSYS: 22743d24e76SNicolin Chen clksrc = esai_priv->fsysclk; 22843d24e76SNicolin Chen break; 22943d24e76SNicolin Chen case ESAI_HCKT_EXTAL: 23043d24e76SNicolin Chen ecr |= ESAI_ECR_ETI; 23143d24e76SNicolin Chen case ESAI_HCKR_EXTAL: 23243d24e76SNicolin Chen ecr |= ESAI_ECR_ERI; 23343d24e76SNicolin Chen break; 23443d24e76SNicolin Chen default: 23543d24e76SNicolin Chen return -EINVAL; 23643d24e76SNicolin Chen } 23743d24e76SNicolin Chen 23843d24e76SNicolin Chen if (IS_ERR(clksrc)) { 23943d24e76SNicolin Chen dev_err(dai->dev, "no assigned %s clock\n", 24043d24e76SNicolin Chen clk_id % 2 ? "extal" : "fsys"); 24143d24e76SNicolin Chen return PTR_ERR(clksrc); 24243d24e76SNicolin Chen } 24343d24e76SNicolin Chen clk_rate = clk_get_rate(clksrc); 24443d24e76SNicolin Chen 24543d24e76SNicolin Chen ratio = clk_rate / freq; 24643d24e76SNicolin Chen if (ratio * freq > clk_rate) 24743d24e76SNicolin Chen ret = ratio * freq - clk_rate; 24843d24e76SNicolin Chen else if (ratio * freq < clk_rate) 24943d24e76SNicolin Chen ret = clk_rate - ratio * freq; 25043d24e76SNicolin Chen else 25143d24e76SNicolin Chen ret = 0; 25243d24e76SNicolin Chen 25343d24e76SNicolin Chen /* Block if clock source can not be divided into the required rate */ 25443d24e76SNicolin Chen if (ret != 0 && clk_rate / ret < 1000) { 25543d24e76SNicolin Chen dev_err(dai->dev, "failed to derive required HCK%c rate\n", 25643d24e76SNicolin Chen tx ? 'T' : 'R'); 25743d24e76SNicolin Chen return -EINVAL; 25843d24e76SNicolin Chen } 25943d24e76SNicolin Chen 26043d24e76SNicolin Chen if (ratio == 1) { 26143d24e76SNicolin Chen /* Bypass all the dividers if not being needed */ 26243d24e76SNicolin Chen ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO; 26343d24e76SNicolin Chen goto out; 26443d24e76SNicolin Chen } 26543d24e76SNicolin Chen 26643d24e76SNicolin Chen ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0); 26743d24e76SNicolin Chen if (ret) 26843d24e76SNicolin Chen return ret; 26943d24e76SNicolin Chen 27043d24e76SNicolin Chen esai_priv->sck_div[tx] = false; 27143d24e76SNicolin Chen 27243d24e76SNicolin Chen out: 27343d24e76SNicolin Chen esai_priv->hck_rate[tx] = freq; 27443d24e76SNicolin Chen 27543d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR, 27643d24e76SNicolin Chen tx ? ESAI_ECR_ETI | ESAI_ECR_ETO : 27743d24e76SNicolin Chen ESAI_ECR_ERI | ESAI_ECR_ERO, ecr); 27843d24e76SNicolin Chen 27943d24e76SNicolin Chen return 0; 28043d24e76SNicolin Chen } 28143d24e76SNicolin Chen 28243d24e76SNicolin Chen /** 28343d24e76SNicolin Chen * This function configures the related dividers according to the bclk rate 28443d24e76SNicolin Chen */ 28543d24e76SNicolin Chen static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) 28643d24e76SNicolin Chen { 28743d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 28843d24e76SNicolin Chen u32 hck_rate = esai_priv->hck_rate[tx]; 28943d24e76SNicolin Chen u32 sub, ratio = hck_rate / freq; 29043d24e76SNicolin Chen 29143d24e76SNicolin Chen /* Don't apply for fully slave mode*/ 29243d24e76SNicolin Chen if (esai_priv->slave_mode) 29343d24e76SNicolin Chen return 0; 29443d24e76SNicolin Chen 29543d24e76SNicolin Chen if (ratio * freq > hck_rate) 29643d24e76SNicolin Chen sub = ratio * freq - hck_rate; 29743d24e76SNicolin Chen else if (ratio * freq < hck_rate) 29843d24e76SNicolin Chen sub = hck_rate - ratio * freq; 29943d24e76SNicolin Chen else 30043d24e76SNicolin Chen sub = 0; 30143d24e76SNicolin Chen 30243d24e76SNicolin Chen /* Block if clock source can not be divided into the required rate */ 30343d24e76SNicolin Chen if (sub != 0 && hck_rate / sub < 1000) { 30443d24e76SNicolin Chen dev_err(dai->dev, "failed to derive required SCK%c rate\n", 30543d24e76SNicolin Chen tx ? 'T' : 'R'); 30643d24e76SNicolin Chen return -EINVAL; 30743d24e76SNicolin Chen } 30843d24e76SNicolin Chen 30943d24e76SNicolin Chen if (esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) { 31043d24e76SNicolin Chen dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n"); 31143d24e76SNicolin Chen return -EINVAL; 31243d24e76SNicolin Chen } 31343d24e76SNicolin Chen 31443d24e76SNicolin Chen return fsl_esai_divisor_cal(dai, tx, ratio, true, 31543d24e76SNicolin Chen esai_priv->sck_div[tx] ? 0 : ratio); 31643d24e76SNicolin Chen } 31743d24e76SNicolin Chen 31843d24e76SNicolin Chen static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, 31943d24e76SNicolin Chen u32 rx_mask, int slots, int slot_width) 32043d24e76SNicolin Chen { 32143d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 32243d24e76SNicolin Chen 32343d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 32443d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 32543d24e76SNicolin Chen 32643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA, 32743d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask)); 32843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB, 32943d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMB_xS(tx_mask)); 33043d24e76SNicolin Chen 33143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 33243d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots)); 33343d24e76SNicolin Chen 33443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA, 33543d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask)); 33643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB, 33743d24e76SNicolin Chen ESAI_xSMA_xS_MASK, ESAI_xSMB_xS(rx_mask)); 33843d24e76SNicolin Chen 33943d24e76SNicolin Chen esai_priv->slot_width = slot_width; 34043d24e76SNicolin Chen 34143d24e76SNicolin Chen return 0; 34243d24e76SNicolin Chen } 34343d24e76SNicolin Chen 34443d24e76SNicolin Chen static int fsl_esai_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 34543d24e76SNicolin Chen { 34643d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 34743d24e76SNicolin Chen u32 xcr = 0, xccr = 0, mask; 34843d24e76SNicolin Chen 34943d24e76SNicolin Chen /* DAI mode */ 35043d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 35143d24e76SNicolin Chen case SND_SOC_DAIFMT_I2S: 35243d24e76SNicolin Chen /* Data on rising edge of bclk, frame low, 1clk before data */ 35343d24e76SNicolin Chen xcr |= ESAI_xCR_xFSR; 35443d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSP | ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 35543d24e76SNicolin Chen break; 35643d24e76SNicolin Chen case SND_SOC_DAIFMT_LEFT_J: 35743d24e76SNicolin Chen /* Data on rising edge of bclk, frame high */ 35843d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 35943d24e76SNicolin Chen break; 36043d24e76SNicolin Chen case SND_SOC_DAIFMT_RIGHT_J: 36143d24e76SNicolin Chen /* Data on rising edge of bclk, frame high, right aligned */ 36243d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCR_xWA; 36343d24e76SNicolin Chen break; 36443d24e76SNicolin Chen case SND_SOC_DAIFMT_DSP_A: 36543d24e76SNicolin Chen /* Data on rising edge of bclk, frame high, 1clk before data */ 36643d24e76SNicolin Chen xcr |= ESAI_xCR_xFSL | ESAI_xCR_xFSR; 36743d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 36843d24e76SNicolin Chen break; 36943d24e76SNicolin Chen case SND_SOC_DAIFMT_DSP_B: 37043d24e76SNicolin Chen /* Data on rising edge of bclk, frame high */ 37143d24e76SNicolin Chen xcr |= ESAI_xCR_xFSL; 37243d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 37343d24e76SNicolin Chen break; 37443d24e76SNicolin Chen default: 37543d24e76SNicolin Chen return -EINVAL; 37643d24e76SNicolin Chen } 37743d24e76SNicolin Chen 37843d24e76SNicolin Chen /* DAI clock inversion */ 37943d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 38043d24e76SNicolin Chen case SND_SOC_DAIFMT_NB_NF: 38143d24e76SNicolin Chen /* Nothing to do for both normal cases */ 38243d24e76SNicolin Chen break; 38343d24e76SNicolin Chen case SND_SOC_DAIFMT_IB_NF: 38443d24e76SNicolin Chen /* Invert bit clock */ 38543d24e76SNicolin Chen xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP; 38643d24e76SNicolin Chen break; 38743d24e76SNicolin Chen case SND_SOC_DAIFMT_NB_IF: 38843d24e76SNicolin Chen /* Invert frame clock */ 38943d24e76SNicolin Chen xccr ^= ESAI_xCCR_xFSP; 39043d24e76SNicolin Chen break; 39143d24e76SNicolin Chen case SND_SOC_DAIFMT_IB_IF: 39243d24e76SNicolin Chen /* Invert both clocks */ 39343d24e76SNicolin Chen xccr ^= ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP; 39443d24e76SNicolin Chen break; 39543d24e76SNicolin Chen default: 39643d24e76SNicolin Chen return -EINVAL; 39743d24e76SNicolin Chen } 39843d24e76SNicolin Chen 39943d24e76SNicolin Chen esai_priv->slave_mode = false; 40043d24e76SNicolin Chen 40143d24e76SNicolin Chen /* DAI clock master masks */ 40243d24e76SNicolin Chen switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 40343d24e76SNicolin Chen case SND_SOC_DAIFMT_CBM_CFM: 40443d24e76SNicolin Chen esai_priv->slave_mode = true; 40543d24e76SNicolin Chen break; 40643d24e76SNicolin Chen case SND_SOC_DAIFMT_CBS_CFM: 40743d24e76SNicolin Chen xccr |= ESAI_xCCR_xCKD; 40843d24e76SNicolin Chen break; 40943d24e76SNicolin Chen case SND_SOC_DAIFMT_CBM_CFS: 41043d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSD; 41143d24e76SNicolin Chen break; 41243d24e76SNicolin Chen case SND_SOC_DAIFMT_CBS_CFS: 41343d24e76SNicolin Chen xccr |= ESAI_xCCR_xFSD | ESAI_xCCR_xCKD; 41443d24e76SNicolin Chen break; 41543d24e76SNicolin Chen default: 41643d24e76SNicolin Chen return -EINVAL; 41743d24e76SNicolin Chen } 41843d24e76SNicolin Chen 41943d24e76SNicolin Chen mask = ESAI_xCR_xFSL | ESAI_xCR_xFSR; 42043d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, xcr); 42143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, mask, xcr); 42243d24e76SNicolin Chen 42343d24e76SNicolin Chen mask = ESAI_xCCR_xCKP | ESAI_xCCR_xHCKP | ESAI_xCCR_xFSP | 42443d24e76SNicolin Chen ESAI_xCCR_xFSD | ESAI_xCCR_xCKD | ESAI_xCR_xWA; 42543d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, mask, xccr); 42643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, mask, xccr); 42743d24e76SNicolin Chen 42843d24e76SNicolin Chen return 0; 42943d24e76SNicolin Chen } 43043d24e76SNicolin Chen 43143d24e76SNicolin Chen static int fsl_esai_startup(struct snd_pcm_substream *substream, 43243d24e76SNicolin Chen struct snd_soc_dai *dai) 43343d24e76SNicolin Chen { 43433529ec9SFabio Estevam int ret; 43543d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 43643d24e76SNicolin Chen 43743d24e76SNicolin Chen /* 43843d24e76SNicolin Chen * Some platforms might use the same bit to gate all three or two of 43943d24e76SNicolin Chen * clocks, so keep all clocks open/close at the same time for safety 44043d24e76SNicolin Chen */ 44133529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->coreclk); 44233529ec9SFabio Estevam if (ret) 44333529ec9SFabio Estevam return ret; 44433529ec9SFabio Estevam if (!IS_ERR(esai_priv->extalclk)) { 44533529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->extalclk); 44633529ec9SFabio Estevam if (ret) 44733529ec9SFabio Estevam goto err_extalck; 44833529ec9SFabio Estevam } 44933529ec9SFabio Estevam if (!IS_ERR(esai_priv->fsysclk)) { 45033529ec9SFabio Estevam ret = clk_prepare_enable(esai_priv->fsysclk); 45133529ec9SFabio Estevam if (ret) 45233529ec9SFabio Estevam goto err_fsysclk; 45333529ec9SFabio Estevam } 45443d24e76SNicolin Chen 45543d24e76SNicolin Chen if (!dai->active) { 45643d24e76SNicolin Chen /* Reset Port C */ 45743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, 45843d24e76SNicolin Chen ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO)); 45943d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, 46043d24e76SNicolin Chen ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO)); 46143d24e76SNicolin Chen 46243d24e76SNicolin Chen /* Set synchronous mode */ 46343d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR, 46443d24e76SNicolin Chen ESAI_SAICR_SYNC, esai_priv->synchronous ? 46543d24e76SNicolin Chen ESAI_SAICR_SYNC : 0); 46643d24e76SNicolin Chen 46743d24e76SNicolin Chen /* Set a default slot number -- 2 */ 46843d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR, 46943d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 47043d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR, 47143d24e76SNicolin Chen ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2)); 47243d24e76SNicolin Chen } 47343d24e76SNicolin Chen 47443d24e76SNicolin Chen return 0; 47533529ec9SFabio Estevam 47633529ec9SFabio Estevam err_fsysclk: 47733529ec9SFabio Estevam if (!IS_ERR(esai_priv->extalclk)) 47833529ec9SFabio Estevam clk_disable_unprepare(esai_priv->extalclk); 47933529ec9SFabio Estevam err_extalck: 48033529ec9SFabio Estevam clk_disable_unprepare(esai_priv->coreclk); 48133529ec9SFabio Estevam 48233529ec9SFabio Estevam return ret; 48343d24e76SNicolin Chen } 48443d24e76SNicolin Chen 48543d24e76SNicolin Chen static int fsl_esai_hw_params(struct snd_pcm_substream *substream, 48643d24e76SNicolin Chen struct snd_pcm_hw_params *params, 48743d24e76SNicolin Chen struct snd_soc_dai *dai) 48843d24e76SNicolin Chen { 48943d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 49043d24e76SNicolin Chen bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 49143d24e76SNicolin Chen u32 width = snd_pcm_format_width(params_format(params)); 49243d24e76SNicolin Chen u32 channels = params_channels(params); 49343d24e76SNicolin Chen u32 bclk, mask, val, ret; 49443d24e76SNicolin Chen 49543d24e76SNicolin Chen bclk = params_rate(params) * esai_priv->slot_width * 2; 49643d24e76SNicolin Chen 49743d24e76SNicolin Chen ret = fsl_esai_set_bclk(dai, tx, bclk); 49843d24e76SNicolin Chen if (ret) 49943d24e76SNicolin Chen return ret; 50043d24e76SNicolin Chen 50143d24e76SNicolin Chen /* Use Normal mode to support monaural audio */ 50243d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 50343d24e76SNicolin Chen ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ? 50443d24e76SNicolin Chen ESAI_xCR_xMOD_NETWORK : 0); 50543d24e76SNicolin Chen 50643d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 50743d24e76SNicolin Chen ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR); 50843d24e76SNicolin Chen 50943d24e76SNicolin Chen mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK | 51043d24e76SNicolin Chen (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK); 51143d24e76SNicolin Chen val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) | 51243d24e76SNicolin Chen (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels)); 51343d24e76SNicolin Chen 51443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val); 51543d24e76SNicolin Chen 51643d24e76SNicolin Chen mask = ESAI_xCR_xSWS_MASK | (tx ? ESAI_xCR_PADC : 0); 51743d24e76SNicolin Chen val = ESAI_xCR_xSWS(esai_priv->slot_width, width) | (tx ? ESAI_xCR_PADC : 0); 51843d24e76SNicolin Chen 51943d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val); 52043d24e76SNicolin Chen 52143d24e76SNicolin Chen return 0; 52243d24e76SNicolin Chen } 52343d24e76SNicolin Chen 52443d24e76SNicolin Chen static void fsl_esai_shutdown(struct snd_pcm_substream *substream, 52543d24e76SNicolin Chen struct snd_soc_dai *dai) 52643d24e76SNicolin Chen { 52743d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 52843d24e76SNicolin Chen 52943d24e76SNicolin Chen if (!IS_ERR(esai_priv->fsysclk)) 53043d24e76SNicolin Chen clk_disable_unprepare(esai_priv->fsysclk); 53143d24e76SNicolin Chen if (!IS_ERR(esai_priv->extalclk)) 53243d24e76SNicolin Chen clk_disable_unprepare(esai_priv->extalclk); 53343d24e76SNicolin Chen clk_disable_unprepare(esai_priv->coreclk); 53443d24e76SNicolin Chen } 53543d24e76SNicolin Chen 53643d24e76SNicolin Chen static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd, 53743d24e76SNicolin Chen struct snd_soc_dai *dai) 53843d24e76SNicolin Chen { 53943d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 54043d24e76SNicolin Chen bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 54143d24e76SNicolin Chen u8 i, channels = substream->runtime->channels; 54243d24e76SNicolin Chen 54343d24e76SNicolin Chen switch (cmd) { 54443d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_START: 54543d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_RESUME: 54643d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 54743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 54843d24e76SNicolin Chen ESAI_xFCR_xFEN_MASK, ESAI_xFCR_xFEN); 54943d24e76SNicolin Chen 55043d24e76SNicolin Chen /* Write initial words reqiured by ESAI as normal procedure */ 55143d24e76SNicolin Chen for (i = 0; tx && i < channels; i++) 55243d24e76SNicolin Chen regmap_write(esai_priv->regmap, REG_ESAI_ETDR, 0x0); 55343d24e76SNicolin Chen 55443d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 55543d24e76SNicolin Chen tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 55643d24e76SNicolin Chen tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels)); 55743d24e76SNicolin Chen break; 55843d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_SUSPEND: 55943d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_STOP: 56043d24e76SNicolin Chen case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 56143d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), 56243d24e76SNicolin Chen tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0); 56343d24e76SNicolin Chen 56443d24e76SNicolin Chen /* Disable and reset FIFO */ 56543d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 56643d24e76SNicolin Chen ESAI_xFCR_xFR | ESAI_xFCR_xFEN, ESAI_xFCR_xFR); 56743d24e76SNicolin Chen regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), 56843d24e76SNicolin Chen ESAI_xFCR_xFR, 0); 56943d24e76SNicolin Chen break; 57043d24e76SNicolin Chen default: 57143d24e76SNicolin Chen return -EINVAL; 57243d24e76SNicolin Chen } 57343d24e76SNicolin Chen 57443d24e76SNicolin Chen return 0; 57543d24e76SNicolin Chen } 57643d24e76SNicolin Chen 57743d24e76SNicolin Chen static struct snd_soc_dai_ops fsl_esai_dai_ops = { 57843d24e76SNicolin Chen .startup = fsl_esai_startup, 57943d24e76SNicolin Chen .shutdown = fsl_esai_shutdown, 58043d24e76SNicolin Chen .trigger = fsl_esai_trigger, 58143d24e76SNicolin Chen .hw_params = fsl_esai_hw_params, 58243d24e76SNicolin Chen .set_sysclk = fsl_esai_set_dai_sysclk, 58343d24e76SNicolin Chen .set_fmt = fsl_esai_set_dai_fmt, 58443d24e76SNicolin Chen .set_tdm_slot = fsl_esai_set_dai_tdm_slot, 58543d24e76SNicolin Chen }; 58643d24e76SNicolin Chen 58743d24e76SNicolin Chen static int fsl_esai_dai_probe(struct snd_soc_dai *dai) 58843d24e76SNicolin Chen { 58943d24e76SNicolin Chen struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai); 59043d24e76SNicolin Chen 59143d24e76SNicolin Chen snd_soc_dai_init_dma_data(dai, &esai_priv->dma_params_tx, 59243d24e76SNicolin Chen &esai_priv->dma_params_rx); 59343d24e76SNicolin Chen 59443d24e76SNicolin Chen return 0; 59543d24e76SNicolin Chen } 59643d24e76SNicolin Chen 59743d24e76SNicolin Chen static struct snd_soc_dai_driver fsl_esai_dai = { 59843d24e76SNicolin Chen .probe = fsl_esai_dai_probe, 59943d24e76SNicolin Chen .playback = { 60043d24e76SNicolin Chen .channels_min = 1, 60143d24e76SNicolin Chen .channels_max = 12, 60243d24e76SNicolin Chen .rates = FSL_ESAI_RATES, 60343d24e76SNicolin Chen .formats = FSL_ESAI_FORMATS, 60443d24e76SNicolin Chen }, 60543d24e76SNicolin Chen .capture = { 60643d24e76SNicolin Chen .channels_min = 1, 60743d24e76SNicolin Chen .channels_max = 8, 60843d24e76SNicolin Chen .rates = FSL_ESAI_RATES, 60943d24e76SNicolin Chen .formats = FSL_ESAI_FORMATS, 61043d24e76SNicolin Chen }, 61143d24e76SNicolin Chen .ops = &fsl_esai_dai_ops, 61243d24e76SNicolin Chen }; 61343d24e76SNicolin Chen 61443d24e76SNicolin Chen static const struct snd_soc_component_driver fsl_esai_component = { 61543d24e76SNicolin Chen .name = "fsl-esai", 61643d24e76SNicolin Chen }; 61743d24e76SNicolin Chen 61843d24e76SNicolin Chen static bool fsl_esai_readable_reg(struct device *dev, unsigned int reg) 61943d24e76SNicolin Chen { 62043d24e76SNicolin Chen switch (reg) { 62143d24e76SNicolin Chen case REG_ESAI_ERDR: 62243d24e76SNicolin Chen case REG_ESAI_ECR: 62343d24e76SNicolin Chen case REG_ESAI_ESR: 62443d24e76SNicolin Chen case REG_ESAI_TFCR: 62543d24e76SNicolin Chen case REG_ESAI_TFSR: 62643d24e76SNicolin Chen case REG_ESAI_RFCR: 62743d24e76SNicolin Chen case REG_ESAI_RFSR: 62843d24e76SNicolin Chen case REG_ESAI_RX0: 62943d24e76SNicolin Chen case REG_ESAI_RX1: 63043d24e76SNicolin Chen case REG_ESAI_RX2: 63143d24e76SNicolin Chen case REG_ESAI_RX3: 63243d24e76SNicolin Chen case REG_ESAI_SAISR: 63343d24e76SNicolin Chen case REG_ESAI_SAICR: 63443d24e76SNicolin Chen case REG_ESAI_TCR: 63543d24e76SNicolin Chen case REG_ESAI_TCCR: 63643d24e76SNicolin Chen case REG_ESAI_RCR: 63743d24e76SNicolin Chen case REG_ESAI_RCCR: 63843d24e76SNicolin Chen case REG_ESAI_TSMA: 63943d24e76SNicolin Chen case REG_ESAI_TSMB: 64043d24e76SNicolin Chen case REG_ESAI_RSMA: 64143d24e76SNicolin Chen case REG_ESAI_RSMB: 64243d24e76SNicolin Chen case REG_ESAI_PRRC: 64343d24e76SNicolin Chen case REG_ESAI_PCRC: 64443d24e76SNicolin Chen return true; 64543d24e76SNicolin Chen default: 64643d24e76SNicolin Chen return false; 64743d24e76SNicolin Chen } 64843d24e76SNicolin Chen } 64943d24e76SNicolin Chen 65043d24e76SNicolin Chen static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg) 65143d24e76SNicolin Chen { 65243d24e76SNicolin Chen switch (reg) { 65343d24e76SNicolin Chen case REG_ESAI_ETDR: 65443d24e76SNicolin Chen case REG_ESAI_ECR: 65543d24e76SNicolin Chen case REG_ESAI_TFCR: 65643d24e76SNicolin Chen case REG_ESAI_RFCR: 65743d24e76SNicolin Chen case REG_ESAI_TX0: 65843d24e76SNicolin Chen case REG_ESAI_TX1: 65943d24e76SNicolin Chen case REG_ESAI_TX2: 66043d24e76SNicolin Chen case REG_ESAI_TX3: 66143d24e76SNicolin Chen case REG_ESAI_TX4: 66243d24e76SNicolin Chen case REG_ESAI_TX5: 66343d24e76SNicolin Chen case REG_ESAI_TSR: 66443d24e76SNicolin Chen case REG_ESAI_SAICR: 66543d24e76SNicolin Chen case REG_ESAI_TCR: 66643d24e76SNicolin Chen case REG_ESAI_TCCR: 66743d24e76SNicolin Chen case REG_ESAI_RCR: 66843d24e76SNicolin Chen case REG_ESAI_RCCR: 66943d24e76SNicolin Chen case REG_ESAI_TSMA: 67043d24e76SNicolin Chen case REG_ESAI_TSMB: 67143d24e76SNicolin Chen case REG_ESAI_RSMA: 67243d24e76SNicolin Chen case REG_ESAI_RSMB: 67343d24e76SNicolin Chen case REG_ESAI_PRRC: 67443d24e76SNicolin Chen case REG_ESAI_PCRC: 67543d24e76SNicolin Chen return true; 67643d24e76SNicolin Chen default: 67743d24e76SNicolin Chen return false; 67843d24e76SNicolin Chen } 67943d24e76SNicolin Chen } 68043d24e76SNicolin Chen 68143d24e76SNicolin Chen static const struct regmap_config fsl_esai_regmap_config = { 68243d24e76SNicolin Chen .reg_bits = 32, 68343d24e76SNicolin Chen .reg_stride = 4, 68443d24e76SNicolin Chen .val_bits = 32, 68543d24e76SNicolin Chen 68643d24e76SNicolin Chen .max_register = REG_ESAI_PCRC, 68743d24e76SNicolin Chen .readable_reg = fsl_esai_readable_reg, 68843d24e76SNicolin Chen .writeable_reg = fsl_esai_writeable_reg, 68943d24e76SNicolin Chen }; 69043d24e76SNicolin Chen 69143d24e76SNicolin Chen static int fsl_esai_probe(struct platform_device *pdev) 69243d24e76SNicolin Chen { 69343d24e76SNicolin Chen struct device_node *np = pdev->dev.of_node; 69443d24e76SNicolin Chen struct fsl_esai *esai_priv; 69543d24e76SNicolin Chen struct resource *res; 69643d24e76SNicolin Chen const uint32_t *iprop; 69743d24e76SNicolin Chen void __iomem *regs; 69843d24e76SNicolin Chen int irq, ret; 69943d24e76SNicolin Chen 70043d24e76SNicolin Chen esai_priv = devm_kzalloc(&pdev->dev, sizeof(*esai_priv), GFP_KERNEL); 70143d24e76SNicolin Chen if (!esai_priv) 70243d24e76SNicolin Chen return -ENOMEM; 70343d24e76SNicolin Chen 70443d24e76SNicolin Chen esai_priv->pdev = pdev; 70543d24e76SNicolin Chen strcpy(esai_priv->name, np->name); 70643d24e76SNicolin Chen 70743d24e76SNicolin Chen /* Get the addresses and IRQ */ 70843d24e76SNicolin Chen res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 70943d24e76SNicolin Chen regs = devm_ioremap_resource(&pdev->dev, res); 71043d24e76SNicolin Chen if (IS_ERR(regs)) 71143d24e76SNicolin Chen return PTR_ERR(regs); 71243d24e76SNicolin Chen 71343d24e76SNicolin Chen esai_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, 71443d24e76SNicolin Chen "core", regs, &fsl_esai_regmap_config); 71543d24e76SNicolin Chen if (IS_ERR(esai_priv->regmap)) { 71643d24e76SNicolin Chen dev_err(&pdev->dev, "failed to init regmap: %ld\n", 71743d24e76SNicolin Chen PTR_ERR(esai_priv->regmap)); 71843d24e76SNicolin Chen return PTR_ERR(esai_priv->regmap); 71943d24e76SNicolin Chen } 72043d24e76SNicolin Chen 72143d24e76SNicolin Chen esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); 72243d24e76SNicolin Chen if (IS_ERR(esai_priv->coreclk)) { 72343d24e76SNicolin Chen dev_err(&pdev->dev, "failed to get core clock: %ld\n", 72443d24e76SNicolin Chen PTR_ERR(esai_priv->coreclk)); 72543d24e76SNicolin Chen return PTR_ERR(esai_priv->coreclk); 72643d24e76SNicolin Chen } 72743d24e76SNicolin Chen 72843d24e76SNicolin Chen esai_priv->extalclk = devm_clk_get(&pdev->dev, "extal"); 72943d24e76SNicolin Chen if (IS_ERR(esai_priv->extalclk)) 73043d24e76SNicolin Chen dev_warn(&pdev->dev, "failed to get extal clock: %ld\n", 73143d24e76SNicolin Chen PTR_ERR(esai_priv->extalclk)); 73243d24e76SNicolin Chen 73343d24e76SNicolin Chen esai_priv->fsysclk = devm_clk_get(&pdev->dev, "fsys"); 73443d24e76SNicolin Chen if (IS_ERR(esai_priv->fsysclk)) 73543d24e76SNicolin Chen dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n", 73643d24e76SNicolin Chen PTR_ERR(esai_priv->fsysclk)); 73743d24e76SNicolin Chen 73843d24e76SNicolin Chen irq = platform_get_irq(pdev, 0); 73943d24e76SNicolin Chen if (irq < 0) { 74043d24e76SNicolin Chen dev_err(&pdev->dev, "no irq for node %s\n", np->full_name); 74143d24e76SNicolin Chen return irq; 74243d24e76SNicolin Chen } 74343d24e76SNicolin Chen 74443d24e76SNicolin Chen ret = devm_request_irq(&pdev->dev, irq, esai_isr, 0, 74543d24e76SNicolin Chen esai_priv->name, esai_priv); 74643d24e76SNicolin Chen if (ret) { 74743d24e76SNicolin Chen dev_err(&pdev->dev, "failed to claim irq %u\n", irq); 74843d24e76SNicolin Chen return ret; 74943d24e76SNicolin Chen } 75043d24e76SNicolin Chen 75143d24e76SNicolin Chen /* Set a default slot size */ 75243d24e76SNicolin Chen esai_priv->slot_width = 32; 75343d24e76SNicolin Chen 75443d24e76SNicolin Chen /* Set a default master/slave state */ 75543d24e76SNicolin Chen esai_priv->slave_mode = true; 75643d24e76SNicolin Chen 75743d24e76SNicolin Chen /* Determine the FIFO depth */ 75843d24e76SNicolin Chen iprop = of_get_property(np, "fsl,fifo-depth", NULL); 75943d24e76SNicolin Chen if (iprop) 76043d24e76SNicolin Chen esai_priv->fifo_depth = be32_to_cpup(iprop); 76143d24e76SNicolin Chen else 76243d24e76SNicolin Chen esai_priv->fifo_depth = 64; 76343d24e76SNicolin Chen 76443d24e76SNicolin Chen esai_priv->dma_params_tx.maxburst = 16; 76543d24e76SNicolin Chen esai_priv->dma_params_rx.maxburst = 16; 76643d24e76SNicolin Chen esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR; 76743d24e76SNicolin Chen esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR; 76843d24e76SNicolin Chen 76943d24e76SNicolin Chen esai_priv->synchronous = 77043d24e76SNicolin Chen of_property_read_bool(np, "fsl,esai-synchronous"); 77143d24e76SNicolin Chen 77243d24e76SNicolin Chen /* Implement full symmetry for synchronous mode */ 77343d24e76SNicolin Chen if (esai_priv->synchronous) { 77443d24e76SNicolin Chen fsl_esai_dai.symmetric_rates = 1; 77543d24e76SNicolin Chen fsl_esai_dai.symmetric_channels = 1; 77643d24e76SNicolin Chen fsl_esai_dai.symmetric_samplebits = 1; 77743d24e76SNicolin Chen } 77843d24e76SNicolin Chen 77943d24e76SNicolin Chen dev_set_drvdata(&pdev->dev, esai_priv); 78043d24e76SNicolin Chen 78143d24e76SNicolin Chen /* Reset ESAI unit */ 78243d24e76SNicolin Chen ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ERST); 78343d24e76SNicolin Chen if (ret) { 78443d24e76SNicolin Chen dev_err(&pdev->dev, "failed to reset ESAI: %d\n", ret); 78543d24e76SNicolin Chen return ret; 78643d24e76SNicolin Chen } 78743d24e76SNicolin Chen 78843d24e76SNicolin Chen /* 78943d24e76SNicolin Chen * We need to enable ESAI so as to access some of its registers. 79043d24e76SNicolin Chen * Otherwise, we would fail to dump regmap from user space. 79143d24e76SNicolin Chen */ 79243d24e76SNicolin Chen ret = regmap_write(esai_priv->regmap, REG_ESAI_ECR, ESAI_ECR_ESAIEN); 79343d24e76SNicolin Chen if (ret) { 79443d24e76SNicolin Chen dev_err(&pdev->dev, "failed to enable ESAI: %d\n", ret); 79543d24e76SNicolin Chen return ret; 79643d24e76SNicolin Chen } 79743d24e76SNicolin Chen 79843d24e76SNicolin Chen ret = devm_snd_soc_register_component(&pdev->dev, &fsl_esai_component, 79943d24e76SNicolin Chen &fsl_esai_dai, 1); 80043d24e76SNicolin Chen if (ret) { 80143d24e76SNicolin Chen dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); 80243d24e76SNicolin Chen return ret; 80343d24e76SNicolin Chen } 80443d24e76SNicolin Chen 80543d24e76SNicolin Chen ret = imx_pcm_dma_init(pdev); 80643d24e76SNicolin Chen if (ret) 80743d24e76SNicolin Chen dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret); 80843d24e76SNicolin Chen 80943d24e76SNicolin Chen return ret; 81043d24e76SNicolin Chen } 81143d24e76SNicolin Chen 81243d24e76SNicolin Chen static const struct of_device_id fsl_esai_dt_ids[] = { 81343d24e76SNicolin Chen { .compatible = "fsl,imx35-esai", }, 81443d24e76SNicolin Chen {} 81543d24e76SNicolin Chen }; 81643d24e76SNicolin Chen MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids); 81743d24e76SNicolin Chen 81843d24e76SNicolin Chen static struct platform_driver fsl_esai_driver = { 81943d24e76SNicolin Chen .probe = fsl_esai_probe, 82043d24e76SNicolin Chen .driver = { 82143d24e76SNicolin Chen .name = "fsl-esai-dai", 82243d24e76SNicolin Chen .owner = THIS_MODULE, 82343d24e76SNicolin Chen .of_match_table = fsl_esai_dt_ids, 82443d24e76SNicolin Chen }, 82543d24e76SNicolin Chen }; 82643d24e76SNicolin Chen 82743d24e76SNicolin Chen module_platform_driver(fsl_esai_driver); 82843d24e76SNicolin Chen 82943d24e76SNicolin Chen MODULE_AUTHOR("Freescale Semiconductor, Inc."); 83043d24e76SNicolin Chen MODULE_DESCRIPTION("Freescale ESAI CPU DAI driver"); 83143d24e76SNicolin Chen MODULE_LICENSE("GPL v2"); 83243d24e76SNicolin Chen MODULE_ALIAS("platform:fsl-esai-dai"); 833