1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright 2019 NXP 3 4 #include <linux/atomic.h> 5 #include <linux/clk.h> 6 #include <linux/device.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/firmware.h> 9 #include <linux/interrupt.h> 10 #include <linux/kobject.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/miscdevice.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/sched/signal.h> 21 #include <linux/sysfs.h> 22 #include <linux/types.h> 23 #include <linux/gcd.h> 24 #include <sound/dmaengine_pcm.h> 25 #include <sound/pcm.h> 26 #include <sound/pcm_params.h> 27 #include <sound/soc.h> 28 #include <sound/tlv.h> 29 #include <sound/core.h> 30 31 #include "fsl_easrc.h" 32 #include "imx-pcm.h" 33 34 #define FSL_EASRC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 35 SNDRV_PCM_FMTBIT_U16_LE | \ 36 SNDRV_PCM_FMTBIT_S24_LE | \ 37 SNDRV_PCM_FMTBIT_S24_3LE | \ 38 SNDRV_PCM_FMTBIT_U24_LE | \ 39 SNDRV_PCM_FMTBIT_U24_3LE | \ 40 SNDRV_PCM_FMTBIT_S32_LE | \ 41 SNDRV_PCM_FMTBIT_U32_LE | \ 42 SNDRV_PCM_FMTBIT_S20_3LE | \ 43 SNDRV_PCM_FMTBIT_U20_3LE | \ 44 SNDRV_PCM_FMTBIT_FLOAT_LE) 45 46 static int fsl_easrc_iec958_put_bits(struct snd_kcontrol *kcontrol, 47 struct snd_ctl_elem_value *ucontrol) 48 { 49 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 50 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); 51 struct fsl_easrc_priv *easrc_priv = easrc->private; 52 struct soc_mreg_control *mc = 53 (struct soc_mreg_control *)kcontrol->private_value; 54 unsigned int regval = ucontrol->value.integer.value[0]; 55 56 easrc_priv->bps_iec958[mc->regbase] = regval; 57 58 return 0; 59 } 60 61 static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol, 62 struct snd_ctl_elem_value *ucontrol) 63 { 64 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 65 struct fsl_asrc *easrc = snd_soc_component_get_drvdata(comp); 66 struct fsl_easrc_priv *easrc_priv = easrc->private; 67 struct soc_mreg_control *mc = 68 (struct soc_mreg_control *)kcontrol->private_value; 69 70 ucontrol->value.enumerated.item[0] = easrc_priv->bps_iec958[mc->regbase]; 71 72 return 0; 73 } 74 75 static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol, 76 struct snd_ctl_elem_value *ucontrol) 77 { 78 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 79 struct soc_mreg_control *mc = 80 (struct soc_mreg_control *)kcontrol->private_value; 81 unsigned int regval; 82 int ret; 83 84 ret = snd_soc_component_read(component, mc->regbase, ®val); 85 if (ret < 0) 86 return ret; 87 88 ucontrol->value.integer.value[0] = regval; 89 90 return 0; 91 } 92 93 static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol, 94 struct snd_ctl_elem_value *ucontrol) 95 { 96 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 97 struct soc_mreg_control *mc = 98 (struct soc_mreg_control *)kcontrol->private_value; 99 unsigned int regval = ucontrol->value.integer.value[0]; 100 int ret; 101 102 ret = snd_soc_component_write(component, mc->regbase, regval); 103 if (ret < 0) 104 return ret; 105 106 return 0; 107 } 108 109 #define SOC_SINGLE_REG_RW(xname, xreg) \ 110 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \ 111 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 112 .info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \ 113 .put = fsl_easrc_set_reg, \ 114 .private_value = (unsigned long)&(struct soc_mreg_control) \ 115 { .regbase = xreg, .regcount = 1, .nbits = 32, \ 116 .invert = 0, .min = 0, .max = 0xffffffff, } } 117 118 #define SOC_SINGLE_VAL_RW(xname, xreg) \ 119 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \ 120 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 121 .info = snd_soc_info_xr_sx, .get = fsl_easrc_iec958_get_bits, \ 122 .put = fsl_easrc_iec958_put_bits, \ 123 .private_value = (unsigned long)&(struct soc_mreg_control) \ 124 { .regbase = xreg, .regcount = 1, .nbits = 32, \ 125 .invert = 0, .min = 0, .max = 2, } } 126 127 static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = { 128 SOC_SINGLE("Context 0 Dither Switch", REG_EASRC_COC(0), 0, 1, 0), 129 SOC_SINGLE("Context 1 Dither Switch", REG_EASRC_COC(1), 0, 1, 0), 130 SOC_SINGLE("Context 2 Dither Switch", REG_EASRC_COC(2), 0, 1, 0), 131 SOC_SINGLE("Context 3 Dither Switch", REG_EASRC_COC(3), 0, 1, 0), 132 133 SOC_SINGLE("Context 0 IEC958 Validity", REG_EASRC_COC(0), 2, 1, 0), 134 SOC_SINGLE("Context 1 IEC958 Validity", REG_EASRC_COC(1), 2, 1, 0), 135 SOC_SINGLE("Context 2 IEC958 Validity", REG_EASRC_COC(2), 2, 1, 0), 136 SOC_SINGLE("Context 3 IEC958 Validity", REG_EASRC_COC(3), 2, 1, 0), 137 138 SOC_SINGLE_VAL_RW("Context 0 IEC958 Bits Per Sample", 0), 139 SOC_SINGLE_VAL_RW("Context 1 IEC958 Bits Per Sample", 1), 140 SOC_SINGLE_VAL_RW("Context 2 IEC958 Bits Per Sample", 2), 141 SOC_SINGLE_VAL_RW("Context 3 IEC958 Bits Per Sample", 3), 142 143 SOC_SINGLE_REG_RW("Context 0 IEC958 CS0", REG_EASRC_CS0(0)), 144 SOC_SINGLE_REG_RW("Context 1 IEC958 CS0", REG_EASRC_CS0(1)), 145 SOC_SINGLE_REG_RW("Context 2 IEC958 CS0", REG_EASRC_CS0(2)), 146 SOC_SINGLE_REG_RW("Context 3 IEC958 CS0", REG_EASRC_CS0(3)), 147 SOC_SINGLE_REG_RW("Context 0 IEC958 CS1", REG_EASRC_CS1(0)), 148 SOC_SINGLE_REG_RW("Context 1 IEC958 CS1", REG_EASRC_CS1(1)), 149 SOC_SINGLE_REG_RW("Context 2 IEC958 CS1", REG_EASRC_CS1(2)), 150 SOC_SINGLE_REG_RW("Context 3 IEC958 CS1", REG_EASRC_CS1(3)), 151 SOC_SINGLE_REG_RW("Context 0 IEC958 CS2", REG_EASRC_CS2(0)), 152 SOC_SINGLE_REG_RW("Context 1 IEC958 CS2", REG_EASRC_CS2(1)), 153 SOC_SINGLE_REG_RW("Context 2 IEC958 CS2", REG_EASRC_CS2(2)), 154 SOC_SINGLE_REG_RW("Context 3 IEC958 CS2", REG_EASRC_CS2(3)), 155 SOC_SINGLE_REG_RW("Context 0 IEC958 CS3", REG_EASRC_CS3(0)), 156 SOC_SINGLE_REG_RW("Context 1 IEC958 CS3", REG_EASRC_CS3(1)), 157 SOC_SINGLE_REG_RW("Context 2 IEC958 CS3", REG_EASRC_CS3(2)), 158 SOC_SINGLE_REG_RW("Context 3 IEC958 CS3", REG_EASRC_CS3(3)), 159 SOC_SINGLE_REG_RW("Context 0 IEC958 CS4", REG_EASRC_CS4(0)), 160 SOC_SINGLE_REG_RW("Context 1 IEC958 CS4", REG_EASRC_CS4(1)), 161 SOC_SINGLE_REG_RW("Context 2 IEC958 CS4", REG_EASRC_CS4(2)), 162 SOC_SINGLE_REG_RW("Context 3 IEC958 CS4", REG_EASRC_CS4(3)), 163 SOC_SINGLE_REG_RW("Context 0 IEC958 CS5", REG_EASRC_CS5(0)), 164 SOC_SINGLE_REG_RW("Context 1 IEC958 CS5", REG_EASRC_CS5(1)), 165 SOC_SINGLE_REG_RW("Context 2 IEC958 CS5", REG_EASRC_CS5(2)), 166 SOC_SINGLE_REG_RW("Context 3 IEC958 CS5", REG_EASRC_CS5(3)), 167 }; 168 169 /* 170 * fsl_easrc_set_rs_ratio 171 * 172 * According to the resample taps, calculate the resample ratio 173 * ratio = in_rate / out_rate 174 */ 175 static int fsl_easrc_set_rs_ratio(struct fsl_asrc_pair *ctx) 176 { 177 struct fsl_asrc *easrc = ctx->asrc; 178 struct fsl_easrc_priv *easrc_priv = easrc->private; 179 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 180 unsigned int in_rate = ctx_priv->in_params.norm_rate; 181 unsigned int out_rate = ctx_priv->out_params.norm_rate; 182 unsigned int int_bits; 183 unsigned int frac_bits; 184 u64 val; 185 u32 *r; 186 187 switch (easrc_priv->rs_num_taps) { 188 case EASRC_RS_32_TAPS: 189 int_bits = 5; 190 frac_bits = 39; 191 break; 192 case EASRC_RS_64_TAPS: 193 int_bits = 6; 194 frac_bits = 38; 195 break; 196 case EASRC_RS_128_TAPS: 197 int_bits = 7; 198 frac_bits = 37; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 val = (u64)in_rate << frac_bits; 205 do_div(val, out_rate); 206 r = (uint32_t *)&val; 207 208 if (r[1] & 0xFFFFF000) { 209 dev_err(&easrc->pdev->dev, "ratio exceed range\n"); 210 return -EINVAL; 211 } 212 213 regmap_write(easrc->regmap, REG_EASRC_RRL(ctx->index), 214 EASRC_RRL_RS_RL(r[0])); 215 regmap_write(easrc->regmap, REG_EASRC_RRH(ctx->index), 216 EASRC_RRH_RS_RH(r[1])); 217 218 return 0; 219 } 220 221 /* Normalize input and output sample rates */ 222 static void fsl_easrc_normalize_rates(struct fsl_asrc_pair *ctx) 223 { 224 struct fsl_easrc_ctx_priv *ctx_priv; 225 int a, b; 226 227 if (!ctx) 228 return; 229 230 ctx_priv = ctx->private; 231 232 a = ctx_priv->in_params.sample_rate; 233 b = ctx_priv->out_params.sample_rate; 234 235 a = gcd(a, b); 236 237 /* Divide by gcd to normalize the rate */ 238 ctx_priv->in_params.norm_rate = ctx_priv->in_params.sample_rate / a; 239 ctx_priv->out_params.norm_rate = ctx_priv->out_params.sample_rate / a; 240 } 241 242 /* Resets the pointer of the coeff memory pointers */ 243 static int fsl_easrc_coeff_mem_ptr_reset(struct fsl_asrc *easrc, 244 unsigned int ctx_id, int mem_type) 245 { 246 struct device *dev; 247 u32 reg, mask, val; 248 249 if (!easrc) 250 return -ENODEV; 251 252 dev = &easrc->pdev->dev; 253 254 switch (mem_type) { 255 case EASRC_PF_COEFF_MEM: 256 /* This resets the prefilter memory pointer addr */ 257 if (ctx_id >= EASRC_CTX_MAX_NUM) { 258 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 259 return -EINVAL; 260 } 261 262 reg = REG_EASRC_CCE1(ctx_id); 263 mask = EASRC_CCE1_COEF_MEM_RST_MASK; 264 val = EASRC_CCE1_COEF_MEM_RST; 265 break; 266 case EASRC_RS_COEFF_MEM: 267 /* This resets the resampling memory pointer addr */ 268 reg = REG_EASRC_CRCC; 269 mask = EASRC_CRCC_RS_CPR_MASK; 270 val = EASRC_CRCC_RS_CPR; 271 break; 272 default: 273 dev_err(dev, "Unknown memory type\n"); 274 return -EINVAL; 275 } 276 277 /* 278 * To reset the write pointer back to zero, the register field 279 * ASRC_CTX_CTRL_EXT1x[PF_COEFF_MEM_RST] can be toggled from 280 * 0x0 to 0x1 to 0x0. 281 */ 282 regmap_update_bits(easrc->regmap, reg, mask, 0); 283 regmap_update_bits(easrc->regmap, reg, mask, val); 284 regmap_update_bits(easrc->regmap, reg, mask, 0); 285 286 return 0; 287 } 288 289 static inline uint32_t bits_taps_to_val(unsigned int t) 290 { 291 switch (t) { 292 case EASRC_RS_32_TAPS: 293 return 32; 294 case EASRC_RS_64_TAPS: 295 return 64; 296 case EASRC_RS_128_TAPS: 297 return 128; 298 } 299 300 return 0; 301 } 302 303 static int fsl_easrc_resampler_config(struct fsl_asrc *easrc) 304 { 305 struct device *dev = &easrc->pdev->dev; 306 struct fsl_easrc_priv *easrc_priv = easrc->private; 307 struct asrc_firmware_hdr *hdr = easrc_priv->firmware_hdr; 308 struct interp_params *interp = easrc_priv->interp; 309 struct interp_params *selected_interp = NULL; 310 unsigned int num_coeff; 311 unsigned int i; 312 u64 *coef; 313 u32 *r; 314 int ret; 315 316 if (!hdr) { 317 dev_err(dev, "firmware not loaded!\n"); 318 return -ENODEV; 319 } 320 321 for (i = 0; i < hdr->interp_scen; i++) { 322 if ((interp[i].num_taps - 1) != 323 bits_taps_to_val(easrc_priv->rs_num_taps)) 324 continue; 325 326 coef = interp[i].coeff; 327 selected_interp = &interp[i]; 328 dev_dbg(dev, "Selected interp_filter: %u taps - %u phases\n", 329 selected_interp->num_taps, 330 selected_interp->num_phases); 331 break; 332 } 333 334 if (!selected_interp) { 335 dev_err(dev, "failed to get interpreter configuration\n"); 336 return -EINVAL; 337 } 338 339 /* 340 * RS_LOW - first half of center tap of the sinc function 341 * RS_HIGH - second half of center tap of the sinc function 342 * This is due to the fact the resampling function must be 343 * symetrical - i.e. odd number of taps 344 */ 345 r = (uint32_t *)&selected_interp->center_tap; 346 regmap_write(easrc->regmap, REG_EASRC_RCTCL, EASRC_RCTCL_RS_CL(r[0])); 347 regmap_write(easrc->regmap, REG_EASRC_RCTCH, EASRC_RCTCH_RS_CH(r[1])); 348 349 /* 350 * Write Number of Resampling Coefficient Taps 351 * 00b - 32-Tap Resampling Filter 352 * 01b - 64-Tap Resampling Filter 353 * 10b - 128-Tap Resampling Filter 354 * 11b - N/A 355 */ 356 regmap_update_bits(easrc->regmap, REG_EASRC_CRCC, 357 EASRC_CRCC_RS_TAPS_MASK, 358 EASRC_CRCC_RS_TAPS(easrc_priv->rs_num_taps)); 359 360 /* Reset prefilter coefficient pointer back to 0 */ 361 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, 0, EASRC_RS_COEFF_MEM); 362 if (ret) 363 return ret; 364 365 /* 366 * When the filter is programmed to run in: 367 * 32-tap mode, 16-taps, 128-phases 4-coefficients per phase 368 * 64-tap mode, 32-taps, 64-phases 4-coefficients per phase 369 * 128-tap mode, 64-taps, 32-phases 4-coefficients per phase 370 * This means the number of writes is constant no matter 371 * the mode we are using 372 */ 373 num_coeff = 16 * 128 * 4; 374 375 for (i = 0; i < num_coeff; i++) { 376 r = (uint32_t *)&coef[i]; 377 regmap_write(easrc->regmap, REG_EASRC_CRCM, 378 EASRC_CRCM_RS_CWD(r[0])); 379 regmap_write(easrc->regmap, REG_EASRC_CRCM, 380 EASRC_CRCM_RS_CWD(r[1])); 381 } 382 383 return 0; 384 } 385 386 /** 387 * Scale filter coefficients (64 bits float) 388 * For input float32 normalized range (1.0,-1.0) -> output int[16,24,32]: 389 * scale it by multiplying filter coefficients by 2^31 390 * For input int[16, 24, 32] -> output float32 391 * scale it by multiplying filter coefficients by 2^-15, 2^-23, 2^-31 392 * input: 393 * asrc: Structure pointer of fsl_asrc 394 * infilter : Pointer to non-scaled input filter 395 * shift: The multiply factor 396 * output: 397 * outfilter: scaled filter 398 */ 399 static int fsl_easrc_normalize_filter(struct fsl_asrc *easrc, 400 u64 *infilter, 401 u64 *outfilter, 402 int shift) 403 { 404 struct device *dev = &easrc->pdev->dev; 405 u64 coef = *infilter; 406 s64 exp = (coef & 0x7ff0000000000000ll) >> 52; 407 u64 outcoef; 408 409 /* 410 * If exponent is zero (value == 0), or 7ff (value == NaNs) 411 * dont touch the content 412 */ 413 if (exp == 0 || exp == 0x7ff) { 414 *outfilter = coef; 415 return 0; 416 } 417 418 /* coef * 2^shift ==> exp + shift */ 419 exp += shift; 420 421 if ((shift > 0 && exp >= 0x7ff) || (shift < 0 && exp <= 0)) { 422 dev_err(dev, "coef out of range\n"); 423 return -EINVAL; 424 } 425 426 outcoef = (u64)(coef & 0x800FFFFFFFFFFFFFll) + ((u64)exp << 52); 427 *outfilter = outcoef; 428 429 return 0; 430 } 431 432 static int fsl_easrc_write_pf_coeff_mem(struct fsl_asrc *easrc, int ctx_id, 433 u64 *coef, int n_taps, int shift) 434 { 435 struct device *dev = &easrc->pdev->dev; 436 int ret = 0; 437 int i; 438 u32 *r; 439 u64 tmp; 440 441 /* If STx_NUM_TAPS is set to 0x0 then return */ 442 if (!n_taps) 443 return 0; 444 445 if (!coef) { 446 dev_err(dev, "coef table is NULL\n"); 447 return -EINVAL; 448 } 449 450 /* 451 * When switching between stages, the address pointer 452 * should be reset back to 0x0 before performing a write 453 */ 454 ret = fsl_easrc_coeff_mem_ptr_reset(easrc, ctx_id, EASRC_PF_COEFF_MEM); 455 if (ret) 456 return ret; 457 458 for (i = 0; i < (n_taps + 1) / 2; i++) { 459 ret = fsl_easrc_normalize_filter(easrc, &coef[i], &tmp, shift); 460 if (ret) 461 return ret; 462 463 r = (uint32_t *)&tmp; 464 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), 465 EASRC_PCF_CD(r[0])); 466 regmap_write(easrc->regmap, REG_EASRC_PCF(ctx_id), 467 EASRC_PCF_CD(r[1])); 468 } 469 470 return 0; 471 } 472 473 static int fsl_easrc_prefilter_config(struct fsl_asrc *easrc, 474 unsigned int ctx_id) 475 { 476 struct prefil_params *prefil, *selected_prefil = NULL; 477 struct fsl_easrc_ctx_priv *ctx_priv; 478 struct fsl_easrc_priv *easrc_priv; 479 struct asrc_firmware_hdr *hdr; 480 struct fsl_asrc_pair *ctx; 481 struct device *dev; 482 u32 inrate, outrate, offset = 0; 483 u32 in_s_rate, out_s_rate, in_s_fmt, out_s_fmt; 484 int ret, i; 485 486 if (!easrc) 487 return -ENODEV; 488 489 dev = &easrc->pdev->dev; 490 491 if (ctx_id >= EASRC_CTX_MAX_NUM) { 492 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 493 return -EINVAL; 494 } 495 496 easrc_priv = easrc->private; 497 498 ctx = easrc->pair[ctx_id]; 499 ctx_priv = ctx->private; 500 501 in_s_rate = ctx_priv->in_params.sample_rate; 502 out_s_rate = ctx_priv->out_params.sample_rate; 503 in_s_fmt = ctx_priv->in_params.sample_format; 504 out_s_fmt = ctx_priv->out_params.sample_format; 505 506 ctx_priv->in_filled_sample = bits_taps_to_val(easrc_priv->rs_num_taps) / 2; 507 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; 508 509 ctx_priv->st1_num_taps = 0; 510 ctx_priv->st2_num_taps = 0; 511 512 regmap_write(easrc->regmap, REG_EASRC_CCE1(ctx_id), 0); 513 regmap_write(easrc->regmap, REG_EASRC_CCE2(ctx_id), 0); 514 515 /* 516 * The audio float point data range is (-1, 1), the asrc would output 517 * all zero for float point input and integer output case, that is to 518 * drop the fractional part of the data directly. 519 * 520 * In order to support float to int conversion or int to float 521 * conversion we need to do special operation on the coefficient to 522 * enlarge/reduce the data to the expected range. 523 * 524 * For float to int case: 525 * Up sampling: 526 * 1. Create a 1 tap filter with center tap (only tap) of 2^31 527 * in 64 bits floating point. 528 * double value = (double)(((uint64_t)1) << 31) 529 * 2. Program 1 tap prefilter with center tap above. 530 * 531 * Down sampling, 532 * 1. If the filter is single stage filter, add "shift" to the exponent 533 * of stage 1 coefficients. 534 * 2. If the filter is two stage filter , add "shift" to the exponent 535 * of stage 2 coefficients. 536 * 537 * The "shift" is 31, same for int16, int24, int32 case. 538 * 539 * For int to float case: 540 * Up sampling: 541 * 1. Create a 1 tap filter with center tap (only tap) of 2^-31 542 * in 64 bits floating point. 543 * 2. Program 1 tap prefilter with center tap above. 544 * 545 * Down sampling, 546 * 1. If the filter is single stage filter, subtract "shift" to the 547 * exponent of stage 1 coefficients. 548 * 2. If the filter is two stage filter , subtract "shift" to the 549 * exponent of stage 2 coefficients. 550 * 551 * The "shift" is 15,23,31, different for int16, int24, int32 case. 552 * 553 */ 554 if (out_s_rate >= in_s_rate) { 555 if (out_s_rate == in_s_rate) 556 regmap_update_bits(easrc->regmap, 557 REG_EASRC_CCE1(ctx_id), 558 EASRC_CCE1_RS_BYPASS_MASK, 559 EASRC_CCE1_RS_BYPASS); 560 561 ctx_priv->st1_num_taps = 1; 562 ctx_priv->st1_coeff = &easrc_priv->const_coeff; 563 ctx_priv->st1_num_exp = 1; 564 ctx_priv->st2_num_taps = 0; 565 566 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE && 567 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) 568 ctx_priv->st1_addexp = 31; 569 else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE && 570 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) 571 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; 572 } else { 573 inrate = ctx_priv->in_params.norm_rate; 574 outrate = ctx_priv->out_params.norm_rate; 575 576 hdr = easrc_priv->firmware_hdr; 577 prefil = easrc_priv->prefil; 578 579 for (i = 0; i < hdr->prefil_scen; i++) { 580 if (inrate == prefil[i].insr && 581 outrate == prefil[i].outsr) { 582 selected_prefil = &prefil[i]; 583 dev_dbg(dev, "Selected prefilter: %u insr, %u outsr, %u st1_taps, %u st2_taps\n", 584 selected_prefil->insr, 585 selected_prefil->outsr, 586 selected_prefil->st1_taps, 587 selected_prefil->st2_taps); 588 break; 589 } 590 } 591 592 if (!selected_prefil) { 593 dev_err(dev, "Conversion from in ratio %u(%u) to out ratio %u(%u) is not supported\n", 594 in_s_rate, inrate, 595 out_s_rate, outrate); 596 return -EINVAL; 597 } 598 599 /* 600 * In prefilter coeff array, first st1_num_taps represent the 601 * stage1 prefilter coefficients followed by next st2_num_taps 602 * representing stage 2 coefficients 603 */ 604 ctx_priv->st1_num_taps = selected_prefil->st1_taps; 605 ctx_priv->st1_coeff = selected_prefil->coeff; 606 ctx_priv->st1_num_exp = selected_prefil->st1_exp; 607 608 offset = ((selected_prefil->st1_taps + 1) / 2); 609 ctx_priv->st2_num_taps = selected_prefil->st2_taps; 610 ctx_priv->st2_coeff = selected_prefil->coeff + offset; 611 612 if (in_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE && 613 out_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE) { 614 /* only change stage2 coefficient for 2 stage case */ 615 if (ctx_priv->st2_num_taps > 0) 616 ctx_priv->st2_addexp = 31; 617 else 618 ctx_priv->st1_addexp = 31; 619 } else if (in_s_fmt != SNDRV_PCM_FORMAT_FLOAT_LE && 620 out_s_fmt == SNDRV_PCM_FORMAT_FLOAT_LE) { 621 if (ctx_priv->st2_num_taps > 0) 622 ctx_priv->st2_addexp -= ctx_priv->in_params.fmt.addexp; 623 else 624 ctx_priv->st1_addexp -= ctx_priv->in_params.fmt.addexp; 625 } 626 } 627 628 ctx_priv->in_filled_sample += (ctx_priv->st1_num_taps / 2) * ctx_priv->st1_num_exp + 629 ctx_priv->st2_num_taps / 2; 630 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * out_s_rate / in_s_rate; 631 632 if (ctx_priv->in_filled_sample * out_s_rate % in_s_rate != 0) 633 ctx_priv->out_missed_sample += 1; 634 /* 635 * To modify the value of a prefilter coefficient, the user must 636 * perform a write to the register ASRC_PRE_COEFF_FIFOn[COEFF_DATA] 637 * while the respective context RUN_EN bit is set to 0b0 638 */ 639 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 640 EASRC_CC_EN_MASK, 0); 641 642 if (ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { 643 dev_err(dev, "ST1 taps [%d] mus be lower than %d\n", 644 ctx_priv->st1_num_taps, EASRC_MAX_PF_TAPS); 645 ret = -EINVAL; 646 goto ctx_error; 647 } 648 649 /* Update ctx ST1_NUM_TAPS in Context Control Extended 2 register */ 650 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), 651 EASRC_CCE2_ST1_TAPS_MASK, 652 EASRC_CCE2_ST1_TAPS(ctx_priv->st1_num_taps - 1)); 653 654 /* Prefilter Coefficient Write Select to write in ST1 coeff */ 655 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 656 EASRC_CCE1_COEF_WS_MASK, 657 EASRC_PF_ST1_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT); 658 659 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, 660 ctx_priv->st1_coeff, 661 ctx_priv->st1_num_taps, 662 ctx_priv->st1_addexp); 663 if (ret) 664 goto ctx_error; 665 666 if (ctx_priv->st2_num_taps > 0) { 667 if (ctx_priv->st2_num_taps + ctx_priv->st1_num_taps > EASRC_MAX_PF_TAPS) { 668 dev_err(dev, "ST2 taps [%d] mus be lower than %d\n", 669 ctx_priv->st2_num_taps, EASRC_MAX_PF_TAPS); 670 ret = -EINVAL; 671 goto ctx_error; 672 } 673 674 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 675 EASRC_CCE1_PF_TSEN_MASK, 676 EASRC_CCE1_PF_TSEN); 677 /* 678 * Enable prefilter stage1 writeback floating point 679 * which is used for FLOAT_LE case 680 */ 681 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 682 EASRC_CCE1_PF_ST1_WBFP_MASK, 683 EASRC_CCE1_PF_ST1_WBFP); 684 685 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 686 EASRC_CCE1_PF_EXP_MASK, 687 EASRC_CCE1_PF_EXP(ctx_priv->st1_num_exp - 1)); 688 689 /* Update ctx ST2_NUM_TAPS in Context Control Extended 2 reg */ 690 regmap_update_bits(easrc->regmap, REG_EASRC_CCE2(ctx_id), 691 EASRC_CCE2_ST2_TAPS_MASK, 692 EASRC_CCE2_ST2_TAPS(ctx_priv->st2_num_taps - 1)); 693 694 /* Prefilter Coefficient Write Select to write in ST2 coeff */ 695 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 696 EASRC_CCE1_COEF_WS_MASK, 697 EASRC_PF_ST2_COEFF_WR << EASRC_CCE1_COEF_WS_SHIFT); 698 699 ret = fsl_easrc_write_pf_coeff_mem(easrc, ctx_id, 700 ctx_priv->st2_coeff, 701 ctx_priv->st2_num_taps, 702 ctx_priv->st2_addexp); 703 if (ret) 704 goto ctx_error; 705 } 706 707 return 0; 708 709 ctx_error: 710 return ret; 711 } 712 713 static int fsl_easrc_max_ch_for_slot(struct fsl_asrc_pair *ctx, 714 struct fsl_easrc_slot *slot) 715 { 716 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 717 int st1_mem_alloc = 0, st2_mem_alloc = 0; 718 int pf_mem_alloc = 0; 719 int max_channels = 8 - slot->num_channel; 720 int channels = 0; 721 722 if (ctx_priv->st1_num_taps > 0) { 723 if (ctx_priv->st2_num_taps > 0) 724 st1_mem_alloc = 725 (ctx_priv->st1_num_taps - 1) * ctx_priv->st1_num_exp + 1; 726 else 727 st1_mem_alloc = ctx_priv->st1_num_taps; 728 } 729 730 if (ctx_priv->st2_num_taps > 0) 731 st2_mem_alloc = ctx_priv->st2_num_taps; 732 733 pf_mem_alloc = st1_mem_alloc + st2_mem_alloc; 734 735 if (pf_mem_alloc != 0) 736 channels = (6144 - slot->pf_mem_used) / pf_mem_alloc; 737 else 738 channels = 8; 739 740 if (channels < max_channels) 741 max_channels = channels; 742 743 return max_channels; 744 } 745 746 static int fsl_easrc_config_one_slot(struct fsl_asrc_pair *ctx, 747 struct fsl_easrc_slot *slot, 748 unsigned int slot_ctx_idx, 749 unsigned int *req_channels, 750 unsigned int *start_channel, 751 unsigned int *avail_channel) 752 { 753 struct fsl_asrc *easrc = ctx->asrc; 754 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 755 int st1_chanxexp, st1_mem_alloc = 0, st2_mem_alloc = 0; 756 unsigned int reg0, reg1, reg2, reg3; 757 unsigned int addr; 758 759 if (slot->slot_index == 0) { 760 reg0 = REG_EASRC_DPCS0R0(slot_ctx_idx); 761 reg1 = REG_EASRC_DPCS0R1(slot_ctx_idx); 762 reg2 = REG_EASRC_DPCS0R2(slot_ctx_idx); 763 reg3 = REG_EASRC_DPCS0R3(slot_ctx_idx); 764 } else { 765 reg0 = REG_EASRC_DPCS1R0(slot_ctx_idx); 766 reg1 = REG_EASRC_DPCS1R1(slot_ctx_idx); 767 reg2 = REG_EASRC_DPCS1R2(slot_ctx_idx); 768 reg3 = REG_EASRC_DPCS1R3(slot_ctx_idx); 769 } 770 771 if (*req_channels <= *avail_channel) { 772 slot->num_channel = *req_channels; 773 *req_channels = 0; 774 } else { 775 slot->num_channel = *avail_channel; 776 *req_channels -= *avail_channel; 777 } 778 779 slot->min_channel = *start_channel; 780 slot->max_channel = *start_channel + slot->num_channel - 1; 781 slot->ctx_index = ctx->index; 782 slot->busy = true; 783 *start_channel += slot->num_channel; 784 785 regmap_update_bits(easrc->regmap, reg0, 786 EASRC_DPCS0R0_MAXCH_MASK, 787 EASRC_DPCS0R0_MAXCH(slot->max_channel)); 788 789 regmap_update_bits(easrc->regmap, reg0, 790 EASRC_DPCS0R0_MINCH_MASK, 791 EASRC_DPCS0R0_MINCH(slot->min_channel)); 792 793 regmap_update_bits(easrc->regmap, reg0, 794 EASRC_DPCS0R0_NUMCH_MASK, 795 EASRC_DPCS0R0_NUMCH(slot->num_channel - 1)); 796 797 regmap_update_bits(easrc->regmap, reg0, 798 EASRC_DPCS0R0_CTXNUM_MASK, 799 EASRC_DPCS0R0_CTXNUM(slot->ctx_index)); 800 801 if (ctx_priv->st1_num_taps > 0) { 802 if (ctx_priv->st2_num_taps > 0) 803 st1_mem_alloc = 804 (ctx_priv->st1_num_taps - 1) * slot->num_channel * 805 ctx_priv->st1_num_exp + slot->num_channel; 806 else 807 st1_mem_alloc = ctx_priv->st1_num_taps * slot->num_channel; 808 809 slot->pf_mem_used = st1_mem_alloc; 810 regmap_update_bits(easrc->regmap, reg2, 811 EASRC_DPCS0R2_ST1_MA_MASK, 812 EASRC_DPCS0R2_ST1_MA(st1_mem_alloc)); 813 814 if (slot->slot_index == 1) 815 addr = PREFILTER_MEM_LEN - st1_mem_alloc; 816 else 817 addr = 0; 818 819 regmap_update_bits(easrc->regmap, reg2, 820 EASRC_DPCS0R2_ST1_SA_MASK, 821 EASRC_DPCS0R2_ST1_SA(addr)); 822 } 823 824 if (ctx_priv->st2_num_taps > 0) { 825 st1_chanxexp = slot->num_channel * (ctx_priv->st1_num_exp - 1); 826 827 regmap_update_bits(easrc->regmap, reg1, 828 EASRC_DPCS0R1_ST1_EXP_MASK, 829 EASRC_DPCS0R1_ST1_EXP(st1_chanxexp)); 830 831 st2_mem_alloc = slot->num_channel * ctx_priv->st2_num_taps; 832 slot->pf_mem_used += st2_mem_alloc; 833 regmap_update_bits(easrc->regmap, reg3, 834 EASRC_DPCS0R3_ST2_MA_MASK, 835 EASRC_DPCS0R3_ST2_MA(st2_mem_alloc)); 836 837 if (slot->slot_index == 1) 838 addr = PREFILTER_MEM_LEN - st1_mem_alloc - st2_mem_alloc; 839 else 840 addr = st1_mem_alloc; 841 842 regmap_update_bits(easrc->regmap, reg3, 843 EASRC_DPCS0R3_ST2_SA_MASK, 844 EASRC_DPCS0R3_ST2_SA(addr)); 845 } 846 847 regmap_update_bits(easrc->regmap, reg0, 848 EASRC_DPCS0R0_EN_MASK, EASRC_DPCS0R0_EN); 849 850 return 0; 851 } 852 853 /* 854 * fsl_easrc_config_slot 855 * 856 * A single context can be split amongst any of the 4 context processing pipes 857 * in the design. 858 * The total number of channels consumed within the context processor must be 859 * less than or equal to 8. if a single context is configured to contain more 860 * than 8 channels then it must be distributed across multiple context 861 * processing pipe slots. 862 * 863 */ 864 static int fsl_easrc_config_slot(struct fsl_asrc *easrc, unsigned int ctx_id) 865 { 866 struct fsl_easrc_priv *easrc_priv = easrc->private; 867 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; 868 int req_channels = ctx->channels; 869 int start_channel = 0, avail_channel; 870 struct fsl_easrc_slot *slot0, *slot1; 871 struct fsl_easrc_slot *slota, *slotb; 872 int i, ret; 873 874 if (req_channels <= 0) 875 return -EINVAL; 876 877 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) { 878 slot0 = &easrc_priv->slot[i][0]; 879 slot1 = &easrc_priv->slot[i][1]; 880 881 if (slot0->busy && slot1->busy) { 882 continue; 883 } else if ((slot0->busy && slot0->ctx_index == ctx->index) || 884 (slot1->busy && slot1->ctx_index == ctx->index)) { 885 continue; 886 } else if (!slot0->busy) { 887 slota = slot0; 888 slotb = slot1; 889 slota->slot_index = 0; 890 } else if (!slot1->busy) { 891 slota = slot1; 892 slotb = slot0; 893 slota->slot_index = 1; 894 } 895 896 if (!slota || !slotb) 897 continue; 898 899 avail_channel = fsl_easrc_max_ch_for_slot(ctx, slotb); 900 if (avail_channel <= 0) 901 continue; 902 903 ret = fsl_easrc_config_one_slot(ctx, slota, i, &req_channels, 904 &start_channel, &avail_channel); 905 if (ret) 906 return ret; 907 908 if (req_channels > 0) 909 continue; 910 else 911 break; 912 } 913 914 if (req_channels > 0) { 915 dev_err(&easrc->pdev->dev, "no avail slot.\n"); 916 return -EINVAL; 917 } 918 919 return 0; 920 } 921 922 /* 923 * fsl_easrc_release_slot 924 * 925 * Clear the slot configuration 926 */ 927 static int fsl_easrc_release_slot(struct fsl_asrc *easrc, unsigned int ctx_id) 928 { 929 struct fsl_easrc_priv *easrc_priv = easrc->private; 930 struct fsl_asrc_pair *ctx = easrc->pair[ctx_id]; 931 int i; 932 933 for (i = 0; i < EASRC_CTX_MAX_NUM; i++) { 934 if (easrc_priv->slot[i][0].busy && 935 easrc_priv->slot[i][0].ctx_index == ctx->index) { 936 easrc_priv->slot[i][0].busy = false; 937 easrc_priv->slot[i][0].num_channel = 0; 938 easrc_priv->slot[i][0].pf_mem_used = 0; 939 /* set registers */ 940 regmap_write(easrc->regmap, REG_EASRC_DPCS0R0(i), 0); 941 regmap_write(easrc->regmap, REG_EASRC_DPCS0R1(i), 0); 942 regmap_write(easrc->regmap, REG_EASRC_DPCS0R2(i), 0); 943 regmap_write(easrc->regmap, REG_EASRC_DPCS0R3(i), 0); 944 } 945 946 if (easrc_priv->slot[i][1].busy && 947 easrc_priv->slot[i][1].ctx_index == ctx->index) { 948 easrc_priv->slot[i][1].busy = false; 949 easrc_priv->slot[i][1].num_channel = 0; 950 easrc_priv->slot[i][1].pf_mem_used = 0; 951 /* set registers */ 952 regmap_write(easrc->regmap, REG_EASRC_DPCS1R0(i), 0); 953 regmap_write(easrc->regmap, REG_EASRC_DPCS1R1(i), 0); 954 regmap_write(easrc->regmap, REG_EASRC_DPCS1R2(i), 0); 955 regmap_write(easrc->regmap, REG_EASRC_DPCS1R3(i), 0); 956 } 957 } 958 959 return 0; 960 } 961 962 /* 963 * fsl_easrc_config_context 964 * 965 * Configure the register relate with context. 966 */ 967 int fsl_easrc_config_context(struct fsl_asrc *easrc, unsigned int ctx_id) 968 { 969 struct fsl_easrc_ctx_priv *ctx_priv; 970 struct fsl_asrc_pair *ctx; 971 struct device *dev; 972 unsigned long lock_flags; 973 int ret; 974 975 if (!easrc) 976 return -ENODEV; 977 978 dev = &easrc->pdev->dev; 979 980 if (ctx_id >= EASRC_CTX_MAX_NUM) { 981 dev_err(dev, "Invalid context id[%d]\n", ctx_id); 982 return -EINVAL; 983 } 984 985 ctx = easrc->pair[ctx_id]; 986 987 ctx_priv = ctx->private; 988 989 fsl_easrc_normalize_rates(ctx); 990 991 ret = fsl_easrc_set_rs_ratio(ctx); 992 if (ret) 993 return ret; 994 995 /* Initialize the context coeficients */ 996 ret = fsl_easrc_prefilter_config(easrc, ctx->index); 997 if (ret) 998 return ret; 999 1000 spin_lock_irqsave(&easrc->lock, lock_flags); 1001 ret = fsl_easrc_config_slot(easrc, ctx->index); 1002 spin_unlock_irqrestore(&easrc->lock, lock_flags); 1003 if (ret) 1004 return ret; 1005 1006 /* 1007 * Both prefilter and resampling filters can use following 1008 * initialization modes: 1009 * 2 - zero-fil mode 1010 * 1 - replication mode 1011 * 0 - software control 1012 */ 1013 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 1014 EASRC_CCE1_RS_INIT_MASK, 1015 EASRC_CCE1_RS_INIT(ctx_priv->rs_init_mode)); 1016 1017 regmap_update_bits(easrc->regmap, REG_EASRC_CCE1(ctx_id), 1018 EASRC_CCE1_PF_INIT_MASK, 1019 EASRC_CCE1_PF_INIT(ctx_priv->pf_init_mode)); 1020 1021 /* 1022 * Context Input FIFO Watermark 1023 * DMA request is generated when input FIFO < FIFO_WTMK 1024 */ 1025 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 1026 EASRC_CC_FIFO_WTMK_MASK, 1027 EASRC_CC_FIFO_WTMK(ctx_priv->in_params.fifo_wtmk)); 1028 1029 /* 1030 * Context Output FIFO Watermark 1031 * DMA request is generated when output FIFO > FIFO_WTMK 1032 * So we set fifo_wtmk -1 to register. 1033 */ 1034 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx_id), 1035 EASRC_COC_FIFO_WTMK_MASK, 1036 EASRC_COC_FIFO_WTMK(ctx_priv->out_params.fifo_wtmk - 1)); 1037 1038 /* Number of channels */ 1039 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx_id), 1040 EASRC_CC_CHEN_MASK, 1041 EASRC_CC_CHEN(ctx->channels - 1)); 1042 return 0; 1043 } 1044 1045 static int fsl_easrc_process_format(struct fsl_asrc_pair *ctx, 1046 struct fsl_easrc_data_fmt *fmt, 1047 snd_pcm_format_t raw_fmt) 1048 { 1049 struct fsl_asrc *easrc = ctx->asrc; 1050 struct fsl_easrc_priv *easrc_priv = easrc->private; 1051 int ret; 1052 1053 if (!fmt) 1054 return -EINVAL; 1055 1056 /* 1057 * Context Input Floating Point Format 1058 * 0 - Integer Format 1059 * 1 - Single Precision FP Format 1060 */ 1061 fmt->floating_point = !snd_pcm_format_linear(raw_fmt); 1062 fmt->sample_pos = 0; 1063 fmt->iec958 = 0; 1064 1065 /* Get the data width */ 1066 switch (snd_pcm_format_width(raw_fmt)) { 1067 case 16: 1068 fmt->width = EASRC_WIDTH_16_BIT; 1069 fmt->addexp = 15; 1070 break; 1071 case 20: 1072 fmt->width = EASRC_WIDTH_20_BIT; 1073 fmt->addexp = 19; 1074 break; 1075 case 24: 1076 fmt->width = EASRC_WIDTH_24_BIT; 1077 fmt->addexp = 23; 1078 break; 1079 case 32: 1080 fmt->width = EASRC_WIDTH_32_BIT; 1081 fmt->addexp = 31; 1082 break; 1083 default: 1084 return -EINVAL; 1085 } 1086 1087 switch (raw_fmt) { 1088 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 1089 fmt->width = easrc_priv->bps_iec958[ctx->index]; 1090 fmt->iec958 = 1; 1091 fmt->floating_point = 0; 1092 if (fmt->width == EASRC_WIDTH_16_BIT) { 1093 fmt->sample_pos = 12; 1094 fmt->addexp = 15; 1095 } else if (fmt->width == EASRC_WIDTH_20_BIT) { 1096 fmt->sample_pos = 8; 1097 fmt->addexp = 19; 1098 } else if (fmt->width == EASRC_WIDTH_24_BIT) { 1099 fmt->sample_pos = 4; 1100 fmt->addexp = 23; 1101 } 1102 break; 1103 default: 1104 break; 1105 } 1106 1107 /* 1108 * Data Endianness 1109 * 0 - Little-Endian 1110 * 1 - Big-Endian 1111 */ 1112 ret = snd_pcm_format_big_endian(raw_fmt); 1113 if (ret < 0) 1114 return ret; 1115 1116 fmt->endianness = ret; 1117 1118 /* 1119 * Input Data sign 1120 * 0b - Signed Format 1121 * 1b - Unsigned Format 1122 */ 1123 fmt->unsign = snd_pcm_format_unsigned(raw_fmt) > 0 ? 1 : 0; 1124 1125 return 0; 1126 } 1127 1128 int fsl_easrc_set_ctx_format(struct fsl_asrc_pair *ctx, 1129 snd_pcm_format_t *in_raw_format, 1130 snd_pcm_format_t *out_raw_format) 1131 { 1132 struct fsl_asrc *easrc = ctx->asrc; 1133 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 1134 struct fsl_easrc_data_fmt *in_fmt = &ctx_priv->in_params.fmt; 1135 struct fsl_easrc_data_fmt *out_fmt = &ctx_priv->out_params.fmt; 1136 int ret; 1137 1138 /* Get the bitfield values for input data format */ 1139 if (in_raw_format && out_raw_format) { 1140 ret = fsl_easrc_process_format(ctx, in_fmt, *in_raw_format); 1141 if (ret) 1142 return ret; 1143 } 1144 1145 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1146 EASRC_CC_BPS_MASK, 1147 EASRC_CC_BPS(in_fmt->width)); 1148 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1149 EASRC_CC_ENDIANNESS_MASK, 1150 in_fmt->endianness << EASRC_CC_ENDIANNESS_SHIFT); 1151 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1152 EASRC_CC_FMT_MASK, 1153 in_fmt->floating_point << EASRC_CC_FMT_SHIFT); 1154 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1155 EASRC_CC_INSIGN_MASK, 1156 in_fmt->unsign << EASRC_CC_INSIGN_SHIFT); 1157 1158 /* In Sample Position */ 1159 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1160 EASRC_CC_SAMPLE_POS_MASK, 1161 EASRC_CC_SAMPLE_POS(in_fmt->sample_pos)); 1162 1163 /* Get the bitfield values for input data format */ 1164 if (in_raw_format && out_raw_format) { 1165 ret = fsl_easrc_process_format(ctx, out_fmt, *out_raw_format); 1166 if (ret) 1167 return ret; 1168 } 1169 1170 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1171 EASRC_COC_BPS_MASK, 1172 EASRC_COC_BPS(out_fmt->width)); 1173 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1174 EASRC_COC_ENDIANNESS_MASK, 1175 out_fmt->endianness << EASRC_COC_ENDIANNESS_SHIFT); 1176 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1177 EASRC_COC_FMT_MASK, 1178 out_fmt->floating_point << EASRC_COC_FMT_SHIFT); 1179 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1180 EASRC_COC_OUTSIGN_MASK, 1181 out_fmt->unsign << EASRC_COC_OUTSIGN_SHIFT); 1182 1183 /* Out Sample Position */ 1184 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1185 EASRC_COC_SAMPLE_POS_MASK, 1186 EASRC_COC_SAMPLE_POS(out_fmt->sample_pos)); 1187 1188 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1189 EASRC_COC_IEC_EN_MASK, 1190 out_fmt->iec958 << EASRC_COC_IEC_EN_SHIFT); 1191 1192 return ret; 1193 } 1194 1195 /* 1196 * The ASRC provides interleaving support in hardware to ensure that a 1197 * variety of sample sources can be internally combined 1198 * to conform with this format. Interleaving parameters are accessed 1199 * through the ASRC_CTRL_IN_ACCESSa and ASRC_CTRL_OUT_ACCESSa registers 1200 */ 1201 int fsl_easrc_set_ctx_organziation(struct fsl_asrc_pair *ctx) 1202 { 1203 struct fsl_easrc_ctx_priv *ctx_priv; 1204 struct device *dev; 1205 struct fsl_asrc *easrc; 1206 1207 if (!ctx) 1208 return -ENODEV; 1209 1210 easrc = ctx->asrc; 1211 ctx_priv = ctx->private; 1212 dev = &easrc->pdev->dev; 1213 1214 /* input interleaving parameters */ 1215 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1216 EASRC_CIA_ITER_MASK, 1217 EASRC_CIA_ITER(ctx_priv->in_params.iterations)); 1218 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1219 EASRC_CIA_GRLEN_MASK, 1220 EASRC_CIA_GRLEN(ctx_priv->in_params.group_len)); 1221 regmap_update_bits(easrc->regmap, REG_EASRC_CIA(ctx->index), 1222 EASRC_CIA_ACCLEN_MASK, 1223 EASRC_CIA_ACCLEN(ctx_priv->in_params.access_len)); 1224 1225 /* output interleaving parameters */ 1226 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1227 EASRC_COA_ITER_MASK, 1228 EASRC_COA_ITER(ctx_priv->out_params.iterations)); 1229 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1230 EASRC_COA_GRLEN_MASK, 1231 EASRC_COA_GRLEN(ctx_priv->out_params.group_len)); 1232 regmap_update_bits(easrc->regmap, REG_EASRC_COA(ctx->index), 1233 EASRC_COA_ACCLEN_MASK, 1234 EASRC_COA_ACCLEN(ctx_priv->out_params.access_len)); 1235 1236 return 0; 1237 } 1238 1239 /* 1240 * Request one of the available contexts 1241 * 1242 * Returns a negative number on error and >=0 as context id 1243 * on success 1244 */ 1245 int fsl_easrc_request_context(int channels, struct fsl_asrc_pair *ctx) 1246 { 1247 enum asrc_pair_index index = ASRC_INVALID_PAIR; 1248 struct fsl_asrc *easrc = ctx->asrc; 1249 struct device *dev; 1250 unsigned long lock_flags; 1251 int ret = 0; 1252 int i; 1253 1254 dev = &easrc->pdev->dev; 1255 1256 spin_lock_irqsave(&easrc->lock, lock_flags); 1257 1258 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) { 1259 if (easrc->pair[i]) 1260 continue; 1261 1262 index = i; 1263 break; 1264 } 1265 1266 if (index == ASRC_INVALID_PAIR) { 1267 dev_err(dev, "all contexts are busy\n"); 1268 ret = -EBUSY; 1269 } else if (channels > easrc->channel_avail) { 1270 dev_err(dev, "can't give the required channels: %d\n", 1271 channels); 1272 ret = -EINVAL; 1273 } else { 1274 ctx->index = index; 1275 ctx->channels = channels; 1276 easrc->pair[index] = ctx; 1277 easrc->channel_avail -= channels; 1278 } 1279 1280 spin_unlock_irqrestore(&easrc->lock, lock_flags); 1281 1282 return ret; 1283 } 1284 1285 /* 1286 * Release the context 1287 * 1288 * This funciton is mainly doing the revert thing in request context 1289 */ 1290 void fsl_easrc_release_context(struct fsl_asrc_pair *ctx) 1291 { 1292 unsigned long lock_flags; 1293 struct fsl_asrc *easrc; 1294 struct device *dev; 1295 1296 if (!ctx) 1297 return; 1298 1299 easrc = ctx->asrc; 1300 dev = &easrc->pdev->dev; 1301 1302 spin_lock_irqsave(&easrc->lock, lock_flags); 1303 1304 fsl_easrc_release_slot(easrc, ctx->index); 1305 1306 easrc->channel_avail += ctx->channels; 1307 easrc->pair[ctx->index] = NULL; 1308 1309 spin_unlock_irqrestore(&easrc->lock, lock_flags); 1310 } 1311 1312 /* 1313 * Start the context 1314 * 1315 * Enable the DMA request and context 1316 */ 1317 int fsl_easrc_start_context(struct fsl_asrc_pair *ctx) 1318 { 1319 struct fsl_asrc *easrc = ctx->asrc; 1320 1321 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1322 EASRC_CC_FWMDE_MASK, EASRC_CC_FWMDE); 1323 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1324 EASRC_COC_FWMDE_MASK, EASRC_COC_FWMDE); 1325 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1326 EASRC_CC_EN_MASK, EASRC_CC_EN); 1327 return 0; 1328 } 1329 1330 /* 1331 * Stop the context 1332 * 1333 * Disable the DMA request and context 1334 */ 1335 int fsl_easrc_stop_context(struct fsl_asrc_pair *ctx) 1336 { 1337 struct fsl_asrc *easrc = ctx->asrc; 1338 int val, i; 1339 int size = 0; 1340 int retry = 200; 1341 1342 regmap_read(easrc->regmap, REG_EASRC_CC(ctx->index), &val); 1343 1344 if (val & EASRC_CC_EN_MASK) { 1345 regmap_update_bits(easrc->regmap, 1346 REG_EASRC_CC(ctx->index), 1347 EASRC_CC_STOP_MASK, EASRC_CC_STOP); 1348 do { 1349 regmap_read(easrc->regmap, REG_EASRC_SFS(ctx->index), &val); 1350 val &= EASRC_SFS_NSGO_MASK; 1351 size = val >> EASRC_SFS_NSGO_SHIFT; 1352 1353 /* Read FIFO, drop the data */ 1354 for (i = 0; i < size * ctx->channels; i++) 1355 regmap_read(easrc->regmap, REG_EASRC_RDFIFO(ctx->index), &val); 1356 /* Check RUN_STOP_DONE */ 1357 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); 1358 if (val & EASRC_IRQF_RSD(1 << ctx->index)) { 1359 /*Clear RUN_STOP_DONE*/ 1360 regmap_write_bits(easrc->regmap, 1361 REG_EASRC_IRQF, 1362 EASRC_IRQF_RSD(1 << ctx->index), 1363 EASRC_IRQF_RSD(1 << ctx->index)); 1364 break; 1365 } 1366 udelay(100); 1367 } while (--retry); 1368 1369 if (retry == 0) 1370 dev_warn(&easrc->pdev->dev, "RUN STOP fail\n"); 1371 } 1372 1373 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1374 EASRC_CC_EN_MASK | EASRC_CC_STOP_MASK, 0); 1375 regmap_update_bits(easrc->regmap, REG_EASRC_CC(ctx->index), 1376 EASRC_CC_FWMDE_MASK, 0); 1377 regmap_update_bits(easrc->regmap, REG_EASRC_COC(ctx->index), 1378 EASRC_COC_FWMDE_MASK, 0); 1379 return 0; 1380 } 1381 1382 struct dma_chan *fsl_easrc_get_dma_channel(struct fsl_asrc_pair *ctx, 1383 bool dir) 1384 { 1385 struct fsl_asrc *easrc = ctx->asrc; 1386 enum asrc_pair_index index = ctx->index; 1387 char name[8]; 1388 1389 /* Example of dma name: ctx0_rx */ 1390 sprintf(name, "ctx%c_%cx", index + '0', dir == IN ? 'r' : 't'); 1391 1392 return dma_request_slave_channel(&easrc->pdev->dev, name); 1393 }; 1394 EXPORT_SYMBOL_GPL(fsl_easrc_get_dma_channel); 1395 1396 static const unsigned int easrc_rates[] = { 1397 8000, 11025, 12000, 16000, 1398 22050, 24000, 32000, 44100, 1399 48000, 64000, 88200, 96000, 1400 128000, 176400, 192000, 256000, 1401 352800, 384000, 705600, 768000, 1402 }; 1403 1404 static const struct snd_pcm_hw_constraint_list easrc_rate_constraints = { 1405 .count = ARRAY_SIZE(easrc_rates), 1406 .list = easrc_rates, 1407 }; 1408 1409 static int fsl_easrc_startup(struct snd_pcm_substream *substream, 1410 struct snd_soc_dai *dai) 1411 { 1412 return snd_pcm_hw_constraint_list(substream->runtime, 0, 1413 SNDRV_PCM_HW_PARAM_RATE, 1414 &easrc_rate_constraints); 1415 } 1416 1417 static int fsl_easrc_trigger(struct snd_pcm_substream *substream, 1418 int cmd, struct snd_soc_dai *dai) 1419 { 1420 struct snd_pcm_runtime *runtime = substream->runtime; 1421 struct fsl_asrc_pair *ctx = runtime->private_data; 1422 int ret; 1423 1424 switch (cmd) { 1425 case SNDRV_PCM_TRIGGER_START: 1426 case SNDRV_PCM_TRIGGER_RESUME: 1427 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1428 ret = fsl_easrc_start_context(ctx); 1429 if (ret) 1430 return ret; 1431 break; 1432 case SNDRV_PCM_TRIGGER_STOP: 1433 case SNDRV_PCM_TRIGGER_SUSPEND: 1434 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1435 ret = fsl_easrc_stop_context(ctx); 1436 if (ret) 1437 return ret; 1438 break; 1439 default: 1440 return -EINVAL; 1441 } 1442 1443 return 0; 1444 } 1445 1446 static int fsl_easrc_hw_params(struct snd_pcm_substream *substream, 1447 struct snd_pcm_hw_params *params, 1448 struct snd_soc_dai *dai) 1449 { 1450 struct fsl_asrc *easrc = snd_soc_dai_get_drvdata(dai); 1451 struct snd_pcm_runtime *runtime = substream->runtime; 1452 struct device *dev = &easrc->pdev->dev; 1453 struct fsl_asrc_pair *ctx = runtime->private_data; 1454 struct fsl_easrc_ctx_priv *ctx_priv = ctx->private; 1455 unsigned int channels = params_channels(params); 1456 unsigned int rate = params_rate(params); 1457 snd_pcm_format_t format = params_format(params); 1458 int ret; 1459 1460 ret = fsl_easrc_request_context(channels, ctx); 1461 if (ret) { 1462 dev_err(dev, "failed to request context\n"); 1463 return ret; 1464 } 1465 1466 ctx_priv->ctx_streams |= BIT(substream->stream); 1467 1468 /* 1469 * Set the input and output ratio so we can compute 1470 * the resampling ratio in RS_LOW/HIGH 1471 */ 1472 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1473 ctx_priv->in_params.sample_rate = rate; 1474 ctx_priv->in_params.sample_format = format; 1475 ctx_priv->out_params.sample_rate = easrc->asrc_rate; 1476 ctx_priv->out_params.sample_format = easrc->asrc_format; 1477 } else { 1478 ctx_priv->out_params.sample_rate = rate; 1479 ctx_priv->out_params.sample_format = format; 1480 ctx_priv->in_params.sample_rate = easrc->asrc_rate; 1481 ctx_priv->in_params.sample_format = easrc->asrc_format; 1482 } 1483 1484 ctx->channels = channels; 1485 ctx_priv->in_params.fifo_wtmk = 0x20; 1486 ctx_priv->out_params.fifo_wtmk = 0x20; 1487 1488 /* 1489 * Do only rate conversion and keep the same format for input 1490 * and output data 1491 */ 1492 ret = fsl_easrc_set_ctx_format(ctx, 1493 &ctx_priv->in_params.sample_format, 1494 &ctx_priv->out_params.sample_format); 1495 if (ret) { 1496 dev_err(dev, "failed to set format %d", ret); 1497 return ret; 1498 } 1499 1500 ret = fsl_easrc_config_context(easrc, ctx->index); 1501 if (ret) { 1502 dev_err(dev, "failed to config context\n"); 1503 return ret; 1504 } 1505 1506 ctx_priv->in_params.iterations = 1; 1507 ctx_priv->in_params.group_len = ctx->channels; 1508 ctx_priv->in_params.access_len = ctx->channels; 1509 ctx_priv->out_params.iterations = 1; 1510 ctx_priv->out_params.group_len = ctx->channels; 1511 ctx_priv->out_params.access_len = ctx->channels; 1512 1513 ret = fsl_easrc_set_ctx_organziation(ctx); 1514 if (ret) { 1515 dev_err(dev, "failed to set fifo organization\n"); 1516 return ret; 1517 } 1518 1519 return 0; 1520 } 1521 1522 static int fsl_easrc_hw_free(struct snd_pcm_substream *substream, 1523 struct snd_soc_dai *dai) 1524 { 1525 struct snd_pcm_runtime *runtime = substream->runtime; 1526 struct fsl_asrc_pair *ctx = runtime->private_data; 1527 struct fsl_easrc_ctx_priv *ctx_priv; 1528 1529 if (!ctx) 1530 return -EINVAL; 1531 1532 ctx_priv = ctx->private; 1533 1534 if (ctx_priv->ctx_streams & BIT(substream->stream)) { 1535 ctx_priv->ctx_streams &= ~BIT(substream->stream); 1536 fsl_easrc_release_context(ctx); 1537 } 1538 1539 return 0; 1540 } 1541 1542 static struct snd_soc_dai_ops fsl_easrc_dai_ops = { 1543 .startup = fsl_easrc_startup, 1544 .trigger = fsl_easrc_trigger, 1545 .hw_params = fsl_easrc_hw_params, 1546 .hw_free = fsl_easrc_hw_free, 1547 }; 1548 1549 static int fsl_easrc_dai_probe(struct snd_soc_dai *cpu_dai) 1550 { 1551 struct fsl_asrc *easrc = dev_get_drvdata(cpu_dai->dev); 1552 1553 snd_soc_dai_init_dma_data(cpu_dai, 1554 &easrc->dma_params_tx, 1555 &easrc->dma_params_rx); 1556 return 0; 1557 } 1558 1559 static struct snd_soc_dai_driver fsl_easrc_dai = { 1560 .probe = fsl_easrc_dai_probe, 1561 .playback = { 1562 .stream_name = "ASRC-Playback", 1563 .channels_min = 1, 1564 .channels_max = 32, 1565 .rate_min = 8000, 1566 .rate_max = 768000, 1567 .rates = SNDRV_PCM_RATE_KNOT, 1568 .formats = FSL_EASRC_FORMATS, 1569 }, 1570 .capture = { 1571 .stream_name = "ASRC-Capture", 1572 .channels_min = 1, 1573 .channels_max = 32, 1574 .rate_min = 8000, 1575 .rate_max = 768000, 1576 .rates = SNDRV_PCM_RATE_KNOT, 1577 .formats = FSL_EASRC_FORMATS | 1578 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1579 }, 1580 .ops = &fsl_easrc_dai_ops, 1581 }; 1582 1583 static const struct snd_soc_component_driver fsl_easrc_component = { 1584 .name = "fsl-easrc-dai", 1585 .controls = fsl_easrc_snd_controls, 1586 .num_controls = ARRAY_SIZE(fsl_easrc_snd_controls), 1587 }; 1588 1589 static const struct reg_default fsl_easrc_reg_defaults[] = { 1590 {REG_EASRC_WRFIFO(0), 0x00000000}, 1591 {REG_EASRC_WRFIFO(1), 0x00000000}, 1592 {REG_EASRC_WRFIFO(2), 0x00000000}, 1593 {REG_EASRC_WRFIFO(3), 0x00000000}, 1594 {REG_EASRC_RDFIFO(0), 0x00000000}, 1595 {REG_EASRC_RDFIFO(1), 0x00000000}, 1596 {REG_EASRC_RDFIFO(2), 0x00000000}, 1597 {REG_EASRC_RDFIFO(3), 0x00000000}, 1598 {REG_EASRC_CC(0), 0x00000000}, 1599 {REG_EASRC_CC(1), 0x00000000}, 1600 {REG_EASRC_CC(2), 0x00000000}, 1601 {REG_EASRC_CC(3), 0x00000000}, 1602 {REG_EASRC_CCE1(0), 0x00000000}, 1603 {REG_EASRC_CCE1(1), 0x00000000}, 1604 {REG_EASRC_CCE1(2), 0x00000000}, 1605 {REG_EASRC_CCE1(3), 0x00000000}, 1606 {REG_EASRC_CCE2(0), 0x00000000}, 1607 {REG_EASRC_CCE2(1), 0x00000000}, 1608 {REG_EASRC_CCE2(2), 0x00000000}, 1609 {REG_EASRC_CCE2(3), 0x00000000}, 1610 {REG_EASRC_CIA(0), 0x00000000}, 1611 {REG_EASRC_CIA(1), 0x00000000}, 1612 {REG_EASRC_CIA(2), 0x00000000}, 1613 {REG_EASRC_CIA(3), 0x00000000}, 1614 {REG_EASRC_DPCS0R0(0), 0x00000000}, 1615 {REG_EASRC_DPCS0R0(1), 0x00000000}, 1616 {REG_EASRC_DPCS0R0(2), 0x00000000}, 1617 {REG_EASRC_DPCS0R0(3), 0x00000000}, 1618 {REG_EASRC_DPCS0R1(0), 0x00000000}, 1619 {REG_EASRC_DPCS0R1(1), 0x00000000}, 1620 {REG_EASRC_DPCS0R1(2), 0x00000000}, 1621 {REG_EASRC_DPCS0R1(3), 0x00000000}, 1622 {REG_EASRC_DPCS0R2(0), 0x00000000}, 1623 {REG_EASRC_DPCS0R2(1), 0x00000000}, 1624 {REG_EASRC_DPCS0R2(2), 0x00000000}, 1625 {REG_EASRC_DPCS0R2(3), 0x00000000}, 1626 {REG_EASRC_DPCS0R3(0), 0x00000000}, 1627 {REG_EASRC_DPCS0R3(1), 0x00000000}, 1628 {REG_EASRC_DPCS0R3(2), 0x00000000}, 1629 {REG_EASRC_DPCS0R3(3), 0x00000000}, 1630 {REG_EASRC_DPCS1R0(0), 0x00000000}, 1631 {REG_EASRC_DPCS1R0(1), 0x00000000}, 1632 {REG_EASRC_DPCS1R0(2), 0x00000000}, 1633 {REG_EASRC_DPCS1R0(3), 0x00000000}, 1634 {REG_EASRC_DPCS1R1(0), 0x00000000}, 1635 {REG_EASRC_DPCS1R1(1), 0x00000000}, 1636 {REG_EASRC_DPCS1R1(2), 0x00000000}, 1637 {REG_EASRC_DPCS1R1(3), 0x00000000}, 1638 {REG_EASRC_DPCS1R2(0), 0x00000000}, 1639 {REG_EASRC_DPCS1R2(1), 0x00000000}, 1640 {REG_EASRC_DPCS1R2(2), 0x00000000}, 1641 {REG_EASRC_DPCS1R2(3), 0x00000000}, 1642 {REG_EASRC_DPCS1R3(0), 0x00000000}, 1643 {REG_EASRC_DPCS1R3(1), 0x00000000}, 1644 {REG_EASRC_DPCS1R3(2), 0x00000000}, 1645 {REG_EASRC_DPCS1R3(3), 0x00000000}, 1646 {REG_EASRC_COC(0), 0x00000000}, 1647 {REG_EASRC_COC(1), 0x00000000}, 1648 {REG_EASRC_COC(2), 0x00000000}, 1649 {REG_EASRC_COC(3), 0x00000000}, 1650 {REG_EASRC_COA(0), 0x00000000}, 1651 {REG_EASRC_COA(1), 0x00000000}, 1652 {REG_EASRC_COA(2), 0x00000000}, 1653 {REG_EASRC_COA(3), 0x00000000}, 1654 {REG_EASRC_SFS(0), 0x00000000}, 1655 {REG_EASRC_SFS(1), 0x00000000}, 1656 {REG_EASRC_SFS(2), 0x00000000}, 1657 {REG_EASRC_SFS(3), 0x00000000}, 1658 {REG_EASRC_RRL(0), 0x00000000}, 1659 {REG_EASRC_RRL(1), 0x00000000}, 1660 {REG_EASRC_RRL(2), 0x00000000}, 1661 {REG_EASRC_RRL(3), 0x00000000}, 1662 {REG_EASRC_RRH(0), 0x00000000}, 1663 {REG_EASRC_RRH(1), 0x00000000}, 1664 {REG_EASRC_RRH(2), 0x00000000}, 1665 {REG_EASRC_RRH(3), 0x00000000}, 1666 {REG_EASRC_RUC(0), 0x00000000}, 1667 {REG_EASRC_RUC(1), 0x00000000}, 1668 {REG_EASRC_RUC(2), 0x00000000}, 1669 {REG_EASRC_RUC(3), 0x00000000}, 1670 {REG_EASRC_RUR(0), 0x7FFFFFFF}, 1671 {REG_EASRC_RUR(1), 0x7FFFFFFF}, 1672 {REG_EASRC_RUR(2), 0x7FFFFFFF}, 1673 {REG_EASRC_RUR(3), 0x7FFFFFFF}, 1674 {REG_EASRC_RCTCL, 0x00000000}, 1675 {REG_EASRC_RCTCH, 0x00000000}, 1676 {REG_EASRC_PCF(0), 0x00000000}, 1677 {REG_EASRC_PCF(1), 0x00000000}, 1678 {REG_EASRC_PCF(2), 0x00000000}, 1679 {REG_EASRC_PCF(3), 0x00000000}, 1680 {REG_EASRC_CRCM, 0x00000000}, 1681 {REG_EASRC_CRCC, 0x00000000}, 1682 {REG_EASRC_IRQC, 0x00000FFF}, 1683 {REG_EASRC_IRQF, 0x00000000}, 1684 {REG_EASRC_CS0(0), 0x00000000}, 1685 {REG_EASRC_CS0(1), 0x00000000}, 1686 {REG_EASRC_CS0(2), 0x00000000}, 1687 {REG_EASRC_CS0(3), 0x00000000}, 1688 {REG_EASRC_CS1(0), 0x00000000}, 1689 {REG_EASRC_CS1(1), 0x00000000}, 1690 {REG_EASRC_CS1(2), 0x00000000}, 1691 {REG_EASRC_CS1(3), 0x00000000}, 1692 {REG_EASRC_CS2(0), 0x00000000}, 1693 {REG_EASRC_CS2(1), 0x00000000}, 1694 {REG_EASRC_CS2(2), 0x00000000}, 1695 {REG_EASRC_CS2(3), 0x00000000}, 1696 {REG_EASRC_CS3(0), 0x00000000}, 1697 {REG_EASRC_CS3(1), 0x00000000}, 1698 {REG_EASRC_CS3(2), 0x00000000}, 1699 {REG_EASRC_CS3(3), 0x00000000}, 1700 {REG_EASRC_CS4(0), 0x00000000}, 1701 {REG_EASRC_CS4(1), 0x00000000}, 1702 {REG_EASRC_CS4(2), 0x00000000}, 1703 {REG_EASRC_CS4(3), 0x00000000}, 1704 {REG_EASRC_CS5(0), 0x00000000}, 1705 {REG_EASRC_CS5(1), 0x00000000}, 1706 {REG_EASRC_CS5(2), 0x00000000}, 1707 {REG_EASRC_CS5(3), 0x00000000}, 1708 {REG_EASRC_DBGC, 0x00000000}, 1709 {REG_EASRC_DBGS, 0x00000000}, 1710 }; 1711 1712 static const struct regmap_range fsl_easrc_readable_ranges[] = { 1713 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RCTCH), 1714 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_PCF(3)), 1715 regmap_reg_range(REG_EASRC_CRCC, REG_EASRC_DBGS), 1716 }; 1717 1718 static const struct regmap_access_table fsl_easrc_readable_table = { 1719 .yes_ranges = fsl_easrc_readable_ranges, 1720 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_readable_ranges), 1721 }; 1722 1723 static const struct regmap_range fsl_easrc_writeable_ranges[] = { 1724 regmap_reg_range(REG_EASRC_WRFIFO(0), REG_EASRC_WRFIFO(3)), 1725 regmap_reg_range(REG_EASRC_CC(0), REG_EASRC_COA(3)), 1726 regmap_reg_range(REG_EASRC_RRL(0), REG_EASRC_RCTCH), 1727 regmap_reg_range(REG_EASRC_PCF(0), REG_EASRC_DBGC), 1728 }; 1729 1730 static const struct regmap_access_table fsl_easrc_writeable_table = { 1731 .yes_ranges = fsl_easrc_writeable_ranges, 1732 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_writeable_ranges), 1733 }; 1734 1735 static const struct regmap_range fsl_easrc_volatileable_ranges[] = { 1736 regmap_reg_range(REG_EASRC_RDFIFO(0), REG_EASRC_RDFIFO(3)), 1737 regmap_reg_range(REG_EASRC_SFS(0), REG_EASRC_SFS(3)), 1738 regmap_reg_range(REG_EASRC_IRQF, REG_EASRC_IRQF), 1739 regmap_reg_range(REG_EASRC_DBGS, REG_EASRC_DBGS), 1740 }; 1741 1742 static const struct regmap_access_table fsl_easrc_volatileable_table = { 1743 .yes_ranges = fsl_easrc_volatileable_ranges, 1744 .n_yes_ranges = ARRAY_SIZE(fsl_easrc_volatileable_ranges), 1745 }; 1746 1747 static const struct regmap_config fsl_easrc_regmap_config = { 1748 .reg_bits = 32, 1749 .reg_stride = 4, 1750 .val_bits = 32, 1751 1752 .max_register = REG_EASRC_DBGS, 1753 .reg_defaults = fsl_easrc_reg_defaults, 1754 .num_reg_defaults = ARRAY_SIZE(fsl_easrc_reg_defaults), 1755 .rd_table = &fsl_easrc_readable_table, 1756 .wr_table = &fsl_easrc_writeable_table, 1757 .volatile_table = &fsl_easrc_volatileable_table, 1758 .cache_type = REGCACHE_RBTREE, 1759 }; 1760 1761 #ifdef DEBUG 1762 static void fsl_easrc_dump_firmware(struct fsl_asrc *easrc) 1763 { 1764 struct fsl_easrc_priv *easrc_priv = easrc->private; 1765 struct asrc_firmware_hdr *firm = easrc_priv->firmware_hdr; 1766 struct interp_params *interp = easrc_priv->interp; 1767 struct prefil_params *prefil = easrc_priv->prefil; 1768 struct device *dev = &easrc->pdev->dev; 1769 int i; 1770 1771 if (firm->magic != FIRMWARE_MAGIC) { 1772 dev_err(dev, "Wrong magic. Something went wrong!"); 1773 return; 1774 } 1775 1776 dev_dbg(dev, "Firmware v%u dump:\n", firm->firmware_version); 1777 dev_dbg(dev, "Num prefilter scenarios: %u\n", firm->prefil_scen); 1778 dev_dbg(dev, "Num interpolation scenarios: %u\n", firm->interp_scen); 1779 dev_dbg(dev, "\nInterpolation scenarios:\n"); 1780 1781 for (i = 0; i < firm->interp_scen; i++) { 1782 if (interp[i].magic != FIRMWARE_MAGIC) { 1783 dev_dbg(dev, "%d. wrong interp magic: %x\n", 1784 i, interp[i].magic); 1785 continue; 1786 } 1787 dev_dbg(dev, "%d. taps: %u, phases: %u, center: %llu\n", i, 1788 interp[i].num_taps, interp[i].num_phases, 1789 interp[i].center_tap); 1790 } 1791 1792 for (i = 0; i < firm->prefil_scen; i++) { 1793 if (prefil[i].magic != FIRMWARE_MAGIC) { 1794 dev_dbg(dev, "%d. wrong prefil magic: %x\n", 1795 i, prefil[i].magic); 1796 continue; 1797 } 1798 dev_dbg(dev, "%d. insr: %u, outsr: %u, st1: %u, st2: %u\n", i, 1799 prefil[i].insr, prefil[i].outsr, 1800 prefil[i].st1_taps, prefil[i].st2_taps); 1801 } 1802 1803 dev_dbg(dev, "end of firmware dump\n"); 1804 } 1805 #endif 1806 1807 static int fsl_easrc_get_firmware(struct fsl_asrc *easrc) 1808 { 1809 struct fsl_easrc_priv *easrc_priv; 1810 const struct firmware **fw_p; 1811 u32 pnum, inum, offset; 1812 const u8 *data; 1813 int ret; 1814 1815 if (!easrc) 1816 return -EINVAL; 1817 1818 easrc_priv = easrc->private; 1819 fw_p = &easrc_priv->fw; 1820 1821 ret = request_firmware(fw_p, easrc_priv->fw_name, &easrc->pdev->dev); 1822 if (ret) 1823 return ret; 1824 1825 data = easrc_priv->fw->data; 1826 1827 easrc_priv->firmware_hdr = (struct asrc_firmware_hdr *)data; 1828 pnum = easrc_priv->firmware_hdr->prefil_scen; 1829 inum = easrc_priv->firmware_hdr->interp_scen; 1830 1831 if (inum) { 1832 offset = sizeof(struct asrc_firmware_hdr); 1833 easrc_priv->interp = (struct interp_params *)(data + offset); 1834 } 1835 1836 if (pnum) { 1837 offset = sizeof(struct asrc_firmware_hdr) + 1838 inum * sizeof(struct interp_params); 1839 easrc_priv->prefil = (struct prefil_params *)(data + offset); 1840 } 1841 1842 #ifdef DEBUG 1843 fsl_easrc_dump_firmware(easrc); 1844 #endif 1845 1846 return 0; 1847 } 1848 1849 static irqreturn_t fsl_easrc_isr(int irq, void *dev_id) 1850 { 1851 struct fsl_asrc *easrc = (struct fsl_asrc *)dev_id; 1852 struct device *dev = &easrc->pdev->dev; 1853 int val; 1854 1855 regmap_read(easrc->regmap, REG_EASRC_IRQF, &val); 1856 1857 if (val & EASRC_IRQF_OER_MASK) 1858 dev_dbg(dev, "output FIFO underflow\n"); 1859 1860 if (val & EASRC_IRQF_IFO_MASK) 1861 dev_dbg(dev, "input FIFO overflow\n"); 1862 1863 return IRQ_HANDLED; 1864 } 1865 1866 static int fsl_easrc_get_fifo_addr(u8 dir, enum asrc_pair_index index) 1867 { 1868 return REG_EASRC_FIFO(dir, index); 1869 } 1870 1871 static const struct of_device_id fsl_easrc_dt_ids[] = { 1872 { .compatible = "fsl,imx8mn-easrc",}, 1873 {} 1874 }; 1875 MODULE_DEVICE_TABLE(of, fsl_easrc_dt_ids); 1876 1877 static int fsl_easrc_probe(struct platform_device *pdev) 1878 { 1879 struct fsl_easrc_priv *easrc_priv; 1880 struct device *dev = &pdev->dev; 1881 struct fsl_asrc *easrc; 1882 struct resource *res; 1883 struct device_node *np; 1884 void __iomem *regs; 1885 int ret, irq; 1886 1887 easrc = devm_kzalloc(dev, sizeof(*easrc), GFP_KERNEL); 1888 if (!easrc) 1889 return -ENOMEM; 1890 1891 easrc_priv = devm_kzalloc(dev, sizeof(*easrc_priv), GFP_KERNEL); 1892 if (!easrc_priv) 1893 return -ENOMEM; 1894 1895 easrc->pdev = pdev; 1896 easrc->private = easrc_priv; 1897 np = dev->of_node; 1898 1899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1900 regs = devm_ioremap_resource(dev, res); 1901 if (IS_ERR(regs)) { 1902 dev_err(&pdev->dev, "failed ioremap\n"); 1903 return PTR_ERR(regs); 1904 } 1905 1906 easrc->paddr = res->start; 1907 1908 easrc->regmap = devm_regmap_init_mmio_clk(dev, "mem", regs, 1909 &fsl_easrc_regmap_config); 1910 if (IS_ERR(easrc->regmap)) { 1911 dev_err(dev, "failed to init regmap"); 1912 return PTR_ERR(easrc->regmap); 1913 } 1914 1915 irq = platform_get_irq(pdev, 0); 1916 if (irq < 0) { 1917 dev_err(dev, "no irq for node %pOF\n", np); 1918 return irq; 1919 } 1920 1921 ret = devm_request_irq(&pdev->dev, irq, fsl_easrc_isr, 0, 1922 dev_name(dev), easrc); 1923 if (ret) { 1924 dev_err(dev, "failed to claim irq %u: %d\n", irq, ret); 1925 return ret; 1926 } 1927 1928 easrc->mem_clk = devm_clk_get(dev, "mem"); 1929 if (IS_ERR(easrc->mem_clk)) { 1930 dev_err(dev, "failed to get mem clock\n"); 1931 return PTR_ERR(easrc->mem_clk); 1932 } 1933 1934 /* Set default value */ 1935 easrc->channel_avail = 32; 1936 easrc->get_dma_channel = fsl_easrc_get_dma_channel; 1937 easrc->request_pair = fsl_easrc_request_context; 1938 easrc->release_pair = fsl_easrc_release_context; 1939 easrc->get_fifo_addr = fsl_easrc_get_fifo_addr; 1940 easrc->pair_priv_size = sizeof(struct fsl_easrc_ctx_priv); 1941 1942 easrc_priv->rs_num_taps = EASRC_RS_32_TAPS; 1943 easrc_priv->const_coeff = 0x3FF0000000000000; 1944 1945 ret = of_property_read_u32(np, "fsl,asrc-rate", &easrc->asrc_rate); 1946 if (ret) { 1947 dev_err(dev, "failed to asrc rate\n"); 1948 return ret; 1949 } 1950 1951 ret = of_property_read_u32(np, "fsl,asrc-format", &easrc->asrc_format); 1952 if (ret) { 1953 dev_err(dev, "failed to asrc format\n"); 1954 return ret; 1955 } 1956 1957 if (!(FSL_EASRC_FORMATS & (1ULL << easrc->asrc_format))) { 1958 dev_warn(dev, "unsupported format, switching to S24_LE\n"); 1959 easrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1960 } 1961 1962 ret = of_property_read_string(np, "firmware-name", 1963 &easrc_priv->fw_name); 1964 if (ret) { 1965 dev_err(dev, "failed to get firmware name\n"); 1966 return ret; 1967 } 1968 1969 platform_set_drvdata(pdev, easrc); 1970 pm_runtime_enable(dev); 1971 1972 spin_lock_init(&easrc->lock); 1973 1974 regcache_cache_only(easrc->regmap, true); 1975 1976 ret = devm_snd_soc_register_component(dev, &fsl_easrc_component, 1977 &fsl_easrc_dai, 1); 1978 if (ret) { 1979 dev_err(dev, "failed to register ASoC DAI\n"); 1980 return ret; 1981 } 1982 1983 ret = devm_snd_soc_register_component(dev, &fsl_asrc_component, 1984 NULL, 0); 1985 if (ret) { 1986 dev_err(&pdev->dev, "failed to register ASoC platform\n"); 1987 return ret; 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int fsl_easrc_remove(struct platform_device *pdev) 1994 { 1995 pm_runtime_disable(&pdev->dev); 1996 1997 return 0; 1998 } 1999 2000 static __maybe_unused int fsl_easrc_runtime_suspend(struct device *dev) 2001 { 2002 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2003 struct fsl_easrc_priv *easrc_priv = easrc->private; 2004 unsigned long lock_flags; 2005 2006 regcache_cache_only(easrc->regmap, true); 2007 2008 clk_disable_unprepare(easrc->mem_clk); 2009 2010 spin_lock_irqsave(&easrc->lock, lock_flags); 2011 easrc_priv->firmware_loaded = 0; 2012 spin_unlock_irqrestore(&easrc->lock, lock_flags); 2013 2014 return 0; 2015 } 2016 2017 static __maybe_unused int fsl_easrc_runtime_resume(struct device *dev) 2018 { 2019 struct fsl_asrc *easrc = dev_get_drvdata(dev); 2020 struct fsl_easrc_priv *easrc_priv = easrc->private; 2021 struct fsl_easrc_ctx_priv *ctx_priv; 2022 struct fsl_asrc_pair *ctx; 2023 unsigned long lock_flags; 2024 int ret; 2025 int i; 2026 2027 ret = clk_prepare_enable(easrc->mem_clk); 2028 if (ret) 2029 return ret; 2030 2031 regcache_cache_only(easrc->regmap, false); 2032 regcache_mark_dirty(easrc->regmap); 2033 regcache_sync(easrc->regmap); 2034 2035 spin_lock_irqsave(&easrc->lock, lock_flags); 2036 if (easrc_priv->firmware_loaded) { 2037 spin_unlock_irqrestore(&easrc->lock, lock_flags); 2038 goto skip_load; 2039 } 2040 easrc_priv->firmware_loaded = 1; 2041 spin_unlock_irqrestore(&easrc->lock, lock_flags); 2042 2043 ret = fsl_easrc_get_firmware(easrc); 2044 if (ret) { 2045 dev_err(dev, "failed to get firmware\n"); 2046 goto disable_mem_clk; 2047 } 2048 2049 /* 2050 * Write Resampling Coefficients 2051 * The coefficient RAM must be configured prior to beginning of 2052 * any context processing within the ASRC 2053 */ 2054 ret = fsl_easrc_resampler_config(easrc); 2055 if (ret) { 2056 dev_err(dev, "resampler config failed\n"); 2057 goto disable_mem_clk; 2058 } 2059 2060 for (i = ASRC_PAIR_A; i < EASRC_CTX_MAX_NUM; i++) { 2061 ctx = easrc->pair[i]; 2062 if (!ctx) 2063 continue; 2064 2065 ctx_priv = ctx->private; 2066 fsl_easrc_set_rs_ratio(ctx); 2067 ctx_priv->out_missed_sample = ctx_priv->in_filled_sample * 2068 ctx_priv->out_params.sample_rate / 2069 ctx_priv->in_params.sample_rate; 2070 if (ctx_priv->in_filled_sample * ctx_priv->out_params.sample_rate 2071 % ctx_priv->in_params.sample_rate != 0) 2072 ctx_priv->out_missed_sample += 1; 2073 2074 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, 2075 ctx_priv->st1_coeff, 2076 ctx_priv->st1_num_taps, 2077 ctx_priv->st1_addexp); 2078 if (ret) 2079 goto disable_mem_clk; 2080 2081 ret = fsl_easrc_write_pf_coeff_mem(easrc, i, 2082 ctx_priv->st2_coeff, 2083 ctx_priv->st2_num_taps, 2084 ctx_priv->st2_addexp); 2085 if (ret) 2086 goto disable_mem_clk; 2087 } 2088 2089 skip_load: 2090 return 0; 2091 2092 disable_mem_clk: 2093 clk_disable_unprepare(easrc->mem_clk); 2094 return ret; 2095 } 2096 2097 static const struct dev_pm_ops fsl_easrc_pm_ops = { 2098 SET_RUNTIME_PM_OPS(fsl_easrc_runtime_suspend, 2099 fsl_easrc_runtime_resume, 2100 NULL) 2101 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2102 pm_runtime_force_resume) 2103 }; 2104 2105 static struct platform_driver fsl_easrc_driver = { 2106 .probe = fsl_easrc_probe, 2107 .remove = fsl_easrc_remove, 2108 .driver = { 2109 .name = "fsl-easrc", 2110 .pm = &fsl_easrc_pm_ops, 2111 .of_match_table = fsl_easrc_dt_ids, 2112 }, 2113 }; 2114 module_platform_driver(fsl_easrc_driver); 2115 2116 MODULE_DESCRIPTION("NXP Enhanced Asynchronous Sample Rate (eASRC) driver"); 2117 MODULE_LICENSE("GPL v2"); 2118