xref: /openbmc/linux/sound/soc/fsl/fsl_audmix.c (revision fb8d6c8d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver
4  *
5  * Copyright 2017 NXP
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/module.h>
10 #include <linux/of_platform.h>
11 #include <linux/pm_runtime.h>
12 #include <sound/soc.h>
13 #include <sound/pcm_params.h>
14 
15 #include "fsl_audmix.h"
16 
17 #define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \
18 	SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts)
19 
20 static const char
21 	*tdm_sel[] = { "TDM1", "TDM2", },
22 	*mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", },
23 	*width_sel[] = { "16b", "18b", "20b", "24b", "32b", },
24 	*endis_sel[] = { "Disabled", "Enabled", },
25 	*updn_sel[] = { "Downward", "Upward", },
26 	*mask_sel[] = { "Unmask", "Mask", };
27 
28 static const struct soc_enum fsl_audmix_enum[] = {
29 /* FSL_AUDMIX_CTR enums */
30 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel),
31 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel),
32 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel),
33 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel),
34 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel),
35 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel),
36 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel),
37 /* FSL_AUDMIX_ATCR0 enums */
38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel),
39 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel),
40 /* FSL_AUDMIX_ATCR1 enums */
41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel),
42 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel),
43 };
44 
45 struct fsl_audmix_state {
46 	u8 tdms;
47 	u8 clk;
48 	char msg[64];
49 };
50 
51 static const struct fsl_audmix_state prms[4][4] = {{
52 	/* DIS->DIS, do nothing */
53 	{ .tdms = 0, .clk = 0, .msg = "" },
54 	/* DIS->TDM1*/
55 	{ .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" },
56 	/* DIS->TDM2*/
57 	{ .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" },
58 	/* DIS->MIX */
59 	{ .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" }
60 }, {	/* TDM1->DIS */
61 	{ .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" },
62 	/* TDM1->TDM1, do nothing */
63 	{ .tdms = 0, .clk = 0, .msg = "" },
64 	/* TDM1->TDM2 */
65 	{ .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" },
66 	/* TDM1->MIX */
67 	{ .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" }
68 }, {	/* TDM2->DIS */
69 	{ .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" },
70 	/* TDM2->TDM1 */
71 	{ .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" },
72 	/* TDM2->TDM2, do nothing */
73 	{ .tdms = 0, .clk = 0, .msg = "" },
74 	/* TDM2->MIX */
75 	{ .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" }
76 }, {	/* MIX->DIS */
77 	{ .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" },
78 	/* MIX->TDM1 */
79 	{ .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" },
80 	/* MIX->TDM2 */
81 	{ .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" },
82 	/* MIX->MIX, do nothing */
83 	{ .tdms = 0, .clk = 0, .msg = "" }
84 }, };
85 
86 static int fsl_audmix_state_trans(struct snd_soc_component *comp,
87 				  unsigned int *mask, unsigned int *ctr,
88 				  const struct fsl_audmix_state prm)
89 {
90 	struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
91 	/* Enforce all required TDMs are started */
92 	if ((priv->tdms & prm.tdms) != prm.tdms) {
93 		dev_dbg(comp->dev, "%s", prm.msg);
94 		return -EINVAL;
95 	}
96 
97 	switch (prm.clk) {
98 	case 1:
99 	case 2:
100 		/* Set mix clock */
101 		(*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK;
102 		(*ctr)  |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1);
103 		break;
104 	default:
105 		break;
106 	}
107 
108 	return 0;
109 }
110 
111 static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol,
112 				      struct snd_ctl_elem_value *ucontrol)
113 {
114 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
115 	struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
116 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
117 	unsigned int *item = ucontrol->value.enumerated.item;
118 	unsigned int reg_val, val, mix_clk;
119 	int ret = 0;
120 
121 	/* Get current state */
122 	ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, &reg_val);
123 	if (ret)
124 		return ret;
125 
126 	mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
127 			>> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
128 	val = snd_soc_enum_item_to_val(e, item[0]);
129 
130 	dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
131 
132 	/**
133 	 * Ensure the current selected mixer clock is available
134 	 * for configuration propagation
135 	 */
136 	if (!(priv->tdms & BIT(mix_clk))) {
137 		dev_err(comp->dev,
138 			"Started TDM%d needed for config propagation!\n",
139 			mix_clk + 1);
140 		return -EINVAL;
141 	}
142 
143 	if (!(priv->tdms & BIT(val))) {
144 		dev_err(comp->dev,
145 			"The selected clock source has no TDM%d enabled!\n",
146 			val + 1);
147 		return -EINVAL;
148 	}
149 
150 	return snd_soc_put_enum_double(kcontrol, ucontrol);
151 }
152 
153 static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol,
154 				  struct snd_ctl_elem_value *ucontrol)
155 {
156 	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
157 	struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp);
158 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
159 	unsigned int *item = ucontrol->value.enumerated.item;
160 	u32 out_src, mix_clk;
161 	unsigned int reg_val, val, mask = 0, ctr = 0;
162 	int ret = 0;
163 
164 	/* Get current state */
165 	ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, &reg_val);
166 	if (ret)
167 		return ret;
168 
169 	/* "From" state */
170 	out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK)
171 			>> FSL_AUDMIX_CTR_OUTSRC_SHIFT);
172 	mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK)
173 			>> FSL_AUDMIX_CTR_MIXCLK_SHIFT);
174 
175 	/* "To" state */
176 	val = snd_soc_enum_item_to_val(e, item[0]);
177 
178 	dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val);
179 
180 	/* Check if state is changing ... */
181 	if (out_src == val)
182 		return 0;
183 	/**
184 	 * Ensure the current selected mixer clock is available
185 	 * for configuration propagation
186 	 */
187 	if (!(priv->tdms & BIT(mix_clk))) {
188 		dev_err(comp->dev,
189 			"Started TDM%d needed for config propagation!\n",
190 			mix_clk + 1);
191 		return -EINVAL;
192 	}
193 
194 	/* Check state transition constraints */
195 	ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]);
196 	if (ret)
197 		return ret;
198 
199 	/* Complete transition to new state */
200 	mask |= FSL_AUDMIX_CTR_OUTSRC_MASK;
201 	ctr  |= FSL_AUDMIX_CTR_OUTSRC(val);
202 
203 	return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
204 }
205 
206 static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = {
207 	/* FSL_AUDMIX_CTR controls */
208 	SOC_ENUM_EXT("Mixing Clock Source", fsl_audmix_enum[0],
209 		     snd_soc_get_enum_double, fsl_audmix_put_mix_clk_src),
210 	SOC_ENUM_EXT("Output Source", fsl_audmix_enum[1],
211 		     snd_soc_get_enum_double, fsl_audmix_put_out_src),
212 	SOC_ENUM("Output Width", fsl_audmix_enum[2]),
213 	SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]),
214 	SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]),
215 	SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]),
216 	SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]),
217 	/* TDM1 Attenuation controls */
218 	SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]),
219 	SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]),
220 	SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0,
221 		   2, 0x00fff, 0),
222 	SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0,
223 		   0, 0x3ffff, 0),
224 	SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0,
225 		   0, 0x3ffff, 0),
226 	SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0,
227 		   0, 0x3ffff, 0),
228 	SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0,
229 		   0, 0x3ffff, 0),
230 	/* TDM2 Attenuation controls */
231 	SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]),
232 	SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]),
233 	SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1,
234 		   2, 0x00fff, 0),
235 	SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1,
236 		   0, 0x3ffff, 0),
237 	SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1,
238 		   0, 0x3ffff, 0),
239 	SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1,
240 		   0, 0x3ffff, 0),
241 	SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1,
242 		   0, 0x3ffff, 0),
243 };
244 
245 static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
246 {
247 	struct snd_soc_component *comp = dai->component;
248 	u32 mask = 0, ctr = 0;
249 
250 	/* AUDMIX is working in DSP_A format only */
251 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
252 	case SND_SOC_DAIFMT_DSP_A:
253 		break;
254 	default:
255 		return -EINVAL;
256 	}
257 
258 	/* For playback the AUDMIX is slave, and for record is master */
259 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
260 	case SND_SOC_DAIFMT_CBM_CFM:
261 	case SND_SOC_DAIFMT_CBS_CFS:
262 		break;
263 	default:
264 		return -EINVAL;
265 	}
266 
267 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
268 	case SND_SOC_DAIFMT_IB_NF:
269 		/* Output data will be written on positive edge of the clock */
270 		ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0);
271 		break;
272 	case SND_SOC_DAIFMT_NB_NF:
273 		/* Output data will be written on negative edge of the clock */
274 		ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1);
275 		break;
276 	default:
277 		return -EINVAL;
278 	}
279 
280 	mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK;
281 
282 	return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr);
283 }
284 
285 static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd,
286 				  struct snd_soc_dai *dai)
287 {
288 	struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai);
289 
290 	/* Capture stream shall not be handled */
291 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
292 		return 0;
293 
294 	switch (cmd) {
295 	case SNDRV_PCM_TRIGGER_START:
296 	case SNDRV_PCM_TRIGGER_RESUME:
297 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
298 		priv->tdms |= BIT(dai->driver->id);
299 		break;
300 	case SNDRV_PCM_TRIGGER_STOP:
301 	case SNDRV_PCM_TRIGGER_SUSPEND:
302 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
303 		priv->tdms &= ~BIT(dai->driver->id);
304 		break;
305 	default:
306 		return -EINVAL;
307 	}
308 
309 	return 0;
310 }
311 
312 static const struct snd_soc_dai_ops fsl_audmix_dai_ops = {
313 	.set_fmt      = fsl_audmix_dai_set_fmt,
314 	.trigger      = fsl_audmix_dai_trigger,
315 };
316 
317 static struct snd_soc_dai_driver fsl_audmix_dai[] = {
318 	{
319 		.id   = 0,
320 		.name = "audmix-0",
321 		.playback = {
322 			.stream_name = "AUDMIX-Playback-0",
323 			.channels_min = 8,
324 			.channels_max = 8,
325 			.rate_min = 8000,
326 			.rate_max = 96000,
327 			.rates = SNDRV_PCM_RATE_8000_96000,
328 			.formats = FSL_AUDMIX_FORMATS,
329 		},
330 		.capture = {
331 			.stream_name = "AUDMIX-Capture-0",
332 			.channels_min = 8,
333 			.channels_max = 8,
334 			.rate_min = 8000,
335 			.rate_max = 96000,
336 			.rates = SNDRV_PCM_RATE_8000_96000,
337 			.formats = FSL_AUDMIX_FORMATS,
338 		},
339 		.ops = &fsl_audmix_dai_ops,
340 	},
341 	{
342 		.id   = 1,
343 		.name = "audmix-1",
344 		.playback = {
345 			.stream_name = "AUDMIX-Playback-1",
346 			.channels_min = 8,
347 			.channels_max = 8,
348 			.rate_min = 8000,
349 			.rate_max = 96000,
350 			.rates = SNDRV_PCM_RATE_8000_96000,
351 			.formats = FSL_AUDMIX_FORMATS,
352 		},
353 		.capture = {
354 			.stream_name = "AUDMIX-Capture-1",
355 			.channels_min = 8,
356 			.channels_max = 8,
357 			.rate_min = 8000,
358 			.rate_max = 96000,
359 			.rates = SNDRV_PCM_RATE_8000_96000,
360 			.formats = FSL_AUDMIX_FORMATS,
361 		},
362 		.ops = &fsl_audmix_dai_ops,
363 	},
364 };
365 
366 static const struct snd_soc_component_driver fsl_audmix_component = {
367 	.name		  = "fsl-audmix-dai",
368 	.controls	  = fsl_audmix_snd_controls,
369 	.num_controls	  = ARRAY_SIZE(fsl_audmix_snd_controls),
370 };
371 
372 static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg)
373 {
374 	switch (reg) {
375 	case FSL_AUDMIX_CTR:
376 	case FSL_AUDMIX_STR:
377 	case FSL_AUDMIX_ATCR0:
378 	case FSL_AUDMIX_ATIVAL0:
379 	case FSL_AUDMIX_ATSTPUP0:
380 	case FSL_AUDMIX_ATSTPDN0:
381 	case FSL_AUDMIX_ATSTPTGT0:
382 	case FSL_AUDMIX_ATTNVAL0:
383 	case FSL_AUDMIX_ATSTP0:
384 	case FSL_AUDMIX_ATCR1:
385 	case FSL_AUDMIX_ATIVAL1:
386 	case FSL_AUDMIX_ATSTPUP1:
387 	case FSL_AUDMIX_ATSTPDN1:
388 	case FSL_AUDMIX_ATSTPTGT1:
389 	case FSL_AUDMIX_ATTNVAL1:
390 	case FSL_AUDMIX_ATSTP1:
391 		return true;
392 	default:
393 		return false;
394 	}
395 }
396 
397 static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg)
398 {
399 	switch (reg) {
400 	case FSL_AUDMIX_CTR:
401 	case FSL_AUDMIX_ATCR0:
402 	case FSL_AUDMIX_ATIVAL0:
403 	case FSL_AUDMIX_ATSTPUP0:
404 	case FSL_AUDMIX_ATSTPDN0:
405 	case FSL_AUDMIX_ATSTPTGT0:
406 	case FSL_AUDMIX_ATCR1:
407 	case FSL_AUDMIX_ATIVAL1:
408 	case FSL_AUDMIX_ATSTPUP1:
409 	case FSL_AUDMIX_ATSTPDN1:
410 	case FSL_AUDMIX_ATSTPTGT1:
411 		return true;
412 	default:
413 		return false;
414 	}
415 }
416 
417 static const struct reg_default fsl_audmix_reg[] = {
418 	{ FSL_AUDMIX_CTR,       0x00060 },
419 	{ FSL_AUDMIX_STR,       0x00003 },
420 	{ FSL_AUDMIX_ATCR0,     0x00000 },
421 	{ FSL_AUDMIX_ATIVAL0,   0x3FFFF },
422 	{ FSL_AUDMIX_ATSTPUP0,  0x2AAAA },
423 	{ FSL_AUDMIX_ATSTPDN0,  0x30000 },
424 	{ FSL_AUDMIX_ATSTPTGT0, 0x00010 },
425 	{ FSL_AUDMIX_ATTNVAL0,  0x00000 },
426 	{ FSL_AUDMIX_ATSTP0,    0x00000 },
427 	{ FSL_AUDMIX_ATCR1,     0x00000 },
428 	{ FSL_AUDMIX_ATIVAL1,   0x3FFFF },
429 	{ FSL_AUDMIX_ATSTPUP1,  0x2AAAA },
430 	{ FSL_AUDMIX_ATSTPDN1,  0x30000 },
431 	{ FSL_AUDMIX_ATSTPTGT1, 0x00010 },
432 	{ FSL_AUDMIX_ATTNVAL1,  0x00000 },
433 	{ FSL_AUDMIX_ATSTP1,    0x00000 },
434 };
435 
436 static const struct regmap_config fsl_audmix_regmap_config = {
437 	.reg_bits = 32,
438 	.reg_stride = 4,
439 	.val_bits = 32,
440 	.max_register = FSL_AUDMIX_ATSTP1,
441 	.reg_defaults = fsl_audmix_reg,
442 	.num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg),
443 	.readable_reg = fsl_audmix_readable_reg,
444 	.writeable_reg = fsl_audmix_writeable_reg,
445 	.cache_type = REGCACHE_FLAT,
446 };
447 
448 static const struct of_device_id fsl_audmix_ids[] = {
449 	{
450 		.compatible = "fsl,imx8qm-audmix",
451 		.data = "imx-audmix",
452 	},
453 	{ /* sentinel */ }
454 };
455 MODULE_DEVICE_TABLE(of, fsl_audmix_ids);
456 
457 static int fsl_audmix_probe(struct platform_device *pdev)
458 {
459 	struct device *dev = &pdev->dev;
460 	struct fsl_audmix *priv;
461 	const char *mdrv;
462 	const struct of_device_id *of_id;
463 	void __iomem *regs;
464 	int ret;
465 
466 	of_id = of_match_device(fsl_audmix_ids, dev);
467 	if (!of_id || !of_id->data)
468 		return -EINVAL;
469 
470 	mdrv = of_id->data;
471 
472 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
473 	if (!priv)
474 		return -ENOMEM;
475 
476 	/* Get the addresses */
477 	regs = devm_platform_ioremap_resource(pdev, 0);
478 	if (IS_ERR(regs))
479 		return PTR_ERR(regs);
480 
481 	priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs,
482 						 &fsl_audmix_regmap_config);
483 	if (IS_ERR(priv->regmap)) {
484 		dev_err(dev, "failed to init regmap\n");
485 		return PTR_ERR(priv->regmap);
486 	}
487 
488 	priv->ipg_clk = devm_clk_get(dev, "ipg");
489 	if (IS_ERR(priv->ipg_clk)) {
490 		dev_err(dev, "failed to get ipg clock\n");
491 		return PTR_ERR(priv->ipg_clk);
492 	}
493 
494 	platform_set_drvdata(pdev, priv);
495 	pm_runtime_enable(dev);
496 
497 	ret = devm_snd_soc_register_component(dev, &fsl_audmix_component,
498 					      fsl_audmix_dai,
499 					      ARRAY_SIZE(fsl_audmix_dai));
500 	if (ret) {
501 		dev_err(dev, "failed to register ASoC DAI\n");
502 		return ret;
503 	}
504 
505 	priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0);
506 	if (IS_ERR(priv->pdev)) {
507 		ret = PTR_ERR(priv->pdev);
508 		dev_err(dev, "failed to register platform %s: %d\n", mdrv, ret);
509 	}
510 
511 	return ret;
512 }
513 
514 static int fsl_audmix_remove(struct platform_device *pdev)
515 {
516 	struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev);
517 
518 	if (priv->pdev)
519 		platform_device_unregister(priv->pdev);
520 
521 	return 0;
522 }
523 
524 #ifdef CONFIG_PM
525 static int fsl_audmix_runtime_resume(struct device *dev)
526 {
527 	struct fsl_audmix *priv = dev_get_drvdata(dev);
528 	int ret;
529 
530 	ret = clk_prepare_enable(priv->ipg_clk);
531 	if (ret) {
532 		dev_err(dev, "Failed to enable IPG clock: %d\n", ret);
533 		return ret;
534 	}
535 
536 	regcache_cache_only(priv->regmap, false);
537 	regcache_mark_dirty(priv->regmap);
538 
539 	return regcache_sync(priv->regmap);
540 }
541 
542 static int fsl_audmix_runtime_suspend(struct device *dev)
543 {
544 	struct fsl_audmix *priv = dev_get_drvdata(dev);
545 
546 	regcache_cache_only(priv->regmap, true);
547 
548 	clk_disable_unprepare(priv->ipg_clk);
549 
550 	return 0;
551 }
552 #endif /* CONFIG_PM */
553 
554 static const struct dev_pm_ops fsl_audmix_pm = {
555 	SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend,
556 			   fsl_audmix_runtime_resume,
557 			   NULL)
558 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
559 				pm_runtime_force_resume)
560 };
561 
562 static struct platform_driver fsl_audmix_driver = {
563 	.probe = fsl_audmix_probe,
564 	.remove = fsl_audmix_remove,
565 	.driver = {
566 		.name = "fsl-audmix",
567 		.of_match_table = fsl_audmix_ids,
568 		.pm = &fsl_audmix_pm,
569 	},
570 };
571 module_platform_driver(fsl_audmix_driver);
572 
573 MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver");
574 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>");
575 MODULE_ALIAS("platform:fsl-audmix");
576 MODULE_LICENSE("GPL v2");
577