1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP AUDMIX ALSA SoC Digital Audio Interface (DAI) driver 4 * 5 * Copyright 2017 NXP 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/pm_runtime.h> 12 #include <sound/soc.h> 13 #include <sound/pcm_params.h> 14 15 #include "fsl_audmix.h" 16 17 #define SOC_ENUM_SINGLE_S(xreg, xshift, xtexts) \ 18 SOC_ENUM_SINGLE(xreg, xshift, ARRAY_SIZE(xtexts), xtexts) 19 20 static const char 21 *tdm_sel[] = { "TDM1", "TDM2", }, 22 *mode_sel[] = { "Disabled", "TDM1", "TDM2", "Mixed", }, 23 *width_sel[] = { "16b", "18b", "20b", "24b", "32b", }, 24 *endis_sel[] = { "Disabled", "Enabled", }, 25 *updn_sel[] = { "Downward", "Upward", }, 26 *mask_sel[] = { "Unmask", "Mask", }; 27 28 static const struct soc_enum fsl_audmix_enum[] = { 29 /* FSL_AUDMIX_CTR enums */ 30 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MIXCLK_SHIFT, tdm_sel), 31 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTSRC_SHIFT, mode_sel), 32 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_OUTWIDTH_SHIFT, width_sel), 33 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKRTDF_SHIFT, mask_sel), 34 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_MASKCKDF_SHIFT, mask_sel), 35 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCMODE_SHIFT, endis_sel), 36 SOC_ENUM_SINGLE_S(FSL_AUDMIX_CTR, FSL_AUDMIX_CTR_SYNCSRC_SHIFT, tdm_sel), 37 /* FSL_AUDMIX_ATCR0 enums */ 38 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 0, endis_sel), 39 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR0, 1, updn_sel), 40 /* FSL_AUDMIX_ATCR1 enums */ 41 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 0, endis_sel), 42 SOC_ENUM_SINGLE_S(FSL_AUDMIX_ATCR1, 1, updn_sel), 43 }; 44 45 struct fsl_audmix_state { 46 u8 tdms; 47 u8 clk; 48 char msg[64]; 49 }; 50 51 static const struct fsl_audmix_state prms[4][4] = {{ 52 /* DIS->DIS, do nothing */ 53 { .tdms = 0, .clk = 0, .msg = "" }, 54 /* DIS->TDM1*/ 55 { .tdms = 1, .clk = 1, .msg = "DIS->TDM1: TDM1 not started!\n" }, 56 /* DIS->TDM2*/ 57 { .tdms = 2, .clk = 2, .msg = "DIS->TDM2: TDM2 not started!\n" }, 58 /* DIS->MIX */ 59 { .tdms = 3, .clk = 0, .msg = "DIS->MIX: Please start both TDMs!\n" } 60 }, { /* TDM1->DIS */ 61 { .tdms = 1, .clk = 0, .msg = "TDM1->DIS: TDM1 not started!\n" }, 62 /* TDM1->TDM1, do nothing */ 63 { .tdms = 0, .clk = 0, .msg = "" }, 64 /* TDM1->TDM2 */ 65 { .tdms = 3, .clk = 2, .msg = "TDM1->TDM2: Please start both TDMs!\n" }, 66 /* TDM1->MIX */ 67 { .tdms = 3, .clk = 0, .msg = "TDM1->MIX: Please start both TDMs!\n" } 68 }, { /* TDM2->DIS */ 69 { .tdms = 2, .clk = 0, .msg = "TDM2->DIS: TDM2 not started!\n" }, 70 /* TDM2->TDM1 */ 71 { .tdms = 3, .clk = 1, .msg = "TDM2->TDM1: Please start both TDMs!\n" }, 72 /* TDM2->TDM2, do nothing */ 73 { .tdms = 0, .clk = 0, .msg = "" }, 74 /* TDM2->MIX */ 75 { .tdms = 3, .clk = 0, .msg = "TDM2->MIX: Please start both TDMs!\n" } 76 }, { /* MIX->DIS */ 77 { .tdms = 3, .clk = 0, .msg = "MIX->DIS: Please start both TDMs!\n" }, 78 /* MIX->TDM1 */ 79 { .tdms = 3, .clk = 1, .msg = "MIX->TDM1: Please start both TDMs!\n" }, 80 /* MIX->TDM2 */ 81 { .tdms = 3, .clk = 2, .msg = "MIX->TDM2: Please start both TDMs!\n" }, 82 /* MIX->MIX, do nothing */ 83 { .tdms = 0, .clk = 0, .msg = "" } 84 }, }; 85 86 static int fsl_audmix_state_trans(struct snd_soc_component *comp, 87 unsigned int *mask, unsigned int *ctr, 88 const struct fsl_audmix_state prm) 89 { 90 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp); 91 /* Enforce all required TDMs are started */ 92 if ((priv->tdms & prm.tdms) != prm.tdms) { 93 dev_dbg(comp->dev, "%s", prm.msg); 94 return -EINVAL; 95 } 96 97 switch (prm.clk) { 98 case 1: 99 case 2: 100 /* Set mix clock */ 101 (*mask) |= FSL_AUDMIX_CTR_MIXCLK_MASK; 102 (*ctr) |= FSL_AUDMIX_CTR_MIXCLK(prm.clk - 1); 103 break; 104 default: 105 break; 106 } 107 108 return 0; 109 } 110 111 static int fsl_audmix_put_mix_clk_src(struct snd_kcontrol *kcontrol, 112 struct snd_ctl_elem_value *ucontrol) 113 { 114 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 115 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp); 116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 117 unsigned int *item = ucontrol->value.enumerated.item; 118 unsigned int reg_val, val, mix_clk; 119 int ret = 0; 120 121 /* Get current state */ 122 ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, ®_val); 123 if (ret) 124 return ret; 125 126 mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK) 127 >> FSL_AUDMIX_CTR_MIXCLK_SHIFT); 128 val = snd_soc_enum_item_to_val(e, item[0]); 129 130 dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val); 131 132 /** 133 * Ensure the current selected mixer clock is available 134 * for configuration propagation 135 */ 136 if (!(priv->tdms & BIT(mix_clk))) { 137 dev_err(comp->dev, 138 "Started TDM%d needed for config propagation!\n", 139 mix_clk + 1); 140 return -EINVAL; 141 } 142 143 if (!(priv->tdms & BIT(val))) { 144 dev_err(comp->dev, 145 "The selected clock source has no TDM%d enabled!\n", 146 val + 1); 147 return -EINVAL; 148 } 149 150 return snd_soc_put_enum_double(kcontrol, ucontrol); 151 } 152 153 static int fsl_audmix_put_out_src(struct snd_kcontrol *kcontrol, 154 struct snd_ctl_elem_value *ucontrol) 155 { 156 struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol); 157 struct fsl_audmix *priv = snd_soc_component_get_drvdata(comp); 158 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 159 unsigned int *item = ucontrol->value.enumerated.item; 160 u32 out_src, mix_clk; 161 unsigned int reg_val, val, mask = 0, ctr = 0; 162 int ret = 0; 163 164 /* Get current state */ 165 ret = snd_soc_component_read(comp, FSL_AUDMIX_CTR, ®_val); 166 if (ret) 167 return ret; 168 169 /* "From" state */ 170 out_src = ((reg_val & FSL_AUDMIX_CTR_OUTSRC_MASK) 171 >> FSL_AUDMIX_CTR_OUTSRC_SHIFT); 172 mix_clk = ((reg_val & FSL_AUDMIX_CTR_MIXCLK_MASK) 173 >> FSL_AUDMIX_CTR_MIXCLK_SHIFT); 174 175 /* "To" state */ 176 val = snd_soc_enum_item_to_val(e, item[0]); 177 178 dev_dbg(comp->dev, "TDMs=x%08x, val=x%08x\n", priv->tdms, val); 179 180 /* Check if state is changing ... */ 181 if (out_src == val) 182 return 0; 183 /** 184 * Ensure the current selected mixer clock is available 185 * for configuration propagation 186 */ 187 if (!(priv->tdms & BIT(mix_clk))) { 188 dev_err(comp->dev, 189 "Started TDM%d needed for config propagation!\n", 190 mix_clk + 1); 191 return -EINVAL; 192 } 193 194 /* Check state transition constraints */ 195 ret = fsl_audmix_state_trans(comp, &mask, &ctr, prms[out_src][val]); 196 if (ret) 197 return ret; 198 199 /* Complete transition to new state */ 200 mask |= FSL_AUDMIX_CTR_OUTSRC_MASK; 201 ctr |= FSL_AUDMIX_CTR_OUTSRC(val); 202 203 return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); 204 } 205 206 static const struct snd_kcontrol_new fsl_audmix_snd_controls[] = { 207 /* FSL_AUDMIX_CTR controls */ 208 SOC_ENUM_EXT("Mixing Clock Source", fsl_audmix_enum[0], 209 snd_soc_get_enum_double, fsl_audmix_put_mix_clk_src), 210 SOC_ENUM_EXT("Output Source", fsl_audmix_enum[1], 211 snd_soc_get_enum_double, fsl_audmix_put_out_src), 212 SOC_ENUM("Output Width", fsl_audmix_enum[2]), 213 SOC_ENUM("Frame Rate Diff Error", fsl_audmix_enum[3]), 214 SOC_ENUM("Clock Freq Diff Error", fsl_audmix_enum[4]), 215 SOC_ENUM("Sync Mode Config", fsl_audmix_enum[5]), 216 SOC_ENUM("Sync Mode Clk Source", fsl_audmix_enum[6]), 217 /* TDM1 Attenuation controls */ 218 SOC_ENUM("TDM1 Attenuation", fsl_audmix_enum[7]), 219 SOC_ENUM("TDM1 Attenuation Direction", fsl_audmix_enum[8]), 220 SOC_SINGLE("TDM1 Attenuation Step Divider", FSL_AUDMIX_ATCR0, 221 2, 0x00fff, 0), 222 SOC_SINGLE("TDM1 Attenuation Initial Value", FSL_AUDMIX_ATIVAL0, 223 0, 0x3ffff, 0), 224 SOC_SINGLE("TDM1 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP0, 225 0, 0x3ffff, 0), 226 SOC_SINGLE("TDM1 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN0, 227 0, 0x3ffff, 0), 228 SOC_SINGLE("TDM1 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT0, 229 0, 0x3ffff, 0), 230 /* TDM2 Attenuation controls */ 231 SOC_ENUM("TDM2 Attenuation", fsl_audmix_enum[9]), 232 SOC_ENUM("TDM2 Attenuation Direction", fsl_audmix_enum[10]), 233 SOC_SINGLE("TDM2 Attenuation Step Divider", FSL_AUDMIX_ATCR1, 234 2, 0x00fff, 0), 235 SOC_SINGLE("TDM2 Attenuation Initial Value", FSL_AUDMIX_ATIVAL1, 236 0, 0x3ffff, 0), 237 SOC_SINGLE("TDM2 Attenuation Step Up Factor", FSL_AUDMIX_ATSTPUP1, 238 0, 0x3ffff, 0), 239 SOC_SINGLE("TDM2 Attenuation Step Down Factor", FSL_AUDMIX_ATSTPDN1, 240 0, 0x3ffff, 0), 241 SOC_SINGLE("TDM2 Attenuation Step Target", FSL_AUDMIX_ATSTPTGT1, 242 0, 0x3ffff, 0), 243 }; 244 245 static int fsl_audmix_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 246 { 247 struct snd_soc_component *comp = dai->component; 248 u32 mask = 0, ctr = 0; 249 250 /* AUDMIX is working in DSP_A format only */ 251 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 252 case SND_SOC_DAIFMT_DSP_A: 253 break; 254 default: 255 return -EINVAL; 256 } 257 258 /* For playback the AUDMIX is slave, and for record is master */ 259 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 260 case SND_SOC_DAIFMT_CBM_CFM: 261 case SND_SOC_DAIFMT_CBS_CFS: 262 break; 263 default: 264 return -EINVAL; 265 } 266 267 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 268 case SND_SOC_DAIFMT_IB_NF: 269 /* Output data will be written on positive edge of the clock */ 270 ctr |= FSL_AUDMIX_CTR_OUTCKPOL(0); 271 break; 272 case SND_SOC_DAIFMT_NB_NF: 273 /* Output data will be written on negative edge of the clock */ 274 ctr |= FSL_AUDMIX_CTR_OUTCKPOL(1); 275 break; 276 default: 277 return -EINVAL; 278 } 279 280 mask |= FSL_AUDMIX_CTR_OUTCKPOL_MASK; 281 282 return snd_soc_component_update_bits(comp, FSL_AUDMIX_CTR, mask, ctr); 283 } 284 285 static int fsl_audmix_dai_trigger(struct snd_pcm_substream *substream, int cmd, 286 struct snd_soc_dai *dai) 287 { 288 struct fsl_audmix *priv = snd_soc_dai_get_drvdata(dai); 289 unsigned long lock_flags; 290 291 /* Capture stream shall not be handled */ 292 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 293 return 0; 294 295 switch (cmd) { 296 case SNDRV_PCM_TRIGGER_START: 297 case SNDRV_PCM_TRIGGER_RESUME: 298 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 299 spin_lock_irqsave(&priv->lock, lock_flags); 300 priv->tdms |= BIT(dai->driver->id); 301 spin_unlock_irqrestore(&priv->lock, lock_flags); 302 break; 303 case SNDRV_PCM_TRIGGER_STOP: 304 case SNDRV_PCM_TRIGGER_SUSPEND: 305 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 306 spin_lock_irqsave(&priv->lock, lock_flags); 307 priv->tdms &= ~BIT(dai->driver->id); 308 spin_unlock_irqrestore(&priv->lock, lock_flags); 309 break; 310 default: 311 return -EINVAL; 312 } 313 314 return 0; 315 } 316 317 static const struct snd_soc_dai_ops fsl_audmix_dai_ops = { 318 .set_fmt = fsl_audmix_dai_set_fmt, 319 .trigger = fsl_audmix_dai_trigger, 320 }; 321 322 static struct snd_soc_dai_driver fsl_audmix_dai[] = { 323 { 324 .id = 0, 325 .name = "audmix-0", 326 .playback = { 327 .stream_name = "AUDMIX-Playback-0", 328 .channels_min = 8, 329 .channels_max = 8, 330 .rate_min = 8000, 331 .rate_max = 96000, 332 .rates = SNDRV_PCM_RATE_8000_96000, 333 .formats = FSL_AUDMIX_FORMATS, 334 }, 335 .capture = { 336 .stream_name = "AUDMIX-Capture-0", 337 .channels_min = 8, 338 .channels_max = 8, 339 .rate_min = 8000, 340 .rate_max = 96000, 341 .rates = SNDRV_PCM_RATE_8000_96000, 342 .formats = FSL_AUDMIX_FORMATS, 343 }, 344 .ops = &fsl_audmix_dai_ops, 345 }, 346 { 347 .id = 1, 348 .name = "audmix-1", 349 .playback = { 350 .stream_name = "AUDMIX-Playback-1", 351 .channels_min = 8, 352 .channels_max = 8, 353 .rate_min = 8000, 354 .rate_max = 96000, 355 .rates = SNDRV_PCM_RATE_8000_96000, 356 .formats = FSL_AUDMIX_FORMATS, 357 }, 358 .capture = { 359 .stream_name = "AUDMIX-Capture-1", 360 .channels_min = 8, 361 .channels_max = 8, 362 .rate_min = 8000, 363 .rate_max = 96000, 364 .rates = SNDRV_PCM_RATE_8000_96000, 365 .formats = FSL_AUDMIX_FORMATS, 366 }, 367 .ops = &fsl_audmix_dai_ops, 368 }, 369 }; 370 371 static const struct snd_soc_component_driver fsl_audmix_component = { 372 .name = "fsl-audmix-dai", 373 .controls = fsl_audmix_snd_controls, 374 .num_controls = ARRAY_SIZE(fsl_audmix_snd_controls), 375 }; 376 377 static bool fsl_audmix_readable_reg(struct device *dev, unsigned int reg) 378 { 379 switch (reg) { 380 case FSL_AUDMIX_CTR: 381 case FSL_AUDMIX_STR: 382 case FSL_AUDMIX_ATCR0: 383 case FSL_AUDMIX_ATIVAL0: 384 case FSL_AUDMIX_ATSTPUP0: 385 case FSL_AUDMIX_ATSTPDN0: 386 case FSL_AUDMIX_ATSTPTGT0: 387 case FSL_AUDMIX_ATTNVAL0: 388 case FSL_AUDMIX_ATSTP0: 389 case FSL_AUDMIX_ATCR1: 390 case FSL_AUDMIX_ATIVAL1: 391 case FSL_AUDMIX_ATSTPUP1: 392 case FSL_AUDMIX_ATSTPDN1: 393 case FSL_AUDMIX_ATSTPTGT1: 394 case FSL_AUDMIX_ATTNVAL1: 395 case FSL_AUDMIX_ATSTP1: 396 return true; 397 default: 398 return false; 399 } 400 } 401 402 static bool fsl_audmix_writeable_reg(struct device *dev, unsigned int reg) 403 { 404 switch (reg) { 405 case FSL_AUDMIX_CTR: 406 case FSL_AUDMIX_ATCR0: 407 case FSL_AUDMIX_ATIVAL0: 408 case FSL_AUDMIX_ATSTPUP0: 409 case FSL_AUDMIX_ATSTPDN0: 410 case FSL_AUDMIX_ATSTPTGT0: 411 case FSL_AUDMIX_ATCR1: 412 case FSL_AUDMIX_ATIVAL1: 413 case FSL_AUDMIX_ATSTPUP1: 414 case FSL_AUDMIX_ATSTPDN1: 415 case FSL_AUDMIX_ATSTPTGT1: 416 return true; 417 default: 418 return false; 419 } 420 } 421 422 static const struct reg_default fsl_audmix_reg[] = { 423 { FSL_AUDMIX_CTR, 0x00060 }, 424 { FSL_AUDMIX_STR, 0x00003 }, 425 { FSL_AUDMIX_ATCR0, 0x00000 }, 426 { FSL_AUDMIX_ATIVAL0, 0x3FFFF }, 427 { FSL_AUDMIX_ATSTPUP0, 0x2AAAA }, 428 { FSL_AUDMIX_ATSTPDN0, 0x30000 }, 429 { FSL_AUDMIX_ATSTPTGT0, 0x00010 }, 430 { FSL_AUDMIX_ATTNVAL0, 0x00000 }, 431 { FSL_AUDMIX_ATSTP0, 0x00000 }, 432 { FSL_AUDMIX_ATCR1, 0x00000 }, 433 { FSL_AUDMIX_ATIVAL1, 0x3FFFF }, 434 { FSL_AUDMIX_ATSTPUP1, 0x2AAAA }, 435 { FSL_AUDMIX_ATSTPDN1, 0x30000 }, 436 { FSL_AUDMIX_ATSTPTGT1, 0x00010 }, 437 { FSL_AUDMIX_ATTNVAL1, 0x00000 }, 438 { FSL_AUDMIX_ATSTP1, 0x00000 }, 439 }; 440 441 static const struct regmap_config fsl_audmix_regmap_config = { 442 .reg_bits = 32, 443 .reg_stride = 4, 444 .val_bits = 32, 445 .max_register = FSL_AUDMIX_ATSTP1, 446 .reg_defaults = fsl_audmix_reg, 447 .num_reg_defaults = ARRAY_SIZE(fsl_audmix_reg), 448 .readable_reg = fsl_audmix_readable_reg, 449 .writeable_reg = fsl_audmix_writeable_reg, 450 .cache_type = REGCACHE_FLAT, 451 }; 452 453 static const struct of_device_id fsl_audmix_ids[] = { 454 { 455 .compatible = "fsl,imx8qm-audmix", 456 .data = "imx-audmix", 457 }, 458 { /* sentinel */ } 459 }; 460 MODULE_DEVICE_TABLE(of, fsl_audmix_ids); 461 462 static int fsl_audmix_probe(struct platform_device *pdev) 463 { 464 struct device *dev = &pdev->dev; 465 struct fsl_audmix *priv; 466 const char *mdrv; 467 const struct of_device_id *of_id; 468 void __iomem *regs; 469 int ret; 470 471 of_id = of_match_device(fsl_audmix_ids, dev); 472 if (!of_id || !of_id->data) 473 return -EINVAL; 474 475 mdrv = of_id->data; 476 477 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 478 if (!priv) 479 return -ENOMEM; 480 481 /* Get the addresses */ 482 regs = devm_platform_ioremap_resource(pdev, 0); 483 if (IS_ERR(regs)) 484 return PTR_ERR(regs); 485 486 priv->regmap = devm_regmap_init_mmio_clk(dev, "ipg", regs, 487 &fsl_audmix_regmap_config); 488 if (IS_ERR(priv->regmap)) { 489 dev_err(dev, "failed to init regmap\n"); 490 return PTR_ERR(priv->regmap); 491 } 492 493 priv->ipg_clk = devm_clk_get(dev, "ipg"); 494 if (IS_ERR(priv->ipg_clk)) { 495 dev_err(dev, "failed to get ipg clock\n"); 496 return PTR_ERR(priv->ipg_clk); 497 } 498 499 spin_lock_init(&priv->lock); 500 platform_set_drvdata(pdev, priv); 501 pm_runtime_enable(dev); 502 503 ret = devm_snd_soc_register_component(dev, &fsl_audmix_component, 504 fsl_audmix_dai, 505 ARRAY_SIZE(fsl_audmix_dai)); 506 if (ret) { 507 dev_err(dev, "failed to register ASoC DAI\n"); 508 goto err_disable_pm; 509 } 510 511 priv->pdev = platform_device_register_data(dev, mdrv, 0, NULL, 0); 512 if (IS_ERR(priv->pdev)) { 513 ret = PTR_ERR(priv->pdev); 514 dev_err(dev, "failed to register platform %s: %d\n", mdrv, ret); 515 goto err_disable_pm; 516 } 517 518 return 0; 519 520 err_disable_pm: 521 pm_runtime_disable(dev); 522 return ret; 523 } 524 525 static int fsl_audmix_remove(struct platform_device *pdev) 526 { 527 struct fsl_audmix *priv = dev_get_drvdata(&pdev->dev); 528 529 pm_runtime_disable(&pdev->dev); 530 531 if (priv->pdev) 532 platform_device_unregister(priv->pdev); 533 534 return 0; 535 } 536 537 #ifdef CONFIG_PM 538 static int fsl_audmix_runtime_resume(struct device *dev) 539 { 540 struct fsl_audmix *priv = dev_get_drvdata(dev); 541 int ret; 542 543 ret = clk_prepare_enable(priv->ipg_clk); 544 if (ret) { 545 dev_err(dev, "Failed to enable IPG clock: %d\n", ret); 546 return ret; 547 } 548 549 regcache_cache_only(priv->regmap, false); 550 regcache_mark_dirty(priv->regmap); 551 552 return regcache_sync(priv->regmap); 553 } 554 555 static int fsl_audmix_runtime_suspend(struct device *dev) 556 { 557 struct fsl_audmix *priv = dev_get_drvdata(dev); 558 559 regcache_cache_only(priv->regmap, true); 560 561 clk_disable_unprepare(priv->ipg_clk); 562 563 return 0; 564 } 565 #endif /* CONFIG_PM */ 566 567 static const struct dev_pm_ops fsl_audmix_pm = { 568 SET_RUNTIME_PM_OPS(fsl_audmix_runtime_suspend, 569 fsl_audmix_runtime_resume, 570 NULL) 571 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 572 pm_runtime_force_resume) 573 }; 574 575 static struct platform_driver fsl_audmix_driver = { 576 .probe = fsl_audmix_probe, 577 .remove = fsl_audmix_remove, 578 .driver = { 579 .name = "fsl-audmix", 580 .of_match_table = fsl_audmix_ids, 581 .pm = &fsl_audmix_pm, 582 }, 583 }; 584 module_platform_driver(fsl_audmix_driver); 585 586 MODULE_DESCRIPTION("NXP AUDMIX ASoC DAI driver"); 587 MODULE_AUTHOR("Viorel Suman <viorel.suman@nxp.com>"); 588 MODULE_ALIAS("platform:fsl-audmix"); 589 MODULE_LICENSE("GPL v2"); 590