1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_data/dma-imx.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 23 #define pair_err(fmt, ...) \ 24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 25 26 #define pair_dbg(fmt, ...) \ 27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 28 29 /* Corresponding to process_option */ 30 static unsigned int supported_asrc_rate[] = { 31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 32 64000, 88200, 96000, 128000, 176400, 192000, 33 }; 34 35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 36 .count = ARRAY_SIZE(supported_asrc_rate), 37 .list = supported_asrc_rate, 38 }; 39 40 /** 41 * The following tables map the relationship between asrc_inclk/asrc_outclk in 42 * fsl_asrc.h and the registers of ASRCSR 43 */ 44 static unsigned char input_clk_map_imx35[] = { 45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 46 }; 47 48 static unsigned char output_clk_map_imx35[] = { 49 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 50 }; 51 52 /* i.MX53 uses the same map for input and output */ 53 static unsigned char input_clk_map_imx53[] = { 54 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 55 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 56 }; 57 58 static unsigned char output_clk_map_imx53[] = { 59 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 60 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 61 }; 62 63 static unsigned char *clk_map[2]; 64 65 /** 66 * Select the pre-processing and post-processing options 67 * Make sure to exclude following unsupported cases before 68 * calling this function: 69 * 1) inrate > 8.125 * outrate 70 * 2) inrate > 16.125 * outrate 71 * 72 * inrate: input sample rate 73 * outrate: output sample rate 74 * pre_proc: return value for pre-processing option 75 * post_proc: return value for post-processing option 76 */ 77 static void fsl_asrc_sel_proc(int inrate, int outrate, 78 int *pre_proc, int *post_proc) 79 { 80 bool post_proc_cond2; 81 bool post_proc_cond0; 82 83 /* select pre_proc between [0, 2] */ 84 if (inrate * 8 > 33 * outrate) 85 *pre_proc = 2; 86 else if (inrate * 8 > 15 * outrate) { 87 if (inrate > 152000) 88 *pre_proc = 2; 89 else 90 *pre_proc = 1; 91 } else if (inrate < 76000) 92 *pre_proc = 0; 93 else if (inrate > 152000) 94 *pre_proc = 2; 95 else 96 *pre_proc = 1; 97 98 /* Condition for selection of post-processing */ 99 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 100 (inrate > 56000 && outrate < 56000); 101 post_proc_cond0 = inrate * 23 < outrate * 8; 102 103 if (post_proc_cond2) 104 *post_proc = 2; 105 else if (post_proc_cond0) 106 *post_proc = 0; 107 else 108 *post_proc = 1; 109 } 110 111 /** 112 * Request ASRC pair 113 * 114 * It assigns pair by the order of A->C->B because allocation of pair B, 115 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 116 * while pair A and pair C are comparatively independent. 117 */ 118 int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 119 { 120 enum asrc_pair_index index = ASRC_INVALID_PAIR; 121 struct fsl_asrc *asrc_priv = pair->asrc_priv; 122 struct device *dev = &asrc_priv->pdev->dev; 123 unsigned long lock_flags; 124 int i, ret = 0; 125 126 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 127 128 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 129 if (asrc_priv->pair[i] != NULL) 130 continue; 131 132 index = i; 133 134 if (i != ASRC_PAIR_B) 135 break; 136 } 137 138 if (index == ASRC_INVALID_PAIR) { 139 dev_err(dev, "all pairs are busy now\n"); 140 ret = -EBUSY; 141 } else if (asrc_priv->channel_avail < channels) { 142 dev_err(dev, "can't afford required channels: %d\n", channels); 143 ret = -EINVAL; 144 } else { 145 asrc_priv->channel_avail -= channels; 146 asrc_priv->pair[index] = pair; 147 pair->channels = channels; 148 pair->index = index; 149 } 150 151 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 152 153 return ret; 154 } 155 156 /** 157 * Release ASRC pair 158 * 159 * It clears the resource from asrc_priv and releases the occupied channels. 160 */ 161 void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 162 { 163 struct fsl_asrc *asrc_priv = pair->asrc_priv; 164 enum asrc_pair_index index = pair->index; 165 unsigned long lock_flags; 166 167 /* Make sure the pair is disabled */ 168 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 169 ASRCTR_ASRCEi_MASK(index), 0); 170 171 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 172 173 asrc_priv->channel_avail += pair->channels; 174 asrc_priv->pair[index] = NULL; 175 pair->error = 0; 176 177 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 178 } 179 180 /** 181 * Configure input and output thresholds 182 */ 183 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 184 { 185 struct fsl_asrc *asrc_priv = pair->asrc_priv; 186 enum asrc_pair_index index = pair->index; 187 188 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 189 ASRMCRi_EXTTHRSHi_MASK | 190 ASRMCRi_INFIFO_THRESHOLD_MASK | 191 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 192 ASRMCRi_EXTTHRSHi | 193 ASRMCRi_INFIFO_THRESHOLD(in) | 194 ASRMCRi_OUTFIFO_THRESHOLD(out)); 195 } 196 197 /** 198 * Calculate the total divisor between asrck clock rate and sample rate 199 * 200 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 201 */ 202 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 203 { 204 u32 ps; 205 206 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 207 for (ps = 0; div > 8; ps++) 208 div >>= 1; 209 210 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 211 } 212 213 /** 214 * Calculate and set the ratio for Ideal Ratio mode only 215 * 216 * The ratio is a 32-bit fixed point value with 26 fractional bits. 217 */ 218 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 219 int inrate, int outrate) 220 { 221 struct fsl_asrc *asrc_priv = pair->asrc_priv; 222 enum asrc_pair_index index = pair->index; 223 unsigned long ratio; 224 int i; 225 226 if (!outrate) { 227 pair_err("output rate should not be zero\n"); 228 return -EINVAL; 229 } 230 231 /* Calculate the intergal part of the ratio */ 232 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 233 234 /* ... and then the 26 depth decimal part */ 235 inrate %= outrate; 236 237 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 238 inrate <<= 1; 239 240 if (inrate < outrate) 241 continue; 242 243 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 244 inrate -= outrate; 245 246 if (!inrate) 247 break; 248 } 249 250 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); 251 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); 252 253 return 0; 254 } 255 256 /** 257 * Configure the assigned ASRC pair 258 * 259 * It configures those ASRC registers according to a configuration instance 260 * of struct asrc_config which includes in/output sample rate, width, channel 261 * and clock settings. 262 */ 263 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair) 264 { 265 struct asrc_config *config = pair->config; 266 struct fsl_asrc *asrc_priv = pair->asrc_priv; 267 enum asrc_pair_index index = pair->index; 268 enum asrc_word_width input_word_width; 269 enum asrc_word_width output_word_width; 270 u32 inrate, outrate, indiv, outdiv; 271 u32 clk_index[2], div[2]; 272 int in, out, channels; 273 int pre_proc, post_proc; 274 struct clk *clk; 275 bool ideal; 276 277 if (!config) { 278 pair_err("invalid pair config\n"); 279 return -EINVAL; 280 } 281 282 /* Validate channels */ 283 if (config->channel_num < 1 || config->channel_num > 10) { 284 pair_err("does not support %d channels\n", config->channel_num); 285 return -EINVAL; 286 } 287 288 switch (snd_pcm_format_width(config->input_format)) { 289 case 8: 290 input_word_width = ASRC_WIDTH_8_BIT; 291 break; 292 case 16: 293 input_word_width = ASRC_WIDTH_16_BIT; 294 break; 295 case 24: 296 input_word_width = ASRC_WIDTH_24_BIT; 297 break; 298 default: 299 pair_err("does not support this input format, %d\n", 300 config->input_format); 301 return -EINVAL; 302 } 303 304 switch (snd_pcm_format_width(config->output_format)) { 305 case 16: 306 output_word_width = ASRC_WIDTH_16_BIT; 307 break; 308 case 24: 309 output_word_width = ASRC_WIDTH_24_BIT; 310 break; 311 default: 312 pair_err("does not support this output format, %d\n", 313 config->output_format); 314 return -EINVAL; 315 } 316 317 inrate = config->input_sample_rate; 318 outrate = config->output_sample_rate; 319 ideal = config->inclk == INCLK_NONE; 320 321 /* Validate input and output sample rates */ 322 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 323 if (inrate == supported_asrc_rate[in]) 324 break; 325 326 if (in == ARRAY_SIZE(supported_asrc_rate)) { 327 pair_err("unsupported input sample rate: %dHz\n", inrate); 328 return -EINVAL; 329 } 330 331 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 332 if (outrate == supported_asrc_rate[out]) 333 break; 334 335 if (out == ARRAY_SIZE(supported_asrc_rate)) { 336 pair_err("unsupported output sample rate: %dHz\n", outrate); 337 return -EINVAL; 338 } 339 340 if ((outrate >= 5512 && outrate <= 30000) && 341 (outrate > 24 * inrate || inrate > 8 * outrate)) { 342 pair_err("exceed supported ratio range [1/24, 8] for \ 343 inrate/outrate: %d/%d\n", inrate, outrate); 344 return -EINVAL; 345 } 346 347 /* Validate input and output clock sources */ 348 clk_index[IN] = clk_map[IN][config->inclk]; 349 clk_index[OUT] = clk_map[OUT][config->outclk]; 350 351 /* We only have output clock for ideal ratio mode */ 352 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 353 354 div[IN] = clk_get_rate(clk) / inrate; 355 if (div[IN] == 0) { 356 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 357 inrate, clk_index[ideal ? OUT : IN]); 358 return -EINVAL; 359 } 360 361 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 362 363 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */ 364 if (ideal) 365 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE; 366 else 367 div[OUT] = clk_get_rate(clk) / outrate; 368 369 if (div[OUT] == 0) { 370 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 371 outrate, clk_index[OUT]); 372 return -EINVAL; 373 } 374 375 /* Set the channel number */ 376 channels = config->channel_num; 377 378 if (asrc_priv->channel_bits < 4) 379 channels /= 2; 380 381 /* Update channels for current pair */ 382 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, 383 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), 384 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); 385 386 /* Default setting: Automatic selection for processing mode */ 387 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 388 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 389 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 390 ASRCTR_USRi_MASK(index), 0); 391 392 /* Set the input and output clock sources */ 393 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, 394 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 395 ASRCSR_AICS(index, clk_index[IN]) | 396 ASRCSR_AOCS(index, clk_index[OUT])); 397 398 /* Calculate the input clock divisors */ 399 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 400 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 401 402 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 403 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), 404 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 405 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 406 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 407 408 /* Implement word_width configurations */ 409 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), 410 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 411 ASRMCR1i_OW16(output_word_width) | 412 ASRMCR1i_IWD(input_word_width)); 413 414 /* Enable BUFFER STALL */ 415 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 416 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 417 418 /* Set default thresholds for input and output FIFO */ 419 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 420 ASRC_INPUTFIFO_THRESHOLD); 421 422 /* Configure the following only for Ideal Ratio mode */ 423 if (!ideal) 424 return 0; 425 426 /* Clear ASTSx bit to use Ideal Ratio mode */ 427 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 428 ASRCTR_ATSi_MASK(index), 0); 429 430 /* Enable Ideal Ratio mode */ 431 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 432 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 433 ASRCTR_IDR(index) | ASRCTR_USR(index)); 434 435 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 436 437 /* Apply configurations for pre- and post-processing */ 438 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 439 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 440 ASRCFG_PREMOD(index, pre_proc) | 441 ASRCFG_POSTMOD(index, post_proc)); 442 443 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 444 } 445 446 /** 447 * Start the assigned ASRC pair 448 * 449 * It enables the assigned pair and makes it stopped at the stall level. 450 */ 451 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 452 { 453 struct fsl_asrc *asrc_priv = pair->asrc_priv; 454 enum asrc_pair_index index = pair->index; 455 int reg, retry = 10, i; 456 457 /* Enable the current pair */ 458 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 459 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 460 461 /* Wait for status of initialization */ 462 do { 463 udelay(5); 464 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); 465 reg &= ASRCFG_INIRQi_MASK(index); 466 } while (!reg && --retry); 467 468 /* Make the input fifo to ASRC STALL level */ 469 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); 470 for (i = 0; i < pair->channels * 4; i++) 471 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); 472 473 /* Enable overload interrupt */ 474 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); 475 } 476 477 /** 478 * Stop the assigned ASRC pair 479 */ 480 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 481 { 482 struct fsl_asrc *asrc_priv = pair->asrc_priv; 483 enum asrc_pair_index index = pair->index; 484 485 /* Stop the current pair */ 486 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 487 ASRCTR_ASRCEi_MASK(index), 0); 488 } 489 490 /** 491 * Get DMA channel according to the pair and direction. 492 */ 493 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) 494 { 495 struct fsl_asrc *asrc_priv = pair->asrc_priv; 496 enum asrc_pair_index index = pair->index; 497 char name[4]; 498 499 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 500 501 return dma_request_slave_channel(&asrc_priv->pdev->dev, name); 502 } 503 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); 504 505 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 506 struct snd_soc_dai *dai) 507 { 508 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 509 510 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 511 if (asrc_priv->channel_bits == 3) 512 snd_pcm_hw_constraint_step(substream->runtime, 0, 513 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 514 515 516 return snd_pcm_hw_constraint_list(substream->runtime, 0, 517 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 518 } 519 520 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 521 struct snd_pcm_hw_params *params, 522 struct snd_soc_dai *dai) 523 { 524 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 525 struct snd_pcm_runtime *runtime = substream->runtime; 526 struct fsl_asrc_pair *pair = runtime->private_data; 527 unsigned int channels = params_channels(params); 528 unsigned int rate = params_rate(params); 529 struct asrc_config config; 530 snd_pcm_format_t format; 531 int ret; 532 533 ret = fsl_asrc_request_pair(channels, pair); 534 if (ret) { 535 dev_err(dai->dev, "fail to request asrc pair\n"); 536 return ret; 537 } 538 539 pair->config = &config; 540 541 if (asrc_priv->asrc_width == 16) 542 format = SNDRV_PCM_FORMAT_S16_LE; 543 else 544 format = SNDRV_PCM_FORMAT_S24_LE; 545 546 config.pair = pair->index; 547 config.channel_num = channels; 548 config.inclk = INCLK_NONE; 549 config.outclk = OUTCLK_ASRCK1_CLK; 550 551 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 552 config.input_format = params_format(params); 553 config.output_format = format; 554 config.input_sample_rate = rate; 555 config.output_sample_rate = asrc_priv->asrc_rate; 556 } else { 557 config.input_format = format; 558 config.output_format = params_format(params); 559 config.input_sample_rate = asrc_priv->asrc_rate; 560 config.output_sample_rate = rate; 561 } 562 563 ret = fsl_asrc_config_pair(pair); 564 if (ret) { 565 dev_err(dai->dev, "fail to config asrc pair\n"); 566 return ret; 567 } 568 569 return 0; 570 } 571 572 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 573 struct snd_soc_dai *dai) 574 { 575 struct snd_pcm_runtime *runtime = substream->runtime; 576 struct fsl_asrc_pair *pair = runtime->private_data; 577 578 if (pair) 579 fsl_asrc_release_pair(pair); 580 581 return 0; 582 } 583 584 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 585 struct snd_soc_dai *dai) 586 { 587 struct snd_pcm_runtime *runtime = substream->runtime; 588 struct fsl_asrc_pair *pair = runtime->private_data; 589 590 switch (cmd) { 591 case SNDRV_PCM_TRIGGER_START: 592 case SNDRV_PCM_TRIGGER_RESUME: 593 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 594 fsl_asrc_start_pair(pair); 595 break; 596 case SNDRV_PCM_TRIGGER_STOP: 597 case SNDRV_PCM_TRIGGER_SUSPEND: 598 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 599 fsl_asrc_stop_pair(pair); 600 break; 601 default: 602 return -EINVAL; 603 } 604 605 return 0; 606 } 607 608 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 609 .startup = fsl_asrc_dai_startup, 610 .hw_params = fsl_asrc_dai_hw_params, 611 .hw_free = fsl_asrc_dai_hw_free, 612 .trigger = fsl_asrc_dai_trigger, 613 }; 614 615 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 616 { 617 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 618 619 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, 620 &asrc_priv->dma_params_rx); 621 622 return 0; 623 } 624 625 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 626 SNDRV_PCM_FMTBIT_S16_LE | \ 627 SNDRV_PCM_FMTBIT_S24_3LE) 628 629 static struct snd_soc_dai_driver fsl_asrc_dai = { 630 .probe = fsl_asrc_dai_probe, 631 .playback = { 632 .stream_name = "ASRC-Playback", 633 .channels_min = 1, 634 .channels_max = 10, 635 .rate_min = 5512, 636 .rate_max = 192000, 637 .rates = SNDRV_PCM_RATE_KNOT, 638 .formats = FSL_ASRC_FORMATS | 639 SNDRV_PCM_FMTBIT_S8, 640 }, 641 .capture = { 642 .stream_name = "ASRC-Capture", 643 .channels_min = 1, 644 .channels_max = 10, 645 .rate_min = 5512, 646 .rate_max = 192000, 647 .rates = SNDRV_PCM_RATE_KNOT, 648 .formats = FSL_ASRC_FORMATS, 649 }, 650 .ops = &fsl_asrc_dai_ops, 651 }; 652 653 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 654 { 655 switch (reg) { 656 case REG_ASRCTR: 657 case REG_ASRIER: 658 case REG_ASRCNCR: 659 case REG_ASRCFG: 660 case REG_ASRCSR: 661 case REG_ASRCDR1: 662 case REG_ASRCDR2: 663 case REG_ASRSTR: 664 case REG_ASRPM1: 665 case REG_ASRPM2: 666 case REG_ASRPM3: 667 case REG_ASRPM4: 668 case REG_ASRPM5: 669 case REG_ASRTFR1: 670 case REG_ASRCCR: 671 case REG_ASRDOA: 672 case REG_ASRDOB: 673 case REG_ASRDOC: 674 case REG_ASRIDRHA: 675 case REG_ASRIDRLA: 676 case REG_ASRIDRHB: 677 case REG_ASRIDRLB: 678 case REG_ASRIDRHC: 679 case REG_ASRIDRLC: 680 case REG_ASR76K: 681 case REG_ASR56K: 682 case REG_ASRMCRA: 683 case REG_ASRFSTA: 684 case REG_ASRMCRB: 685 case REG_ASRFSTB: 686 case REG_ASRMCRC: 687 case REG_ASRFSTC: 688 case REG_ASRMCR1A: 689 case REG_ASRMCR1B: 690 case REG_ASRMCR1C: 691 return true; 692 default: 693 return false; 694 } 695 } 696 697 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 698 { 699 switch (reg) { 700 case REG_ASRSTR: 701 case REG_ASRDIA: 702 case REG_ASRDIB: 703 case REG_ASRDIC: 704 case REG_ASRDOA: 705 case REG_ASRDOB: 706 case REG_ASRDOC: 707 case REG_ASRFSTA: 708 case REG_ASRFSTB: 709 case REG_ASRFSTC: 710 case REG_ASRCFG: 711 return true; 712 default: 713 return false; 714 } 715 } 716 717 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 718 { 719 switch (reg) { 720 case REG_ASRCTR: 721 case REG_ASRIER: 722 case REG_ASRCNCR: 723 case REG_ASRCFG: 724 case REG_ASRCSR: 725 case REG_ASRCDR1: 726 case REG_ASRCDR2: 727 case REG_ASRSTR: 728 case REG_ASRPM1: 729 case REG_ASRPM2: 730 case REG_ASRPM3: 731 case REG_ASRPM4: 732 case REG_ASRPM5: 733 case REG_ASRTFR1: 734 case REG_ASRCCR: 735 case REG_ASRDIA: 736 case REG_ASRDIB: 737 case REG_ASRDIC: 738 case REG_ASRIDRHA: 739 case REG_ASRIDRLA: 740 case REG_ASRIDRHB: 741 case REG_ASRIDRLB: 742 case REG_ASRIDRHC: 743 case REG_ASRIDRLC: 744 case REG_ASR76K: 745 case REG_ASR56K: 746 case REG_ASRMCRA: 747 case REG_ASRMCRB: 748 case REG_ASRMCRC: 749 case REG_ASRMCR1A: 750 case REG_ASRMCR1B: 751 case REG_ASRMCR1C: 752 return true; 753 default: 754 return false; 755 } 756 } 757 758 static struct reg_default fsl_asrc_reg[] = { 759 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 760 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 761 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 762 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 763 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 764 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 765 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 766 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 767 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 768 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 769 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 770 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 771 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 772 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 773 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 774 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 775 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 776 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 777 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 778 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 779 { REG_ASRMCR1C, 0x0000 }, 780 }; 781 782 static const struct regmap_config fsl_asrc_regmap_config = { 783 .reg_bits = 32, 784 .reg_stride = 4, 785 .val_bits = 32, 786 787 .max_register = REG_ASRMCR1C, 788 .reg_defaults = fsl_asrc_reg, 789 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 790 .readable_reg = fsl_asrc_readable_reg, 791 .volatile_reg = fsl_asrc_volatile_reg, 792 .writeable_reg = fsl_asrc_writeable_reg, 793 .cache_type = REGCACHE_FLAT, 794 }; 795 796 /** 797 * Initialize ASRC registers with a default configurations 798 */ 799 static int fsl_asrc_init(struct fsl_asrc *asrc_priv) 800 { 801 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 802 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 803 804 /* Disable interrupt by default */ 805 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); 806 807 /* Apply recommended settings for parameters from Reference Manual */ 808 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); 809 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); 810 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); 811 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); 812 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); 813 814 /* Base address for task queue FIFO. Set to 0x7C */ 815 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, 816 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 817 818 /* Set the processing clock for 76KHz to 133M */ 819 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); 820 821 /* Set the processing clock for 56KHz to 133M */ 822 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); 823 } 824 825 /** 826 * Interrupt handler for ASRC 827 */ 828 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 829 { 830 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; 831 struct device *dev = &asrc_priv->pdev->dev; 832 enum asrc_pair_index index; 833 u32 status; 834 835 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); 836 837 /* Clean overload error */ 838 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); 839 840 /* 841 * We here use dev_dbg() for all exceptions because ASRC itself does 842 * not care if FIFO overflowed or underrun while a warning in the 843 * interrupt would result a ridged conversion. 844 */ 845 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 846 if (!asrc_priv->pair[index]) 847 continue; 848 849 if (status & ASRSTR_ATQOL) { 850 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 851 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 852 } 853 854 if (status & ASRSTR_AOOL(index)) { 855 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 856 pair_dbg("Output Task Overload\n"); 857 } 858 859 if (status & ASRSTR_AIOL(index)) { 860 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 861 pair_dbg("Input Task Overload\n"); 862 } 863 864 if (status & ASRSTR_AODO(index)) { 865 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 866 pair_dbg("Output Data Buffer has overflowed\n"); 867 } 868 869 if (status & ASRSTR_AIDU(index)) { 870 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 871 pair_dbg("Input Data Buffer has underflowed\n"); 872 } 873 } 874 875 return IRQ_HANDLED; 876 } 877 878 static int fsl_asrc_probe(struct platform_device *pdev) 879 { 880 struct device_node *np = pdev->dev.of_node; 881 struct fsl_asrc *asrc_priv; 882 struct resource *res; 883 void __iomem *regs; 884 int irq, ret, i; 885 char tmp[16]; 886 887 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 888 if (!asrc_priv) 889 return -ENOMEM; 890 891 asrc_priv->pdev = pdev; 892 893 /* Get the addresses and IRQ */ 894 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 895 regs = devm_ioremap_resource(&pdev->dev, res); 896 if (IS_ERR(regs)) 897 return PTR_ERR(regs); 898 899 asrc_priv->paddr = res->start; 900 901 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 902 &fsl_asrc_regmap_config); 903 if (IS_ERR(asrc_priv->regmap)) { 904 dev_err(&pdev->dev, "failed to init regmap\n"); 905 return PTR_ERR(asrc_priv->regmap); 906 } 907 908 irq = platform_get_irq(pdev, 0); 909 if (irq < 0) 910 return irq; 911 912 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 913 dev_name(&pdev->dev), asrc_priv); 914 if (ret) { 915 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 916 return ret; 917 } 918 919 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); 920 if (IS_ERR(asrc_priv->mem_clk)) { 921 dev_err(&pdev->dev, "failed to get mem clock\n"); 922 return PTR_ERR(asrc_priv->mem_clk); 923 } 924 925 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 926 if (IS_ERR(asrc_priv->ipg_clk)) { 927 dev_err(&pdev->dev, "failed to get ipg clock\n"); 928 return PTR_ERR(asrc_priv->ipg_clk); 929 } 930 931 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba"); 932 if (IS_ERR(asrc_priv->spba_clk)) 933 dev_warn(&pdev->dev, "failed to get spba clock\n"); 934 935 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 936 sprintf(tmp, "asrck_%x", i); 937 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 938 if (IS_ERR(asrc_priv->asrck_clk[i])) { 939 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 940 return PTR_ERR(asrc_priv->asrck_clk[i]); 941 } 942 } 943 944 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 945 asrc_priv->channel_bits = 3; 946 clk_map[IN] = input_clk_map_imx35; 947 clk_map[OUT] = output_clk_map_imx35; 948 } else { 949 asrc_priv->channel_bits = 4; 950 clk_map[IN] = input_clk_map_imx53; 951 clk_map[OUT] = output_clk_map_imx53; 952 } 953 954 ret = fsl_asrc_init(asrc_priv); 955 if (ret) { 956 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 957 return ret; 958 } 959 960 asrc_priv->channel_avail = 10; 961 962 ret = of_property_read_u32(np, "fsl,asrc-rate", 963 &asrc_priv->asrc_rate); 964 if (ret) { 965 dev_err(&pdev->dev, "failed to get output rate\n"); 966 return ret; 967 } 968 969 ret = of_property_read_u32(np, "fsl,asrc-width", 970 &asrc_priv->asrc_width); 971 if (ret) { 972 dev_err(&pdev->dev, "failed to get output width\n"); 973 return ret; 974 } 975 976 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { 977 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); 978 asrc_priv->asrc_width = 24; 979 } 980 981 platform_set_drvdata(pdev, asrc_priv); 982 pm_runtime_enable(&pdev->dev); 983 spin_lock_init(&asrc_priv->lock); 984 985 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 986 &fsl_asrc_dai, 1); 987 if (ret) { 988 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 989 return ret; 990 } 991 992 return 0; 993 } 994 995 #ifdef CONFIG_PM 996 static int fsl_asrc_runtime_resume(struct device *dev) 997 { 998 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 999 int i, ret; 1000 1001 ret = clk_prepare_enable(asrc_priv->mem_clk); 1002 if (ret) 1003 return ret; 1004 ret = clk_prepare_enable(asrc_priv->ipg_clk); 1005 if (ret) 1006 goto disable_mem_clk; 1007 if (!IS_ERR(asrc_priv->spba_clk)) { 1008 ret = clk_prepare_enable(asrc_priv->spba_clk); 1009 if (ret) 1010 goto disable_ipg_clk; 1011 } 1012 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1013 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1014 if (ret) 1015 goto disable_asrck_clk; 1016 } 1017 1018 return 0; 1019 1020 disable_asrck_clk: 1021 for (i--; i >= 0; i--) 1022 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1023 if (!IS_ERR(asrc_priv->spba_clk)) 1024 clk_disable_unprepare(asrc_priv->spba_clk); 1025 disable_ipg_clk: 1026 clk_disable_unprepare(asrc_priv->ipg_clk); 1027 disable_mem_clk: 1028 clk_disable_unprepare(asrc_priv->mem_clk); 1029 return ret; 1030 } 1031 1032 static int fsl_asrc_runtime_suspend(struct device *dev) 1033 { 1034 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1035 int i; 1036 1037 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1038 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1039 if (!IS_ERR(asrc_priv->spba_clk)) 1040 clk_disable_unprepare(asrc_priv->spba_clk); 1041 clk_disable_unprepare(asrc_priv->ipg_clk); 1042 clk_disable_unprepare(asrc_priv->mem_clk); 1043 1044 return 0; 1045 } 1046 #endif /* CONFIG_PM */ 1047 1048 #ifdef CONFIG_PM_SLEEP 1049 static int fsl_asrc_suspend(struct device *dev) 1050 { 1051 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1052 1053 regmap_read(asrc_priv->regmap, REG_ASRCFG, 1054 &asrc_priv->regcache_cfg); 1055 1056 regcache_cache_only(asrc_priv->regmap, true); 1057 regcache_mark_dirty(asrc_priv->regmap); 1058 1059 return 0; 1060 } 1061 1062 static int fsl_asrc_resume(struct device *dev) 1063 { 1064 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1065 u32 asrctr; 1066 1067 /* Stop all pairs provisionally */ 1068 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); 1069 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1070 ASRCTR_ASRCEi_ALL_MASK, 0); 1071 1072 /* Restore all registers */ 1073 regcache_cache_only(asrc_priv->regmap, false); 1074 regcache_sync(asrc_priv->regmap); 1075 1076 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 1077 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1078 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1079 1080 /* Restart enabled pairs */ 1081 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1082 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1083 1084 return 0; 1085 } 1086 #endif /* CONFIG_PM_SLEEP */ 1087 1088 static const struct dev_pm_ops fsl_asrc_pm = { 1089 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1090 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1091 }; 1092 1093 static const struct of_device_id fsl_asrc_ids[] = { 1094 { .compatible = "fsl,imx35-asrc", }, 1095 { .compatible = "fsl,imx53-asrc", }, 1096 {} 1097 }; 1098 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1099 1100 static struct platform_driver fsl_asrc_driver = { 1101 .probe = fsl_asrc_probe, 1102 .driver = { 1103 .name = "fsl-asrc", 1104 .of_match_table = fsl_asrc_ids, 1105 .pm = &fsl_asrc_pm, 1106 }, 1107 }; 1108 module_platform_driver(fsl_asrc_driver); 1109 1110 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1111 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1112 MODULE_ALIAS("platform:fsl-asrc"); 1113 MODULE_LICENSE("GPL v2"); 1114