1 /* 2 * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 3 * 4 * Copyright (C) 2014 Freescale Semiconductor, Inc. 5 * 6 * Author: Nicolin Chen <nicoleotsuka@gmail.com> 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/module.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_data/dma-imx.h> 19 #include <linux/pm_runtime.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "fsl_asrc.h" 24 25 #define IDEAL_RATIO_DECIMAL_DEPTH 26 26 27 #define pair_err(fmt, ...) \ 28 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 29 30 #define pair_dbg(fmt, ...) \ 31 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 32 33 /* Sample rates are aligned with that defined in pcm.h file */ 34 static const u8 process_option[][8][2] = { 35 /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */ 36 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */ 37 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */ 38 {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */ 39 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */ 40 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */ 41 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */ 42 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */ 43 {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */ 44 {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */ 45 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */ 46 {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */ 47 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */ 48 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */ 49 }; 50 51 /* Corresponding to process_option */ 52 static int supported_input_rate[] = { 53 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 54 96000, 176400, 192000, 55 }; 56 57 static int supported_asrc_rate[] = { 58 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000, 59 }; 60 61 /** 62 * The following tables map the relationship between asrc_inclk/asrc_outclk in 63 * fsl_asrc.h and the registers of ASRCSR 64 */ 65 static unsigned char input_clk_map_imx35[] = { 66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 67 }; 68 69 static unsigned char output_clk_map_imx35[] = { 70 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 71 }; 72 73 /* i.MX53 uses the same map for input and output */ 74 static unsigned char input_clk_map_imx53[] = { 75 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 76 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 77 }; 78 79 static unsigned char output_clk_map_imx53[] = { 80 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 81 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 82 }; 83 84 static unsigned char *clk_map[2]; 85 86 /** 87 * Request ASRC pair 88 * 89 * It assigns pair by the order of A->C->B because allocation of pair B, 90 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 91 * while pair A and pair C are comparatively independent. 92 */ 93 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 94 { 95 enum asrc_pair_index index = ASRC_INVALID_PAIR; 96 struct fsl_asrc *asrc_priv = pair->asrc_priv; 97 struct device *dev = &asrc_priv->pdev->dev; 98 unsigned long lock_flags; 99 int i, ret = 0; 100 101 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 102 103 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 104 if (asrc_priv->pair[i] != NULL) 105 continue; 106 107 index = i; 108 109 if (i != ASRC_PAIR_B) 110 break; 111 } 112 113 if (index == ASRC_INVALID_PAIR) { 114 dev_err(dev, "all pairs are busy now\n"); 115 ret = -EBUSY; 116 } else if (asrc_priv->channel_avail < channels) { 117 dev_err(dev, "can't afford required channels: %d\n", channels); 118 ret = -EINVAL; 119 } else { 120 asrc_priv->channel_avail -= channels; 121 asrc_priv->pair[index] = pair; 122 pair->channels = channels; 123 pair->index = index; 124 } 125 126 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 127 128 return ret; 129 } 130 131 /** 132 * Release ASRC pair 133 * 134 * It clears the resource from asrc_priv and releases the occupied channels. 135 */ 136 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 137 { 138 struct fsl_asrc *asrc_priv = pair->asrc_priv; 139 enum asrc_pair_index index = pair->index; 140 unsigned long lock_flags; 141 142 /* Make sure the pair is disabled */ 143 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 144 ASRCTR_ASRCEi_MASK(index), 0); 145 146 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 147 148 asrc_priv->channel_avail += pair->channels; 149 asrc_priv->pair[index] = NULL; 150 pair->error = 0; 151 152 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 153 } 154 155 /** 156 * Configure input and output thresholds 157 */ 158 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 159 { 160 struct fsl_asrc *asrc_priv = pair->asrc_priv; 161 enum asrc_pair_index index = pair->index; 162 163 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 164 ASRMCRi_EXTTHRSHi_MASK | 165 ASRMCRi_INFIFO_THRESHOLD_MASK | 166 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 167 ASRMCRi_EXTTHRSHi | 168 ASRMCRi_INFIFO_THRESHOLD(in) | 169 ASRMCRi_OUTFIFO_THRESHOLD(out)); 170 } 171 172 /** 173 * Calculate the total divisor between asrck clock rate and sample rate 174 * 175 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 176 */ 177 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 178 { 179 u32 ps; 180 181 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 182 for (ps = 0; div > 8; ps++) 183 div >>= 1; 184 185 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 186 } 187 188 /** 189 * Calculate and set the ratio for Ideal Ratio mode only 190 * 191 * The ratio is a 32-bit fixed point value with 26 fractional bits. 192 */ 193 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 194 int inrate, int outrate) 195 { 196 struct fsl_asrc *asrc_priv = pair->asrc_priv; 197 enum asrc_pair_index index = pair->index; 198 unsigned long ratio; 199 int i; 200 201 if (!outrate) { 202 pair_err("output rate should not be zero\n"); 203 return -EINVAL; 204 } 205 206 /* Calculate the intergal part of the ratio */ 207 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 208 209 /* ... and then the 26 depth decimal part */ 210 inrate %= outrate; 211 212 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 213 inrate <<= 1; 214 215 if (inrate < outrate) 216 continue; 217 218 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 219 inrate -= outrate; 220 221 if (!inrate) 222 break; 223 } 224 225 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); 226 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); 227 228 return 0; 229 } 230 231 /** 232 * Configure the assigned ASRC pair 233 * 234 * It configures those ASRC registers according to a configuration instance 235 * of struct asrc_config which includes in/output sample rate, width, channel 236 * and clock settings. 237 */ 238 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair) 239 { 240 struct asrc_config *config = pair->config; 241 struct fsl_asrc *asrc_priv = pair->asrc_priv; 242 enum asrc_pair_index index = pair->index; 243 u32 inrate, outrate, indiv, outdiv; 244 u32 clk_index[2], div[2]; 245 int in, out, channels; 246 struct clk *clk; 247 bool ideal; 248 249 if (!config) { 250 pair_err("invalid pair config\n"); 251 return -EINVAL; 252 } 253 254 /* Validate channels */ 255 if (config->channel_num < 1 || config->channel_num > 10) { 256 pair_err("does not support %d channels\n", config->channel_num); 257 return -EINVAL; 258 } 259 260 /* Validate output width */ 261 if (config->output_word_width == ASRC_WIDTH_8_BIT) { 262 pair_err("does not support 8bit width output\n"); 263 return -EINVAL; 264 } 265 266 inrate = config->input_sample_rate; 267 outrate = config->output_sample_rate; 268 ideal = config->inclk == INCLK_NONE; 269 270 /* Validate input and output sample rates */ 271 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) 272 if (inrate == supported_input_rate[in]) 273 break; 274 275 if (in == ARRAY_SIZE(supported_input_rate)) { 276 pair_err("unsupported input sample rate: %dHz\n", inrate); 277 return -EINVAL; 278 } 279 280 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 281 if (outrate == supported_asrc_rate[out]) 282 break; 283 284 if (out == ARRAY_SIZE(supported_asrc_rate)) { 285 pair_err("unsupported output sample rate: %dHz\n", outrate); 286 return -EINVAL; 287 } 288 289 /* Validate input and output clock sources */ 290 clk_index[IN] = clk_map[IN][config->inclk]; 291 clk_index[OUT] = clk_map[OUT][config->outclk]; 292 293 /* We only have output clock for ideal ratio mode */ 294 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 295 296 div[IN] = clk_get_rate(clk) / inrate; 297 if (div[IN] == 0) { 298 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 299 inrate, clk_index[ideal ? OUT : IN]); 300 return -EINVAL; 301 } 302 303 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 304 305 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */ 306 if (ideal) 307 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE; 308 else 309 div[OUT] = clk_get_rate(clk) / outrate; 310 311 if (div[OUT] == 0) { 312 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 313 outrate, clk_index[OUT]); 314 return -EINVAL; 315 } 316 317 /* Set the channel number */ 318 channels = config->channel_num; 319 320 if (asrc_priv->channel_bits < 4) 321 channels /= 2; 322 323 /* Update channels for current pair */ 324 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, 325 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), 326 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); 327 328 /* Default setting: Automatic selection for processing mode */ 329 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 330 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 331 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 332 ASRCTR_USRi_MASK(index), 0); 333 334 /* Set the input and output clock sources */ 335 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, 336 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 337 ASRCSR_AICS(index, clk_index[IN]) | 338 ASRCSR_AOCS(index, clk_index[OUT])); 339 340 /* Calculate the input clock divisors */ 341 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 342 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 343 344 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 345 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), 346 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 347 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 348 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 349 350 /* Implement word_width configurations */ 351 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), 352 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 353 ASRMCR1i_OW16(config->output_word_width) | 354 ASRMCR1i_IWD(config->input_word_width)); 355 356 /* Enable BUFFER STALL */ 357 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 358 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 359 360 /* Set default thresholds for input and output FIFO */ 361 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 362 ASRC_INPUTFIFO_THRESHOLD); 363 364 /* Configure the followings only for Ideal Ratio mode */ 365 if (!ideal) 366 return 0; 367 368 /* Clear ASTSx bit to use Ideal Ratio mode */ 369 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 370 ASRCTR_ATSi_MASK(index), 0); 371 372 /* Enable Ideal Ratio mode */ 373 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 374 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 375 ASRCTR_IDR(index) | ASRCTR_USR(index)); 376 377 /* Apply configurations for pre- and post-processing */ 378 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 379 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 380 ASRCFG_PREMOD(index, process_option[in][out][0]) | 381 ASRCFG_POSTMOD(index, process_option[in][out][1])); 382 383 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 384 } 385 386 /** 387 * Start the assigned ASRC pair 388 * 389 * It enables the assigned pair and makes it stopped at the stall level. 390 */ 391 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 392 { 393 struct fsl_asrc *asrc_priv = pair->asrc_priv; 394 enum asrc_pair_index index = pair->index; 395 int reg, retry = 10, i; 396 397 /* Enable the current pair */ 398 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 399 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 400 401 /* Wait for status of initialization */ 402 do { 403 udelay(5); 404 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); 405 reg &= ASRCFG_INIRQi_MASK(index); 406 } while (!reg && --retry); 407 408 /* Make the input fifo to ASRC STALL level */ 409 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); 410 for (i = 0; i < pair->channels * 4; i++) 411 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); 412 413 /* Enable overload interrupt */ 414 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); 415 } 416 417 /** 418 * Stop the assigned ASRC pair 419 */ 420 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 421 { 422 struct fsl_asrc *asrc_priv = pair->asrc_priv; 423 enum asrc_pair_index index = pair->index; 424 425 /* Stop the current pair */ 426 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 427 ASRCTR_ASRCEi_MASK(index), 0); 428 } 429 430 /** 431 * Get DMA channel according to the pair and direction. 432 */ 433 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) 434 { 435 struct fsl_asrc *asrc_priv = pair->asrc_priv; 436 enum asrc_pair_index index = pair->index; 437 char name[4]; 438 439 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 440 441 return dma_request_slave_channel(&asrc_priv->pdev->dev, name); 442 } 443 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); 444 445 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 446 struct snd_pcm_hw_params *params, 447 struct snd_soc_dai *dai) 448 { 449 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 450 int width = snd_pcm_format_width(params_format(params)); 451 struct snd_pcm_runtime *runtime = substream->runtime; 452 struct fsl_asrc_pair *pair = runtime->private_data; 453 unsigned int channels = params_channels(params); 454 unsigned int rate = params_rate(params); 455 struct asrc_config config; 456 int word_width, ret; 457 458 ret = fsl_asrc_request_pair(channels, pair); 459 if (ret) { 460 dev_err(dai->dev, "fail to request asrc pair\n"); 461 return ret; 462 } 463 464 pair->config = &config; 465 466 if (width == 16) 467 width = ASRC_WIDTH_16_BIT; 468 else 469 width = ASRC_WIDTH_24_BIT; 470 471 if (asrc_priv->asrc_width == 16) 472 word_width = ASRC_WIDTH_16_BIT; 473 else 474 word_width = ASRC_WIDTH_24_BIT; 475 476 config.pair = pair->index; 477 config.channel_num = channels; 478 config.inclk = INCLK_NONE; 479 config.outclk = OUTCLK_ASRCK1_CLK; 480 481 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 482 config.input_word_width = width; 483 config.output_word_width = word_width; 484 config.input_sample_rate = rate; 485 config.output_sample_rate = asrc_priv->asrc_rate; 486 } else { 487 config.input_word_width = word_width; 488 config.output_word_width = width; 489 config.input_sample_rate = asrc_priv->asrc_rate; 490 config.output_sample_rate = rate; 491 } 492 493 ret = fsl_asrc_config_pair(pair); 494 if (ret) { 495 dev_err(dai->dev, "fail to config asrc pair\n"); 496 return ret; 497 } 498 499 return 0; 500 } 501 502 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 503 struct snd_soc_dai *dai) 504 { 505 struct snd_pcm_runtime *runtime = substream->runtime; 506 struct fsl_asrc_pair *pair = runtime->private_data; 507 508 if (pair) 509 fsl_asrc_release_pair(pair); 510 511 return 0; 512 } 513 514 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 515 struct snd_soc_dai *dai) 516 { 517 struct snd_pcm_runtime *runtime = substream->runtime; 518 struct fsl_asrc_pair *pair = runtime->private_data; 519 520 switch (cmd) { 521 case SNDRV_PCM_TRIGGER_START: 522 case SNDRV_PCM_TRIGGER_RESUME: 523 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 524 fsl_asrc_start_pair(pair); 525 break; 526 case SNDRV_PCM_TRIGGER_STOP: 527 case SNDRV_PCM_TRIGGER_SUSPEND: 528 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 529 fsl_asrc_stop_pair(pair); 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 return 0; 536 } 537 538 static struct snd_soc_dai_ops fsl_asrc_dai_ops = { 539 .hw_params = fsl_asrc_dai_hw_params, 540 .hw_free = fsl_asrc_dai_hw_free, 541 .trigger = fsl_asrc_dai_trigger, 542 }; 543 544 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 545 { 546 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 547 548 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, 549 &asrc_priv->dma_params_rx); 550 551 return 0; 552 } 553 554 #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000 555 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 556 SNDRV_PCM_FMTBIT_S16_LE | \ 557 SNDRV_PCM_FMTBIT_S20_3LE) 558 559 static struct snd_soc_dai_driver fsl_asrc_dai = { 560 .probe = fsl_asrc_dai_probe, 561 .playback = { 562 .stream_name = "ASRC-Playback", 563 .channels_min = 1, 564 .channels_max = 10, 565 .rates = FSL_ASRC_RATES, 566 .formats = FSL_ASRC_FORMATS, 567 }, 568 .capture = { 569 .stream_name = "ASRC-Capture", 570 .channels_min = 1, 571 .channels_max = 10, 572 .rates = FSL_ASRC_RATES, 573 .formats = FSL_ASRC_FORMATS, 574 }, 575 .ops = &fsl_asrc_dai_ops, 576 }; 577 578 static const struct snd_soc_component_driver fsl_asrc_component = { 579 .name = "fsl-asrc-dai", 580 }; 581 582 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 583 { 584 switch (reg) { 585 case REG_ASRCTR: 586 case REG_ASRIER: 587 case REG_ASRCNCR: 588 case REG_ASRCFG: 589 case REG_ASRCSR: 590 case REG_ASRCDR1: 591 case REG_ASRCDR2: 592 case REG_ASRSTR: 593 case REG_ASRPM1: 594 case REG_ASRPM2: 595 case REG_ASRPM3: 596 case REG_ASRPM4: 597 case REG_ASRPM5: 598 case REG_ASRTFR1: 599 case REG_ASRCCR: 600 case REG_ASRDOA: 601 case REG_ASRDOB: 602 case REG_ASRDOC: 603 case REG_ASRIDRHA: 604 case REG_ASRIDRLA: 605 case REG_ASRIDRHB: 606 case REG_ASRIDRLB: 607 case REG_ASRIDRHC: 608 case REG_ASRIDRLC: 609 case REG_ASR76K: 610 case REG_ASR56K: 611 case REG_ASRMCRA: 612 case REG_ASRFSTA: 613 case REG_ASRMCRB: 614 case REG_ASRFSTB: 615 case REG_ASRMCRC: 616 case REG_ASRFSTC: 617 case REG_ASRMCR1A: 618 case REG_ASRMCR1B: 619 case REG_ASRMCR1C: 620 return true; 621 default: 622 return false; 623 } 624 } 625 626 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 627 { 628 switch (reg) { 629 case REG_ASRSTR: 630 case REG_ASRDIA: 631 case REG_ASRDIB: 632 case REG_ASRDIC: 633 case REG_ASRDOA: 634 case REG_ASRDOB: 635 case REG_ASRDOC: 636 case REG_ASRFSTA: 637 case REG_ASRFSTB: 638 case REG_ASRFSTC: 639 case REG_ASRCFG: 640 return true; 641 default: 642 return false; 643 } 644 } 645 646 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 647 { 648 switch (reg) { 649 case REG_ASRCTR: 650 case REG_ASRIER: 651 case REG_ASRCNCR: 652 case REG_ASRCFG: 653 case REG_ASRCSR: 654 case REG_ASRCDR1: 655 case REG_ASRCDR2: 656 case REG_ASRSTR: 657 case REG_ASRPM1: 658 case REG_ASRPM2: 659 case REG_ASRPM3: 660 case REG_ASRPM4: 661 case REG_ASRPM5: 662 case REG_ASRTFR1: 663 case REG_ASRCCR: 664 case REG_ASRDIA: 665 case REG_ASRDIB: 666 case REG_ASRDIC: 667 case REG_ASRIDRHA: 668 case REG_ASRIDRLA: 669 case REG_ASRIDRHB: 670 case REG_ASRIDRLB: 671 case REG_ASRIDRHC: 672 case REG_ASRIDRLC: 673 case REG_ASR76K: 674 case REG_ASR56K: 675 case REG_ASRMCRA: 676 case REG_ASRMCRB: 677 case REG_ASRMCRC: 678 case REG_ASRMCR1A: 679 case REG_ASRMCR1B: 680 case REG_ASRMCR1C: 681 return true; 682 default: 683 return false; 684 } 685 } 686 687 static struct reg_default fsl_asrc_reg[] = { 688 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 689 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 690 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 691 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 692 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 693 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 694 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 695 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 696 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 697 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 698 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 699 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 700 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 701 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 702 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 703 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 704 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 705 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 706 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 707 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 708 { REG_ASRMCR1C, 0x0000 }, 709 }; 710 711 static const struct regmap_config fsl_asrc_regmap_config = { 712 .reg_bits = 32, 713 .reg_stride = 4, 714 .val_bits = 32, 715 716 .max_register = REG_ASRMCR1C, 717 .reg_defaults = fsl_asrc_reg, 718 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 719 .readable_reg = fsl_asrc_readable_reg, 720 .volatile_reg = fsl_asrc_volatile_reg, 721 .writeable_reg = fsl_asrc_writeable_reg, 722 .cache_type = REGCACHE_RBTREE, 723 }; 724 725 /** 726 * Initialize ASRC registers with a default configurations 727 */ 728 static int fsl_asrc_init(struct fsl_asrc *asrc_priv) 729 { 730 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 731 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 732 733 /* Disable interrupt by default */ 734 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); 735 736 /* Apply recommended settings for parameters from Reference Manual */ 737 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); 738 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); 739 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); 740 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); 741 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); 742 743 /* Base address for task queue FIFO. Set to 0x7C */ 744 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, 745 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 746 747 /* Set the processing clock for 76KHz to 133M */ 748 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); 749 750 /* Set the processing clock for 56KHz to 133M */ 751 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); 752 } 753 754 /** 755 * Interrupt handler for ASRC 756 */ 757 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 758 { 759 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; 760 struct device *dev = &asrc_priv->pdev->dev; 761 enum asrc_pair_index index; 762 u32 status; 763 764 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); 765 766 /* Clean overload error */ 767 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); 768 769 /* 770 * We here use dev_dbg() for all exceptions because ASRC itself does 771 * not care if FIFO overflowed or underrun while a warning in the 772 * interrupt would result a ridged conversion. 773 */ 774 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 775 if (!asrc_priv->pair[index]) 776 continue; 777 778 if (status & ASRSTR_ATQOL) { 779 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 780 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 781 } 782 783 if (status & ASRSTR_AOOL(index)) { 784 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 785 pair_dbg("Output Task Overload\n"); 786 } 787 788 if (status & ASRSTR_AIOL(index)) { 789 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 790 pair_dbg("Input Task Overload\n"); 791 } 792 793 if (status & ASRSTR_AODO(index)) { 794 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 795 pair_dbg("Output Data Buffer has overflowed\n"); 796 } 797 798 if (status & ASRSTR_AIDU(index)) { 799 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 800 pair_dbg("Input Data Buffer has underflowed\n"); 801 } 802 } 803 804 return IRQ_HANDLED; 805 } 806 807 static int fsl_asrc_probe(struct platform_device *pdev) 808 { 809 struct device_node *np = pdev->dev.of_node; 810 struct fsl_asrc *asrc_priv; 811 struct resource *res; 812 void __iomem *regs; 813 int irq, ret, i; 814 char tmp[16]; 815 816 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 817 if (!asrc_priv) 818 return -ENOMEM; 819 820 asrc_priv->pdev = pdev; 821 822 /* Get the addresses and IRQ */ 823 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 824 regs = devm_ioremap_resource(&pdev->dev, res); 825 if (IS_ERR(regs)) 826 return PTR_ERR(regs); 827 828 asrc_priv->paddr = res->start; 829 830 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 831 &fsl_asrc_regmap_config); 832 if (IS_ERR(asrc_priv->regmap)) { 833 dev_err(&pdev->dev, "failed to init regmap\n"); 834 return PTR_ERR(asrc_priv->regmap); 835 } 836 837 irq = platform_get_irq(pdev, 0); 838 if (irq < 0) { 839 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 840 return irq; 841 } 842 843 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 844 dev_name(&pdev->dev), asrc_priv); 845 if (ret) { 846 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 847 return ret; 848 } 849 850 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); 851 if (IS_ERR(asrc_priv->mem_clk)) { 852 dev_err(&pdev->dev, "failed to get mem clock\n"); 853 return PTR_ERR(asrc_priv->mem_clk); 854 } 855 856 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 857 if (IS_ERR(asrc_priv->ipg_clk)) { 858 dev_err(&pdev->dev, "failed to get ipg clock\n"); 859 return PTR_ERR(asrc_priv->ipg_clk); 860 } 861 862 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 863 sprintf(tmp, "asrck_%x", i); 864 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 865 if (IS_ERR(asrc_priv->asrck_clk[i])) { 866 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 867 return PTR_ERR(asrc_priv->asrck_clk[i]); 868 } 869 } 870 871 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-asrc")) { 872 asrc_priv->channel_bits = 3; 873 clk_map[IN] = input_clk_map_imx35; 874 clk_map[OUT] = output_clk_map_imx35; 875 } else { 876 asrc_priv->channel_bits = 4; 877 clk_map[IN] = input_clk_map_imx53; 878 clk_map[OUT] = output_clk_map_imx53; 879 } 880 881 ret = fsl_asrc_init(asrc_priv); 882 if (ret) { 883 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 884 return -EINVAL; 885 } 886 887 asrc_priv->channel_avail = 10; 888 889 ret = of_property_read_u32(np, "fsl,asrc-rate", 890 &asrc_priv->asrc_rate); 891 if (ret) { 892 dev_err(&pdev->dev, "failed to get output rate\n"); 893 return -EINVAL; 894 } 895 896 ret = of_property_read_u32(np, "fsl,asrc-width", 897 &asrc_priv->asrc_width); 898 if (ret) { 899 dev_err(&pdev->dev, "failed to get output width\n"); 900 return -EINVAL; 901 } 902 903 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { 904 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); 905 asrc_priv->asrc_width = 24; 906 } 907 908 platform_set_drvdata(pdev, asrc_priv); 909 pm_runtime_enable(&pdev->dev); 910 spin_lock_init(&asrc_priv->lock); 911 912 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 913 &fsl_asrc_dai, 1); 914 if (ret) { 915 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 916 return ret; 917 } 918 919 ret = devm_snd_soc_register_platform(&pdev->dev, &fsl_asrc_platform); 920 if (ret) { 921 dev_err(&pdev->dev, "failed to register ASoC platform\n"); 922 return ret; 923 } 924 925 dev_info(&pdev->dev, "driver registered\n"); 926 927 return 0; 928 } 929 930 #ifdef CONFIG_PM 931 static int fsl_asrc_runtime_resume(struct device *dev) 932 { 933 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 934 int i; 935 936 clk_prepare_enable(asrc_priv->mem_clk); 937 clk_prepare_enable(asrc_priv->ipg_clk); 938 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 939 clk_prepare_enable(asrc_priv->asrck_clk[i]); 940 941 return 0; 942 } 943 944 static int fsl_asrc_runtime_suspend(struct device *dev) 945 { 946 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 947 int i; 948 949 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 950 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 951 clk_disable_unprepare(asrc_priv->ipg_clk); 952 clk_disable_unprepare(asrc_priv->mem_clk); 953 954 return 0; 955 } 956 #endif /* CONFIG_PM */ 957 958 #ifdef CONFIG_PM_SLEEP 959 static int fsl_asrc_suspend(struct device *dev) 960 { 961 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 962 963 regcache_cache_only(asrc_priv->regmap, true); 964 regcache_mark_dirty(asrc_priv->regmap); 965 966 return 0; 967 } 968 969 static int fsl_asrc_resume(struct device *dev) 970 { 971 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 972 u32 asrctr; 973 974 /* Stop all pairs provisionally */ 975 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); 976 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 977 ASRCTR_ASRCEi_ALL_MASK, 0); 978 979 /* Restore all registers */ 980 regcache_cache_only(asrc_priv->regmap, false); 981 regcache_sync(asrc_priv->regmap); 982 983 /* Restart enabled pairs */ 984 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 985 ASRCTR_ASRCEi_ALL_MASK, asrctr); 986 987 return 0; 988 } 989 #endif /* CONFIG_PM_SLEEP */ 990 991 static const struct dev_pm_ops fsl_asrc_pm = { 992 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 993 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 994 }; 995 996 static const struct of_device_id fsl_asrc_ids[] = { 997 { .compatible = "fsl,imx35-asrc", }, 998 { .compatible = "fsl,imx53-asrc", }, 999 {} 1000 }; 1001 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1002 1003 static struct platform_driver fsl_asrc_driver = { 1004 .probe = fsl_asrc_probe, 1005 .driver = { 1006 .name = "fsl-asrc", 1007 .of_match_table = fsl_asrc_ids, 1008 .pm = &fsl_asrc_pm, 1009 }, 1010 }; 1011 module_platform_driver(fsl_asrc_driver); 1012 1013 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1014 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1015 MODULE_ALIAS("platform:fsl-asrc"); 1016 MODULE_LICENSE("GPL v2"); 1017