1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_data/dma-imx.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 23 #define pair_err(fmt, ...) \ 24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 25 26 #define pair_dbg(fmt, ...) \ 27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 28 29 /* Sample rates are aligned with that defined in pcm.h file */ 30 static const u8 process_option[][12][2] = { 31 /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */ 32 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */ 33 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */ 34 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */ 35 {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */ 36 {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */ 37 {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */ 38 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */ 39 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */ 40 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */ 41 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */ 42 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */ 43 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */ 44 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */ 45 }; 46 47 /* Corresponding to process_option */ 48 static int supported_input_rate[] = { 49 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 50 96000, 176400, 192000, 51 }; 52 53 static int supported_asrc_rate[] = { 54 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000, 55 }; 56 57 /** 58 * The following tables map the relationship between asrc_inclk/asrc_outclk in 59 * fsl_asrc.h and the registers of ASRCSR 60 */ 61 static unsigned char input_clk_map_imx35[] = { 62 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 63 }; 64 65 static unsigned char output_clk_map_imx35[] = { 66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 67 }; 68 69 /* i.MX53 uses the same map for input and output */ 70 static unsigned char input_clk_map_imx53[] = { 71 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 72 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 73 }; 74 75 static unsigned char output_clk_map_imx53[] = { 76 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 77 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 78 }; 79 80 static unsigned char *clk_map[2]; 81 82 /** 83 * Request ASRC pair 84 * 85 * It assigns pair by the order of A->C->B because allocation of pair B, 86 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 87 * while pair A and pair C are comparatively independent. 88 */ 89 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 90 { 91 enum asrc_pair_index index = ASRC_INVALID_PAIR; 92 struct fsl_asrc *asrc_priv = pair->asrc_priv; 93 struct device *dev = &asrc_priv->pdev->dev; 94 unsigned long lock_flags; 95 int i, ret = 0; 96 97 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 98 99 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 100 if (asrc_priv->pair[i] != NULL) 101 continue; 102 103 index = i; 104 105 if (i != ASRC_PAIR_B) 106 break; 107 } 108 109 if (index == ASRC_INVALID_PAIR) { 110 dev_err(dev, "all pairs are busy now\n"); 111 ret = -EBUSY; 112 } else if (asrc_priv->channel_avail < channels) { 113 dev_err(dev, "can't afford required channels: %d\n", channels); 114 ret = -EINVAL; 115 } else { 116 asrc_priv->channel_avail -= channels; 117 asrc_priv->pair[index] = pair; 118 pair->channels = channels; 119 pair->index = index; 120 } 121 122 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 123 124 return ret; 125 } 126 127 /** 128 * Release ASRC pair 129 * 130 * It clears the resource from asrc_priv and releases the occupied channels. 131 */ 132 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 133 { 134 struct fsl_asrc *asrc_priv = pair->asrc_priv; 135 enum asrc_pair_index index = pair->index; 136 unsigned long lock_flags; 137 138 /* Make sure the pair is disabled */ 139 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 140 ASRCTR_ASRCEi_MASK(index), 0); 141 142 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 143 144 asrc_priv->channel_avail += pair->channels; 145 asrc_priv->pair[index] = NULL; 146 pair->error = 0; 147 148 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 149 } 150 151 /** 152 * Configure input and output thresholds 153 */ 154 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 155 { 156 struct fsl_asrc *asrc_priv = pair->asrc_priv; 157 enum asrc_pair_index index = pair->index; 158 159 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 160 ASRMCRi_EXTTHRSHi_MASK | 161 ASRMCRi_INFIFO_THRESHOLD_MASK | 162 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 163 ASRMCRi_EXTTHRSHi | 164 ASRMCRi_INFIFO_THRESHOLD(in) | 165 ASRMCRi_OUTFIFO_THRESHOLD(out)); 166 } 167 168 /** 169 * Calculate the total divisor between asrck clock rate and sample rate 170 * 171 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 172 */ 173 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 174 { 175 u32 ps; 176 177 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 178 for (ps = 0; div > 8; ps++) 179 div >>= 1; 180 181 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 182 } 183 184 /** 185 * Calculate and set the ratio for Ideal Ratio mode only 186 * 187 * The ratio is a 32-bit fixed point value with 26 fractional bits. 188 */ 189 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 190 int inrate, int outrate) 191 { 192 struct fsl_asrc *asrc_priv = pair->asrc_priv; 193 enum asrc_pair_index index = pair->index; 194 unsigned long ratio; 195 int i; 196 197 if (!outrate) { 198 pair_err("output rate should not be zero\n"); 199 return -EINVAL; 200 } 201 202 /* Calculate the intergal part of the ratio */ 203 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 204 205 /* ... and then the 26 depth decimal part */ 206 inrate %= outrate; 207 208 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 209 inrate <<= 1; 210 211 if (inrate < outrate) 212 continue; 213 214 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 215 inrate -= outrate; 216 217 if (!inrate) 218 break; 219 } 220 221 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); 222 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); 223 224 return 0; 225 } 226 227 /** 228 * Configure the assigned ASRC pair 229 * 230 * It configures those ASRC registers according to a configuration instance 231 * of struct asrc_config which includes in/output sample rate, width, channel 232 * and clock settings. 233 */ 234 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair) 235 { 236 struct asrc_config *config = pair->config; 237 struct fsl_asrc *asrc_priv = pair->asrc_priv; 238 enum asrc_pair_index index = pair->index; 239 u32 inrate, outrate, indiv, outdiv; 240 u32 clk_index[2], div[2]; 241 int in, out, channels; 242 struct clk *clk; 243 bool ideal; 244 245 if (!config) { 246 pair_err("invalid pair config\n"); 247 return -EINVAL; 248 } 249 250 /* Validate channels */ 251 if (config->channel_num < 1 || config->channel_num > 10) { 252 pair_err("does not support %d channels\n", config->channel_num); 253 return -EINVAL; 254 } 255 256 /* Validate output width */ 257 if (config->output_word_width == ASRC_WIDTH_8_BIT) { 258 pair_err("does not support 8bit width output\n"); 259 return -EINVAL; 260 } 261 262 inrate = config->input_sample_rate; 263 outrate = config->output_sample_rate; 264 ideal = config->inclk == INCLK_NONE; 265 266 /* Validate input and output sample rates */ 267 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) 268 if (inrate == supported_input_rate[in]) 269 break; 270 271 if (in == ARRAY_SIZE(supported_input_rate)) { 272 pair_err("unsupported input sample rate: %dHz\n", inrate); 273 return -EINVAL; 274 } 275 276 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 277 if (outrate == supported_asrc_rate[out]) 278 break; 279 280 if (out == ARRAY_SIZE(supported_asrc_rate)) { 281 pair_err("unsupported output sample rate: %dHz\n", outrate); 282 return -EINVAL; 283 } 284 285 if ((outrate > 8000 && outrate < 30000) && 286 (outrate/inrate > 24 || inrate/outrate > 8)) { 287 pair_err("exceed supported ratio range [1/24, 8] for \ 288 inrate/outrate: %d/%d\n", inrate, outrate); 289 return -EINVAL; 290 } 291 292 /* Validate input and output clock sources */ 293 clk_index[IN] = clk_map[IN][config->inclk]; 294 clk_index[OUT] = clk_map[OUT][config->outclk]; 295 296 /* We only have output clock for ideal ratio mode */ 297 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 298 299 div[IN] = clk_get_rate(clk) / inrate; 300 if (div[IN] == 0) { 301 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 302 inrate, clk_index[ideal ? OUT : IN]); 303 return -EINVAL; 304 } 305 306 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 307 308 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */ 309 if (ideal) 310 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE; 311 else 312 div[OUT] = clk_get_rate(clk) / outrate; 313 314 if (div[OUT] == 0) { 315 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 316 outrate, clk_index[OUT]); 317 return -EINVAL; 318 } 319 320 /* Set the channel number */ 321 channels = config->channel_num; 322 323 if (asrc_priv->channel_bits < 4) 324 channels /= 2; 325 326 /* Update channels for current pair */ 327 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, 328 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), 329 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); 330 331 /* Default setting: Automatic selection for processing mode */ 332 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 333 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 334 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 335 ASRCTR_USRi_MASK(index), 0); 336 337 /* Set the input and output clock sources */ 338 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, 339 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 340 ASRCSR_AICS(index, clk_index[IN]) | 341 ASRCSR_AOCS(index, clk_index[OUT])); 342 343 /* Calculate the input clock divisors */ 344 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 345 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 346 347 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 348 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), 349 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 350 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 351 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 352 353 /* Implement word_width configurations */ 354 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), 355 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 356 ASRMCR1i_OW16(config->output_word_width) | 357 ASRMCR1i_IWD(config->input_word_width)); 358 359 /* Enable BUFFER STALL */ 360 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 361 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 362 363 /* Set default thresholds for input and output FIFO */ 364 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 365 ASRC_INPUTFIFO_THRESHOLD); 366 367 /* Configure the following only for Ideal Ratio mode */ 368 if (!ideal) 369 return 0; 370 371 /* Clear ASTSx bit to use Ideal Ratio mode */ 372 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 373 ASRCTR_ATSi_MASK(index), 0); 374 375 /* Enable Ideal Ratio mode */ 376 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 377 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 378 ASRCTR_IDR(index) | ASRCTR_USR(index)); 379 380 /* Apply configurations for pre- and post-processing */ 381 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 382 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 383 ASRCFG_PREMOD(index, process_option[in][out][0]) | 384 ASRCFG_POSTMOD(index, process_option[in][out][1])); 385 386 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 387 } 388 389 /** 390 * Start the assigned ASRC pair 391 * 392 * It enables the assigned pair and makes it stopped at the stall level. 393 */ 394 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 395 { 396 struct fsl_asrc *asrc_priv = pair->asrc_priv; 397 enum asrc_pair_index index = pair->index; 398 int reg, retry = 10, i; 399 400 /* Enable the current pair */ 401 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 402 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 403 404 /* Wait for status of initialization */ 405 do { 406 udelay(5); 407 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); 408 reg &= ASRCFG_INIRQi_MASK(index); 409 } while (!reg && --retry); 410 411 /* Make the input fifo to ASRC STALL level */ 412 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); 413 for (i = 0; i < pair->channels * 4; i++) 414 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); 415 416 /* Enable overload interrupt */ 417 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); 418 } 419 420 /** 421 * Stop the assigned ASRC pair 422 */ 423 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 424 { 425 struct fsl_asrc *asrc_priv = pair->asrc_priv; 426 enum asrc_pair_index index = pair->index; 427 428 /* Stop the current pair */ 429 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 430 ASRCTR_ASRCEi_MASK(index), 0); 431 } 432 433 /** 434 * Get DMA channel according to the pair and direction. 435 */ 436 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) 437 { 438 struct fsl_asrc *asrc_priv = pair->asrc_priv; 439 enum asrc_pair_index index = pair->index; 440 char name[4]; 441 442 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 443 444 return dma_request_slave_channel(&asrc_priv->pdev->dev, name); 445 } 446 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); 447 448 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 449 struct snd_soc_dai *dai) 450 { 451 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 452 453 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 454 if (asrc_priv->channel_bits == 3) 455 snd_pcm_hw_constraint_step(substream->runtime, 0, 456 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 457 458 return 0; 459 } 460 461 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 462 struct snd_pcm_hw_params *params, 463 struct snd_soc_dai *dai) 464 { 465 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 466 int width = params_width(params); 467 struct snd_pcm_runtime *runtime = substream->runtime; 468 struct fsl_asrc_pair *pair = runtime->private_data; 469 unsigned int channels = params_channels(params); 470 unsigned int rate = params_rate(params); 471 struct asrc_config config; 472 int word_width, ret; 473 474 ret = fsl_asrc_request_pair(channels, pair); 475 if (ret) { 476 dev_err(dai->dev, "fail to request asrc pair\n"); 477 return ret; 478 } 479 480 pair->config = &config; 481 482 if (width == 16) 483 width = ASRC_WIDTH_16_BIT; 484 else 485 width = ASRC_WIDTH_24_BIT; 486 487 if (asrc_priv->asrc_width == 16) 488 word_width = ASRC_WIDTH_16_BIT; 489 else 490 word_width = ASRC_WIDTH_24_BIT; 491 492 config.pair = pair->index; 493 config.channel_num = channels; 494 config.inclk = INCLK_NONE; 495 config.outclk = OUTCLK_ASRCK1_CLK; 496 497 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 498 config.input_word_width = width; 499 config.output_word_width = word_width; 500 config.input_sample_rate = rate; 501 config.output_sample_rate = asrc_priv->asrc_rate; 502 } else { 503 config.input_word_width = word_width; 504 config.output_word_width = width; 505 config.input_sample_rate = asrc_priv->asrc_rate; 506 config.output_sample_rate = rate; 507 } 508 509 ret = fsl_asrc_config_pair(pair); 510 if (ret) { 511 dev_err(dai->dev, "fail to config asrc pair\n"); 512 return ret; 513 } 514 515 return 0; 516 } 517 518 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 519 struct snd_soc_dai *dai) 520 { 521 struct snd_pcm_runtime *runtime = substream->runtime; 522 struct fsl_asrc_pair *pair = runtime->private_data; 523 524 if (pair) 525 fsl_asrc_release_pair(pair); 526 527 return 0; 528 } 529 530 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 531 struct snd_soc_dai *dai) 532 { 533 struct snd_pcm_runtime *runtime = substream->runtime; 534 struct fsl_asrc_pair *pair = runtime->private_data; 535 536 switch (cmd) { 537 case SNDRV_PCM_TRIGGER_START: 538 case SNDRV_PCM_TRIGGER_RESUME: 539 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 540 fsl_asrc_start_pair(pair); 541 break; 542 case SNDRV_PCM_TRIGGER_STOP: 543 case SNDRV_PCM_TRIGGER_SUSPEND: 544 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 545 fsl_asrc_stop_pair(pair); 546 break; 547 default: 548 return -EINVAL; 549 } 550 551 return 0; 552 } 553 554 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 555 .startup = fsl_asrc_dai_startup, 556 .hw_params = fsl_asrc_dai_hw_params, 557 .hw_free = fsl_asrc_dai_hw_free, 558 .trigger = fsl_asrc_dai_trigger, 559 }; 560 561 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 562 { 563 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 564 565 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, 566 &asrc_priv->dma_params_rx); 567 568 return 0; 569 } 570 571 #define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000 572 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 573 SNDRV_PCM_FMTBIT_S16_LE | \ 574 SNDRV_PCM_FMTBIT_S20_3LE) 575 576 static struct snd_soc_dai_driver fsl_asrc_dai = { 577 .probe = fsl_asrc_dai_probe, 578 .playback = { 579 .stream_name = "ASRC-Playback", 580 .channels_min = 1, 581 .channels_max = 10, 582 .rates = FSL_ASRC_RATES, 583 .formats = FSL_ASRC_FORMATS, 584 }, 585 .capture = { 586 .stream_name = "ASRC-Capture", 587 .channels_min = 1, 588 .channels_max = 10, 589 .rates = FSL_ASRC_RATES, 590 .formats = FSL_ASRC_FORMATS, 591 }, 592 .ops = &fsl_asrc_dai_ops, 593 }; 594 595 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 596 { 597 switch (reg) { 598 case REG_ASRCTR: 599 case REG_ASRIER: 600 case REG_ASRCNCR: 601 case REG_ASRCFG: 602 case REG_ASRCSR: 603 case REG_ASRCDR1: 604 case REG_ASRCDR2: 605 case REG_ASRSTR: 606 case REG_ASRPM1: 607 case REG_ASRPM2: 608 case REG_ASRPM3: 609 case REG_ASRPM4: 610 case REG_ASRPM5: 611 case REG_ASRTFR1: 612 case REG_ASRCCR: 613 case REG_ASRDOA: 614 case REG_ASRDOB: 615 case REG_ASRDOC: 616 case REG_ASRIDRHA: 617 case REG_ASRIDRLA: 618 case REG_ASRIDRHB: 619 case REG_ASRIDRLB: 620 case REG_ASRIDRHC: 621 case REG_ASRIDRLC: 622 case REG_ASR76K: 623 case REG_ASR56K: 624 case REG_ASRMCRA: 625 case REG_ASRFSTA: 626 case REG_ASRMCRB: 627 case REG_ASRFSTB: 628 case REG_ASRMCRC: 629 case REG_ASRFSTC: 630 case REG_ASRMCR1A: 631 case REG_ASRMCR1B: 632 case REG_ASRMCR1C: 633 return true; 634 default: 635 return false; 636 } 637 } 638 639 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 640 { 641 switch (reg) { 642 case REG_ASRSTR: 643 case REG_ASRDIA: 644 case REG_ASRDIB: 645 case REG_ASRDIC: 646 case REG_ASRDOA: 647 case REG_ASRDOB: 648 case REG_ASRDOC: 649 case REG_ASRFSTA: 650 case REG_ASRFSTB: 651 case REG_ASRFSTC: 652 case REG_ASRCFG: 653 return true; 654 default: 655 return false; 656 } 657 } 658 659 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 660 { 661 switch (reg) { 662 case REG_ASRCTR: 663 case REG_ASRIER: 664 case REG_ASRCNCR: 665 case REG_ASRCFG: 666 case REG_ASRCSR: 667 case REG_ASRCDR1: 668 case REG_ASRCDR2: 669 case REG_ASRSTR: 670 case REG_ASRPM1: 671 case REG_ASRPM2: 672 case REG_ASRPM3: 673 case REG_ASRPM4: 674 case REG_ASRPM5: 675 case REG_ASRTFR1: 676 case REG_ASRCCR: 677 case REG_ASRDIA: 678 case REG_ASRDIB: 679 case REG_ASRDIC: 680 case REG_ASRIDRHA: 681 case REG_ASRIDRLA: 682 case REG_ASRIDRHB: 683 case REG_ASRIDRLB: 684 case REG_ASRIDRHC: 685 case REG_ASRIDRLC: 686 case REG_ASR76K: 687 case REG_ASR56K: 688 case REG_ASRMCRA: 689 case REG_ASRMCRB: 690 case REG_ASRMCRC: 691 case REG_ASRMCR1A: 692 case REG_ASRMCR1B: 693 case REG_ASRMCR1C: 694 return true; 695 default: 696 return false; 697 } 698 } 699 700 static struct reg_default fsl_asrc_reg[] = { 701 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 702 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 703 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 704 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 705 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 706 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 707 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 708 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 709 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 710 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 711 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 712 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 713 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 714 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 715 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 716 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 717 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 718 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 719 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 720 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 721 { REG_ASRMCR1C, 0x0000 }, 722 }; 723 724 static const struct regmap_config fsl_asrc_regmap_config = { 725 .reg_bits = 32, 726 .reg_stride = 4, 727 .val_bits = 32, 728 729 .max_register = REG_ASRMCR1C, 730 .reg_defaults = fsl_asrc_reg, 731 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 732 .readable_reg = fsl_asrc_readable_reg, 733 .volatile_reg = fsl_asrc_volatile_reg, 734 .writeable_reg = fsl_asrc_writeable_reg, 735 .cache_type = REGCACHE_FLAT, 736 }; 737 738 /** 739 * Initialize ASRC registers with a default configurations 740 */ 741 static int fsl_asrc_init(struct fsl_asrc *asrc_priv) 742 { 743 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 744 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 745 746 /* Disable interrupt by default */ 747 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); 748 749 /* Apply recommended settings for parameters from Reference Manual */ 750 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); 751 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); 752 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); 753 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); 754 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); 755 756 /* Base address for task queue FIFO. Set to 0x7C */ 757 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, 758 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 759 760 /* Set the processing clock for 76KHz to 133M */ 761 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); 762 763 /* Set the processing clock for 56KHz to 133M */ 764 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); 765 } 766 767 /** 768 * Interrupt handler for ASRC 769 */ 770 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 771 { 772 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; 773 struct device *dev = &asrc_priv->pdev->dev; 774 enum asrc_pair_index index; 775 u32 status; 776 777 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); 778 779 /* Clean overload error */ 780 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); 781 782 /* 783 * We here use dev_dbg() for all exceptions because ASRC itself does 784 * not care if FIFO overflowed or underrun while a warning in the 785 * interrupt would result a ridged conversion. 786 */ 787 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 788 if (!asrc_priv->pair[index]) 789 continue; 790 791 if (status & ASRSTR_ATQOL) { 792 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 793 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 794 } 795 796 if (status & ASRSTR_AOOL(index)) { 797 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 798 pair_dbg("Output Task Overload\n"); 799 } 800 801 if (status & ASRSTR_AIOL(index)) { 802 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 803 pair_dbg("Input Task Overload\n"); 804 } 805 806 if (status & ASRSTR_AODO(index)) { 807 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 808 pair_dbg("Output Data Buffer has overflowed\n"); 809 } 810 811 if (status & ASRSTR_AIDU(index)) { 812 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 813 pair_dbg("Input Data Buffer has underflowed\n"); 814 } 815 } 816 817 return IRQ_HANDLED; 818 } 819 820 static int fsl_asrc_probe(struct platform_device *pdev) 821 { 822 struct device_node *np = pdev->dev.of_node; 823 struct fsl_asrc *asrc_priv; 824 struct resource *res; 825 void __iomem *regs; 826 int irq, ret, i; 827 char tmp[16]; 828 829 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 830 if (!asrc_priv) 831 return -ENOMEM; 832 833 asrc_priv->pdev = pdev; 834 835 /* Get the addresses and IRQ */ 836 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 837 regs = devm_ioremap_resource(&pdev->dev, res); 838 if (IS_ERR(regs)) 839 return PTR_ERR(regs); 840 841 asrc_priv->paddr = res->start; 842 843 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 844 &fsl_asrc_regmap_config); 845 if (IS_ERR(asrc_priv->regmap)) { 846 dev_err(&pdev->dev, "failed to init regmap\n"); 847 return PTR_ERR(asrc_priv->regmap); 848 } 849 850 irq = platform_get_irq(pdev, 0); 851 if (irq < 0) { 852 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); 853 return irq; 854 } 855 856 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 857 dev_name(&pdev->dev), asrc_priv); 858 if (ret) { 859 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 860 return ret; 861 } 862 863 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); 864 if (IS_ERR(asrc_priv->mem_clk)) { 865 dev_err(&pdev->dev, "failed to get mem clock\n"); 866 return PTR_ERR(asrc_priv->mem_clk); 867 } 868 869 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 870 if (IS_ERR(asrc_priv->ipg_clk)) { 871 dev_err(&pdev->dev, "failed to get ipg clock\n"); 872 return PTR_ERR(asrc_priv->ipg_clk); 873 } 874 875 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba"); 876 if (IS_ERR(asrc_priv->spba_clk)) 877 dev_warn(&pdev->dev, "failed to get spba clock\n"); 878 879 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 880 sprintf(tmp, "asrck_%x", i); 881 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 882 if (IS_ERR(asrc_priv->asrck_clk[i])) { 883 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 884 return PTR_ERR(asrc_priv->asrck_clk[i]); 885 } 886 } 887 888 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 889 asrc_priv->channel_bits = 3; 890 clk_map[IN] = input_clk_map_imx35; 891 clk_map[OUT] = output_clk_map_imx35; 892 } else { 893 asrc_priv->channel_bits = 4; 894 clk_map[IN] = input_clk_map_imx53; 895 clk_map[OUT] = output_clk_map_imx53; 896 } 897 898 ret = fsl_asrc_init(asrc_priv); 899 if (ret) { 900 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 901 return ret; 902 } 903 904 asrc_priv->channel_avail = 10; 905 906 ret = of_property_read_u32(np, "fsl,asrc-rate", 907 &asrc_priv->asrc_rate); 908 if (ret) { 909 dev_err(&pdev->dev, "failed to get output rate\n"); 910 return ret; 911 } 912 913 ret = of_property_read_u32(np, "fsl,asrc-width", 914 &asrc_priv->asrc_width); 915 if (ret) { 916 dev_err(&pdev->dev, "failed to get output width\n"); 917 return ret; 918 } 919 920 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { 921 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); 922 asrc_priv->asrc_width = 24; 923 } 924 925 platform_set_drvdata(pdev, asrc_priv); 926 pm_runtime_enable(&pdev->dev); 927 spin_lock_init(&asrc_priv->lock); 928 929 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 930 &fsl_asrc_dai, 1); 931 if (ret) { 932 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 933 return ret; 934 } 935 936 return 0; 937 } 938 939 #ifdef CONFIG_PM 940 static int fsl_asrc_runtime_resume(struct device *dev) 941 { 942 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 943 int i, ret; 944 945 ret = clk_prepare_enable(asrc_priv->mem_clk); 946 if (ret) 947 return ret; 948 ret = clk_prepare_enable(asrc_priv->ipg_clk); 949 if (ret) 950 goto disable_mem_clk; 951 if (!IS_ERR(asrc_priv->spba_clk)) { 952 ret = clk_prepare_enable(asrc_priv->spba_clk); 953 if (ret) 954 goto disable_ipg_clk; 955 } 956 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 957 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 958 if (ret) 959 goto disable_asrck_clk; 960 } 961 962 return 0; 963 964 disable_asrck_clk: 965 for (i--; i >= 0; i--) 966 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 967 if (!IS_ERR(asrc_priv->spba_clk)) 968 clk_disable_unprepare(asrc_priv->spba_clk); 969 disable_ipg_clk: 970 clk_disable_unprepare(asrc_priv->ipg_clk); 971 disable_mem_clk: 972 clk_disable_unprepare(asrc_priv->mem_clk); 973 return ret; 974 } 975 976 static int fsl_asrc_runtime_suspend(struct device *dev) 977 { 978 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 979 int i; 980 981 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 982 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 983 if (!IS_ERR(asrc_priv->spba_clk)) 984 clk_disable_unprepare(asrc_priv->spba_clk); 985 clk_disable_unprepare(asrc_priv->ipg_clk); 986 clk_disable_unprepare(asrc_priv->mem_clk); 987 988 return 0; 989 } 990 #endif /* CONFIG_PM */ 991 992 #ifdef CONFIG_PM_SLEEP 993 static int fsl_asrc_suspend(struct device *dev) 994 { 995 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 996 997 regmap_read(asrc_priv->regmap, REG_ASRCFG, 998 &asrc_priv->regcache_cfg); 999 1000 regcache_cache_only(asrc_priv->regmap, true); 1001 regcache_mark_dirty(asrc_priv->regmap); 1002 1003 return 0; 1004 } 1005 1006 static int fsl_asrc_resume(struct device *dev) 1007 { 1008 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1009 u32 asrctr; 1010 1011 /* Stop all pairs provisionally */ 1012 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); 1013 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1014 ASRCTR_ASRCEi_ALL_MASK, 0); 1015 1016 /* Restore all registers */ 1017 regcache_cache_only(asrc_priv->regmap, false); 1018 regcache_sync(asrc_priv->regmap); 1019 1020 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 1021 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1022 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1023 1024 /* Restart enabled pairs */ 1025 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1026 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1027 1028 return 0; 1029 } 1030 #endif /* CONFIG_PM_SLEEP */ 1031 1032 static const struct dev_pm_ops fsl_asrc_pm = { 1033 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1034 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1035 }; 1036 1037 static const struct of_device_id fsl_asrc_ids[] = { 1038 { .compatible = "fsl,imx35-asrc", }, 1039 { .compatible = "fsl,imx53-asrc", }, 1040 {} 1041 }; 1042 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1043 1044 static struct platform_driver fsl_asrc_driver = { 1045 .probe = fsl_asrc_probe, 1046 .driver = { 1047 .name = "fsl-asrc", 1048 .of_match_table = fsl_asrc_ids, 1049 .pm = &fsl_asrc_pm, 1050 }, 1051 }; 1052 module_platform_driver(fsl_asrc_driver); 1053 1054 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1055 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1056 MODULE_ALIAS("platform:fsl-asrc"); 1057 MODULE_LICENSE("GPL v2"); 1058