1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_data/dma-imx.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 23 #define pair_err(fmt, ...) \ 24 dev_err(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 25 26 #define pair_dbg(fmt, ...) \ 27 dev_dbg(&asrc->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 28 29 /* Corresponding to process_option */ 30 static unsigned int supported_asrc_rate[] = { 31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 32 64000, 88200, 96000, 128000, 176400, 192000, 33 }; 34 35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 36 .count = ARRAY_SIZE(supported_asrc_rate), 37 .list = supported_asrc_rate, 38 }; 39 40 /** 41 * The following tables map the relationship between asrc_inclk/asrc_outclk in 42 * fsl_asrc.h and the registers of ASRCSR 43 */ 44 static unsigned char input_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 46 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 47 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 48 }; 49 50 static unsigned char output_clk_map_imx35[ASRC_CLK_MAP_LEN] = { 51 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 52 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 53 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 54 }; 55 56 /* i.MX53 uses the same map for input and output */ 57 static unsigned char input_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 58 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 59 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 60 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 61 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 62 }; 63 64 static unsigned char output_clk_map_imx53[ASRC_CLK_MAP_LEN] = { 65 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 66 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 67 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 68 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 69 }; 70 71 /** 72 * i.MX8QM/i.MX8QXP uses the same map for input and output. 73 * clk_map_imx8qm[0] is for i.MX8QM asrc0 74 * clk_map_imx8qm[1] is for i.MX8QM asrc1 75 * clk_map_imx8qxp[0] is for i.MX8QXP asrc0 76 * clk_map_imx8qxp[1] is for i.MX8QXP asrc1 77 */ 78 static unsigned char clk_map_imx8qm[2][ASRC_CLK_MAP_LEN] = { 79 { 80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 81 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 82 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 83 }, 84 { 85 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 86 0x0, 0x1, 0x2, 0x3, 0xb, 0xc, 0xf, 0xf, 0xd, 0xe, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 87 0x4, 0x5, 0x6, 0xf, 0x8, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 88 }, 89 }; 90 91 static unsigned char clk_map_imx8qxp[2][ASRC_CLK_MAP_LEN] = { 92 { 93 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 94 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0xf, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xf, 95 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 96 }, 97 { 98 0xf, 0xf, 0xf, 0xf, 0xf, 0x7, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 99 0x0, 0x1, 0x2, 0x3, 0x7, 0x8, 0xf, 0xf, 0x9, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 100 0xf, 0xf, 0x6, 0xf, 0xf, 0xf, 0xa, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 101 }, 102 }; 103 104 /** 105 * Select the pre-processing and post-processing options 106 * Make sure to exclude following unsupported cases before 107 * calling this function: 108 * 1) inrate > 8.125 * outrate 109 * 2) inrate > 16.125 * outrate 110 * 111 * inrate: input sample rate 112 * outrate: output sample rate 113 * pre_proc: return value for pre-processing option 114 * post_proc: return value for post-processing option 115 */ 116 static void fsl_asrc_sel_proc(int inrate, int outrate, 117 int *pre_proc, int *post_proc) 118 { 119 bool post_proc_cond2; 120 bool post_proc_cond0; 121 122 /* select pre_proc between [0, 2] */ 123 if (inrate * 8 > 33 * outrate) 124 *pre_proc = 2; 125 else if (inrate * 8 > 15 * outrate) { 126 if (inrate > 152000) 127 *pre_proc = 2; 128 else 129 *pre_proc = 1; 130 } else if (inrate < 76000) 131 *pre_proc = 0; 132 else if (inrate > 152000) 133 *pre_proc = 2; 134 else 135 *pre_proc = 1; 136 137 /* Condition for selection of post-processing */ 138 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 139 (inrate > 56000 && outrate < 56000); 140 post_proc_cond0 = inrate * 23 < outrate * 8; 141 142 if (post_proc_cond2) 143 *post_proc = 2; 144 else if (post_proc_cond0) 145 *post_proc = 0; 146 else 147 *post_proc = 1; 148 } 149 150 /** 151 * Request ASRC pair 152 * 153 * It assigns pair by the order of A->C->B because allocation of pair B, 154 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 155 * while pair A and pair C are comparatively independent. 156 */ 157 static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 158 { 159 enum asrc_pair_index index = ASRC_INVALID_PAIR; 160 struct fsl_asrc *asrc = pair->asrc; 161 struct device *dev = &asrc->pdev->dev; 162 unsigned long lock_flags; 163 int i, ret = 0; 164 165 spin_lock_irqsave(&asrc->lock, lock_flags); 166 167 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 168 if (asrc->pair[i] != NULL) 169 continue; 170 171 index = i; 172 173 if (i != ASRC_PAIR_B) 174 break; 175 } 176 177 if (index == ASRC_INVALID_PAIR) { 178 dev_err(dev, "all pairs are busy now\n"); 179 ret = -EBUSY; 180 } else if (asrc->channel_avail < channels) { 181 dev_err(dev, "can't afford required channels: %d\n", channels); 182 ret = -EINVAL; 183 } else { 184 asrc->channel_avail -= channels; 185 asrc->pair[index] = pair; 186 pair->channels = channels; 187 pair->index = index; 188 } 189 190 spin_unlock_irqrestore(&asrc->lock, lock_flags); 191 192 return ret; 193 } 194 195 /** 196 * Release ASRC pair 197 * 198 * It clears the resource from asrc and releases the occupied channels. 199 */ 200 static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 201 { 202 struct fsl_asrc *asrc = pair->asrc; 203 enum asrc_pair_index index = pair->index; 204 unsigned long lock_flags; 205 206 /* Make sure the pair is disabled */ 207 regmap_update_bits(asrc->regmap, REG_ASRCTR, 208 ASRCTR_ASRCEi_MASK(index), 0); 209 210 spin_lock_irqsave(&asrc->lock, lock_flags); 211 212 asrc->channel_avail += pair->channels; 213 asrc->pair[index] = NULL; 214 pair->error = 0; 215 216 spin_unlock_irqrestore(&asrc->lock, lock_flags); 217 } 218 219 /** 220 * Configure input and output thresholds 221 */ 222 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 223 { 224 struct fsl_asrc *asrc = pair->asrc; 225 enum asrc_pair_index index = pair->index; 226 227 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 228 ASRMCRi_EXTTHRSHi_MASK | 229 ASRMCRi_INFIFO_THRESHOLD_MASK | 230 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 231 ASRMCRi_EXTTHRSHi | 232 ASRMCRi_INFIFO_THRESHOLD(in) | 233 ASRMCRi_OUTFIFO_THRESHOLD(out)); 234 } 235 236 /** 237 * Calculate the total divisor between asrck clock rate and sample rate 238 * 239 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 240 */ 241 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 242 { 243 u32 ps; 244 245 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 246 for (ps = 0; div > 8; ps++) 247 div >>= 1; 248 249 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 250 } 251 252 /** 253 * Calculate and set the ratio for Ideal Ratio mode only 254 * 255 * The ratio is a 32-bit fixed point value with 26 fractional bits. 256 */ 257 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 258 int inrate, int outrate) 259 { 260 struct fsl_asrc *asrc = pair->asrc; 261 enum asrc_pair_index index = pair->index; 262 unsigned long ratio; 263 int i; 264 265 if (!outrate) { 266 pair_err("output rate should not be zero\n"); 267 return -EINVAL; 268 } 269 270 /* Calculate the intergal part of the ratio */ 271 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 272 273 /* ... and then the 26 depth decimal part */ 274 inrate %= outrate; 275 276 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 277 inrate <<= 1; 278 279 if (inrate < outrate) 280 continue; 281 282 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 283 inrate -= outrate; 284 285 if (!inrate) 286 break; 287 } 288 289 regmap_write(asrc->regmap, REG_ASRIDRL(index), ratio); 290 regmap_write(asrc->regmap, REG_ASRIDRH(index), ratio >> 24); 291 292 return 0; 293 } 294 295 /** 296 * Configure the assigned ASRC pair 297 * 298 * It configures those ASRC registers according to a configuration instance 299 * of struct asrc_config which includes in/output sample rate, width, channel 300 * and clock settings. 301 * 302 * Note: 303 * The ideal ratio configuration can work with a flexible clock rate setting. 304 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC. 305 * For a regular audio playback, the clock rate should not be slower than an 306 * clock rate aligning with the output sample rate; For a use case requiring 307 * faster conversion, set use_ideal_rate to have the faster speed. 308 */ 309 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) 310 { 311 struct fsl_asrc_pair_priv *pair_priv = pair->private; 312 struct asrc_config *config = pair_priv->config; 313 struct fsl_asrc *asrc = pair->asrc; 314 struct fsl_asrc_priv *asrc_priv = asrc->private; 315 enum asrc_pair_index index = pair->index; 316 enum asrc_word_width input_word_width; 317 enum asrc_word_width output_word_width; 318 u32 inrate, outrate, indiv, outdiv; 319 u32 clk_index[2], div[2], rem[2]; 320 u64 clk_rate; 321 int in, out, channels; 322 int pre_proc, post_proc; 323 struct clk *clk; 324 bool ideal; 325 326 if (!config) { 327 pair_err("invalid pair config\n"); 328 return -EINVAL; 329 } 330 331 /* Validate channels */ 332 if (config->channel_num < 1 || config->channel_num > 10) { 333 pair_err("does not support %d channels\n", config->channel_num); 334 return -EINVAL; 335 } 336 337 switch (snd_pcm_format_width(config->input_format)) { 338 case 8: 339 input_word_width = ASRC_WIDTH_8_BIT; 340 break; 341 case 16: 342 input_word_width = ASRC_WIDTH_16_BIT; 343 break; 344 case 24: 345 input_word_width = ASRC_WIDTH_24_BIT; 346 break; 347 default: 348 pair_err("does not support this input format, %d\n", 349 config->input_format); 350 return -EINVAL; 351 } 352 353 switch (snd_pcm_format_width(config->output_format)) { 354 case 16: 355 output_word_width = ASRC_WIDTH_16_BIT; 356 break; 357 case 24: 358 output_word_width = ASRC_WIDTH_24_BIT; 359 break; 360 default: 361 pair_err("does not support this output format, %d\n", 362 config->output_format); 363 return -EINVAL; 364 } 365 366 inrate = config->input_sample_rate; 367 outrate = config->output_sample_rate; 368 ideal = config->inclk == INCLK_NONE; 369 370 /* Validate input and output sample rates */ 371 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 372 if (inrate == supported_asrc_rate[in]) 373 break; 374 375 if (in == ARRAY_SIZE(supported_asrc_rate)) { 376 pair_err("unsupported input sample rate: %dHz\n", inrate); 377 return -EINVAL; 378 } 379 380 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 381 if (outrate == supported_asrc_rate[out]) 382 break; 383 384 if (out == ARRAY_SIZE(supported_asrc_rate)) { 385 pair_err("unsupported output sample rate: %dHz\n", outrate); 386 return -EINVAL; 387 } 388 389 if ((outrate >= 5512 && outrate <= 30000) && 390 (outrate > 24 * inrate || inrate > 8 * outrate)) { 391 pair_err("exceed supported ratio range [1/24, 8] for \ 392 inrate/outrate: %d/%d\n", inrate, outrate); 393 return -EINVAL; 394 } 395 396 /* Validate input and output clock sources */ 397 clk_index[IN] = asrc_priv->clk_map[IN][config->inclk]; 398 clk_index[OUT] = asrc_priv->clk_map[OUT][config->outclk]; 399 400 /* We only have output clock for ideal ratio mode */ 401 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 402 403 clk_rate = clk_get_rate(clk); 404 rem[IN] = do_div(clk_rate, inrate); 405 div[IN] = (u32)clk_rate; 406 407 /* 408 * The divider range is [1, 1024], defined by the hardware. For non- 409 * ideal ratio configuration, clock rate has to be strictly aligned 410 * with the sample rate. For ideal ratio configuration, clock rates 411 * only result in different converting speeds. So remainder does not 412 * matter, as long as we keep the divider within its valid range. 413 */ 414 if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) { 415 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 416 inrate, clk_index[ideal ? OUT : IN]); 417 return -EINVAL; 418 } 419 420 div[IN] = min_t(u32, 1024, div[IN]); 421 422 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 423 clk_rate = clk_get_rate(clk); 424 if (ideal && use_ideal_rate) 425 rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE); 426 else 427 rem[OUT] = do_div(clk_rate, outrate); 428 div[OUT] = clk_rate; 429 430 /* Output divider has the same limitation as the input one */ 431 if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) { 432 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 433 outrate, clk_index[OUT]); 434 return -EINVAL; 435 } 436 437 div[OUT] = min_t(u32, 1024, div[OUT]); 438 439 /* Set the channel number */ 440 channels = config->channel_num; 441 442 if (asrc_priv->soc->channel_bits < 4) 443 channels /= 2; 444 445 /* Update channels for current pair */ 446 regmap_update_bits(asrc->regmap, REG_ASRCNCR, 447 ASRCNCR_ANCi_MASK(index, asrc_priv->soc->channel_bits), 448 ASRCNCR_ANCi(index, channels, asrc_priv->soc->channel_bits)); 449 450 /* Default setting: Automatic selection for processing mode */ 451 regmap_update_bits(asrc->regmap, REG_ASRCTR, 452 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 453 regmap_update_bits(asrc->regmap, REG_ASRCTR, 454 ASRCTR_USRi_MASK(index), 0); 455 456 /* Set the input and output clock sources */ 457 regmap_update_bits(asrc->regmap, REG_ASRCSR, 458 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 459 ASRCSR_AICS(index, clk_index[IN]) | 460 ASRCSR_AOCS(index, clk_index[OUT])); 461 462 /* Calculate the input clock divisors */ 463 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 464 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 465 466 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 467 regmap_update_bits(asrc->regmap, REG_ASRCDR(index), 468 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 469 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 470 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 471 472 /* Implement word_width configurations */ 473 regmap_update_bits(asrc->regmap, REG_ASRMCR1(index), 474 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 475 ASRMCR1i_OW16(output_word_width) | 476 ASRMCR1i_IWD(input_word_width)); 477 478 /* Enable BUFFER STALL */ 479 regmap_update_bits(asrc->regmap, REG_ASRMCR(index), 480 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 481 482 /* Set default thresholds for input and output FIFO */ 483 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 484 ASRC_INPUTFIFO_THRESHOLD); 485 486 /* Configure the following only for Ideal Ratio mode */ 487 if (!ideal) 488 return 0; 489 490 /* Clear ASTSx bit to use Ideal Ratio mode */ 491 regmap_update_bits(asrc->regmap, REG_ASRCTR, 492 ASRCTR_ATSi_MASK(index), 0); 493 494 /* Enable Ideal Ratio mode */ 495 regmap_update_bits(asrc->regmap, REG_ASRCTR, 496 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 497 ASRCTR_IDR(index) | ASRCTR_USR(index)); 498 499 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 500 501 /* Apply configurations for pre- and post-processing */ 502 regmap_update_bits(asrc->regmap, REG_ASRCFG, 503 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 504 ASRCFG_PREMOD(index, pre_proc) | 505 ASRCFG_POSTMOD(index, post_proc)); 506 507 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 508 } 509 510 /** 511 * Start the assigned ASRC pair 512 * 513 * It enables the assigned pair and makes it stopped at the stall level. 514 */ 515 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 516 { 517 struct fsl_asrc *asrc = pair->asrc; 518 enum asrc_pair_index index = pair->index; 519 int reg, retry = 10, i; 520 521 /* Enable the current pair */ 522 regmap_update_bits(asrc->regmap, REG_ASRCTR, 523 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 524 525 /* Wait for status of initialization */ 526 do { 527 udelay(5); 528 regmap_read(asrc->regmap, REG_ASRCFG, ®); 529 reg &= ASRCFG_INIRQi_MASK(index); 530 } while (!reg && --retry); 531 532 /* Make the input fifo to ASRC STALL level */ 533 regmap_read(asrc->regmap, REG_ASRCNCR, ®); 534 for (i = 0; i < pair->channels * 4; i++) 535 regmap_write(asrc->regmap, REG_ASRDI(index), 0); 536 537 /* Enable overload interrupt */ 538 regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE); 539 } 540 541 /** 542 * Stop the assigned ASRC pair 543 */ 544 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 545 { 546 struct fsl_asrc *asrc = pair->asrc; 547 enum asrc_pair_index index = pair->index; 548 549 /* Stop the current pair */ 550 regmap_update_bits(asrc->regmap, REG_ASRCTR, 551 ASRCTR_ASRCEi_MASK(index), 0); 552 } 553 554 /** 555 * Get DMA channel according to the pair and direction. 556 */ 557 static struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, 558 bool dir) 559 { 560 struct fsl_asrc *asrc = pair->asrc; 561 enum asrc_pair_index index = pair->index; 562 char name[4]; 563 564 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 565 566 return dma_request_slave_channel(&asrc->pdev->dev, name); 567 } 568 569 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 570 struct snd_soc_dai *dai) 571 { 572 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 573 struct fsl_asrc_priv *asrc_priv = asrc->private; 574 575 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 576 if (asrc_priv->soc->channel_bits == 3) 577 snd_pcm_hw_constraint_step(substream->runtime, 0, 578 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 579 580 581 return snd_pcm_hw_constraint_list(substream->runtime, 0, 582 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 583 } 584 585 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 586 struct snd_pcm_hw_params *params, 587 struct snd_soc_dai *dai) 588 { 589 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 590 struct snd_pcm_runtime *runtime = substream->runtime; 591 struct fsl_asrc_pair *pair = runtime->private_data; 592 struct fsl_asrc_pair_priv *pair_priv = pair->private; 593 unsigned int channels = params_channels(params); 594 unsigned int rate = params_rate(params); 595 struct asrc_config config; 596 int ret; 597 598 ret = fsl_asrc_request_pair(channels, pair); 599 if (ret) { 600 dev_err(dai->dev, "fail to request asrc pair\n"); 601 return ret; 602 } 603 604 pair_priv->config = &config; 605 606 config.pair = pair->index; 607 config.channel_num = channels; 608 config.inclk = INCLK_NONE; 609 config.outclk = OUTCLK_ASRCK1_CLK; 610 611 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 612 config.input_format = params_format(params); 613 config.output_format = asrc->asrc_format; 614 config.input_sample_rate = rate; 615 config.output_sample_rate = asrc->asrc_rate; 616 } else { 617 config.input_format = asrc->asrc_format; 618 config.output_format = params_format(params); 619 config.input_sample_rate = asrc->asrc_rate; 620 config.output_sample_rate = rate; 621 } 622 623 ret = fsl_asrc_config_pair(pair, false); 624 if (ret) { 625 dev_err(dai->dev, "fail to config asrc pair\n"); 626 return ret; 627 } 628 629 return 0; 630 } 631 632 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 633 struct snd_soc_dai *dai) 634 { 635 struct snd_pcm_runtime *runtime = substream->runtime; 636 struct fsl_asrc_pair *pair = runtime->private_data; 637 638 if (pair) 639 fsl_asrc_release_pair(pair); 640 641 return 0; 642 } 643 644 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 645 struct snd_soc_dai *dai) 646 { 647 struct snd_pcm_runtime *runtime = substream->runtime; 648 struct fsl_asrc_pair *pair = runtime->private_data; 649 650 switch (cmd) { 651 case SNDRV_PCM_TRIGGER_START: 652 case SNDRV_PCM_TRIGGER_RESUME: 653 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 654 fsl_asrc_start_pair(pair); 655 break; 656 case SNDRV_PCM_TRIGGER_STOP: 657 case SNDRV_PCM_TRIGGER_SUSPEND: 658 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 659 fsl_asrc_stop_pair(pair); 660 break; 661 default: 662 return -EINVAL; 663 } 664 665 return 0; 666 } 667 668 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 669 .startup = fsl_asrc_dai_startup, 670 .hw_params = fsl_asrc_dai_hw_params, 671 .hw_free = fsl_asrc_dai_hw_free, 672 .trigger = fsl_asrc_dai_trigger, 673 }; 674 675 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 676 { 677 struct fsl_asrc *asrc = snd_soc_dai_get_drvdata(dai); 678 679 snd_soc_dai_init_dma_data(dai, &asrc->dma_params_tx, 680 &asrc->dma_params_rx); 681 682 return 0; 683 } 684 685 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 686 SNDRV_PCM_FMTBIT_S16_LE | \ 687 SNDRV_PCM_FMTBIT_S24_3LE) 688 689 static struct snd_soc_dai_driver fsl_asrc_dai = { 690 .probe = fsl_asrc_dai_probe, 691 .playback = { 692 .stream_name = "ASRC-Playback", 693 .channels_min = 1, 694 .channels_max = 10, 695 .rate_min = 5512, 696 .rate_max = 192000, 697 .rates = SNDRV_PCM_RATE_KNOT, 698 .formats = FSL_ASRC_FORMATS | 699 SNDRV_PCM_FMTBIT_S8, 700 }, 701 .capture = { 702 .stream_name = "ASRC-Capture", 703 .channels_min = 1, 704 .channels_max = 10, 705 .rate_min = 5512, 706 .rate_max = 192000, 707 .rates = SNDRV_PCM_RATE_KNOT, 708 .formats = FSL_ASRC_FORMATS, 709 }, 710 .ops = &fsl_asrc_dai_ops, 711 }; 712 713 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 714 { 715 switch (reg) { 716 case REG_ASRCTR: 717 case REG_ASRIER: 718 case REG_ASRCNCR: 719 case REG_ASRCFG: 720 case REG_ASRCSR: 721 case REG_ASRCDR1: 722 case REG_ASRCDR2: 723 case REG_ASRSTR: 724 case REG_ASRPM1: 725 case REG_ASRPM2: 726 case REG_ASRPM3: 727 case REG_ASRPM4: 728 case REG_ASRPM5: 729 case REG_ASRTFR1: 730 case REG_ASRCCR: 731 case REG_ASRDOA: 732 case REG_ASRDOB: 733 case REG_ASRDOC: 734 case REG_ASRIDRHA: 735 case REG_ASRIDRLA: 736 case REG_ASRIDRHB: 737 case REG_ASRIDRLB: 738 case REG_ASRIDRHC: 739 case REG_ASRIDRLC: 740 case REG_ASR76K: 741 case REG_ASR56K: 742 case REG_ASRMCRA: 743 case REG_ASRFSTA: 744 case REG_ASRMCRB: 745 case REG_ASRFSTB: 746 case REG_ASRMCRC: 747 case REG_ASRFSTC: 748 case REG_ASRMCR1A: 749 case REG_ASRMCR1B: 750 case REG_ASRMCR1C: 751 return true; 752 default: 753 return false; 754 } 755 } 756 757 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 758 { 759 switch (reg) { 760 case REG_ASRSTR: 761 case REG_ASRDIA: 762 case REG_ASRDIB: 763 case REG_ASRDIC: 764 case REG_ASRDOA: 765 case REG_ASRDOB: 766 case REG_ASRDOC: 767 case REG_ASRFSTA: 768 case REG_ASRFSTB: 769 case REG_ASRFSTC: 770 case REG_ASRCFG: 771 return true; 772 default: 773 return false; 774 } 775 } 776 777 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 778 { 779 switch (reg) { 780 case REG_ASRCTR: 781 case REG_ASRIER: 782 case REG_ASRCNCR: 783 case REG_ASRCFG: 784 case REG_ASRCSR: 785 case REG_ASRCDR1: 786 case REG_ASRCDR2: 787 case REG_ASRSTR: 788 case REG_ASRPM1: 789 case REG_ASRPM2: 790 case REG_ASRPM3: 791 case REG_ASRPM4: 792 case REG_ASRPM5: 793 case REG_ASRTFR1: 794 case REG_ASRCCR: 795 case REG_ASRDIA: 796 case REG_ASRDIB: 797 case REG_ASRDIC: 798 case REG_ASRIDRHA: 799 case REG_ASRIDRLA: 800 case REG_ASRIDRHB: 801 case REG_ASRIDRLB: 802 case REG_ASRIDRHC: 803 case REG_ASRIDRLC: 804 case REG_ASR76K: 805 case REG_ASR56K: 806 case REG_ASRMCRA: 807 case REG_ASRMCRB: 808 case REG_ASRMCRC: 809 case REG_ASRMCR1A: 810 case REG_ASRMCR1B: 811 case REG_ASRMCR1C: 812 return true; 813 default: 814 return false; 815 } 816 } 817 818 static struct reg_default fsl_asrc_reg[] = { 819 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 820 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 821 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 822 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 823 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 824 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 825 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 826 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 827 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 828 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 829 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 830 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 831 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 832 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 833 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 834 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 835 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 836 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 837 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 838 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 839 { REG_ASRMCR1C, 0x0000 }, 840 }; 841 842 static const struct regmap_config fsl_asrc_regmap_config = { 843 .reg_bits = 32, 844 .reg_stride = 4, 845 .val_bits = 32, 846 847 .max_register = REG_ASRMCR1C, 848 .reg_defaults = fsl_asrc_reg, 849 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 850 .readable_reg = fsl_asrc_readable_reg, 851 .volatile_reg = fsl_asrc_volatile_reg, 852 .writeable_reg = fsl_asrc_writeable_reg, 853 .cache_type = REGCACHE_FLAT, 854 }; 855 856 /** 857 * Initialize ASRC registers with a default configurations 858 */ 859 static int fsl_asrc_init(struct fsl_asrc *asrc) 860 { 861 unsigned long ipg_rate; 862 863 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 864 regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 865 866 /* Disable interrupt by default */ 867 regmap_write(asrc->regmap, REG_ASRIER, 0x0); 868 869 /* Apply recommended settings for parameters from Reference Manual */ 870 regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff); 871 regmap_write(asrc->regmap, REG_ASRPM2, 0x255555); 872 regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280); 873 regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280); 874 regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280); 875 876 /* Base address for task queue FIFO. Set to 0x7C */ 877 regmap_update_bits(asrc->regmap, REG_ASRTFR1, 878 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 879 880 /* 881 * Set the period of the 76KHz and 56KHz sampling clocks based on 882 * the ASRC processing clock. 883 * On iMX6, ipg_clk = 133MHz, REG_ASR76K = 0x06D6, REG_ASR56K = 0x0947 884 */ 885 ipg_rate = clk_get_rate(asrc->ipg_clk); 886 regmap_write(asrc->regmap, REG_ASR76K, ipg_rate / 76000); 887 return regmap_write(asrc->regmap, REG_ASR56K, ipg_rate / 56000); 888 } 889 890 /** 891 * Interrupt handler for ASRC 892 */ 893 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 894 { 895 struct fsl_asrc *asrc = (struct fsl_asrc *)dev_id; 896 struct device *dev = &asrc->pdev->dev; 897 enum asrc_pair_index index; 898 u32 status; 899 900 regmap_read(asrc->regmap, REG_ASRSTR, &status); 901 902 /* Clean overload error */ 903 regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE); 904 905 /* 906 * We here use dev_dbg() for all exceptions because ASRC itself does 907 * not care if FIFO overflowed or underrun while a warning in the 908 * interrupt would result a ridged conversion. 909 */ 910 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 911 if (!asrc->pair[index]) 912 continue; 913 914 if (status & ASRSTR_ATQOL) { 915 asrc->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 916 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 917 } 918 919 if (status & ASRSTR_AOOL(index)) { 920 asrc->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 921 pair_dbg("Output Task Overload\n"); 922 } 923 924 if (status & ASRSTR_AIOL(index)) { 925 asrc->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 926 pair_dbg("Input Task Overload\n"); 927 } 928 929 if (status & ASRSTR_AODO(index)) { 930 asrc->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 931 pair_dbg("Output Data Buffer has overflowed\n"); 932 } 933 934 if (status & ASRSTR_AIDU(index)) { 935 asrc->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 936 pair_dbg("Input Data Buffer has underflowed\n"); 937 } 938 } 939 940 return IRQ_HANDLED; 941 } 942 943 static int fsl_asrc_get_fifo_addr(u8 dir, enum asrc_pair_index index) 944 { 945 return REG_ASRDx(dir, index); 946 } 947 948 static int fsl_asrc_probe(struct platform_device *pdev) 949 { 950 struct device_node *np = pdev->dev.of_node; 951 struct fsl_asrc_priv *asrc_priv; 952 struct fsl_asrc *asrc; 953 struct resource *res; 954 void __iomem *regs; 955 int irq, ret, i; 956 u32 map_idx; 957 char tmp[16]; 958 u32 width; 959 960 asrc = devm_kzalloc(&pdev->dev, sizeof(*asrc), GFP_KERNEL); 961 if (!asrc) 962 return -ENOMEM; 963 964 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 965 if (!asrc_priv) 966 return -ENOMEM; 967 968 asrc->pdev = pdev; 969 asrc->private = asrc_priv; 970 971 /* Get the addresses and IRQ */ 972 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 973 regs = devm_ioremap_resource(&pdev->dev, res); 974 if (IS_ERR(regs)) 975 return PTR_ERR(regs); 976 977 asrc->paddr = res->start; 978 979 asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 980 &fsl_asrc_regmap_config); 981 if (IS_ERR(asrc->regmap)) { 982 dev_err(&pdev->dev, "failed to init regmap\n"); 983 return PTR_ERR(asrc->regmap); 984 } 985 986 irq = platform_get_irq(pdev, 0); 987 if (irq < 0) 988 return irq; 989 990 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 991 dev_name(&pdev->dev), asrc); 992 if (ret) { 993 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 994 return ret; 995 } 996 997 asrc->mem_clk = devm_clk_get(&pdev->dev, "mem"); 998 if (IS_ERR(asrc->mem_clk)) { 999 dev_err(&pdev->dev, "failed to get mem clock\n"); 1000 return PTR_ERR(asrc->mem_clk); 1001 } 1002 1003 asrc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 1004 if (IS_ERR(asrc->ipg_clk)) { 1005 dev_err(&pdev->dev, "failed to get ipg clock\n"); 1006 return PTR_ERR(asrc->ipg_clk); 1007 } 1008 1009 asrc->spba_clk = devm_clk_get(&pdev->dev, "spba"); 1010 if (IS_ERR(asrc->spba_clk)) 1011 dev_warn(&pdev->dev, "failed to get spba clock\n"); 1012 1013 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1014 sprintf(tmp, "asrck_%x", i); 1015 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 1016 if (IS_ERR(asrc_priv->asrck_clk[i])) { 1017 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 1018 return PTR_ERR(asrc_priv->asrck_clk[i]); 1019 } 1020 } 1021 1022 asrc_priv->soc = of_device_get_match_data(&pdev->dev); 1023 if (!asrc_priv->soc) { 1024 dev_err(&pdev->dev, "failed to get soc data\n"); 1025 return -ENODEV; 1026 } 1027 1028 asrc->use_edma = asrc_priv->soc->use_edma; 1029 asrc->get_dma_channel = fsl_asrc_get_dma_channel; 1030 asrc->request_pair = fsl_asrc_request_pair; 1031 asrc->release_pair = fsl_asrc_release_pair; 1032 asrc->get_fifo_addr = fsl_asrc_get_fifo_addr; 1033 asrc->pair_priv_size = sizeof(struct fsl_asrc_pair_priv); 1034 1035 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 1036 asrc_priv->clk_map[IN] = input_clk_map_imx35; 1037 asrc_priv->clk_map[OUT] = output_clk_map_imx35; 1038 } else if (of_device_is_compatible(np, "fsl,imx53-asrc")) { 1039 asrc_priv->clk_map[IN] = input_clk_map_imx53; 1040 asrc_priv->clk_map[OUT] = output_clk_map_imx53; 1041 } else if (of_device_is_compatible(np, "fsl,imx8qm-asrc") || 1042 of_device_is_compatible(np, "fsl,imx8qxp-asrc")) { 1043 ret = of_property_read_u32(np, "fsl,asrc-clk-map", &map_idx); 1044 if (ret) { 1045 dev_err(&pdev->dev, "failed to get clk map index\n"); 1046 return ret; 1047 } 1048 1049 if (map_idx > 1) { 1050 dev_err(&pdev->dev, "unsupported clk map index\n"); 1051 return -EINVAL; 1052 } 1053 if (of_device_is_compatible(np, "fsl,imx8qm-asrc")) { 1054 asrc_priv->clk_map[IN] = clk_map_imx8qm[map_idx]; 1055 asrc_priv->clk_map[OUT] = clk_map_imx8qm[map_idx]; 1056 } else { 1057 asrc_priv->clk_map[IN] = clk_map_imx8qxp[map_idx]; 1058 asrc_priv->clk_map[OUT] = clk_map_imx8qxp[map_idx]; 1059 } 1060 } 1061 1062 ret = fsl_asrc_init(asrc); 1063 if (ret) { 1064 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 1065 return ret; 1066 } 1067 1068 asrc->channel_avail = 10; 1069 1070 ret = of_property_read_u32(np, "fsl,asrc-rate", 1071 &asrc->asrc_rate); 1072 if (ret) { 1073 dev_err(&pdev->dev, "failed to get output rate\n"); 1074 return ret; 1075 } 1076 1077 ret = of_property_read_u32(np, "fsl,asrc-format", &asrc->asrc_format); 1078 if (ret) { 1079 ret = of_property_read_u32(np, "fsl,asrc-width", &width); 1080 if (ret) { 1081 dev_err(&pdev->dev, "failed to decide output format\n"); 1082 return ret; 1083 } 1084 1085 switch (width) { 1086 case 16: 1087 asrc->asrc_format = SNDRV_PCM_FORMAT_S16_LE; 1088 break; 1089 case 24: 1090 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1091 break; 1092 default: 1093 dev_warn(&pdev->dev, 1094 "unsupported width, use default S24_LE\n"); 1095 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1096 break; 1097 } 1098 } 1099 1100 if (!(FSL_ASRC_FORMATS & (1ULL << asrc->asrc_format))) { 1101 dev_warn(&pdev->dev, "unsupported width, use default S24_LE\n"); 1102 asrc->asrc_format = SNDRV_PCM_FORMAT_S24_LE; 1103 } 1104 1105 platform_set_drvdata(pdev, asrc); 1106 pm_runtime_enable(&pdev->dev); 1107 spin_lock_init(&asrc->lock); 1108 regcache_cache_only(asrc->regmap, true); 1109 1110 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 1111 &fsl_asrc_dai, 1); 1112 if (ret) { 1113 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 1114 return ret; 1115 } 1116 1117 return 0; 1118 } 1119 1120 #ifdef CONFIG_PM 1121 static int fsl_asrc_runtime_resume(struct device *dev) 1122 { 1123 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1124 struct fsl_asrc_priv *asrc_priv = asrc->private; 1125 int i, ret; 1126 u32 asrctr; 1127 1128 ret = clk_prepare_enable(asrc->mem_clk); 1129 if (ret) 1130 return ret; 1131 ret = clk_prepare_enable(asrc->ipg_clk); 1132 if (ret) 1133 goto disable_mem_clk; 1134 if (!IS_ERR(asrc->spba_clk)) { 1135 ret = clk_prepare_enable(asrc->spba_clk); 1136 if (ret) 1137 goto disable_ipg_clk; 1138 } 1139 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1140 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1141 if (ret) 1142 goto disable_asrck_clk; 1143 } 1144 1145 /* Stop all pairs provisionally */ 1146 regmap_read(asrc->regmap, REG_ASRCTR, &asrctr); 1147 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1148 ASRCTR_ASRCEi_ALL_MASK, 0); 1149 1150 /* Restore all registers */ 1151 regcache_cache_only(asrc->regmap, false); 1152 regcache_mark_dirty(asrc->regmap); 1153 regcache_sync(asrc->regmap); 1154 1155 regmap_update_bits(asrc->regmap, REG_ASRCFG, 1156 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1157 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1158 1159 /* Restart enabled pairs */ 1160 regmap_update_bits(asrc->regmap, REG_ASRCTR, 1161 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1162 1163 return 0; 1164 1165 disable_asrck_clk: 1166 for (i--; i >= 0; i--) 1167 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1168 if (!IS_ERR(asrc->spba_clk)) 1169 clk_disable_unprepare(asrc->spba_clk); 1170 disable_ipg_clk: 1171 clk_disable_unprepare(asrc->ipg_clk); 1172 disable_mem_clk: 1173 clk_disable_unprepare(asrc->mem_clk); 1174 return ret; 1175 } 1176 1177 static int fsl_asrc_runtime_suspend(struct device *dev) 1178 { 1179 struct fsl_asrc *asrc = dev_get_drvdata(dev); 1180 struct fsl_asrc_priv *asrc_priv = asrc->private; 1181 int i; 1182 1183 regmap_read(asrc->regmap, REG_ASRCFG, 1184 &asrc_priv->regcache_cfg); 1185 1186 regcache_cache_only(asrc->regmap, true); 1187 1188 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1189 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1190 if (!IS_ERR(asrc->spba_clk)) 1191 clk_disable_unprepare(asrc->spba_clk); 1192 clk_disable_unprepare(asrc->ipg_clk); 1193 clk_disable_unprepare(asrc->mem_clk); 1194 1195 return 0; 1196 } 1197 #endif /* CONFIG_PM */ 1198 1199 static const struct dev_pm_ops fsl_asrc_pm = { 1200 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1201 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1202 pm_runtime_force_resume) 1203 }; 1204 1205 static const struct fsl_asrc_soc_data fsl_asrc_imx35_data = { 1206 .use_edma = false, 1207 .channel_bits = 3, 1208 }; 1209 1210 static const struct fsl_asrc_soc_data fsl_asrc_imx53_data = { 1211 .use_edma = false, 1212 .channel_bits = 4, 1213 }; 1214 1215 static const struct fsl_asrc_soc_data fsl_asrc_imx8qm_data = { 1216 .use_edma = true, 1217 .channel_bits = 4, 1218 }; 1219 1220 static const struct fsl_asrc_soc_data fsl_asrc_imx8qxp_data = { 1221 .use_edma = true, 1222 .channel_bits = 4, 1223 }; 1224 1225 static const struct of_device_id fsl_asrc_ids[] = { 1226 { .compatible = "fsl,imx35-asrc", .data = &fsl_asrc_imx35_data }, 1227 { .compatible = "fsl,imx53-asrc", .data = &fsl_asrc_imx53_data }, 1228 { .compatible = "fsl,imx8qm-asrc", .data = &fsl_asrc_imx8qm_data }, 1229 { .compatible = "fsl,imx8qxp-asrc", .data = &fsl_asrc_imx8qxp_data }, 1230 {} 1231 }; 1232 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1233 1234 static struct platform_driver fsl_asrc_driver = { 1235 .probe = fsl_asrc_probe, 1236 .driver = { 1237 .name = "fsl-asrc", 1238 .of_match_table = fsl_asrc_ids, 1239 .pm = &fsl_asrc_pm, 1240 }, 1241 }; 1242 module_platform_driver(fsl_asrc_driver); 1243 1244 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1245 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1246 MODULE_ALIAS("platform:fsl-asrc"); 1247 MODULE_LICENSE("GPL v2"); 1248