1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver 4 // 5 // Copyright (C) 2014 Freescale Semiconductor, Inc. 6 // 7 // Author: Nicolin Chen <nicoleotsuka@gmail.com> 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_data/dma-imx.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/dmaengine_pcm.h> 17 #include <sound/pcm_params.h> 18 19 #include "fsl_asrc.h" 20 21 #define IDEAL_RATIO_DECIMAL_DEPTH 26 22 23 #define pair_err(fmt, ...) \ 24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 25 26 #define pair_dbg(fmt, ...) \ 27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__) 28 29 /* Corresponding to process_option */ 30 static unsigned int supported_asrc_rate[] = { 31 5512, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 32 64000, 88200, 96000, 128000, 176400, 192000, 33 }; 34 35 static struct snd_pcm_hw_constraint_list fsl_asrc_rate_constraints = { 36 .count = ARRAY_SIZE(supported_asrc_rate), 37 .list = supported_asrc_rate, 38 }; 39 40 /** 41 * The following tables map the relationship between asrc_inclk/asrc_outclk in 42 * fsl_asrc.h and the registers of ASRCSR 43 */ 44 static unsigned char input_clk_map_imx35[] = { 45 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 46 }; 47 48 static unsigned char output_clk_map_imx35[] = { 49 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 50 }; 51 52 /* i.MX53 uses the same map for input and output */ 53 static unsigned char input_clk_map_imx53[] = { 54 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 55 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd, 56 }; 57 58 static unsigned char output_clk_map_imx53[] = { 59 /* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */ 60 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd, 61 }; 62 63 static unsigned char *clk_map[2]; 64 65 /** 66 * Select the pre-processing and post-processing options 67 * Make sure to exclude following unsupported cases before 68 * calling this function: 69 * 1) inrate > 8.125 * outrate 70 * 2) inrate > 16.125 * outrate 71 * 72 * inrate: input sample rate 73 * outrate: output sample rate 74 * pre_proc: return value for pre-processing option 75 * post_proc: return value for post-processing option 76 */ 77 static void fsl_asrc_sel_proc(int inrate, int outrate, 78 int *pre_proc, int *post_proc) 79 { 80 bool post_proc_cond2; 81 bool post_proc_cond0; 82 83 /* select pre_proc between [0, 2] */ 84 if (inrate * 8 > 33 * outrate) 85 *pre_proc = 2; 86 else if (inrate * 8 > 15 * outrate) { 87 if (inrate > 152000) 88 *pre_proc = 2; 89 else 90 *pre_proc = 1; 91 } else if (inrate < 76000) 92 *pre_proc = 0; 93 else if (inrate > 152000) 94 *pre_proc = 2; 95 else 96 *pre_proc = 1; 97 98 /* Condition for selection of post-processing */ 99 post_proc_cond2 = (inrate * 15 > outrate * 16 && outrate < 56000) || 100 (inrate > 56000 && outrate < 56000); 101 post_proc_cond0 = inrate * 23 < outrate * 8; 102 103 if (post_proc_cond2) 104 *post_proc = 2; 105 else if (post_proc_cond0) 106 *post_proc = 0; 107 else 108 *post_proc = 1; 109 } 110 111 /** 112 * Request ASRC pair 113 * 114 * It assigns pair by the order of A->C->B because allocation of pair B, 115 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A 116 * while pair A and pair C are comparatively independent. 117 */ 118 int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair) 119 { 120 enum asrc_pair_index index = ASRC_INVALID_PAIR; 121 struct fsl_asrc *asrc_priv = pair->asrc_priv; 122 struct device *dev = &asrc_priv->pdev->dev; 123 unsigned long lock_flags; 124 int i, ret = 0; 125 126 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 127 128 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) { 129 if (asrc_priv->pair[i] != NULL) 130 continue; 131 132 index = i; 133 134 if (i != ASRC_PAIR_B) 135 break; 136 } 137 138 if (index == ASRC_INVALID_PAIR) { 139 dev_err(dev, "all pairs are busy now\n"); 140 ret = -EBUSY; 141 } else if (asrc_priv->channel_avail < channels) { 142 dev_err(dev, "can't afford required channels: %d\n", channels); 143 ret = -EINVAL; 144 } else { 145 asrc_priv->channel_avail -= channels; 146 asrc_priv->pair[index] = pair; 147 pair->channels = channels; 148 pair->index = index; 149 } 150 151 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 152 153 return ret; 154 } 155 156 /** 157 * Release ASRC pair 158 * 159 * It clears the resource from asrc_priv and releases the occupied channels. 160 */ 161 void fsl_asrc_release_pair(struct fsl_asrc_pair *pair) 162 { 163 struct fsl_asrc *asrc_priv = pair->asrc_priv; 164 enum asrc_pair_index index = pair->index; 165 unsigned long lock_flags; 166 167 /* Make sure the pair is disabled */ 168 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 169 ASRCTR_ASRCEi_MASK(index), 0); 170 171 spin_lock_irqsave(&asrc_priv->lock, lock_flags); 172 173 asrc_priv->channel_avail += pair->channels; 174 asrc_priv->pair[index] = NULL; 175 pair->error = 0; 176 177 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags); 178 } 179 180 /** 181 * Configure input and output thresholds 182 */ 183 static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out) 184 { 185 struct fsl_asrc *asrc_priv = pair->asrc_priv; 186 enum asrc_pair_index index = pair->index; 187 188 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 189 ASRMCRi_EXTTHRSHi_MASK | 190 ASRMCRi_INFIFO_THRESHOLD_MASK | 191 ASRMCRi_OUTFIFO_THRESHOLD_MASK, 192 ASRMCRi_EXTTHRSHi | 193 ASRMCRi_INFIFO_THRESHOLD(in) | 194 ASRMCRi_OUTFIFO_THRESHOLD(out)); 195 } 196 197 /** 198 * Calculate the total divisor between asrck clock rate and sample rate 199 * 200 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider 201 */ 202 static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div) 203 { 204 u32 ps; 205 206 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */ 207 for (ps = 0; div > 8; ps++) 208 div >>= 1; 209 210 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps; 211 } 212 213 /** 214 * Calculate and set the ratio for Ideal Ratio mode only 215 * 216 * The ratio is a 32-bit fixed point value with 26 fractional bits. 217 */ 218 static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair, 219 int inrate, int outrate) 220 { 221 struct fsl_asrc *asrc_priv = pair->asrc_priv; 222 enum asrc_pair_index index = pair->index; 223 unsigned long ratio; 224 int i; 225 226 if (!outrate) { 227 pair_err("output rate should not be zero\n"); 228 return -EINVAL; 229 } 230 231 /* Calculate the intergal part of the ratio */ 232 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH; 233 234 /* ... and then the 26 depth decimal part */ 235 inrate %= outrate; 236 237 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) { 238 inrate <<= 1; 239 240 if (inrate < outrate) 241 continue; 242 243 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i); 244 inrate -= outrate; 245 246 if (!inrate) 247 break; 248 } 249 250 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio); 251 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24); 252 253 return 0; 254 } 255 256 /** 257 * Configure the assigned ASRC pair 258 * 259 * It configures those ASRC registers according to a configuration instance 260 * of struct asrc_config which includes in/output sample rate, width, channel 261 * and clock settings. 262 * 263 * Note: 264 * The ideal ratio configuration can work with a flexible clock rate setting. 265 * Using IDEAL_RATIO_RATE gives a faster converting speed but overloads ASRC. 266 * For a regular audio playback, the clock rate should not be slower than an 267 * clock rate aligning with the output sample rate; For a use case requiring 268 * faster conversion, set use_ideal_rate to have the faster speed. 269 */ 270 static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate) 271 { 272 struct asrc_config *config = pair->config; 273 struct fsl_asrc *asrc_priv = pair->asrc_priv; 274 enum asrc_pair_index index = pair->index; 275 enum asrc_word_width input_word_width; 276 enum asrc_word_width output_word_width; 277 u32 inrate, outrate, indiv, outdiv; 278 u32 clk_index[2], div[2], rem[2]; 279 u64 clk_rate; 280 int in, out, channels; 281 int pre_proc, post_proc; 282 struct clk *clk; 283 bool ideal; 284 285 if (!config) { 286 pair_err("invalid pair config\n"); 287 return -EINVAL; 288 } 289 290 /* Validate channels */ 291 if (config->channel_num < 1 || config->channel_num > 10) { 292 pair_err("does not support %d channels\n", config->channel_num); 293 return -EINVAL; 294 } 295 296 switch (snd_pcm_format_width(config->input_format)) { 297 case 8: 298 input_word_width = ASRC_WIDTH_8_BIT; 299 break; 300 case 16: 301 input_word_width = ASRC_WIDTH_16_BIT; 302 break; 303 case 24: 304 input_word_width = ASRC_WIDTH_24_BIT; 305 break; 306 default: 307 pair_err("does not support this input format, %d\n", 308 config->input_format); 309 return -EINVAL; 310 } 311 312 switch (snd_pcm_format_width(config->output_format)) { 313 case 16: 314 output_word_width = ASRC_WIDTH_16_BIT; 315 break; 316 case 24: 317 output_word_width = ASRC_WIDTH_24_BIT; 318 break; 319 default: 320 pair_err("does not support this output format, %d\n", 321 config->output_format); 322 return -EINVAL; 323 } 324 325 inrate = config->input_sample_rate; 326 outrate = config->output_sample_rate; 327 ideal = config->inclk == INCLK_NONE; 328 329 /* Validate input and output sample rates */ 330 for (in = 0; in < ARRAY_SIZE(supported_asrc_rate); in++) 331 if (inrate == supported_asrc_rate[in]) 332 break; 333 334 if (in == ARRAY_SIZE(supported_asrc_rate)) { 335 pair_err("unsupported input sample rate: %dHz\n", inrate); 336 return -EINVAL; 337 } 338 339 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++) 340 if (outrate == supported_asrc_rate[out]) 341 break; 342 343 if (out == ARRAY_SIZE(supported_asrc_rate)) { 344 pair_err("unsupported output sample rate: %dHz\n", outrate); 345 return -EINVAL; 346 } 347 348 if ((outrate >= 5512 && outrate <= 30000) && 349 (outrate > 24 * inrate || inrate > 8 * outrate)) { 350 pair_err("exceed supported ratio range [1/24, 8] for \ 351 inrate/outrate: %d/%d\n", inrate, outrate); 352 return -EINVAL; 353 } 354 355 /* Validate input and output clock sources */ 356 clk_index[IN] = clk_map[IN][config->inclk]; 357 clk_index[OUT] = clk_map[OUT][config->outclk]; 358 359 /* We only have output clock for ideal ratio mode */ 360 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]]; 361 362 clk_rate = clk_get_rate(clk); 363 rem[IN] = do_div(clk_rate, inrate); 364 div[IN] = (u32)clk_rate; 365 366 /* 367 * The divider range is [1, 1024], defined by the hardware. For non- 368 * ideal ratio configuration, clock rate has to be strictly aligned 369 * with the sample rate. For ideal ratio configuration, clock rates 370 * only result in different converting speeds. So remainder does not 371 * matter, as long as we keep the divider within its valid range. 372 */ 373 if (div[IN] == 0 || (!ideal && (div[IN] > 1024 || rem[IN] != 0))) { 374 pair_err("failed to support input sample rate %dHz by asrck_%x\n", 375 inrate, clk_index[ideal ? OUT : IN]); 376 return -EINVAL; 377 } 378 379 div[IN] = min_t(u32, 1024, div[IN]); 380 381 clk = asrc_priv->asrck_clk[clk_index[OUT]]; 382 clk_rate = clk_get_rate(clk); 383 if (ideal && use_ideal_rate) 384 rem[OUT] = do_div(clk_rate, IDEAL_RATIO_RATE); 385 else 386 rem[OUT] = do_div(clk_rate, outrate); 387 div[OUT] = clk_rate; 388 389 /* Output divider has the same limitation as the input one */ 390 if (div[OUT] == 0 || (!ideal && (div[OUT] > 1024 || rem[OUT] != 0))) { 391 pair_err("failed to support output sample rate %dHz by asrck_%x\n", 392 outrate, clk_index[OUT]); 393 return -EINVAL; 394 } 395 396 div[OUT] = min_t(u32, 1024, div[OUT]); 397 398 /* Set the channel number */ 399 channels = config->channel_num; 400 401 if (asrc_priv->channel_bits < 4) 402 channels /= 2; 403 404 /* Update channels for current pair */ 405 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR, 406 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits), 407 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits)); 408 409 /* Default setting: Automatic selection for processing mode */ 410 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 411 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index)); 412 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 413 ASRCTR_USRi_MASK(index), 0); 414 415 /* Set the input and output clock sources */ 416 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR, 417 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index), 418 ASRCSR_AICS(index, clk_index[IN]) | 419 ASRCSR_AOCS(index, clk_index[OUT])); 420 421 /* Calculate the input clock divisors */ 422 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]); 423 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]); 424 425 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */ 426 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index), 427 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) | 428 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index), 429 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv)); 430 431 /* Implement word_width configurations */ 432 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index), 433 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK, 434 ASRMCR1i_OW16(output_word_width) | 435 ASRMCR1i_IWD(input_word_width)); 436 437 /* Enable BUFFER STALL */ 438 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index), 439 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi); 440 441 /* Set default thresholds for input and output FIFO */ 442 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD, 443 ASRC_INPUTFIFO_THRESHOLD); 444 445 /* Configure the following only for Ideal Ratio mode */ 446 if (!ideal) 447 return 0; 448 449 /* Clear ASTSx bit to use Ideal Ratio mode */ 450 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 451 ASRCTR_ATSi_MASK(index), 0); 452 453 /* Enable Ideal Ratio mode */ 454 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 455 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index), 456 ASRCTR_IDR(index) | ASRCTR_USR(index)); 457 458 fsl_asrc_sel_proc(inrate, outrate, &pre_proc, &post_proc); 459 460 /* Apply configurations for pre- and post-processing */ 461 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 462 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index), 463 ASRCFG_PREMOD(index, pre_proc) | 464 ASRCFG_POSTMOD(index, post_proc)); 465 466 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate); 467 } 468 469 /** 470 * Start the assigned ASRC pair 471 * 472 * It enables the assigned pair and makes it stopped at the stall level. 473 */ 474 static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair) 475 { 476 struct fsl_asrc *asrc_priv = pair->asrc_priv; 477 enum asrc_pair_index index = pair->index; 478 int reg, retry = 10, i; 479 480 /* Enable the current pair */ 481 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 482 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index)); 483 484 /* Wait for status of initialization */ 485 do { 486 udelay(5); 487 regmap_read(asrc_priv->regmap, REG_ASRCFG, ®); 488 reg &= ASRCFG_INIRQi_MASK(index); 489 } while (!reg && --retry); 490 491 /* Make the input fifo to ASRC STALL level */ 492 regmap_read(asrc_priv->regmap, REG_ASRCNCR, ®); 493 for (i = 0; i < pair->channels * 4; i++) 494 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0); 495 496 /* Enable overload interrupt */ 497 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE); 498 } 499 500 /** 501 * Stop the assigned ASRC pair 502 */ 503 static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair) 504 { 505 struct fsl_asrc *asrc_priv = pair->asrc_priv; 506 enum asrc_pair_index index = pair->index; 507 508 /* Stop the current pair */ 509 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 510 ASRCTR_ASRCEi_MASK(index), 0); 511 } 512 513 /** 514 * Get DMA channel according to the pair and direction. 515 */ 516 struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir) 517 { 518 struct fsl_asrc *asrc_priv = pair->asrc_priv; 519 enum asrc_pair_index index = pair->index; 520 char name[4]; 521 522 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a'); 523 524 return dma_request_slave_channel(&asrc_priv->pdev->dev, name); 525 } 526 EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel); 527 528 static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream, 529 struct snd_soc_dai *dai) 530 { 531 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 532 533 /* Odd channel number is not valid for older ASRC (channel_bits==3) */ 534 if (asrc_priv->channel_bits == 3) 535 snd_pcm_hw_constraint_step(substream->runtime, 0, 536 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 537 538 539 return snd_pcm_hw_constraint_list(substream->runtime, 0, 540 SNDRV_PCM_HW_PARAM_RATE, &fsl_asrc_rate_constraints); 541 } 542 543 static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream, 544 struct snd_pcm_hw_params *params, 545 struct snd_soc_dai *dai) 546 { 547 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 548 struct snd_pcm_runtime *runtime = substream->runtime; 549 struct fsl_asrc_pair *pair = runtime->private_data; 550 unsigned int channels = params_channels(params); 551 unsigned int rate = params_rate(params); 552 struct asrc_config config; 553 snd_pcm_format_t format; 554 int ret; 555 556 ret = fsl_asrc_request_pair(channels, pair); 557 if (ret) { 558 dev_err(dai->dev, "fail to request asrc pair\n"); 559 return ret; 560 } 561 562 pair->config = &config; 563 564 if (asrc_priv->asrc_width == 16) 565 format = SNDRV_PCM_FORMAT_S16_LE; 566 else 567 format = SNDRV_PCM_FORMAT_S24_LE; 568 569 config.pair = pair->index; 570 config.channel_num = channels; 571 config.inclk = INCLK_NONE; 572 config.outclk = OUTCLK_ASRCK1_CLK; 573 574 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 575 config.input_format = params_format(params); 576 config.output_format = format; 577 config.input_sample_rate = rate; 578 config.output_sample_rate = asrc_priv->asrc_rate; 579 } else { 580 config.input_format = format; 581 config.output_format = params_format(params); 582 config.input_sample_rate = asrc_priv->asrc_rate; 583 config.output_sample_rate = rate; 584 } 585 586 ret = fsl_asrc_config_pair(pair, false); 587 if (ret) { 588 dev_err(dai->dev, "fail to config asrc pair\n"); 589 return ret; 590 } 591 592 return 0; 593 } 594 595 static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream, 596 struct snd_soc_dai *dai) 597 { 598 struct snd_pcm_runtime *runtime = substream->runtime; 599 struct fsl_asrc_pair *pair = runtime->private_data; 600 601 if (pair) 602 fsl_asrc_release_pair(pair); 603 604 return 0; 605 } 606 607 static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd, 608 struct snd_soc_dai *dai) 609 { 610 struct snd_pcm_runtime *runtime = substream->runtime; 611 struct fsl_asrc_pair *pair = runtime->private_data; 612 613 switch (cmd) { 614 case SNDRV_PCM_TRIGGER_START: 615 case SNDRV_PCM_TRIGGER_RESUME: 616 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 617 fsl_asrc_start_pair(pair); 618 break; 619 case SNDRV_PCM_TRIGGER_STOP: 620 case SNDRV_PCM_TRIGGER_SUSPEND: 621 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 622 fsl_asrc_stop_pair(pair); 623 break; 624 default: 625 return -EINVAL; 626 } 627 628 return 0; 629 } 630 631 static const struct snd_soc_dai_ops fsl_asrc_dai_ops = { 632 .startup = fsl_asrc_dai_startup, 633 .hw_params = fsl_asrc_dai_hw_params, 634 .hw_free = fsl_asrc_dai_hw_free, 635 .trigger = fsl_asrc_dai_trigger, 636 }; 637 638 static int fsl_asrc_dai_probe(struct snd_soc_dai *dai) 639 { 640 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai); 641 642 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx, 643 &asrc_priv->dma_params_rx); 644 645 return 0; 646 } 647 648 #define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \ 649 SNDRV_PCM_FMTBIT_S16_LE | \ 650 SNDRV_PCM_FMTBIT_S24_3LE) 651 652 static struct snd_soc_dai_driver fsl_asrc_dai = { 653 .probe = fsl_asrc_dai_probe, 654 .playback = { 655 .stream_name = "ASRC-Playback", 656 .channels_min = 1, 657 .channels_max = 10, 658 .rate_min = 5512, 659 .rate_max = 192000, 660 .rates = SNDRV_PCM_RATE_KNOT, 661 .formats = FSL_ASRC_FORMATS | 662 SNDRV_PCM_FMTBIT_S8, 663 }, 664 .capture = { 665 .stream_name = "ASRC-Capture", 666 .channels_min = 1, 667 .channels_max = 10, 668 .rate_min = 5512, 669 .rate_max = 192000, 670 .rates = SNDRV_PCM_RATE_KNOT, 671 .formats = FSL_ASRC_FORMATS, 672 }, 673 .ops = &fsl_asrc_dai_ops, 674 }; 675 676 static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg) 677 { 678 switch (reg) { 679 case REG_ASRCTR: 680 case REG_ASRIER: 681 case REG_ASRCNCR: 682 case REG_ASRCFG: 683 case REG_ASRCSR: 684 case REG_ASRCDR1: 685 case REG_ASRCDR2: 686 case REG_ASRSTR: 687 case REG_ASRPM1: 688 case REG_ASRPM2: 689 case REG_ASRPM3: 690 case REG_ASRPM4: 691 case REG_ASRPM5: 692 case REG_ASRTFR1: 693 case REG_ASRCCR: 694 case REG_ASRDOA: 695 case REG_ASRDOB: 696 case REG_ASRDOC: 697 case REG_ASRIDRHA: 698 case REG_ASRIDRLA: 699 case REG_ASRIDRHB: 700 case REG_ASRIDRLB: 701 case REG_ASRIDRHC: 702 case REG_ASRIDRLC: 703 case REG_ASR76K: 704 case REG_ASR56K: 705 case REG_ASRMCRA: 706 case REG_ASRFSTA: 707 case REG_ASRMCRB: 708 case REG_ASRFSTB: 709 case REG_ASRMCRC: 710 case REG_ASRFSTC: 711 case REG_ASRMCR1A: 712 case REG_ASRMCR1B: 713 case REG_ASRMCR1C: 714 return true; 715 default: 716 return false; 717 } 718 } 719 720 static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg) 721 { 722 switch (reg) { 723 case REG_ASRSTR: 724 case REG_ASRDIA: 725 case REG_ASRDIB: 726 case REG_ASRDIC: 727 case REG_ASRDOA: 728 case REG_ASRDOB: 729 case REG_ASRDOC: 730 case REG_ASRFSTA: 731 case REG_ASRFSTB: 732 case REG_ASRFSTC: 733 case REG_ASRCFG: 734 return true; 735 default: 736 return false; 737 } 738 } 739 740 static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) 741 { 742 switch (reg) { 743 case REG_ASRCTR: 744 case REG_ASRIER: 745 case REG_ASRCNCR: 746 case REG_ASRCFG: 747 case REG_ASRCSR: 748 case REG_ASRCDR1: 749 case REG_ASRCDR2: 750 case REG_ASRSTR: 751 case REG_ASRPM1: 752 case REG_ASRPM2: 753 case REG_ASRPM3: 754 case REG_ASRPM4: 755 case REG_ASRPM5: 756 case REG_ASRTFR1: 757 case REG_ASRCCR: 758 case REG_ASRDIA: 759 case REG_ASRDIB: 760 case REG_ASRDIC: 761 case REG_ASRIDRHA: 762 case REG_ASRIDRLA: 763 case REG_ASRIDRHB: 764 case REG_ASRIDRLB: 765 case REG_ASRIDRHC: 766 case REG_ASRIDRLC: 767 case REG_ASR76K: 768 case REG_ASR56K: 769 case REG_ASRMCRA: 770 case REG_ASRMCRB: 771 case REG_ASRMCRC: 772 case REG_ASRMCR1A: 773 case REG_ASRMCR1B: 774 case REG_ASRMCR1C: 775 return true; 776 default: 777 return false; 778 } 779 } 780 781 static struct reg_default fsl_asrc_reg[] = { 782 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 }, 783 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 }, 784 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 }, 785 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 }, 786 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 }, 787 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 }, 788 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 }, 789 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 }, 790 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 }, 791 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 }, 792 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 }, 793 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 }, 794 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 }, 795 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 }, 796 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 }, 797 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 }, 798 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 }, 799 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 }, 800 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 }, 801 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 }, 802 { REG_ASRMCR1C, 0x0000 }, 803 }; 804 805 static const struct regmap_config fsl_asrc_regmap_config = { 806 .reg_bits = 32, 807 .reg_stride = 4, 808 .val_bits = 32, 809 810 .max_register = REG_ASRMCR1C, 811 .reg_defaults = fsl_asrc_reg, 812 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg), 813 .readable_reg = fsl_asrc_readable_reg, 814 .volatile_reg = fsl_asrc_volatile_reg, 815 .writeable_reg = fsl_asrc_writeable_reg, 816 .cache_type = REGCACHE_FLAT, 817 }; 818 819 /** 820 * Initialize ASRC registers with a default configurations 821 */ 822 static int fsl_asrc_init(struct fsl_asrc *asrc_priv) 823 { 824 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */ 825 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN); 826 827 /* Disable interrupt by default */ 828 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0); 829 830 /* Apply recommended settings for parameters from Reference Manual */ 831 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff); 832 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555); 833 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280); 834 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280); 835 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280); 836 837 /* Base address for task queue FIFO. Set to 0x7C */ 838 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1, 839 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc)); 840 841 /* Set the processing clock for 76KHz to 133M */ 842 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6); 843 844 /* Set the processing clock for 56KHz to 133M */ 845 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947); 846 } 847 848 /** 849 * Interrupt handler for ASRC 850 */ 851 static irqreturn_t fsl_asrc_isr(int irq, void *dev_id) 852 { 853 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id; 854 struct device *dev = &asrc_priv->pdev->dev; 855 enum asrc_pair_index index; 856 u32 status; 857 858 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status); 859 860 /* Clean overload error */ 861 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE); 862 863 /* 864 * We here use dev_dbg() for all exceptions because ASRC itself does 865 * not care if FIFO overflowed or underrun while a warning in the 866 * interrupt would result a ridged conversion. 867 */ 868 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) { 869 if (!asrc_priv->pair[index]) 870 continue; 871 872 if (status & ASRSTR_ATQOL) { 873 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD; 874 dev_dbg(dev, "ASRC Task Queue FIFO overload\n"); 875 } 876 877 if (status & ASRSTR_AOOL(index)) { 878 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD; 879 pair_dbg("Output Task Overload\n"); 880 } 881 882 if (status & ASRSTR_AIOL(index)) { 883 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD; 884 pair_dbg("Input Task Overload\n"); 885 } 886 887 if (status & ASRSTR_AODO(index)) { 888 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW; 889 pair_dbg("Output Data Buffer has overflowed\n"); 890 } 891 892 if (status & ASRSTR_AIDU(index)) { 893 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN; 894 pair_dbg("Input Data Buffer has underflowed\n"); 895 } 896 } 897 898 return IRQ_HANDLED; 899 } 900 901 static int fsl_asrc_probe(struct platform_device *pdev) 902 { 903 struct device_node *np = pdev->dev.of_node; 904 struct fsl_asrc *asrc_priv; 905 struct resource *res; 906 void __iomem *regs; 907 int irq, ret, i; 908 char tmp[16]; 909 910 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL); 911 if (!asrc_priv) 912 return -ENOMEM; 913 914 asrc_priv->pdev = pdev; 915 916 /* Get the addresses and IRQ */ 917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 918 regs = devm_ioremap_resource(&pdev->dev, res); 919 if (IS_ERR(regs)) 920 return PTR_ERR(regs); 921 922 asrc_priv->paddr = res->start; 923 924 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, 925 &fsl_asrc_regmap_config); 926 if (IS_ERR(asrc_priv->regmap)) { 927 dev_err(&pdev->dev, "failed to init regmap\n"); 928 return PTR_ERR(asrc_priv->regmap); 929 } 930 931 irq = platform_get_irq(pdev, 0); 932 if (irq < 0) 933 return irq; 934 935 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0, 936 dev_name(&pdev->dev), asrc_priv); 937 if (ret) { 938 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret); 939 return ret; 940 } 941 942 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem"); 943 if (IS_ERR(asrc_priv->mem_clk)) { 944 dev_err(&pdev->dev, "failed to get mem clock\n"); 945 return PTR_ERR(asrc_priv->mem_clk); 946 } 947 948 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 949 if (IS_ERR(asrc_priv->ipg_clk)) { 950 dev_err(&pdev->dev, "failed to get ipg clock\n"); 951 return PTR_ERR(asrc_priv->ipg_clk); 952 } 953 954 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba"); 955 if (IS_ERR(asrc_priv->spba_clk)) 956 dev_warn(&pdev->dev, "failed to get spba clock\n"); 957 958 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 959 sprintf(tmp, "asrck_%x", i); 960 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp); 961 if (IS_ERR(asrc_priv->asrck_clk[i])) { 962 dev_err(&pdev->dev, "failed to get %s clock\n", tmp); 963 return PTR_ERR(asrc_priv->asrck_clk[i]); 964 } 965 } 966 967 if (of_device_is_compatible(np, "fsl,imx35-asrc")) { 968 asrc_priv->channel_bits = 3; 969 clk_map[IN] = input_clk_map_imx35; 970 clk_map[OUT] = output_clk_map_imx35; 971 } else { 972 asrc_priv->channel_bits = 4; 973 clk_map[IN] = input_clk_map_imx53; 974 clk_map[OUT] = output_clk_map_imx53; 975 } 976 977 ret = fsl_asrc_init(asrc_priv); 978 if (ret) { 979 dev_err(&pdev->dev, "failed to init asrc %d\n", ret); 980 return ret; 981 } 982 983 asrc_priv->channel_avail = 10; 984 985 ret = of_property_read_u32(np, "fsl,asrc-rate", 986 &asrc_priv->asrc_rate); 987 if (ret) { 988 dev_err(&pdev->dev, "failed to get output rate\n"); 989 return ret; 990 } 991 992 ret = of_property_read_u32(np, "fsl,asrc-width", 993 &asrc_priv->asrc_width); 994 if (ret) { 995 dev_err(&pdev->dev, "failed to get output width\n"); 996 return ret; 997 } 998 999 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) { 1000 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n"); 1001 asrc_priv->asrc_width = 24; 1002 } 1003 1004 platform_set_drvdata(pdev, asrc_priv); 1005 pm_runtime_enable(&pdev->dev); 1006 spin_lock_init(&asrc_priv->lock); 1007 1008 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component, 1009 &fsl_asrc_dai, 1); 1010 if (ret) { 1011 dev_err(&pdev->dev, "failed to register ASoC DAI\n"); 1012 return ret; 1013 } 1014 1015 return 0; 1016 } 1017 1018 #ifdef CONFIG_PM 1019 static int fsl_asrc_runtime_resume(struct device *dev) 1020 { 1021 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1022 int i, ret; 1023 1024 ret = clk_prepare_enable(asrc_priv->mem_clk); 1025 if (ret) 1026 return ret; 1027 ret = clk_prepare_enable(asrc_priv->ipg_clk); 1028 if (ret) 1029 goto disable_mem_clk; 1030 if (!IS_ERR(asrc_priv->spba_clk)) { 1031 ret = clk_prepare_enable(asrc_priv->spba_clk); 1032 if (ret) 1033 goto disable_ipg_clk; 1034 } 1035 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) { 1036 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]); 1037 if (ret) 1038 goto disable_asrck_clk; 1039 } 1040 1041 return 0; 1042 1043 disable_asrck_clk: 1044 for (i--; i >= 0; i--) 1045 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1046 if (!IS_ERR(asrc_priv->spba_clk)) 1047 clk_disable_unprepare(asrc_priv->spba_clk); 1048 disable_ipg_clk: 1049 clk_disable_unprepare(asrc_priv->ipg_clk); 1050 disable_mem_clk: 1051 clk_disable_unprepare(asrc_priv->mem_clk); 1052 return ret; 1053 } 1054 1055 static int fsl_asrc_runtime_suspend(struct device *dev) 1056 { 1057 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1058 int i; 1059 1060 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) 1061 clk_disable_unprepare(asrc_priv->asrck_clk[i]); 1062 if (!IS_ERR(asrc_priv->spba_clk)) 1063 clk_disable_unprepare(asrc_priv->spba_clk); 1064 clk_disable_unprepare(asrc_priv->ipg_clk); 1065 clk_disable_unprepare(asrc_priv->mem_clk); 1066 1067 return 0; 1068 } 1069 #endif /* CONFIG_PM */ 1070 1071 #ifdef CONFIG_PM_SLEEP 1072 static int fsl_asrc_suspend(struct device *dev) 1073 { 1074 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1075 1076 regmap_read(asrc_priv->regmap, REG_ASRCFG, 1077 &asrc_priv->regcache_cfg); 1078 1079 regcache_cache_only(asrc_priv->regmap, true); 1080 regcache_mark_dirty(asrc_priv->regmap); 1081 1082 return 0; 1083 } 1084 1085 static int fsl_asrc_resume(struct device *dev) 1086 { 1087 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev); 1088 u32 asrctr; 1089 1090 /* Stop all pairs provisionally */ 1091 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr); 1092 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1093 ASRCTR_ASRCEi_ALL_MASK, 0); 1094 1095 /* Restore all registers */ 1096 regcache_cache_only(asrc_priv->regmap, false); 1097 regcache_sync(asrc_priv->regmap); 1098 1099 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG, 1100 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK | 1101 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg); 1102 1103 /* Restart enabled pairs */ 1104 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR, 1105 ASRCTR_ASRCEi_ALL_MASK, asrctr); 1106 1107 return 0; 1108 } 1109 #endif /* CONFIG_PM_SLEEP */ 1110 1111 static const struct dev_pm_ops fsl_asrc_pm = { 1112 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL) 1113 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume) 1114 }; 1115 1116 static const struct of_device_id fsl_asrc_ids[] = { 1117 { .compatible = "fsl,imx35-asrc", }, 1118 { .compatible = "fsl,imx53-asrc", }, 1119 {} 1120 }; 1121 MODULE_DEVICE_TABLE(of, fsl_asrc_ids); 1122 1123 static struct platform_driver fsl_asrc_driver = { 1124 .probe = fsl_asrc_probe, 1125 .driver = { 1126 .name = "fsl-asrc", 1127 .of_match_table = fsl_asrc_ids, 1128 .pm = &fsl_asrc_pm, 1129 }, 1130 }; 1131 module_platform_driver(fsl_asrc_driver); 1132 1133 MODULE_DESCRIPTION("Freescale ASRC ASoC driver"); 1134 MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>"); 1135 MODULE_ALIAS("platform:fsl-asrc"); 1136 MODULE_LICENSE("GPL v2"); 1137