xref: /openbmc/linux/sound/soc/dwc/dwc-i2s.c (revision c4c3c32d)
1 /*
2  * ALSA SoC Synopsys I2S Audio Layer
3  *
4  * sound/soc/dwc/designware_i2s.c
5  *
6  * Copyright (C) 2010 ST Microelectronics
7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/io.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/pm_runtime.h>
23 #include <sound/designware_i2s.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/dmaengine_pcm.h>
28 #include "local.h"
29 
30 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
31 {
32 	writel(val, io_base + reg);
33 }
34 
35 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
36 {
37 	return readl(io_base + reg);
38 }
39 
40 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
41 {
42 	u32 i = 0;
43 
44 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
45 		for (i = 0; i < 4; i++)
46 			i2s_write_reg(dev->i2s_base, TER(i), 0);
47 	} else {
48 		for (i = 0; i < 4; i++)
49 			i2s_write_reg(dev->i2s_base, RER(i), 0);
50 	}
51 }
52 
53 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
54 {
55 	u32 i = 0;
56 
57 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
58 		for (i = 0; i < 4; i++)
59 			i2s_read_reg(dev->i2s_base, TOR(i));
60 	} else {
61 		for (i = 0; i < 4; i++)
62 			i2s_read_reg(dev->i2s_base, ROR(i));
63 	}
64 }
65 
66 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream,
67 				    int chan_nr)
68 {
69 	u32 i, irq;
70 
71 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
72 		for (i = 0; i < (chan_nr / 2); i++) {
73 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
74 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
75 		}
76 	} else {
77 		for (i = 0; i < (chan_nr / 2); i++) {
78 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
79 			i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
80 		}
81 	}
82 }
83 
84 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream,
85 				   int chan_nr)
86 {
87 	u32 i, irq;
88 
89 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
90 		for (i = 0; i < (chan_nr / 2); i++) {
91 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
92 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
93 		}
94 	} else {
95 		for (i = 0; i < (chan_nr / 2); i++) {
96 			irq = i2s_read_reg(dev->i2s_base, IMR(i));
97 			i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
98 		}
99 	}
100 }
101 
102 static irqreturn_t i2s_irq_handler(int irq, void *dev_id)
103 {
104 	struct dw_i2s_dev *dev = dev_id;
105 	bool irq_valid = false;
106 	u32 isr[4];
107 	int i;
108 
109 	for (i = 0; i < 4; i++)
110 		isr[i] = i2s_read_reg(dev->i2s_base, ISR(i));
111 
112 	i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK);
113 	i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE);
114 
115 	for (i = 0; i < 4; i++) {
116 		/*
117 		 * Check if TX fifo is empty. If empty fill FIFO with samples
118 		 * NOTE: Only two channels supported
119 		 */
120 		if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) {
121 			dw_pcm_push_tx(dev);
122 			irq_valid = true;
123 		}
124 
125 		/*
126 		 * Data available. Retrieve samples from FIFO
127 		 * NOTE: Only two channels supported
128 		 */
129 		if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) {
130 			dw_pcm_pop_rx(dev);
131 			irq_valid = true;
132 		}
133 
134 		/* Error Handling: TX */
135 		if (isr[i] & ISR_TXFO) {
136 			dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i);
137 			irq_valid = true;
138 		}
139 
140 		/* Error Handling: TX */
141 		if (isr[i] & ISR_RXFO) {
142 			dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i);
143 			irq_valid = true;
144 		}
145 	}
146 
147 	if (irq_valid)
148 		return IRQ_HANDLED;
149 	else
150 		return IRQ_NONE;
151 }
152 
153 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream)
154 {
155 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
156 
157 	/* Enable DMA handshake for stream */
158 	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
159 		dma_reg |= I2S_DMAEN_TXBLOCK;
160 	else
161 		dma_reg |= I2S_DMAEN_RXBLOCK;
162 
163 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
164 }
165 
166 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream)
167 {
168 	u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR);
169 
170 	/* Disable DMA handshake for stream */
171 	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
172 		dma_reg &= ~I2S_DMAEN_TXBLOCK;
173 		i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1);
174 	} else {
175 		dma_reg &= ~I2S_DMAEN_RXBLOCK;
176 		i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1);
177 	}
178 	i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg);
179 }
180 
181 static void i2s_start(struct dw_i2s_dev *dev,
182 		      struct snd_pcm_substream *substream)
183 {
184 	struct i2s_clk_config_data *config = &dev->config;
185 
186 	u32 reg = IER_IEN;
187 
188 	if (dev->tdm_slots) {
189 		reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT;
190 		reg |= IER_INTF_TYPE;
191 		reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT;
192 	}
193 
194 	i2s_write_reg(dev->i2s_base, IER, reg);
195 
196 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
197 		i2s_write_reg(dev->i2s_base, ITER, 1);
198 	else
199 		i2s_write_reg(dev->i2s_base, IRER, 1);
200 
201 	if (dev->use_pio)
202 		i2s_enable_irqs(dev, substream->stream, config->chan_nr);
203 	else
204 		i2s_enable_dma(dev, substream->stream);
205 
206 	i2s_write_reg(dev->i2s_base, CER, 1);
207 }
208 
209 static void i2s_stop(struct dw_i2s_dev *dev,
210 		struct snd_pcm_substream *substream)
211 {
212 
213 	i2s_clear_irqs(dev, substream->stream);
214 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
215 		i2s_write_reg(dev->i2s_base, ITER, 0);
216 	else
217 		i2s_write_reg(dev->i2s_base, IRER, 0);
218 
219 	if (dev->use_pio)
220 		i2s_disable_irqs(dev, substream->stream, 8);
221 	else
222 		i2s_disable_dma(dev, substream->stream);
223 
224 	if (!dev->active) {
225 		i2s_write_reg(dev->i2s_base, CER, 0);
226 		i2s_write_reg(dev->i2s_base, IER, 0);
227 	}
228 }
229 
230 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
231 {
232 	u32 ch_reg;
233 	struct i2s_clk_config_data *config = &dev->config;
234 
235 
236 	i2s_disable_channels(dev, stream);
237 
238 	for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
239 		if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
240 			i2s_write_reg(dev->i2s_base, TCR(ch_reg),
241 				      dev->xfer_resolution);
242 			i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
243 				      dev->fifo_th - 1);
244 			i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN |
245 				      dev->tdm_mask << TER_TXSLOT_SHIFT);
246 		} else {
247 			i2s_write_reg(dev->i2s_base, RCR(ch_reg),
248 				      dev->xfer_resolution);
249 			i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
250 				      dev->fifo_th - 1);
251 			i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN |
252 				      dev->tdm_mask << RER_RXSLOT_SHIFT);
253 		}
254 
255 	}
256 }
257 
258 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
259 		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
260 {
261 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
262 	struct i2s_clk_config_data *config = &dev->config;
263 	int ret;
264 
265 	switch (params_format(params)) {
266 	case SNDRV_PCM_FORMAT_S16_LE:
267 		config->data_width = 16;
268 		dev->ccr = 0x00;
269 		dev->xfer_resolution = 0x02;
270 		break;
271 
272 	case SNDRV_PCM_FORMAT_S24_LE:
273 		config->data_width = 24;
274 		dev->ccr = 0x08;
275 		dev->xfer_resolution = 0x04;
276 		break;
277 
278 	case SNDRV_PCM_FORMAT_S32_LE:
279 		config->data_width = 32;
280 		dev->ccr = 0x10;
281 		dev->xfer_resolution = 0x05;
282 		break;
283 
284 	default:
285 		dev_err(dev->dev, "designware-i2s: unsupported PCM fmt");
286 		return -EINVAL;
287 	}
288 
289 	if (dev->tdm_slots)
290 		config->data_width = 32;
291 
292 	config->chan_nr = params_channels(params);
293 
294 	switch (config->chan_nr) {
295 	case EIGHT_CHANNEL_SUPPORT:
296 	case SIX_CHANNEL_SUPPORT:
297 	case FOUR_CHANNEL_SUPPORT:
298 	case TWO_CHANNEL_SUPPORT:
299 		break;
300 	default:
301 		dev_err(dev->dev, "channel not supported\n");
302 		return -EINVAL;
303 	}
304 
305 	dw_i2s_config(dev, substream->stream);
306 
307 	i2s_write_reg(dev->i2s_base, CCR, dev->ccr);
308 
309 	config->sample_rate = params_rate(params);
310 
311 	if (dev->capability & DW_I2S_MASTER) {
312 		if (dev->i2s_clk_cfg) {
313 			ret = dev->i2s_clk_cfg(config);
314 			if (ret < 0) {
315 				dev_err(dev->dev, "runtime audio clk config fail\n");
316 				return ret;
317 			}
318 		} else {
319 			u32 bitclk = config->sample_rate *
320 					config->data_width * 2;
321 
322 			ret = clk_set_rate(dev->clk, bitclk);
323 			if (ret) {
324 				dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
325 					ret);
326 				return ret;
327 			}
328 		}
329 	}
330 	return 0;
331 }
332 
333 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
334 			  struct snd_soc_dai *dai)
335 {
336 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
337 
338 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
339 		i2s_write_reg(dev->i2s_base, TXFFR, 1);
340 	else
341 		i2s_write_reg(dev->i2s_base, RXFFR, 1);
342 
343 	return 0;
344 }
345 
346 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
347 		int cmd, struct snd_soc_dai *dai)
348 {
349 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
350 	int ret = 0;
351 
352 	switch (cmd) {
353 	case SNDRV_PCM_TRIGGER_START:
354 	case SNDRV_PCM_TRIGGER_RESUME:
355 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
356 		dev->active++;
357 		i2s_start(dev, substream);
358 		break;
359 
360 	case SNDRV_PCM_TRIGGER_STOP:
361 	case SNDRV_PCM_TRIGGER_SUSPEND:
362 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
363 		dev->active--;
364 		i2s_stop(dev, substream);
365 		break;
366 	default:
367 		ret = -EINVAL;
368 		break;
369 	}
370 	return ret;
371 }
372 
373 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
374 {
375 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
376 	int ret = 0;
377 
378 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
379 	case SND_SOC_DAIFMT_BC_FC:
380 		if (dev->capability & DW_I2S_SLAVE)
381 			ret = 0;
382 		else
383 			ret = -EINVAL;
384 		break;
385 	case SND_SOC_DAIFMT_BP_FP:
386 		if (dev->capability & DW_I2S_MASTER)
387 			ret = 0;
388 		else
389 			ret = -EINVAL;
390 		break;
391 	case SND_SOC_DAIFMT_BC_FP:
392 	case SND_SOC_DAIFMT_BP_FC:
393 		ret = -EINVAL;
394 		break;
395 	default:
396 		dev_dbg(dev->dev, "dwc : Invalid clock provider format\n");
397 		ret = -EINVAL;
398 		break;
399 	}
400 
401 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
402 	case SND_SOC_DAIFMT_I2S:
403 	case SND_SOC_DAIFMT_LEFT_J:
404 	case SND_SOC_DAIFMT_RIGHT_J:
405 		break;
406 	case SND_SOC_DAIFMT_DSP_A:
407 		dev->frame_offset = 1;
408 		break;
409 	case SND_SOC_DAIFMT_DSP_B:
410 		dev->frame_offset = 0;
411 		break;
412 	default:
413 		dev_err(dev->dev, "DAI format unsupported");
414 		return -EINVAL;
415 	}
416 
417 	return ret;
418 }
419 
420 static int dw_i2s_set_tdm_slot(struct snd_soc_dai *cpu_dai,	unsigned int tx_mask,
421 			   unsigned int rx_mask, int slots, int slot_width)
422 {
423 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
424 
425 	if (slot_width != 32)
426 		return -EINVAL;
427 
428 	if (slots < 0 || slots > 16)
429 		return -EINVAL;
430 
431 	if (rx_mask != tx_mask)
432 		return -EINVAL;
433 
434 	if (!rx_mask)
435 		return -EINVAL;
436 
437 	dev->tdm_slots = slots;
438 	dev->tdm_mask = rx_mask;
439 
440 	dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1);
441 	dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1);
442 
443 	return 0;
444 }
445 
446 static int dw_i2s_dai_probe(struct snd_soc_dai *dai)
447 {
448 	struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
449 
450 	snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data);
451 	return 0;
452 }
453 
454 static const struct snd_soc_dai_ops dw_i2s_dai_ops = {
455 	.probe		= dw_i2s_dai_probe,
456 	.hw_params	= dw_i2s_hw_params,
457 	.prepare	= dw_i2s_prepare,
458 	.trigger	= dw_i2s_trigger,
459 	.set_fmt	= dw_i2s_set_fmt,
460 	.set_tdm_slot	= dw_i2s_set_tdm_slot,
461 };
462 
463 #ifdef CONFIG_PM
464 static int dw_i2s_runtime_suspend(struct device *dev)
465 {
466 	struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
467 
468 	if (dw_dev->capability & DW_I2S_MASTER)
469 		clk_disable(dw_dev->clk);
470 	return 0;
471 }
472 
473 static int dw_i2s_runtime_resume(struct device *dev)
474 {
475 	struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev);
476 	int ret;
477 
478 	if (dw_dev->capability & DW_I2S_MASTER) {
479 		ret = clk_enable(dw_dev->clk);
480 		if (ret)
481 			return ret;
482 	}
483 	return 0;
484 }
485 
486 static int dw_i2s_suspend(struct snd_soc_component *component)
487 {
488 	struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
489 
490 	if (dev->capability & DW_I2S_MASTER)
491 		clk_disable(dev->clk);
492 	return 0;
493 }
494 
495 static int dw_i2s_resume(struct snd_soc_component *component)
496 {
497 	struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component);
498 	struct snd_soc_dai *dai;
499 	int stream, ret;
500 
501 	if (dev->capability & DW_I2S_MASTER) {
502 		ret = clk_enable(dev->clk);
503 		if (ret)
504 			return ret;
505 	}
506 
507 	for_each_component_dais(component, dai) {
508 		for_each_pcm_streams(stream)
509 			if (snd_soc_dai_stream_active(dai, stream))
510 				dw_i2s_config(dev, stream);
511 	}
512 
513 	return 0;
514 }
515 
516 #else
517 #define dw_i2s_suspend	NULL
518 #define dw_i2s_resume	NULL
519 #endif
520 
521 static const struct snd_soc_component_driver dw_i2s_component = {
522 	.name			= "dw-i2s",
523 	.suspend		= dw_i2s_suspend,
524 	.resume			= dw_i2s_resume,
525 	.legacy_dai_naming	= 1,
526 };
527 
528 /*
529  * The following tables allow a direct lookup of various parameters
530  * defined in the I2S block's configuration in terms of sound system
531  * parameters.  Each table is sized to the number of entries possible
532  * according to the number of configuration bits describing an I2S
533  * block parameter.
534  */
535 
536 /* Maximum bit resolution of a channel - not uniformly spaced */
537 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
538 	12, 16, 20, 24, 32, 0, 0, 0
539 };
540 
541 /* Width of (DMA) bus */
542 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
543 	DMA_SLAVE_BUSWIDTH_1_BYTE,
544 	DMA_SLAVE_BUSWIDTH_2_BYTES,
545 	DMA_SLAVE_BUSWIDTH_4_BYTES,
546 	DMA_SLAVE_BUSWIDTH_UNDEFINED
547 };
548 
549 /* PCM format to support channel resolution */
550 static const u32 formats[COMP_MAX_WORDSIZE] = {
551 	SNDRV_PCM_FMTBIT_S16_LE,
552 	SNDRV_PCM_FMTBIT_S16_LE,
553 	SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
554 	SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
555 	SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
556 	0,
557 	0,
558 	0
559 };
560 
561 static int dw_configure_dai(struct dw_i2s_dev *dev,
562 				   struct snd_soc_dai_driver *dw_i2s_dai,
563 				   unsigned int rates)
564 {
565 	/*
566 	 * Read component parameter registers to extract
567 	 * the I2S block's configuration.
568 	 */
569 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
570 	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);
571 	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
572 	u32 idx;
573 
574 	if (dev->capability & DWC_I2S_RECORD &&
575 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
576 		comp1 = comp1 & ~BIT(5);
577 
578 	if (dev->capability & DWC_I2S_PLAY &&
579 			dev->quirks & DW_I2S_QUIRK_COMP_PARAM1)
580 		comp1 = comp1 & ~BIT(6);
581 
582 	if (COMP1_TX_ENABLED(comp1)) {
583 		dev_dbg(dev->dev, " designware: play supported\n");
584 		idx = COMP1_TX_WORDSIZE_0(comp1);
585 		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
586 			return -EINVAL;
587 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
588 			idx = 1;
589 		dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
590 		dw_i2s_dai->playback.channels_max =
591 				1 << (COMP1_TX_CHANNELS(comp1) + 1);
592 		dw_i2s_dai->playback.formats = formats[idx];
593 		dw_i2s_dai->playback.rates = rates;
594 	}
595 
596 	if (COMP1_RX_ENABLED(comp1)) {
597 		dev_dbg(dev->dev, "designware: record supported\n");
598 		idx = COMP2_RX_WORDSIZE_0(comp2);
599 		if (WARN_ON(idx >= ARRAY_SIZE(formats)))
600 			return -EINVAL;
601 		if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
602 			idx = 1;
603 		dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
604 		dw_i2s_dai->capture.channels_max =
605 				1 << (COMP1_RX_CHANNELS(comp1) + 1);
606 		dw_i2s_dai->capture.formats = formats[idx];
607 		dw_i2s_dai->capture.rates = rates;
608 	}
609 
610 	if (COMP1_MODE_EN(comp1)) {
611 		dev_dbg(dev->dev, "designware: i2s master mode supported\n");
612 		dev->capability |= DW_I2S_MASTER;
613 	} else {
614 		dev_dbg(dev->dev, "designware: i2s slave mode supported\n");
615 		dev->capability |= DW_I2S_SLAVE;
616 	}
617 
618 	dev->fifo_th = fifo_depth / 2;
619 	return 0;
620 }
621 
622 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
623 				   struct snd_soc_dai_driver *dw_i2s_dai,
624 				   struct resource *res,
625 				   const struct i2s_platform_data *pdata)
626 {
627 	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);
628 	u32 idx = COMP1_APB_DATA_WIDTH(comp1);
629 	int ret;
630 
631 	if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
632 		return -EINVAL;
633 
634 	ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
635 	if (ret < 0)
636 		return ret;
637 
638 	if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE)
639 		idx = 1;
640 	/* Set DMA slaves info */
641 	dev->play_dma_data.pd.data = pdata->play_dma_data;
642 	dev->capture_dma_data.pd.data = pdata->capture_dma_data;
643 	dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
644 	dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
645 	dev->play_dma_data.pd.max_burst = 16;
646 	dev->capture_dma_data.pd.max_burst = 16;
647 	dev->play_dma_data.pd.addr_width = bus_widths[idx];
648 	dev->capture_dma_data.pd.addr_width = bus_widths[idx];
649 	dev->play_dma_data.pd.filter = pdata->filter;
650 	dev->capture_dma_data.pd.filter = pdata->filter;
651 
652 	return 0;
653 }
654 
655 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
656 				   struct snd_soc_dai_driver *dw_i2s_dai,
657 				   struct resource *res)
658 {
659 	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
660 	u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
661 	u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
662 	u32 idx2;
663 	int ret;
664 
665 	ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
666 	if (ret < 0)
667 		return ret;
668 
669 	if (COMP1_TX_ENABLED(comp1)) {
670 		idx2 = COMP1_TX_WORDSIZE_0(comp1);
671 
672 		dev->capability |= DWC_I2S_PLAY;
673 		dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
674 		dev->play_dma_data.dt.fifo_size = fifo_depth *
675 			(fifo_width[idx2]) >> 8;
676 		dev->play_dma_data.dt.maxburst = 16;
677 	}
678 	if (COMP1_RX_ENABLED(comp1)) {
679 		idx2 = COMP2_RX_WORDSIZE_0(comp2);
680 
681 		dev->capability |= DWC_I2S_RECORD;
682 		dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
683 		dev->capture_dma_data.dt.fifo_size = fifo_depth *
684 			(fifo_width[idx2] >> 8);
685 		dev->capture_dma_data.dt.maxburst = 16;
686 	}
687 
688 	return 0;
689 
690 }
691 
692 static int dw_i2s_probe(struct platform_device *pdev)
693 {
694 	const struct i2s_platform_data *pdata = pdev->dev.platform_data;
695 	struct dw_i2s_dev *dev;
696 	struct resource *res;
697 	int ret, irq;
698 	struct snd_soc_dai_driver *dw_i2s_dai;
699 	const char *clk_id;
700 
701 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
702 	if (!dev)
703 		return -ENOMEM;
704 
705 	dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
706 	if (!dw_i2s_dai)
707 		return -ENOMEM;
708 
709 	dw_i2s_dai->ops = &dw_i2s_dai_ops;
710 
711 	dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
712 	if (IS_ERR(dev->i2s_base))
713 		return PTR_ERR(dev->i2s_base);
714 
715 	dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev);
716 	if (IS_ERR(dev->reset))
717 		return PTR_ERR(dev->reset);
718 
719 	ret = reset_control_deassert(dev->reset);
720 	if (ret)
721 		return ret;
722 
723 	dev->dev = &pdev->dev;
724 
725 	irq = platform_get_irq_optional(pdev, 0);
726 	if (irq >= 0) {
727 		ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0,
728 				pdev->name, dev);
729 		if (ret < 0) {
730 			dev_err(&pdev->dev, "failed to request irq\n");
731 			goto err_assert_reset;
732 		}
733 	}
734 
735 	dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;
736 	dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;
737 	if (pdata) {
738 		dev->capability = pdata->cap;
739 		clk_id = NULL;
740 		dev->quirks = pdata->quirks;
741 		if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {
742 			dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;
743 			dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;
744 		}
745 		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
746 	} else {
747 		clk_id = "i2sclk";
748 		ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
749 	}
750 	if (ret < 0)
751 		goto err_assert_reset;
752 
753 	if (dev->capability & DW_I2S_MASTER) {
754 		if (pdata) {
755 			dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
756 			if (!dev->i2s_clk_cfg) {
757 				dev_err(&pdev->dev, "no clock configure method\n");
758 				ret = -ENODEV;
759 				goto err_assert_reset;
760 			}
761 		}
762 		dev->clk = devm_clk_get(&pdev->dev, clk_id);
763 
764 		if (IS_ERR(dev->clk)) {
765 			ret = PTR_ERR(dev->clk);
766 			goto err_assert_reset;
767 		}
768 
769 		ret = clk_prepare_enable(dev->clk);
770 		if (ret < 0)
771 			goto err_assert_reset;
772 	}
773 
774 	dev_set_drvdata(&pdev->dev, dev);
775 	ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
776 					 dw_i2s_dai, 1);
777 	if (ret != 0) {
778 		dev_err(&pdev->dev, "not able to register dai\n");
779 		goto err_clk_disable;
780 	}
781 
782 	if (!pdata) {
783 		if (irq >= 0) {
784 			ret = dw_pcm_register(pdev);
785 			dev->use_pio = true;
786 			dev->l_reg = LRBR_LTHR(0);
787 			dev->r_reg = RRBR_RTHR(0);
788 		} else {
789 			ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
790 					0);
791 			dev->use_pio = false;
792 		}
793 
794 		if (ret) {
795 			dev_err(&pdev->dev, "could not register pcm: %d\n",
796 					ret);
797 			goto err_clk_disable;
798 		}
799 	}
800 
801 	pm_runtime_enable(&pdev->dev);
802 	return 0;
803 
804 err_clk_disable:
805 	if (dev->capability & DW_I2S_MASTER)
806 		clk_disable_unprepare(dev->clk);
807 err_assert_reset:
808 	reset_control_assert(dev->reset);
809 	return ret;
810 }
811 
812 static void dw_i2s_remove(struct platform_device *pdev)
813 {
814 	struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
815 
816 	if (dev->capability & DW_I2S_MASTER)
817 		clk_disable_unprepare(dev->clk);
818 
819 	reset_control_assert(dev->reset);
820 	pm_runtime_disable(&pdev->dev);
821 }
822 
823 #ifdef CONFIG_OF
824 static const struct of_device_id dw_i2s_of_match[] = {
825 	{ .compatible = "snps,designware-i2s",	 },
826 	{},
827 };
828 
829 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
830 #endif
831 
832 static const struct dev_pm_ops dwc_pm_ops = {
833 	SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL)
834 };
835 
836 static struct platform_driver dw_i2s_driver = {
837 	.probe		= dw_i2s_probe,
838 	.remove_new	= dw_i2s_remove,
839 	.driver		= {
840 		.name	= "designware-i2s",
841 		.of_match_table = of_match_ptr(dw_i2s_of_match),
842 		.pm = &dwc_pm_ops,
843 	},
844 };
845 
846 module_platform_driver(dw_i2s_driver);
847 
848 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
849 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
850 MODULE_LICENSE("GPL");
851 MODULE_ALIAS("platform:designware_i2s");
852