1 /* 2 * ALSA SoC Synopsys I2S Audio Layer 3 * 4 * sound/soc/dwc/designware_i2s.c 5 * 6 * Copyright (C) 2010 ST Microelectronics 7 * Rajeev Kumar <rajeevkumar.linux@gmail.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/pm_runtime.h> 23 #include <sound/designware_i2s.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/dmaengine_pcm.h> 28 #include "local.h" 29 30 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) 31 { 32 writel(val, io_base + reg); 33 } 34 35 static inline u32 i2s_read_reg(void __iomem *io_base, int reg) 36 { 37 return readl(io_base + reg); 38 } 39 40 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) 41 { 42 u32 i = 0; 43 44 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 45 for (i = 0; i < 4; i++) 46 i2s_write_reg(dev->i2s_base, TER(i), 0); 47 } else { 48 for (i = 0; i < 4; i++) 49 i2s_write_reg(dev->i2s_base, RER(i), 0); 50 } 51 } 52 53 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) 54 { 55 u32 i = 0; 56 57 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 58 for (i = 0; i < 4; i++) 59 i2s_read_reg(dev->i2s_base, TOR(i)); 60 } else { 61 for (i = 0; i < 4; i++) 62 i2s_read_reg(dev->i2s_base, ROR(i)); 63 } 64 } 65 66 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, 67 int chan_nr) 68 { 69 u32 i, irq; 70 71 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 72 for (i = 0; i < (chan_nr / 2); i++) { 73 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 74 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); 75 } 76 } else { 77 for (i = 0; i < (chan_nr / 2); i++) { 78 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 79 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); 80 } 81 } 82 } 83 84 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, 85 int chan_nr) 86 { 87 u32 i, irq; 88 89 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 90 for (i = 0; i < (chan_nr / 2); i++) { 91 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 92 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); 93 } 94 } else { 95 for (i = 0; i < (chan_nr / 2); i++) { 96 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 97 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); 98 } 99 } 100 } 101 102 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 103 { 104 struct dw_i2s_dev *dev = dev_id; 105 bool irq_valid = false; 106 u32 isr[4]; 107 int i; 108 109 for (i = 0; i < 4; i++) 110 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); 111 112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); 113 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); 114 115 for (i = 0; i < 4; i++) { 116 /* 117 * Check if TX fifo is empty. If empty fill FIFO with samples 118 * NOTE: Only two channels supported 119 */ 120 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { 121 dw_pcm_push_tx(dev); 122 irq_valid = true; 123 } 124 125 /* 126 * Data available. Retrieve samples from FIFO 127 * NOTE: Only two channels supported 128 */ 129 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { 130 dw_pcm_pop_rx(dev); 131 irq_valid = true; 132 } 133 134 /* Error Handling: TX */ 135 if (isr[i] & ISR_TXFO) { 136 dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i); 137 irq_valid = true; 138 } 139 140 /* Error Handling: TX */ 141 if (isr[i] & ISR_RXFO) { 142 dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); 143 irq_valid = true; 144 } 145 } 146 147 if (irq_valid) 148 return IRQ_HANDLED; 149 else 150 return IRQ_NONE; 151 } 152 153 static void i2s_start(struct dw_i2s_dev *dev, 154 struct snd_pcm_substream *substream) 155 { 156 struct i2s_clk_config_data *config = &dev->config; 157 158 i2s_write_reg(dev->i2s_base, IER, 1); 159 i2s_enable_irqs(dev, substream->stream, config->chan_nr); 160 161 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 162 i2s_write_reg(dev->i2s_base, ITER, 1); 163 else 164 i2s_write_reg(dev->i2s_base, IRER, 1); 165 166 i2s_write_reg(dev->i2s_base, CER, 1); 167 } 168 169 static void i2s_stop(struct dw_i2s_dev *dev, 170 struct snd_pcm_substream *substream) 171 { 172 173 i2s_clear_irqs(dev, substream->stream); 174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 175 i2s_write_reg(dev->i2s_base, ITER, 0); 176 else 177 i2s_write_reg(dev->i2s_base, IRER, 0); 178 179 i2s_disable_irqs(dev, substream->stream, 8); 180 181 if (!dev->active) { 182 i2s_write_reg(dev->i2s_base, CER, 0); 183 i2s_write_reg(dev->i2s_base, IER, 0); 184 } 185 } 186 187 static int dw_i2s_startup(struct snd_pcm_substream *substream, 188 struct snd_soc_dai *cpu_dai) 189 { 190 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 191 union dw_i2s_snd_dma_data *dma_data = NULL; 192 193 if (!(dev->capability & DWC_I2S_RECORD) && 194 (substream->stream == SNDRV_PCM_STREAM_CAPTURE)) 195 return -EINVAL; 196 197 if (!(dev->capability & DWC_I2S_PLAY) && 198 (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) 199 return -EINVAL; 200 201 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 202 dma_data = &dev->play_dma_data; 203 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 204 dma_data = &dev->capture_dma_data; 205 206 snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data); 207 208 return 0; 209 } 210 211 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) 212 { 213 u32 ch_reg; 214 struct i2s_clk_config_data *config = &dev->config; 215 216 217 i2s_disable_channels(dev, stream); 218 219 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { 220 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 221 i2s_write_reg(dev->i2s_base, TCR(ch_reg), 222 dev->xfer_resolution); 223 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 224 dev->fifo_th - 1); 225 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); 226 } else { 227 i2s_write_reg(dev->i2s_base, RCR(ch_reg), 228 dev->xfer_resolution); 229 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 230 dev->fifo_th - 1); 231 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); 232 } 233 234 } 235 } 236 237 static int dw_i2s_hw_params(struct snd_pcm_substream *substream, 238 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 239 { 240 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 241 struct i2s_clk_config_data *config = &dev->config; 242 int ret; 243 244 switch (params_format(params)) { 245 case SNDRV_PCM_FORMAT_S16_LE: 246 config->data_width = 16; 247 dev->ccr = 0x00; 248 dev->xfer_resolution = 0x02; 249 break; 250 251 case SNDRV_PCM_FORMAT_S24_LE: 252 config->data_width = 24; 253 dev->ccr = 0x08; 254 dev->xfer_resolution = 0x04; 255 break; 256 257 case SNDRV_PCM_FORMAT_S32_LE: 258 config->data_width = 32; 259 dev->ccr = 0x10; 260 dev->xfer_resolution = 0x05; 261 break; 262 263 default: 264 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); 265 return -EINVAL; 266 } 267 268 config->chan_nr = params_channels(params); 269 270 switch (config->chan_nr) { 271 case EIGHT_CHANNEL_SUPPORT: 272 case SIX_CHANNEL_SUPPORT: 273 case FOUR_CHANNEL_SUPPORT: 274 case TWO_CHANNEL_SUPPORT: 275 break; 276 default: 277 dev_err(dev->dev, "channel not supported\n"); 278 return -EINVAL; 279 } 280 281 dw_i2s_config(dev, substream->stream); 282 283 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); 284 285 config->sample_rate = params_rate(params); 286 287 if (dev->capability & DW_I2S_MASTER) { 288 if (dev->i2s_clk_cfg) { 289 ret = dev->i2s_clk_cfg(config); 290 if (ret < 0) { 291 dev_err(dev->dev, "runtime audio clk config fail\n"); 292 return ret; 293 } 294 } else { 295 u32 bitclk = config->sample_rate * 296 config->data_width * 2; 297 298 ret = clk_set_rate(dev->clk, bitclk); 299 if (ret) { 300 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", 301 ret); 302 return ret; 303 } 304 } 305 } 306 return 0; 307 } 308 309 static void dw_i2s_shutdown(struct snd_pcm_substream *substream, 310 struct snd_soc_dai *dai) 311 { 312 snd_soc_dai_set_dma_data(dai, substream, NULL); 313 } 314 315 static int dw_i2s_prepare(struct snd_pcm_substream *substream, 316 struct snd_soc_dai *dai) 317 { 318 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 319 320 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 321 i2s_write_reg(dev->i2s_base, TXFFR, 1); 322 else 323 i2s_write_reg(dev->i2s_base, RXFFR, 1); 324 325 return 0; 326 } 327 328 static int dw_i2s_trigger(struct snd_pcm_substream *substream, 329 int cmd, struct snd_soc_dai *dai) 330 { 331 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 332 int ret = 0; 333 334 switch (cmd) { 335 case SNDRV_PCM_TRIGGER_START: 336 case SNDRV_PCM_TRIGGER_RESUME: 337 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 338 dev->active++; 339 i2s_start(dev, substream); 340 break; 341 342 case SNDRV_PCM_TRIGGER_STOP: 343 case SNDRV_PCM_TRIGGER_SUSPEND: 344 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 345 dev->active--; 346 i2s_stop(dev, substream); 347 break; 348 default: 349 ret = -EINVAL; 350 break; 351 } 352 return ret; 353 } 354 355 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 356 { 357 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 358 int ret = 0; 359 360 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 361 case SND_SOC_DAIFMT_BC_FC: 362 if (dev->capability & DW_I2S_SLAVE) 363 ret = 0; 364 else 365 ret = -EINVAL; 366 break; 367 case SND_SOC_DAIFMT_BP_FP: 368 if (dev->capability & DW_I2S_MASTER) 369 ret = 0; 370 else 371 ret = -EINVAL; 372 break; 373 case SND_SOC_DAIFMT_BC_FP: 374 case SND_SOC_DAIFMT_BP_FC: 375 ret = -EINVAL; 376 break; 377 default: 378 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); 379 ret = -EINVAL; 380 break; 381 } 382 return ret; 383 } 384 385 static const struct snd_soc_dai_ops dw_i2s_dai_ops = { 386 .startup = dw_i2s_startup, 387 .shutdown = dw_i2s_shutdown, 388 .hw_params = dw_i2s_hw_params, 389 .prepare = dw_i2s_prepare, 390 .trigger = dw_i2s_trigger, 391 .set_fmt = dw_i2s_set_fmt, 392 }; 393 394 #ifdef CONFIG_PM 395 static int dw_i2s_runtime_suspend(struct device *dev) 396 { 397 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 398 399 if (dw_dev->capability & DW_I2S_MASTER) 400 clk_disable(dw_dev->clk); 401 return 0; 402 } 403 404 static int dw_i2s_runtime_resume(struct device *dev) 405 { 406 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 407 int ret; 408 409 if (dw_dev->capability & DW_I2S_MASTER) { 410 ret = clk_enable(dw_dev->clk); 411 if (ret) 412 return ret; 413 } 414 return 0; 415 } 416 417 static int dw_i2s_suspend(struct snd_soc_component *component) 418 { 419 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 420 421 if (dev->capability & DW_I2S_MASTER) 422 clk_disable(dev->clk); 423 return 0; 424 } 425 426 static int dw_i2s_resume(struct snd_soc_component *component) 427 { 428 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 429 struct snd_soc_dai *dai; 430 int stream, ret; 431 432 if (dev->capability & DW_I2S_MASTER) { 433 ret = clk_enable(dev->clk); 434 if (ret) 435 return ret; 436 } 437 438 for_each_component_dais(component, dai) { 439 for_each_pcm_streams(stream) 440 if (snd_soc_dai_stream_active(dai, stream)) 441 dw_i2s_config(dev, stream); 442 } 443 444 return 0; 445 } 446 447 #else 448 #define dw_i2s_suspend NULL 449 #define dw_i2s_resume NULL 450 #endif 451 452 static const struct snd_soc_component_driver dw_i2s_component = { 453 .name = "dw-i2s", 454 .suspend = dw_i2s_suspend, 455 .resume = dw_i2s_resume, 456 .legacy_dai_naming = 1, 457 }; 458 459 /* 460 * The following tables allow a direct lookup of various parameters 461 * defined in the I2S block's configuration in terms of sound system 462 * parameters. Each table is sized to the number of entries possible 463 * according to the number of configuration bits describing an I2S 464 * block parameter. 465 */ 466 467 /* Maximum bit resolution of a channel - not uniformly spaced */ 468 static const u32 fifo_width[COMP_MAX_WORDSIZE] = { 469 12, 16, 20, 24, 32, 0, 0, 0 470 }; 471 472 /* Width of (DMA) bus */ 473 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { 474 DMA_SLAVE_BUSWIDTH_1_BYTE, 475 DMA_SLAVE_BUSWIDTH_2_BYTES, 476 DMA_SLAVE_BUSWIDTH_4_BYTES, 477 DMA_SLAVE_BUSWIDTH_UNDEFINED 478 }; 479 480 /* PCM format to support channel resolution */ 481 static const u32 formats[COMP_MAX_WORDSIZE] = { 482 SNDRV_PCM_FMTBIT_S16_LE, 483 SNDRV_PCM_FMTBIT_S16_LE, 484 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 485 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 486 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 487 0, 488 0, 489 0 490 }; 491 492 static int dw_configure_dai(struct dw_i2s_dev *dev, 493 struct snd_soc_dai_driver *dw_i2s_dai, 494 unsigned int rates) 495 { 496 /* 497 * Read component parameter registers to extract 498 * the I2S block's configuration. 499 */ 500 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 501 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); 502 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 503 u32 idx; 504 505 if (dev->capability & DWC_I2S_RECORD && 506 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 507 comp1 = comp1 & ~BIT(5); 508 509 if (dev->capability & DWC_I2S_PLAY && 510 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 511 comp1 = comp1 & ~BIT(6); 512 513 if (COMP1_TX_ENABLED(comp1)) { 514 dev_dbg(dev->dev, " designware: play supported\n"); 515 idx = COMP1_TX_WORDSIZE_0(comp1); 516 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 517 return -EINVAL; 518 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 519 idx = 1; 520 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; 521 dw_i2s_dai->playback.channels_max = 522 1 << (COMP1_TX_CHANNELS(comp1) + 1); 523 dw_i2s_dai->playback.formats = formats[idx]; 524 dw_i2s_dai->playback.rates = rates; 525 } 526 527 if (COMP1_RX_ENABLED(comp1)) { 528 dev_dbg(dev->dev, "designware: record supported\n"); 529 idx = COMP2_RX_WORDSIZE_0(comp2); 530 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 531 return -EINVAL; 532 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 533 idx = 1; 534 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; 535 dw_i2s_dai->capture.channels_max = 536 1 << (COMP1_RX_CHANNELS(comp1) + 1); 537 dw_i2s_dai->capture.formats = formats[idx]; 538 dw_i2s_dai->capture.rates = rates; 539 } 540 541 if (COMP1_MODE_EN(comp1)) { 542 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); 543 dev->capability |= DW_I2S_MASTER; 544 } else { 545 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); 546 dev->capability |= DW_I2S_SLAVE; 547 } 548 549 dev->fifo_th = fifo_depth / 2; 550 return 0; 551 } 552 553 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 554 struct snd_soc_dai_driver *dw_i2s_dai, 555 struct resource *res, 556 const struct i2s_platform_data *pdata) 557 { 558 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 559 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 560 int ret; 561 562 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 563 return -EINVAL; 564 565 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); 566 if (ret < 0) 567 return ret; 568 569 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 570 idx = 1; 571 /* Set DMA slaves info */ 572 dev->play_dma_data.pd.data = pdata->play_dma_data; 573 dev->capture_dma_data.pd.data = pdata->capture_dma_data; 574 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; 575 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; 576 dev->play_dma_data.pd.max_burst = 16; 577 dev->capture_dma_data.pd.max_burst = 16; 578 dev->play_dma_data.pd.addr_width = bus_widths[idx]; 579 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; 580 dev->play_dma_data.pd.filter = pdata->filter; 581 dev->capture_dma_data.pd.filter = pdata->filter; 582 583 return 0; 584 } 585 586 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, 587 struct snd_soc_dai_driver *dw_i2s_dai, 588 struct resource *res) 589 { 590 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 591 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 592 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 593 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 594 u32 idx2; 595 int ret; 596 597 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 598 return -EINVAL; 599 600 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); 601 if (ret < 0) 602 return ret; 603 604 if (COMP1_TX_ENABLED(comp1)) { 605 idx2 = COMP1_TX_WORDSIZE_0(comp1); 606 607 dev->capability |= DWC_I2S_PLAY; 608 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 609 dev->play_dma_data.dt.addr_width = bus_widths[idx]; 610 dev->play_dma_data.dt.fifo_size = fifo_depth * 611 (fifo_width[idx2]) >> 8; 612 dev->play_dma_data.dt.maxburst = 16; 613 } 614 if (COMP1_RX_ENABLED(comp1)) { 615 idx2 = COMP2_RX_WORDSIZE_0(comp2); 616 617 dev->capability |= DWC_I2S_RECORD; 618 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 619 dev->capture_dma_data.dt.addr_width = bus_widths[idx]; 620 dev->capture_dma_data.dt.fifo_size = fifo_depth * 621 (fifo_width[idx2] >> 8); 622 dev->capture_dma_data.dt.maxburst = 16; 623 } 624 625 return 0; 626 627 } 628 629 static int dw_i2s_probe(struct platform_device *pdev) 630 { 631 const struct i2s_platform_data *pdata = pdev->dev.platform_data; 632 struct dw_i2s_dev *dev; 633 struct resource *res; 634 int ret, irq; 635 struct snd_soc_dai_driver *dw_i2s_dai; 636 const char *clk_id; 637 638 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 639 if (!dev) 640 return -ENOMEM; 641 642 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); 643 if (!dw_i2s_dai) 644 return -ENOMEM; 645 646 dw_i2s_dai->ops = &dw_i2s_dai_ops; 647 648 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 649 if (IS_ERR(dev->i2s_base)) 650 return PTR_ERR(dev->i2s_base); 651 652 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); 653 if (IS_ERR(dev->reset)) 654 return PTR_ERR(dev->reset); 655 656 ret = reset_control_deassert(dev->reset); 657 if (ret) 658 return ret; 659 660 dev->dev = &pdev->dev; 661 662 irq = platform_get_irq_optional(pdev, 0); 663 if (irq >= 0) { 664 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, 665 pdev->name, dev); 666 if (ret < 0) { 667 dev_err(&pdev->dev, "failed to request irq\n"); 668 goto err_assert_reset; 669 } 670 } 671 672 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; 673 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; 674 if (pdata) { 675 dev->capability = pdata->cap; 676 clk_id = NULL; 677 dev->quirks = pdata->quirks; 678 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { 679 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; 680 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; 681 } 682 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 683 } else { 684 clk_id = "i2sclk"; 685 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); 686 } 687 if (ret < 0) 688 goto err_assert_reset; 689 690 if (dev->capability & DW_I2S_MASTER) { 691 if (pdata) { 692 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; 693 if (!dev->i2s_clk_cfg) { 694 dev_err(&pdev->dev, "no clock configure method\n"); 695 ret = -ENODEV; 696 goto err_assert_reset; 697 } 698 } 699 dev->clk = devm_clk_get(&pdev->dev, clk_id); 700 701 if (IS_ERR(dev->clk)) { 702 ret = PTR_ERR(dev->clk); 703 goto err_assert_reset; 704 } 705 706 ret = clk_prepare_enable(dev->clk); 707 if (ret < 0) 708 goto err_assert_reset; 709 } 710 711 dev_set_drvdata(&pdev->dev, dev); 712 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, 713 dw_i2s_dai, 1); 714 if (ret != 0) { 715 dev_err(&pdev->dev, "not able to register dai\n"); 716 goto err_clk_disable; 717 } 718 719 if (!pdata) { 720 if (irq >= 0) { 721 ret = dw_pcm_register(pdev); 722 dev->use_pio = true; 723 } else { 724 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 725 0); 726 dev->use_pio = false; 727 } 728 729 if (ret) { 730 dev_err(&pdev->dev, "could not register pcm: %d\n", 731 ret); 732 goto err_clk_disable; 733 } 734 } 735 736 pm_runtime_enable(&pdev->dev); 737 return 0; 738 739 err_clk_disable: 740 if (dev->capability & DW_I2S_MASTER) 741 clk_disable_unprepare(dev->clk); 742 err_assert_reset: 743 reset_control_assert(dev->reset); 744 return ret; 745 } 746 747 static void dw_i2s_remove(struct platform_device *pdev) 748 { 749 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); 750 751 if (dev->capability & DW_I2S_MASTER) 752 clk_disable_unprepare(dev->clk); 753 754 reset_control_assert(dev->reset); 755 pm_runtime_disable(&pdev->dev); 756 } 757 758 #ifdef CONFIG_OF 759 static const struct of_device_id dw_i2s_of_match[] = { 760 { .compatible = "snps,designware-i2s", }, 761 {}, 762 }; 763 764 MODULE_DEVICE_TABLE(of, dw_i2s_of_match); 765 #endif 766 767 static const struct dev_pm_ops dwc_pm_ops = { 768 SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) 769 }; 770 771 static struct platform_driver dw_i2s_driver = { 772 .probe = dw_i2s_probe, 773 .remove_new = dw_i2s_remove, 774 .driver = { 775 .name = "designware-i2s", 776 .of_match_table = of_match_ptr(dw_i2s_of_match), 777 .pm = &dwc_pm_ops, 778 }, 779 }; 780 781 module_platform_driver(dw_i2s_driver); 782 783 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); 784 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); 785 MODULE_LICENSE("GPL"); 786 MODULE_ALIAS("platform:designware_i2s"); 787