1 /* 2 * ALSA SoC Synopsys I2S Audio Layer 3 * 4 * sound/soc/dwc/designware_i2s.c 5 * 6 * Copyright (C) 2010 ST Microelectronics 7 * Rajeev Kumar <rajeevkumar.linux@gmail.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/device.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/pm_runtime.h> 23 #include <sound/designware_i2s.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/dmaengine_pcm.h> 28 #include "local.h" 29 30 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) 31 { 32 writel(val, io_base + reg); 33 } 34 35 static inline u32 i2s_read_reg(void __iomem *io_base, int reg) 36 { 37 return readl(io_base + reg); 38 } 39 40 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) 41 { 42 u32 i = 0; 43 44 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 45 for (i = 0; i < 4; i++) 46 i2s_write_reg(dev->i2s_base, TER(i), 0); 47 } else { 48 for (i = 0; i < 4; i++) 49 i2s_write_reg(dev->i2s_base, RER(i), 0); 50 } 51 } 52 53 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) 54 { 55 u32 i = 0; 56 57 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 58 for (i = 0; i < 4; i++) 59 i2s_read_reg(dev->i2s_base, TOR(i)); 60 } else { 61 for (i = 0; i < 4; i++) 62 i2s_read_reg(dev->i2s_base, ROR(i)); 63 } 64 } 65 66 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, 67 int chan_nr) 68 { 69 u32 i, irq; 70 71 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 72 for (i = 0; i < (chan_nr / 2); i++) { 73 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 74 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); 75 } 76 } else { 77 for (i = 0; i < (chan_nr / 2); i++) { 78 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 79 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); 80 } 81 } 82 } 83 84 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, 85 int chan_nr) 86 { 87 u32 i, irq; 88 89 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 90 for (i = 0; i < (chan_nr / 2); i++) { 91 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 92 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); 93 } 94 } else { 95 for (i = 0; i < (chan_nr / 2); i++) { 96 irq = i2s_read_reg(dev->i2s_base, IMR(i)); 97 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); 98 } 99 } 100 } 101 102 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 103 { 104 struct dw_i2s_dev *dev = dev_id; 105 bool irq_valid = false; 106 u32 isr[4]; 107 int i; 108 109 for (i = 0; i < 4; i++) 110 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); 111 112 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); 113 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); 114 115 for (i = 0; i < 4; i++) { 116 /* 117 * Check if TX fifo is empty. If empty fill FIFO with samples 118 * NOTE: Only two channels supported 119 */ 120 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { 121 dw_pcm_push_tx(dev); 122 irq_valid = true; 123 } 124 125 /* 126 * Data available. Retrieve samples from FIFO 127 * NOTE: Only two channels supported 128 */ 129 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { 130 dw_pcm_pop_rx(dev); 131 irq_valid = true; 132 } 133 134 /* Error Handling: TX */ 135 if (isr[i] & ISR_TXFO) { 136 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); 137 irq_valid = true; 138 } 139 140 /* Error Handling: TX */ 141 if (isr[i] & ISR_RXFO) { 142 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); 143 irq_valid = true; 144 } 145 } 146 147 if (irq_valid) 148 return IRQ_HANDLED; 149 else 150 return IRQ_NONE; 151 } 152 153 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) 154 { 155 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 156 157 /* Enable DMA handshake for stream */ 158 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 159 dma_reg |= I2S_DMAEN_TXBLOCK; 160 else 161 dma_reg |= I2S_DMAEN_RXBLOCK; 162 163 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 164 } 165 166 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) 167 { 168 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); 169 170 /* Disable DMA handshake for stream */ 171 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 172 dma_reg &= ~I2S_DMAEN_TXBLOCK; 173 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); 174 } else { 175 dma_reg &= ~I2S_DMAEN_RXBLOCK; 176 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); 177 } 178 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); 179 } 180 181 static void i2s_start(struct dw_i2s_dev *dev, 182 struct snd_pcm_substream *substream) 183 { 184 struct i2s_clk_config_data *config = &dev->config; 185 186 i2s_write_reg(dev->i2s_base, IER, 1); 187 188 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 189 i2s_write_reg(dev->i2s_base, ITER, 1); 190 else 191 i2s_write_reg(dev->i2s_base, IRER, 1); 192 193 if (dev->use_pio) 194 i2s_enable_irqs(dev, substream->stream, config->chan_nr); 195 else 196 i2s_enable_dma(dev, substream->stream); 197 198 i2s_write_reg(dev->i2s_base, CER, 1); 199 } 200 201 static void i2s_stop(struct dw_i2s_dev *dev, 202 struct snd_pcm_substream *substream) 203 { 204 205 i2s_clear_irqs(dev, substream->stream); 206 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 207 i2s_write_reg(dev->i2s_base, ITER, 0); 208 else 209 i2s_write_reg(dev->i2s_base, IRER, 0); 210 211 if (dev->use_pio) 212 i2s_disable_irqs(dev, substream->stream, 8); 213 else 214 i2s_disable_dma(dev, substream->stream); 215 216 if (!dev->active) { 217 i2s_write_reg(dev->i2s_base, CER, 0); 218 i2s_write_reg(dev->i2s_base, IER, 0); 219 } 220 } 221 222 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) 223 { 224 u32 ch_reg; 225 struct i2s_clk_config_data *config = &dev->config; 226 227 228 i2s_disable_channels(dev, stream); 229 230 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { 231 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 232 i2s_write_reg(dev->i2s_base, TCR(ch_reg), 233 dev->xfer_resolution); 234 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 235 dev->fifo_th - 1); 236 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); 237 } else { 238 i2s_write_reg(dev->i2s_base, RCR(ch_reg), 239 dev->xfer_resolution); 240 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 241 dev->fifo_th - 1); 242 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); 243 } 244 245 } 246 } 247 248 static int dw_i2s_hw_params(struct snd_pcm_substream *substream, 249 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 250 { 251 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 252 struct i2s_clk_config_data *config = &dev->config; 253 int ret; 254 255 switch (params_format(params)) { 256 case SNDRV_PCM_FORMAT_S16_LE: 257 config->data_width = 16; 258 dev->ccr = 0x00; 259 dev->xfer_resolution = 0x02; 260 break; 261 262 case SNDRV_PCM_FORMAT_S24_LE: 263 config->data_width = 24; 264 dev->ccr = 0x08; 265 dev->xfer_resolution = 0x04; 266 break; 267 268 case SNDRV_PCM_FORMAT_S32_LE: 269 config->data_width = 32; 270 dev->ccr = 0x10; 271 dev->xfer_resolution = 0x05; 272 break; 273 274 default: 275 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); 276 return -EINVAL; 277 } 278 279 config->chan_nr = params_channels(params); 280 281 switch (config->chan_nr) { 282 case EIGHT_CHANNEL_SUPPORT: 283 case SIX_CHANNEL_SUPPORT: 284 case FOUR_CHANNEL_SUPPORT: 285 case TWO_CHANNEL_SUPPORT: 286 break; 287 default: 288 dev_err(dev->dev, "channel not supported\n"); 289 return -EINVAL; 290 } 291 292 dw_i2s_config(dev, substream->stream); 293 294 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); 295 296 config->sample_rate = params_rate(params); 297 298 if (dev->capability & DW_I2S_MASTER) { 299 if (dev->i2s_clk_cfg) { 300 ret = dev->i2s_clk_cfg(config); 301 if (ret < 0) { 302 dev_err(dev->dev, "runtime audio clk config fail\n"); 303 return ret; 304 } 305 } else { 306 u32 bitclk = config->sample_rate * 307 config->data_width * 2; 308 309 ret = clk_set_rate(dev->clk, bitclk); 310 if (ret) { 311 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", 312 ret); 313 return ret; 314 } 315 } 316 } 317 return 0; 318 } 319 320 static int dw_i2s_prepare(struct snd_pcm_substream *substream, 321 struct snd_soc_dai *dai) 322 { 323 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 324 325 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 326 i2s_write_reg(dev->i2s_base, TXFFR, 1); 327 else 328 i2s_write_reg(dev->i2s_base, RXFFR, 1); 329 330 return 0; 331 } 332 333 static int dw_i2s_trigger(struct snd_pcm_substream *substream, 334 int cmd, struct snd_soc_dai *dai) 335 { 336 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 337 int ret = 0; 338 339 switch (cmd) { 340 case SNDRV_PCM_TRIGGER_START: 341 case SNDRV_PCM_TRIGGER_RESUME: 342 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 343 dev->active++; 344 i2s_start(dev, substream); 345 break; 346 347 case SNDRV_PCM_TRIGGER_STOP: 348 case SNDRV_PCM_TRIGGER_SUSPEND: 349 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 350 dev->active--; 351 i2s_stop(dev, substream); 352 break; 353 default: 354 ret = -EINVAL; 355 break; 356 } 357 return ret; 358 } 359 360 static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 361 { 362 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 363 int ret = 0; 364 365 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 366 case SND_SOC_DAIFMT_BC_FC: 367 if (dev->capability & DW_I2S_SLAVE) 368 ret = 0; 369 else 370 ret = -EINVAL; 371 break; 372 case SND_SOC_DAIFMT_BP_FP: 373 if (dev->capability & DW_I2S_MASTER) 374 ret = 0; 375 else 376 ret = -EINVAL; 377 break; 378 case SND_SOC_DAIFMT_BC_FP: 379 case SND_SOC_DAIFMT_BP_FC: 380 ret = -EINVAL; 381 break; 382 default: 383 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); 384 ret = -EINVAL; 385 break; 386 } 387 return ret; 388 } 389 390 static const struct snd_soc_dai_ops dw_i2s_dai_ops = { 391 .hw_params = dw_i2s_hw_params, 392 .prepare = dw_i2s_prepare, 393 .trigger = dw_i2s_trigger, 394 .set_fmt = dw_i2s_set_fmt, 395 }; 396 397 #ifdef CONFIG_PM 398 static int dw_i2s_runtime_suspend(struct device *dev) 399 { 400 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 401 402 if (dw_dev->capability & DW_I2S_MASTER) 403 clk_disable(dw_dev->clk); 404 return 0; 405 } 406 407 static int dw_i2s_runtime_resume(struct device *dev) 408 { 409 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); 410 int ret; 411 412 if (dw_dev->capability & DW_I2S_MASTER) { 413 ret = clk_enable(dw_dev->clk); 414 if (ret) 415 return ret; 416 } 417 return 0; 418 } 419 420 static int dw_i2s_suspend(struct snd_soc_component *component) 421 { 422 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 423 424 if (dev->capability & DW_I2S_MASTER) 425 clk_disable(dev->clk); 426 return 0; 427 } 428 429 static int dw_i2s_resume(struct snd_soc_component *component) 430 { 431 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); 432 struct snd_soc_dai *dai; 433 int stream, ret; 434 435 if (dev->capability & DW_I2S_MASTER) { 436 ret = clk_enable(dev->clk); 437 if (ret) 438 return ret; 439 } 440 441 for_each_component_dais(component, dai) { 442 for_each_pcm_streams(stream) 443 if (snd_soc_dai_stream_active(dai, stream)) 444 dw_i2s_config(dev, stream); 445 } 446 447 return 0; 448 } 449 450 #else 451 #define dw_i2s_suspend NULL 452 #define dw_i2s_resume NULL 453 #endif 454 455 static const struct snd_soc_component_driver dw_i2s_component = { 456 .name = "dw-i2s", 457 .suspend = dw_i2s_suspend, 458 .resume = dw_i2s_resume, 459 .legacy_dai_naming = 1, 460 }; 461 462 /* 463 * The following tables allow a direct lookup of various parameters 464 * defined in the I2S block's configuration in terms of sound system 465 * parameters. Each table is sized to the number of entries possible 466 * according to the number of configuration bits describing an I2S 467 * block parameter. 468 */ 469 470 /* Maximum bit resolution of a channel - not uniformly spaced */ 471 static const u32 fifo_width[COMP_MAX_WORDSIZE] = { 472 12, 16, 20, 24, 32, 0, 0, 0 473 }; 474 475 /* Width of (DMA) bus */ 476 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = { 477 DMA_SLAVE_BUSWIDTH_1_BYTE, 478 DMA_SLAVE_BUSWIDTH_2_BYTES, 479 DMA_SLAVE_BUSWIDTH_4_BYTES, 480 DMA_SLAVE_BUSWIDTH_UNDEFINED 481 }; 482 483 /* PCM format to support channel resolution */ 484 static const u32 formats[COMP_MAX_WORDSIZE] = { 485 SNDRV_PCM_FMTBIT_S16_LE, 486 SNDRV_PCM_FMTBIT_S16_LE, 487 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 488 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE, 489 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 490 0, 491 0, 492 0 493 }; 494 495 static int dw_configure_dai(struct dw_i2s_dev *dev, 496 struct snd_soc_dai_driver *dw_i2s_dai, 497 unsigned int rates) 498 { 499 /* 500 * Read component parameter registers to extract 501 * the I2S block's configuration. 502 */ 503 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 504 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); 505 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 506 u32 idx; 507 508 if (dev->capability & DWC_I2S_RECORD && 509 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 510 comp1 = comp1 & ~BIT(5); 511 512 if (dev->capability & DWC_I2S_PLAY && 513 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) 514 comp1 = comp1 & ~BIT(6); 515 516 if (COMP1_TX_ENABLED(comp1)) { 517 dev_dbg(dev->dev, " designware: play supported\n"); 518 idx = COMP1_TX_WORDSIZE_0(comp1); 519 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 520 return -EINVAL; 521 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 522 idx = 1; 523 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; 524 dw_i2s_dai->playback.channels_max = 525 1 << (COMP1_TX_CHANNELS(comp1) + 1); 526 dw_i2s_dai->playback.formats = formats[idx]; 527 dw_i2s_dai->playback.rates = rates; 528 } 529 530 if (COMP1_RX_ENABLED(comp1)) { 531 dev_dbg(dev->dev, "designware: record supported\n"); 532 idx = COMP2_RX_WORDSIZE_0(comp2); 533 if (WARN_ON(idx >= ARRAY_SIZE(formats))) 534 return -EINVAL; 535 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 536 idx = 1; 537 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; 538 dw_i2s_dai->capture.channels_max = 539 1 << (COMP1_RX_CHANNELS(comp1) + 1); 540 dw_i2s_dai->capture.formats = formats[idx]; 541 dw_i2s_dai->capture.rates = rates; 542 } 543 544 if (COMP1_MODE_EN(comp1)) { 545 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); 546 dev->capability |= DW_I2S_MASTER; 547 } else { 548 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); 549 dev->capability |= DW_I2S_SLAVE; 550 } 551 552 dev->fifo_th = fifo_depth / 2; 553 return 0; 554 } 555 556 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 557 struct snd_soc_dai_driver *dw_i2s_dai, 558 struct resource *res, 559 const struct i2s_platform_data *pdata) 560 { 561 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); 562 u32 idx = COMP1_APB_DATA_WIDTH(comp1); 563 int ret; 564 565 if (WARN_ON(idx >= ARRAY_SIZE(bus_widths))) 566 return -EINVAL; 567 568 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); 569 if (ret < 0) 570 return ret; 571 572 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) 573 idx = 1; 574 /* Set DMA slaves info */ 575 dev->play_dma_data.pd.data = pdata->play_dma_data; 576 dev->capture_dma_data.pd.data = pdata->capture_dma_data; 577 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; 578 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; 579 dev->play_dma_data.pd.max_burst = 16; 580 dev->capture_dma_data.pd.max_burst = 16; 581 dev->play_dma_data.pd.addr_width = bus_widths[idx]; 582 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; 583 dev->play_dma_data.pd.filter = pdata->filter; 584 dev->capture_dma_data.pd.filter = pdata->filter; 585 586 return 0; 587 } 588 589 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, 590 struct snd_soc_dai_driver *dw_i2s_dai, 591 struct resource *res) 592 { 593 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); 594 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); 595 u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1)); 596 u32 idx2; 597 int ret; 598 599 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); 600 if (ret < 0) 601 return ret; 602 603 if (COMP1_TX_ENABLED(comp1)) { 604 idx2 = COMP1_TX_WORDSIZE_0(comp1); 605 606 dev->capability |= DWC_I2S_PLAY; 607 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; 608 dev->play_dma_data.dt.fifo_size = fifo_depth * 609 (fifo_width[idx2]) >> 8; 610 dev->play_dma_data.dt.maxburst = 16; 611 } 612 if (COMP1_RX_ENABLED(comp1)) { 613 idx2 = COMP2_RX_WORDSIZE_0(comp2); 614 615 dev->capability |= DWC_I2S_RECORD; 616 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; 617 dev->capture_dma_data.dt.fifo_size = fifo_depth * 618 (fifo_width[idx2] >> 8); 619 dev->capture_dma_data.dt.maxburst = 16; 620 } 621 622 return 0; 623 624 } 625 626 static int dw_i2s_dai_probe(struct snd_soc_dai *dai) 627 { 628 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); 629 630 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); 631 return 0; 632 } 633 634 static int dw_i2s_probe(struct platform_device *pdev) 635 { 636 const struct i2s_platform_data *pdata = pdev->dev.platform_data; 637 struct dw_i2s_dev *dev; 638 struct resource *res; 639 int ret, irq; 640 struct snd_soc_dai_driver *dw_i2s_dai; 641 const char *clk_id; 642 643 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 644 if (!dev) 645 return -ENOMEM; 646 647 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); 648 if (!dw_i2s_dai) 649 return -ENOMEM; 650 651 dw_i2s_dai->ops = &dw_i2s_dai_ops; 652 dw_i2s_dai->probe = dw_i2s_dai_probe; 653 654 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 655 if (IS_ERR(dev->i2s_base)) 656 return PTR_ERR(dev->i2s_base); 657 658 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); 659 if (IS_ERR(dev->reset)) 660 return PTR_ERR(dev->reset); 661 662 ret = reset_control_deassert(dev->reset); 663 if (ret) 664 return ret; 665 666 dev->dev = &pdev->dev; 667 668 irq = platform_get_irq_optional(pdev, 0); 669 if (irq >= 0) { 670 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, 671 pdev->name, dev); 672 if (ret < 0) { 673 dev_err(&pdev->dev, "failed to request irq\n"); 674 goto err_assert_reset; 675 } 676 } 677 678 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; 679 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; 680 if (pdata) { 681 dev->capability = pdata->cap; 682 clk_id = NULL; 683 dev->quirks = pdata->quirks; 684 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { 685 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; 686 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; 687 } 688 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); 689 } else { 690 clk_id = "i2sclk"; 691 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); 692 } 693 if (ret < 0) 694 goto err_assert_reset; 695 696 if (dev->capability & DW_I2S_MASTER) { 697 if (pdata) { 698 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; 699 if (!dev->i2s_clk_cfg) { 700 dev_err(&pdev->dev, "no clock configure method\n"); 701 ret = -ENODEV; 702 goto err_assert_reset; 703 } 704 } 705 dev->clk = devm_clk_get(&pdev->dev, clk_id); 706 707 if (IS_ERR(dev->clk)) { 708 ret = PTR_ERR(dev->clk); 709 goto err_assert_reset; 710 } 711 712 ret = clk_prepare_enable(dev->clk); 713 if (ret < 0) 714 goto err_assert_reset; 715 } 716 717 dev_set_drvdata(&pdev->dev, dev); 718 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, 719 dw_i2s_dai, 1); 720 if (ret != 0) { 721 dev_err(&pdev->dev, "not able to register dai\n"); 722 goto err_clk_disable; 723 } 724 725 if (!pdata) { 726 if (irq >= 0) { 727 ret = dw_pcm_register(pdev); 728 dev->use_pio = true; 729 } else { 730 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 731 0); 732 dev->use_pio = false; 733 } 734 735 if (ret) { 736 dev_err(&pdev->dev, "could not register pcm: %d\n", 737 ret); 738 goto err_clk_disable; 739 } 740 } 741 742 pm_runtime_enable(&pdev->dev); 743 return 0; 744 745 err_clk_disable: 746 if (dev->capability & DW_I2S_MASTER) 747 clk_disable_unprepare(dev->clk); 748 err_assert_reset: 749 reset_control_assert(dev->reset); 750 return ret; 751 } 752 753 static void dw_i2s_remove(struct platform_device *pdev) 754 { 755 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); 756 757 if (dev->capability & DW_I2S_MASTER) 758 clk_disable_unprepare(dev->clk); 759 760 reset_control_assert(dev->reset); 761 pm_runtime_disable(&pdev->dev); 762 } 763 764 #ifdef CONFIG_OF 765 static const struct of_device_id dw_i2s_of_match[] = { 766 { .compatible = "snps,designware-i2s", }, 767 {}, 768 }; 769 770 MODULE_DEVICE_TABLE(of, dw_i2s_of_match); 771 #endif 772 773 static const struct dev_pm_ops dwc_pm_ops = { 774 SET_RUNTIME_PM_OPS(dw_i2s_runtime_suspend, dw_i2s_runtime_resume, NULL) 775 }; 776 777 static struct platform_driver dw_i2s_driver = { 778 .probe = dw_i2s_probe, 779 .remove_new = dw_i2s_remove, 780 .driver = { 781 .name = "designware-i2s", 782 .of_match_table = of_match_ptr(dw_i2s_of_match), 783 .pm = &dwc_pm_ops, 784 }, 785 }; 786 787 module_platform_driver(dw_i2s_driver); 788 789 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>"); 790 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface"); 791 MODULE_LICENSE("GPL"); 792 MODULE_ALIAS("platform:designware_i2s"); 793