1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2015-2017, The Linux Foundation. 3 // Copyright (c) 2019, Linaro Limited 4 5 #include <linux/bitops.h> 6 #include <linux/gpio.h> 7 #include <linux/gpio/consumer.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_gpio.h> 12 #include <linux/regmap.h> 13 #include <linux/slab.h> 14 #include <linux/soundwire/sdw.h> 15 #include <linux/soundwire/sdw_registers.h> 16 #include <linux/soundwire/sdw_type.h> 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #define WSA881X_DIGITAL_BASE 0x3000 21 #define WSA881X_ANALOG_BASE 0x3100 22 23 /* Digital register address space */ 24 #define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000) 25 #define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001) 26 #define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002) 27 #define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003) 28 #define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004) 29 #define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005) 30 #define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006) 31 #define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007) 32 #define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008) 33 #define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009) 34 #define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A) 35 #define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B) 36 #define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C) 37 #define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F) 38 #define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010) 39 #define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011) 40 #define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012) 41 #define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013) 42 #define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014) 43 #define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015) 44 #define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016) 45 #define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017) 46 #define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018) 47 #define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019) 48 #define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A) 49 #define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B) 50 #define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C) 51 #define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D) 52 #define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E) 53 #define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F) 54 #define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020) 55 #define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021) 56 #define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022) 57 #define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023) 58 #define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024) 59 #define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025) 60 #define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026) 61 #define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030) 62 #define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031) 63 #define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032) 64 #define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033) 65 #define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034) 66 #define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035) 67 #define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037) 68 #define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038) 69 #define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039) 70 #define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B) 71 #define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C) 72 #define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D) 73 #define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E) 74 #define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F) 75 #define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044) 76 #define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045) 77 #define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050) 78 #define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051) 79 #define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052) 80 #define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080) 81 #define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081) 82 #define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082) 83 #define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083) 84 #define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084) 85 #define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085) 86 #define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086) 87 #define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087) 88 #define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088) 89 #define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089) 90 #define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A) 91 #define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B) 92 #define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C) 93 #define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D) 94 #define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E) 95 #define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F) 96 #define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090) 97 #define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091) 98 #define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092) 99 #define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093) 100 #define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094) 101 #define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095) 102 #define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096) 103 #define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097) 104 #define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098) 105 #define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099) 106 #define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A) 107 #define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B) 108 #define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C) 109 #define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D) 110 #define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E) 111 #define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F) 112 #define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF) 113 114 /* Analog Register address space */ 115 #define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000) 116 #define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001) 117 #define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002) 118 #define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003) 119 #define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004) 120 #define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005) 121 #define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006) 122 #define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007) 123 #define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008) 124 #define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009) 125 #define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A) 126 #define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B) 127 #define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010) 128 #define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011) 129 #define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012) 130 #define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013) 131 #define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014) 132 #define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015) 133 #define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A) 134 #define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B) 135 #define WSA881X_PA_GAIN_SEL_MASK BIT(3) 136 #define WSA881X_PA_GAIN_SEL_REG BIT(3) 137 #define WSA881X_PA_GAIN_SEL_DRE 0 138 #define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4) 139 #define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C) 140 #define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D) 141 #define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E) 142 #define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F) 143 #define WSA881X_SPKR_OCP_MASK GENMASK(7, 6) 144 #define WSA881X_SPKR_OCP_EN BIT(7) 145 #define WSA881X_SPKR_OCP_HOLD BIT(6) 146 #define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020) 147 #define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021) 148 #define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022) 149 #define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023) 150 #define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024) 151 #define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025) 152 #define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026) 153 #define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027) 154 #define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028) 155 #define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029) 156 #define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A) 157 #define WSA881X_BOOST_EN_MASK BIT(7) 158 #define WSA881X_BOOST_EN BIT(7) 159 #define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B) 160 #define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C) 161 #define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D) 162 #define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E) 163 #define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F) 164 #define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030) 165 #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031) 166 #define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032) 167 #define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033) 168 #define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034) 169 #define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035) 170 #define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036) 171 #define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037) 172 #define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038) 173 #define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039) 174 #define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A) 175 #define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B) 176 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C) 177 #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D) 178 #define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E) 179 #define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F) 180 #define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040) 181 #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041) 182 #define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042) 183 #define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043) 184 #define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044) 185 #define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045) 186 187 #define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m)) 188 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m)) 189 #define SWR_SLV_MAX_REG_ADDR 0x390 190 #define SWR_SLV_START_REG_ADDR 0x40 191 #define SWR_SLV_MAX_BUF_LEN 20 192 #define BYTES_PER_LINE 12 193 #define SWR_SLV_RD_BUF_LEN 8 194 #define SWR_SLV_WR_BUF_LEN 32 195 #define SWR_SLV_MAX_DEVICES 2 196 #define WSA881X_MAX_SWR_PORTS 4 197 #define WSA881X_VERSION_ENTRY_SIZE 27 198 #define WSA881X_OCP_CTL_TIMER_SEC 2 199 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25 200 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60 201 202 #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ 203 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 204 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ 205 SNDRV_CTL_ELEM_ACCESS_READWRITE,\ 206 .tlv.p = (tlv_array), \ 207 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ 208 .put = wsa881x_put_pa_gain, \ 209 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } 210 211 static struct reg_default wsa881x_defaults[] = { 212 { WSA881X_CHIP_ID0, 0x00 }, 213 { WSA881X_CHIP_ID1, 0x00 }, 214 { WSA881X_CHIP_ID2, 0x00 }, 215 { WSA881X_CHIP_ID3, 0x02 }, 216 { WSA881X_BUS_ID, 0x00 }, 217 { WSA881X_CDC_RST_CTL, 0x00 }, 218 { WSA881X_CDC_TOP_CLK_CTL, 0x03 }, 219 { WSA881X_CDC_ANA_CLK_CTL, 0x00 }, 220 { WSA881X_CDC_DIG_CLK_CTL, 0x00 }, 221 { WSA881X_CLOCK_CONFIG, 0x00 }, 222 { WSA881X_ANA_CTL, 0x08 }, 223 { WSA881X_SWR_RESET_EN, 0x00 }, 224 { WSA881X_TEMP_DETECT_CTL, 0x01 }, 225 { WSA881X_TEMP_MSB, 0x00 }, 226 { WSA881X_TEMP_LSB, 0x00 }, 227 { WSA881X_TEMP_CONFIG0, 0x00 }, 228 { WSA881X_TEMP_CONFIG1, 0x00 }, 229 { WSA881X_CDC_CLIP_CTL, 0x03 }, 230 { WSA881X_SDM_PDM9_LSB, 0x00 }, 231 { WSA881X_SDM_PDM9_MSB, 0x00 }, 232 { WSA881X_CDC_RX_CTL, 0x7E }, 233 { WSA881X_DEM_BYPASS_DATA0, 0x00 }, 234 { WSA881X_DEM_BYPASS_DATA1, 0x00 }, 235 { WSA881X_DEM_BYPASS_DATA2, 0x00 }, 236 { WSA881X_DEM_BYPASS_DATA3, 0x00 }, 237 { WSA881X_OTP_CTRL0, 0x00 }, 238 { WSA881X_OTP_CTRL1, 0x00 }, 239 { WSA881X_HDRIVE_CTL_GROUP1, 0x00 }, 240 { WSA881X_INTR_MODE, 0x00 }, 241 { WSA881X_INTR_STATUS, 0x00 }, 242 { WSA881X_INTR_CLEAR, 0x00 }, 243 { WSA881X_INTR_LEVEL, 0x00 }, 244 { WSA881X_INTR_SET, 0x00 }, 245 { WSA881X_INTR_TEST, 0x00 }, 246 { WSA881X_PDM_TEST_MODE, 0x00 }, 247 { WSA881X_ATE_TEST_MODE, 0x00 }, 248 { WSA881X_PIN_CTL_MODE, 0x00 }, 249 { WSA881X_PIN_CTL_OE, 0x00 }, 250 { WSA881X_PIN_WDATA_IOPAD, 0x00 }, 251 { WSA881X_PIN_STATUS, 0x00 }, 252 { WSA881X_DIG_DEBUG_MODE, 0x00 }, 253 { WSA881X_DIG_DEBUG_SEL, 0x00 }, 254 { WSA881X_DIG_DEBUG_EN, 0x00 }, 255 { WSA881X_SWR_HM_TEST1, 0x08 }, 256 { WSA881X_SWR_HM_TEST2, 0x00 }, 257 { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 }, 258 { WSA881X_TEMP_DEBUG_MSB, 0x00 }, 259 { WSA881X_TEMP_DEBUG_LSB, 0x00 }, 260 { WSA881X_SAMPLE_EDGE_SEL, 0x0C }, 261 { WSA881X_SPARE_0, 0x00 }, 262 { WSA881X_SPARE_1, 0x00 }, 263 { WSA881X_SPARE_2, 0x00 }, 264 { WSA881X_OTP_REG_0, 0x01 }, 265 { WSA881X_OTP_REG_1, 0xFF }, 266 { WSA881X_OTP_REG_2, 0xC0 }, 267 { WSA881X_OTP_REG_3, 0xFF }, 268 { WSA881X_OTP_REG_4, 0xC0 }, 269 { WSA881X_OTP_REG_5, 0xFF }, 270 { WSA881X_OTP_REG_6, 0xFF }, 271 { WSA881X_OTP_REG_7, 0xFF }, 272 { WSA881X_OTP_REG_8, 0xFF }, 273 { WSA881X_OTP_REG_9, 0xFF }, 274 { WSA881X_OTP_REG_10, 0xFF }, 275 { WSA881X_OTP_REG_11, 0xFF }, 276 { WSA881X_OTP_REG_12, 0xFF }, 277 { WSA881X_OTP_REG_13, 0xFF }, 278 { WSA881X_OTP_REG_14, 0xFF }, 279 { WSA881X_OTP_REG_15, 0xFF }, 280 { WSA881X_OTP_REG_16, 0xFF }, 281 { WSA881X_OTP_REG_17, 0xFF }, 282 { WSA881X_OTP_REG_18, 0xFF }, 283 { WSA881X_OTP_REG_19, 0xFF }, 284 { WSA881X_OTP_REG_20, 0xFF }, 285 { WSA881X_OTP_REG_21, 0xFF }, 286 { WSA881X_OTP_REG_22, 0xFF }, 287 { WSA881X_OTP_REG_23, 0xFF }, 288 { WSA881X_OTP_REG_24, 0x03 }, 289 { WSA881X_OTP_REG_25, 0x01 }, 290 { WSA881X_OTP_REG_26, 0x03 }, 291 { WSA881X_OTP_REG_27, 0x11 }, 292 { WSA881X_OTP_REG_63, 0x40 }, 293 /* WSA881x Analog registers */ 294 { WSA881X_BIAS_REF_CTRL, 0x6C }, 295 { WSA881X_BIAS_TEST, 0x16 }, 296 { WSA881X_BIAS_BIAS, 0xF0 }, 297 { WSA881X_TEMP_OP, 0x00 }, 298 { WSA881X_TEMP_IREF_CTRL, 0x56 }, 299 { WSA881X_TEMP_ISENS_CTRL, 0x47 }, 300 { WSA881X_TEMP_CLK_CTRL, 0x87 }, 301 { WSA881X_TEMP_TEST, 0x00 }, 302 { WSA881X_TEMP_BIAS, 0x51 }, 303 { WSA881X_TEMP_DOUT_MSB, 0x00 }, 304 { WSA881X_TEMP_DOUT_LSB, 0x00 }, 305 { WSA881X_ADC_EN_MODU_V, 0x00 }, 306 { WSA881X_ADC_EN_MODU_I, 0x00 }, 307 { WSA881X_ADC_EN_DET_TEST_V, 0x00 }, 308 { WSA881X_ADC_EN_DET_TEST_I, 0x00 }, 309 { WSA881X_ADC_EN_SEL_IBAIS, 0x10 }, 310 { WSA881X_SPKR_DRV_EN, 0x74 }, 311 { WSA881X_SPKR_DRV_DBG, 0x15 }, 312 { WSA881X_SPKR_PWRSTG_DBG, 0x00 }, 313 { WSA881X_SPKR_OCP_CTL, 0xD4 }, 314 { WSA881X_SPKR_CLIP_CTL, 0x90 }, 315 { WSA881X_SPKR_PA_INT, 0x54 }, 316 { WSA881X_SPKR_BIAS_CAL, 0xAC }, 317 { WSA881X_SPKR_STATUS1, 0x00 }, 318 { WSA881X_SPKR_STATUS2, 0x00 }, 319 { WSA881X_BOOST_EN_CTL, 0x18 }, 320 { WSA881X_BOOST_CURRENT_LIMIT, 0x7A }, 321 { WSA881X_BOOST_PRESET_OUT2, 0x70 }, 322 { WSA881X_BOOST_FORCE_OUT, 0x0E }, 323 { WSA881X_BOOST_LDO_PROG, 0x16 }, 324 { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 }, 325 { WSA881X_BOOST_RON_CTL, 0x0F }, 326 { WSA881X_BOOST_ZX_CTL, 0x34 }, 327 { WSA881X_BOOST_START_CTL, 0x23 }, 328 { WSA881X_BOOST_MISC1_CTL, 0x80 }, 329 { WSA881X_BOOST_MISC2_CTL, 0x00 }, 330 { WSA881X_BOOST_MISC3_CTL, 0x00 }, 331 { WSA881X_BOOST_ATEST_CTL, 0x00 }, 332 { WSA881X_SPKR_PROT_FE_GAIN, 0x46 }, 333 { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B }, 334 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D }, 335 { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D }, 336 { WSA881X_SPKR_PROT_ATEST1, 0x01 }, 337 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D }, 338 { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D }, 339 { WSA881X_SPKR_PROT_SAR, 0x00 }, 340 { WSA881X_SPKR_STATUS3, 0x00 }, 341 }; 342 343 static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = { 344 { WSA881X_SPKR_DRV_GAIN, 0x41, 0 }, 345 { WSA881X_SPKR_MISC_CTL1, 0x87, 0 }, 346 }; 347 348 static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = { 349 { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 }, 350 { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 }, 351 { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 }, 352 }; 353 354 /* Default register reset values for WSA881x rev 2.0 */ 355 static struct reg_sequence wsa881x_rev_2_0[] = { 356 { WSA881X_RESET_CTL, 0x00, 0x00 }, 357 { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 }, 358 { WSA881X_INTR_MASK, 0x1B, 0x00 }, 359 { WSA881X_IOPAD_CTL, 0x00, 0x00 }, 360 { WSA881X_OTP_REG_28, 0x3F, 0x00 }, 361 { WSA881X_OTP_REG_29, 0x3F, 0x00 }, 362 { WSA881X_OTP_REG_30, 0x01, 0x00 }, 363 { WSA881X_OTP_REG_31, 0x01, 0x00 }, 364 { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 }, 365 { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 }, 366 { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 }, 367 { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 }, 368 { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 }, 369 { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 }, 370 { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 }, 371 { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 }, 372 { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 }, 373 { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 }, 374 { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 }, 375 { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 }, 376 { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 }, 377 { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 }, 378 { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 }, 379 }; 380 381 enum wsa_port_ids { 382 WSA881X_PORT_DAC, 383 WSA881X_PORT_COMP, 384 WSA881X_PORT_BOOST, 385 WSA881X_PORT_VISENSE, 386 }; 387 388 /* 4 ports */ 389 static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = { 390 { 391 /* DAC */ 392 .num = 1, 393 .type = SDW_DPN_SIMPLE, 394 .min_ch = 1, 395 .max_ch = 1, 396 .simple_ch_prep_sm = true, 397 .read_only_wordlength = true, 398 }, { 399 /* COMP */ 400 .num = 2, 401 .type = SDW_DPN_SIMPLE, 402 .min_ch = 1, 403 .max_ch = 1, 404 .simple_ch_prep_sm = true, 405 .read_only_wordlength = true, 406 }, { 407 /* BOOST */ 408 .num = 3, 409 .type = SDW_DPN_SIMPLE, 410 .min_ch = 1, 411 .max_ch = 1, 412 .simple_ch_prep_sm = true, 413 .read_only_wordlength = true, 414 }, { 415 /* VISENSE */ 416 .num = 4, 417 .type = SDW_DPN_SIMPLE, 418 .min_ch = 1, 419 .max_ch = 1, 420 .simple_ch_prep_sm = true, 421 .read_only_wordlength = true, 422 } 423 }; 424 425 static struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = { 426 { 427 .num = 1, 428 .ch_mask = 0x1, 429 }, { 430 .num = 2, 431 .ch_mask = 0xf, 432 }, { 433 .num = 3, 434 .ch_mask = 0x3, 435 }, { /* IV feedback */ 436 .num = 4, 437 .ch_mask = 0x3, 438 }, 439 }; 440 441 static bool wsa881x_readable_register(struct device *dev, unsigned int reg) 442 { 443 switch (reg) { 444 case WSA881X_CHIP_ID0: 445 case WSA881X_CHIP_ID1: 446 case WSA881X_CHIP_ID2: 447 case WSA881X_CHIP_ID3: 448 case WSA881X_BUS_ID: 449 case WSA881X_CDC_RST_CTL: 450 case WSA881X_CDC_TOP_CLK_CTL: 451 case WSA881X_CDC_ANA_CLK_CTL: 452 case WSA881X_CDC_DIG_CLK_CTL: 453 case WSA881X_CLOCK_CONFIG: 454 case WSA881X_ANA_CTL: 455 case WSA881X_SWR_RESET_EN: 456 case WSA881X_RESET_CTL: 457 case WSA881X_TADC_VALUE_CTL: 458 case WSA881X_TEMP_DETECT_CTL: 459 case WSA881X_TEMP_MSB: 460 case WSA881X_TEMP_LSB: 461 case WSA881X_TEMP_CONFIG0: 462 case WSA881X_TEMP_CONFIG1: 463 case WSA881X_CDC_CLIP_CTL: 464 case WSA881X_SDM_PDM9_LSB: 465 case WSA881X_SDM_PDM9_MSB: 466 case WSA881X_CDC_RX_CTL: 467 case WSA881X_DEM_BYPASS_DATA0: 468 case WSA881X_DEM_BYPASS_DATA1: 469 case WSA881X_DEM_BYPASS_DATA2: 470 case WSA881X_DEM_BYPASS_DATA3: 471 case WSA881X_OTP_CTRL0: 472 case WSA881X_OTP_CTRL1: 473 case WSA881X_HDRIVE_CTL_GROUP1: 474 case WSA881X_INTR_MODE: 475 case WSA881X_INTR_MASK: 476 case WSA881X_INTR_STATUS: 477 case WSA881X_INTR_CLEAR: 478 case WSA881X_INTR_LEVEL: 479 case WSA881X_INTR_SET: 480 case WSA881X_INTR_TEST: 481 case WSA881X_PDM_TEST_MODE: 482 case WSA881X_ATE_TEST_MODE: 483 case WSA881X_PIN_CTL_MODE: 484 case WSA881X_PIN_CTL_OE: 485 case WSA881X_PIN_WDATA_IOPAD: 486 case WSA881X_PIN_STATUS: 487 case WSA881X_DIG_DEBUG_MODE: 488 case WSA881X_DIG_DEBUG_SEL: 489 case WSA881X_DIG_DEBUG_EN: 490 case WSA881X_SWR_HM_TEST1: 491 case WSA881X_SWR_HM_TEST2: 492 case WSA881X_TEMP_DETECT_DBG_CTL: 493 case WSA881X_TEMP_DEBUG_MSB: 494 case WSA881X_TEMP_DEBUG_LSB: 495 case WSA881X_SAMPLE_EDGE_SEL: 496 case WSA881X_IOPAD_CTL: 497 case WSA881X_SPARE_0: 498 case WSA881X_SPARE_1: 499 case WSA881X_SPARE_2: 500 case WSA881X_OTP_REG_0: 501 case WSA881X_OTP_REG_1: 502 case WSA881X_OTP_REG_2: 503 case WSA881X_OTP_REG_3: 504 case WSA881X_OTP_REG_4: 505 case WSA881X_OTP_REG_5: 506 case WSA881X_OTP_REG_6: 507 case WSA881X_OTP_REG_7: 508 case WSA881X_OTP_REG_8: 509 case WSA881X_OTP_REG_9: 510 case WSA881X_OTP_REG_10: 511 case WSA881X_OTP_REG_11: 512 case WSA881X_OTP_REG_12: 513 case WSA881X_OTP_REG_13: 514 case WSA881X_OTP_REG_14: 515 case WSA881X_OTP_REG_15: 516 case WSA881X_OTP_REG_16: 517 case WSA881X_OTP_REG_17: 518 case WSA881X_OTP_REG_18: 519 case WSA881X_OTP_REG_19: 520 case WSA881X_OTP_REG_20: 521 case WSA881X_OTP_REG_21: 522 case WSA881X_OTP_REG_22: 523 case WSA881X_OTP_REG_23: 524 case WSA881X_OTP_REG_24: 525 case WSA881X_OTP_REG_25: 526 case WSA881X_OTP_REG_26: 527 case WSA881X_OTP_REG_27: 528 case WSA881X_OTP_REG_28: 529 case WSA881X_OTP_REG_29: 530 case WSA881X_OTP_REG_30: 531 case WSA881X_OTP_REG_31: 532 case WSA881X_OTP_REG_63: 533 case WSA881X_BIAS_REF_CTRL: 534 case WSA881X_BIAS_TEST: 535 case WSA881X_BIAS_BIAS: 536 case WSA881X_TEMP_OP: 537 case WSA881X_TEMP_IREF_CTRL: 538 case WSA881X_TEMP_ISENS_CTRL: 539 case WSA881X_TEMP_CLK_CTRL: 540 case WSA881X_TEMP_TEST: 541 case WSA881X_TEMP_BIAS: 542 case WSA881X_TEMP_ADC_CTRL: 543 case WSA881X_TEMP_DOUT_MSB: 544 case WSA881X_TEMP_DOUT_LSB: 545 case WSA881X_ADC_EN_MODU_V: 546 case WSA881X_ADC_EN_MODU_I: 547 case WSA881X_ADC_EN_DET_TEST_V: 548 case WSA881X_ADC_EN_DET_TEST_I: 549 case WSA881X_ADC_SEL_IBIAS: 550 case WSA881X_ADC_EN_SEL_IBAIS: 551 case WSA881X_SPKR_DRV_EN: 552 case WSA881X_SPKR_DRV_GAIN: 553 case WSA881X_SPKR_DAC_CTL: 554 case WSA881X_SPKR_DRV_DBG: 555 case WSA881X_SPKR_PWRSTG_DBG: 556 case WSA881X_SPKR_OCP_CTL: 557 case WSA881X_SPKR_CLIP_CTL: 558 case WSA881X_SPKR_BBM_CTL: 559 case WSA881X_SPKR_MISC_CTL1: 560 case WSA881X_SPKR_MISC_CTL2: 561 case WSA881X_SPKR_BIAS_INT: 562 case WSA881X_SPKR_PA_INT: 563 case WSA881X_SPKR_BIAS_CAL: 564 case WSA881X_SPKR_BIAS_PSRR: 565 case WSA881X_SPKR_STATUS1: 566 case WSA881X_SPKR_STATUS2: 567 case WSA881X_BOOST_EN_CTL: 568 case WSA881X_BOOST_CURRENT_LIMIT: 569 case WSA881X_BOOST_PS_CTL: 570 case WSA881X_BOOST_PRESET_OUT1: 571 case WSA881X_BOOST_PRESET_OUT2: 572 case WSA881X_BOOST_FORCE_OUT: 573 case WSA881X_BOOST_LDO_PROG: 574 case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB: 575 case WSA881X_BOOST_RON_CTL: 576 case WSA881X_BOOST_LOOP_STABILITY: 577 case WSA881X_BOOST_ZX_CTL: 578 case WSA881X_BOOST_START_CTL: 579 case WSA881X_BOOST_MISC1_CTL: 580 case WSA881X_BOOST_MISC2_CTL: 581 case WSA881X_BOOST_MISC3_CTL: 582 case WSA881X_BOOST_ATEST_CTL: 583 case WSA881X_SPKR_PROT_FE_GAIN: 584 case WSA881X_SPKR_PROT_FE_CM_LDO_SET: 585 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1: 586 case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2: 587 case WSA881X_SPKR_PROT_ATEST1: 588 case WSA881X_SPKR_PROT_ATEST2: 589 case WSA881X_SPKR_PROT_FE_VSENSE_VCM: 590 case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1: 591 case WSA881X_BONGO_RESRV_REG1: 592 case WSA881X_BONGO_RESRV_REG2: 593 case WSA881X_SPKR_PROT_SAR: 594 case WSA881X_SPKR_STATUS3: 595 return true; 596 default: 597 return false; 598 } 599 } 600 601 static bool wsa881x_volatile_register(struct device *dev, unsigned int reg) 602 { 603 switch (reg) { 604 case WSA881X_CHIP_ID0: 605 case WSA881X_CHIP_ID1: 606 case WSA881X_CHIP_ID2: 607 case WSA881X_CHIP_ID3: 608 case WSA881X_BUS_ID: 609 case WSA881X_TEMP_MSB: 610 case WSA881X_TEMP_LSB: 611 case WSA881X_SDM_PDM9_LSB: 612 case WSA881X_SDM_PDM9_MSB: 613 case WSA881X_OTP_CTRL1: 614 case WSA881X_INTR_STATUS: 615 case WSA881X_ATE_TEST_MODE: 616 case WSA881X_PIN_STATUS: 617 case WSA881X_SWR_HM_TEST2: 618 case WSA881X_SPKR_STATUS1: 619 case WSA881X_SPKR_STATUS2: 620 case WSA881X_SPKR_STATUS3: 621 case WSA881X_OTP_REG_0: 622 case WSA881X_OTP_REG_1: 623 case WSA881X_OTP_REG_2: 624 case WSA881X_OTP_REG_3: 625 case WSA881X_OTP_REG_4: 626 case WSA881X_OTP_REG_5: 627 case WSA881X_OTP_REG_31: 628 case WSA881X_TEMP_DOUT_MSB: 629 case WSA881X_TEMP_DOUT_LSB: 630 case WSA881X_TEMP_OP: 631 case WSA881X_SPKR_PROT_SAR: 632 return true; 633 default: 634 return false; 635 } 636 } 637 638 static struct regmap_config wsa881x_regmap_config = { 639 .reg_bits = 32, 640 .val_bits = 8, 641 .cache_type = REGCACHE_RBTREE, 642 .reg_defaults = wsa881x_defaults, 643 .max_register = WSA881X_SPKR_STATUS3, 644 .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults), 645 .volatile_reg = wsa881x_volatile_register, 646 .readable_reg = wsa881x_readable_register, 647 .reg_format_endian = REGMAP_ENDIAN_NATIVE, 648 .val_format_endian = REGMAP_ENDIAN_NATIVE, 649 .can_multi_write = true, 650 }; 651 652 enum { 653 G_18DB = 0, 654 G_16P5DB, 655 G_15DB, 656 G_13P5DB, 657 G_12DB, 658 G_10P5DB, 659 G_9DB, 660 G_7P5DB, 661 G_6DB, 662 G_4P5DB, 663 G_3DB, 664 G_1P5DB, 665 G_0DB, 666 }; 667 668 /* 669 * Private data Structure for wsa881x. All parameters related to 670 * WSA881X codec needs to be defined here. 671 */ 672 struct wsa881x_priv { 673 struct regmap *regmap; 674 struct device *dev; 675 struct sdw_slave *slave; 676 struct sdw_stream_config sconfig; 677 struct sdw_stream_runtime *sruntime; 678 struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS]; 679 struct gpio_desc *sd_n; 680 int version; 681 int active_ports; 682 bool port_prepared[WSA881X_MAX_SWR_PORTS]; 683 bool port_enable[WSA881X_MAX_SWR_PORTS]; 684 }; 685 686 static void wsa881x_init(struct wsa881x_priv *wsa881x) 687 { 688 struct regmap *rm = wsa881x->regmap; 689 unsigned int val = 0; 690 691 regmap_read(rm, WSA881X_CHIP_ID1, &wsa881x->version); 692 regmap_register_patch(wsa881x->regmap, wsa881x_rev_2_0, 693 ARRAY_SIZE(wsa881x_rev_2_0)); 694 695 /* Enable software reset output from soundwire slave */ 696 regmap_update_bits(rm, WSA881X_SWR_RESET_EN, 0x07, 0x07); 697 698 /* Bring out of analog reset */ 699 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x02, 0x02); 700 701 /* Bring out of digital reset */ 702 regmap_update_bits(rm, WSA881X_CDC_RST_CTL, 0x01, 0x01); 703 regmap_update_bits(rm, WSA881X_CLOCK_CONFIG, 0x10, 0x10); 704 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x02, 0x02); 705 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80); 706 regmap_update_bits(rm, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06); 707 regmap_update_bits(rm, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00); 708 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0xF0, 0x40); 709 regmap_update_bits(rm, WSA881X_SPKR_PA_INT, 0x0E, 0x0E); 710 regmap_update_bits(rm, WSA881X_BOOST_LOOP_STABILITY, 0x03, 0x03); 711 regmap_update_bits(rm, WSA881X_BOOST_MISC2_CTL, 0xFF, 0x14); 712 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x80, 0x80); 713 regmap_update_bits(rm, WSA881X_BOOST_START_CTL, 0x03, 0x00); 714 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x0C, 0x04); 715 regmap_update_bits(rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x03, 0x00); 716 717 regmap_read(rm, WSA881X_OTP_REG_0, &val); 718 if (val) 719 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT1, 0xF0, 0x70); 720 721 regmap_update_bits(rm, WSA881X_BOOST_PRESET_OUT2, 0xF0, 0x30); 722 regmap_update_bits(rm, WSA881X_SPKR_DRV_EN, 0x08, 0x08); 723 regmap_update_bits(rm, WSA881X_BOOST_CURRENT_LIMIT, 0x0F, 0x08); 724 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x30, 0x30); 725 regmap_update_bits(rm, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00); 726 regmap_update_bits(rm, WSA881X_OTP_REG_28, 0x3F, 0x3A); 727 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG1, 0xFF, 0xB2); 728 regmap_update_bits(rm, WSA881X_BONGO_RESRV_REG2, 0xFF, 0x05); 729 } 730 731 static int wsa881x_component_probe(struct snd_soc_component *comp) 732 { 733 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 734 735 snd_soc_component_init_regmap(comp, wsa881x->regmap); 736 737 return 0; 738 } 739 740 static int wsa881x_put_pa_gain(struct snd_kcontrol *kc, 741 struct snd_ctl_elem_value *ucontrol) 742 { 743 struct snd_soc_component *comp = snd_soc_kcontrol_component(kc); 744 struct soc_mixer_control *mc = 745 (struct soc_mixer_control *)kc->private_value; 746 int max = mc->max; 747 unsigned int mask = (1 << fls(max)) - 1; 748 int val, ret, min_gain, max_gain; 749 750 max_gain = (max - ucontrol->value.integer.value[0]) & mask; 751 /* 752 * Gain has to set incrementally in 4 steps 753 * as per HW sequence 754 */ 755 if (max_gain > G_4P5DB) 756 min_gain = G_0DB; 757 else 758 min_gain = max_gain + 3; 759 /* 760 * 1ms delay is needed before change in gain 761 * as per HW requirement. 762 */ 763 usleep_range(1000, 1010); 764 765 for (val = min_gain; max_gain <= val; val--) { 766 ret = snd_soc_component_update_bits(comp, 767 WSA881X_SPKR_DRV_GAIN, 768 WSA881X_SPKR_PAG_GAIN_MASK, 769 val << 4); 770 if (ret < 0) 771 dev_err(comp->dev, "Failed to change PA gain"); 772 773 usleep_range(1000, 1010); 774 } 775 return 0; 776 } 777 778 static int wsa881x_get_port(struct snd_kcontrol *kcontrol, 779 struct snd_ctl_elem_value *ucontrol) 780 { 781 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 782 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp); 783 struct soc_mixer_control *mixer = 784 (struct soc_mixer_control *)kcontrol->private_value; 785 int portidx = mixer->reg; 786 787 ucontrol->value.integer.value[0] = data->port_enable[portidx]; 788 789 790 return 0; 791 } 792 793 static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable) 794 { 795 if (enable) 796 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL, 797 WSA881X_BOOST_EN_MASK, 798 WSA881X_BOOST_EN); 799 else 800 snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL, 801 WSA881X_BOOST_EN_MASK, 0); 802 /* 803 * 1.5ms sleep is needed after boost enable/disable as per 804 * HW requirement 805 */ 806 usleep_range(1500, 1510); 807 return 0; 808 } 809 810 static int wsa881x_set_port(struct snd_kcontrol *kcontrol, 811 struct snd_ctl_elem_value *ucontrol) 812 { 813 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 814 struct wsa881x_priv *data = snd_soc_component_get_drvdata(comp); 815 struct soc_mixer_control *mixer = 816 (struct soc_mixer_control *)kcontrol->private_value; 817 int portidx = mixer->reg; 818 819 if (ucontrol->value.integer.value[0]) 820 data->port_enable[portidx] = true; 821 else 822 data->port_enable[portidx] = false; 823 824 if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */ 825 wsa881x_boost_ctrl(comp, data->port_enable[portidx]); 826 827 return 0; 828 } 829 830 static const char * const smart_boost_lvl_text[] = { 831 "6.625 V", "6.750 V", "6.875 V", "7.000 V", 832 "7.125 V", "7.250 V", "7.375 V", "7.500 V", 833 "7.625 V", "7.750 V", "7.875 V", "8.000 V", 834 "8.125 V", "8.250 V", "8.375 V", "8.500 V" 835 }; 836 837 static const struct soc_enum smart_boost_lvl_enum = 838 SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0, 839 ARRAY_SIZE(smart_boost_lvl_text), 840 smart_boost_lvl_text); 841 842 static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0); 843 844 static const struct snd_kcontrol_new wsa881x_snd_controls[] = { 845 SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum), 846 WSA881X_PA_GAIN_TLV("PA Volume", WSA881X_SPKR_DRV_GAIN, 847 4, 0xC, 1, pa_gain), 848 SOC_SINGLE_EXT("DAC Switch", WSA881X_PORT_DAC, 0, 1, 0, 849 wsa881x_get_port, wsa881x_set_port), 850 SOC_SINGLE_EXT("COMP Switch", WSA881X_PORT_COMP, 0, 1, 0, 851 wsa881x_get_port, wsa881x_set_port), 852 SOC_SINGLE_EXT("BOOST Switch", WSA881X_PORT_BOOST, 0, 1, 0, 853 wsa881x_get_port, wsa881x_set_port), 854 SOC_SINGLE_EXT("VISENSE Switch", WSA881X_PORT_VISENSE, 0, 1, 0, 855 wsa881x_get_port, wsa881x_set_port), 856 }; 857 858 static const struct snd_soc_dapm_route wsa881x_audio_map[] = { 859 { "RDAC", NULL, "IN" }, 860 { "RDAC", NULL, "DCLK" }, 861 { "RDAC", NULL, "ACLK" }, 862 { "RDAC", NULL, "Bandgap" }, 863 { "SPKR PGA", NULL, "RDAC" }, 864 { "SPKR", NULL, "SPKR PGA" }, 865 }; 866 867 static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp, 868 bool enable) 869 { 870 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 871 872 if (enable) { 873 regmap_multi_reg_write(wsa881x->regmap, wsa881x_vi_txfe_en_2_0, 874 ARRAY_SIZE(wsa881x_vi_txfe_en_2_0)); 875 } else { 876 snd_soc_component_update_bits(comp, 877 WSA881X_SPKR_PROT_FE_VSENSE_VCM, 878 0x08, 0x08); 879 /* 880 * 200us sleep is needed after visense txfe disable as per 881 * HW requirement. 882 */ 883 usleep_range(200, 210); 884 snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN, 885 0x01, 0x00); 886 } 887 return 0; 888 } 889 890 static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp, 891 bool enable) 892 { 893 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, BIT(7), 894 (enable << 7)); 895 snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, BIT(7), 896 (enable << 7)); 897 return 0; 898 } 899 900 static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w, 901 struct snd_kcontrol *kcontrol, int event) 902 { 903 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 904 struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp); 905 906 switch (event) { 907 case SND_SOC_DAPM_PRE_PMU: 908 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 909 WSA881X_SPKR_OCP_MASK, 910 WSA881X_SPKR_OCP_EN); 911 regmap_multi_reg_write(wsa881x->regmap, wsa881x_pre_pmu_pa_2_0, 912 ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0)); 913 914 snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN, 915 WSA881X_PA_GAIN_SEL_MASK, 916 WSA881X_PA_GAIN_SEL_REG); 917 break; 918 case SND_SOC_DAPM_POST_PMU: 919 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { 920 wsa881x_visense_txfe_ctrl(comp, true); 921 snd_soc_component_update_bits(comp, 922 WSA881X_ADC_EN_SEL_IBAIS, 923 0x07, 0x01); 924 wsa881x_visense_adc_ctrl(comp, true); 925 } 926 927 break; 928 case SND_SOC_DAPM_POST_PMD: 929 if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { 930 wsa881x_visense_adc_ctrl(comp, false); 931 wsa881x_visense_txfe_ctrl(comp, false); 932 } 933 934 snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 935 WSA881X_SPKR_OCP_MASK, 936 WSA881X_SPKR_OCP_EN | 937 WSA881X_SPKR_OCP_HOLD); 938 break; 939 } 940 return 0; 941 } 942 943 static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = { 944 SND_SOC_DAPM_INPUT("IN"), 945 SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0, 946 NULL, 947 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 948 SND_SOC_DAPM_PGA_E("SPKR PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 949 wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU | 950 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 951 SND_SOC_DAPM_SUPPLY("DCLK", WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL, 952 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 953 SND_SOC_DAPM_SUPPLY("ACLK", WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL, 954 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 955 SND_SOC_DAPM_SUPPLY("Bandgap", WSA881X_TEMP_OP, 3, 0, 956 NULL, 957 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 958 SND_SOC_DAPM_OUTPUT("SPKR"), 959 }; 960 961 static int wsa881x_hw_params(struct snd_pcm_substream *substream, 962 struct snd_pcm_hw_params *params, 963 struct snd_soc_dai *dai) 964 { 965 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 966 int i; 967 968 wsa881x->active_ports = 0; 969 for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) { 970 if (!wsa881x->port_enable[i]) 971 continue; 972 973 wsa881x->port_config[wsa881x->active_ports] = 974 wsa881x_pconfig[i]; 975 wsa881x->active_ports++; 976 } 977 978 return sdw_stream_add_slave(wsa881x->slave, &wsa881x->sconfig, 979 wsa881x->port_config, wsa881x->active_ports, 980 wsa881x->sruntime); 981 } 982 983 static int wsa881x_hw_free(struct snd_pcm_substream *substream, 984 struct snd_soc_dai *dai) 985 { 986 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 987 988 sdw_stream_remove_slave(wsa881x->slave, wsa881x->sruntime); 989 990 return 0; 991 } 992 993 static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai, 994 void *stream, int direction) 995 { 996 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 997 998 wsa881x->sruntime = stream; 999 1000 return 0; 1001 } 1002 1003 static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1004 { 1005 struct wsa881x_priv *wsa881x = dev_get_drvdata(dai->dev); 1006 1007 if (mute) 1008 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80, 1009 0x00); 1010 else 1011 regmap_update_bits(wsa881x->regmap, WSA881X_SPKR_DRV_EN, 0x80, 1012 0x80); 1013 1014 return 0; 1015 } 1016 1017 static struct snd_soc_dai_ops wsa881x_dai_ops = { 1018 .hw_params = wsa881x_hw_params, 1019 .hw_free = wsa881x_hw_free, 1020 .mute_stream = wsa881x_digital_mute, 1021 .set_sdw_stream = wsa881x_set_sdw_stream, 1022 }; 1023 1024 static struct snd_soc_dai_driver wsa881x_dais[] = { 1025 { 1026 .name = "SPKR", 1027 .id = 0, 1028 .playback = { 1029 .stream_name = "SPKR Playback", 1030 .rates = SNDRV_PCM_RATE_48000, 1031 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1032 .rate_max = 48000, 1033 .rate_min = 48000, 1034 .channels_min = 1, 1035 .channels_max = 1, 1036 }, 1037 .ops = &wsa881x_dai_ops, 1038 }, 1039 }; 1040 1041 static const struct snd_soc_component_driver wsa881x_component_drv = { 1042 .name = "WSA881x", 1043 .probe = wsa881x_component_probe, 1044 .controls = wsa881x_snd_controls, 1045 .num_controls = ARRAY_SIZE(wsa881x_snd_controls), 1046 .dapm_widgets = wsa881x_dapm_widgets, 1047 .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets), 1048 .dapm_routes = wsa881x_audio_map, 1049 .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map), 1050 }; 1051 1052 static int wsa881x_update_status(struct sdw_slave *slave, 1053 enum sdw_slave_status status) 1054 { 1055 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev); 1056 1057 if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0) 1058 wsa881x_init(wsa881x); 1059 1060 return 0; 1061 } 1062 1063 static int wsa881x_port_prep(struct sdw_slave *slave, 1064 struct sdw_prepare_ch *prepare_ch, 1065 enum sdw_port_prep_ops state) 1066 { 1067 struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev); 1068 1069 if (state == SDW_OPS_PORT_POST_PREP) 1070 wsa881x->port_prepared[prepare_ch->num - 1] = true; 1071 else 1072 wsa881x->port_prepared[prepare_ch->num - 1] = false; 1073 1074 return 0; 1075 } 1076 1077 static int wsa881x_bus_config(struct sdw_slave *slave, 1078 struct sdw_bus_params *params) 1079 { 1080 sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank), 1081 0x01); 1082 1083 return 0; 1084 } 1085 1086 static struct sdw_slave_ops wsa881x_slave_ops = { 1087 .update_status = wsa881x_update_status, 1088 .bus_config = wsa881x_bus_config, 1089 .port_prep = wsa881x_port_prep, 1090 }; 1091 1092 static int wsa881x_probe(struct sdw_slave *pdev, 1093 const struct sdw_device_id *id) 1094 { 1095 struct wsa881x_priv *wsa881x; 1096 1097 wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL); 1098 if (!wsa881x) 1099 return -ENOMEM; 1100 1101 wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "powerdown", 1102 GPIOD_FLAGS_BIT_NONEXCLUSIVE); 1103 if (IS_ERR(wsa881x->sd_n)) { 1104 dev_err(&pdev->dev, "Shutdown Control GPIO not found\n"); 1105 return PTR_ERR(wsa881x->sd_n); 1106 } 1107 1108 dev_set_drvdata(&pdev->dev, wsa881x); 1109 wsa881x->slave = pdev; 1110 wsa881x->dev = &pdev->dev; 1111 wsa881x->sconfig.ch_count = 1; 1112 wsa881x->sconfig.bps = 1; 1113 wsa881x->sconfig.frame_rate = 48000; 1114 wsa881x->sconfig.direction = SDW_DATA_DIR_RX; 1115 wsa881x->sconfig.type = SDW_STREAM_PDM; 1116 pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); 1117 pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; 1118 pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 1119 gpiod_direction_output(wsa881x->sd_n, 1); 1120 1121 wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config); 1122 if (IS_ERR(wsa881x->regmap)) { 1123 dev_err(&pdev->dev, "regmap_init failed\n"); 1124 return PTR_ERR(wsa881x->regmap); 1125 } 1126 1127 return devm_snd_soc_register_component(&pdev->dev, 1128 &wsa881x_component_drv, 1129 wsa881x_dais, 1130 ARRAY_SIZE(wsa881x_dais)); 1131 } 1132 1133 static const struct sdw_device_id wsa881x_slave_id[] = { 1134 SDW_SLAVE_ENTRY(0x0217, 0x2010, 0), 1135 SDW_SLAVE_ENTRY(0x0217, 0x2110, 0), 1136 {}, 1137 }; 1138 MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id); 1139 1140 static struct sdw_driver wsa881x_codec_driver = { 1141 .probe = wsa881x_probe, 1142 .ops = &wsa881x_slave_ops, 1143 .id_table = wsa881x_slave_id, 1144 .driver = { 1145 .name = "wsa881x-codec", 1146 } 1147 }; 1148 module_sdw_driver(wsa881x_codec_driver); 1149 1150 MODULE_DESCRIPTION("WSA881x codec driver"); 1151 MODULE_LICENSE("GPL v2"); 1152