1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * wm_adsp.c -- Wolfson ADSP support 4 * 5 * Copyright 2012 Wolfson Microelectronics plc 6 * 7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 */ 9 10 #include <linux/ctype.h> 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/firmware.h> 16 #include <linux/list.h> 17 #include <linux/pm.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regmap.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 #include <linux/vmalloc.h> 23 #include <linux/workqueue.h> 24 #include <linux/debugfs.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/jack.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "wm_adsp.h" 34 35 #define adsp_crit(_dsp, fmt, ...) \ 36 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 37 #define adsp_err(_dsp, fmt, ...) \ 38 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 39 #define adsp_warn(_dsp, fmt, ...) \ 40 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 41 #define adsp_info(_dsp, fmt, ...) \ 42 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 43 #define adsp_dbg(_dsp, fmt, ...) \ 44 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) 45 46 #define compr_err(_obj, fmt, ...) \ 47 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ 48 ##__VA_ARGS__) 49 #define compr_dbg(_obj, fmt, ...) \ 50 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ 51 ##__VA_ARGS__) 52 53 #define ADSP1_CONTROL_1 0x00 54 #define ADSP1_CONTROL_2 0x02 55 #define ADSP1_CONTROL_3 0x03 56 #define ADSP1_CONTROL_4 0x04 57 #define ADSP1_CONTROL_5 0x06 58 #define ADSP1_CONTROL_6 0x07 59 #define ADSP1_CONTROL_7 0x08 60 #define ADSP1_CONTROL_8 0x09 61 #define ADSP1_CONTROL_9 0x0A 62 #define ADSP1_CONTROL_10 0x0B 63 #define ADSP1_CONTROL_11 0x0C 64 #define ADSP1_CONTROL_12 0x0D 65 #define ADSP1_CONTROL_13 0x0F 66 #define ADSP1_CONTROL_14 0x10 67 #define ADSP1_CONTROL_15 0x11 68 #define ADSP1_CONTROL_16 0x12 69 #define ADSP1_CONTROL_17 0x13 70 #define ADSP1_CONTROL_18 0x14 71 #define ADSP1_CONTROL_19 0x16 72 #define ADSP1_CONTROL_20 0x17 73 #define ADSP1_CONTROL_21 0x18 74 #define ADSP1_CONTROL_22 0x1A 75 #define ADSP1_CONTROL_23 0x1B 76 #define ADSP1_CONTROL_24 0x1C 77 #define ADSP1_CONTROL_25 0x1E 78 #define ADSP1_CONTROL_26 0x20 79 #define ADSP1_CONTROL_27 0x21 80 #define ADSP1_CONTROL_28 0x22 81 #define ADSP1_CONTROL_29 0x23 82 #define ADSP1_CONTROL_30 0x24 83 #define ADSP1_CONTROL_31 0x26 84 85 /* 86 * ADSP1 Control 19 87 */ 88 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 89 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 90 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ 91 92 93 /* 94 * ADSP1 Control 30 95 */ 96 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ 97 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ 98 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ 99 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ 100 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 101 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 102 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 103 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 104 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 105 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 106 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 107 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 108 #define ADSP1_START 0x0001 /* DSP1_START */ 109 #define ADSP1_START_MASK 0x0001 /* DSP1_START */ 110 #define ADSP1_START_SHIFT 0 /* DSP1_START */ 111 #define ADSP1_START_WIDTH 1 /* DSP1_START */ 112 113 /* 114 * ADSP1 Control 31 115 */ 116 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 117 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 118 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 119 120 #define ADSP2_CONTROL 0x0 121 #define ADSP2_CLOCKING 0x1 122 #define ADSP2V2_CLOCKING 0x2 123 #define ADSP2_STATUS1 0x4 124 #define ADSP2_WDMA_CONFIG_1 0x30 125 #define ADSP2_WDMA_CONFIG_2 0x31 126 #define ADSP2V2_WDMA_CONFIG_2 0x32 127 #define ADSP2_RDMA_CONFIG_1 0x34 128 129 #define ADSP2_SCRATCH0 0x40 130 #define ADSP2_SCRATCH1 0x41 131 #define ADSP2_SCRATCH2 0x42 132 #define ADSP2_SCRATCH3 0x43 133 134 #define ADSP2V2_SCRATCH0_1 0x40 135 #define ADSP2V2_SCRATCH2_3 0x42 136 137 /* 138 * ADSP2 Control 139 */ 140 141 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ 142 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ 143 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ 144 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ 145 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ 146 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ 147 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ 148 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ 149 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ 150 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ 151 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ 152 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ 153 #define ADSP2_START 0x0001 /* DSP1_START */ 154 #define ADSP2_START_MASK 0x0001 /* DSP1_START */ 155 #define ADSP2_START_SHIFT 0 /* DSP1_START */ 156 #define ADSP2_START_WIDTH 1 /* DSP1_START */ 157 158 /* 159 * ADSP2 clocking 160 */ 161 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ 162 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ 163 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 164 165 /* 166 * ADSP2V2 clocking 167 */ 168 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ 169 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ 170 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ 171 172 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ 173 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ 174 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ 175 176 /* 177 * ADSP2 Status 1 178 */ 179 #define ADSP2_RAM_RDY 0x0001 180 #define ADSP2_RAM_RDY_MASK 0x0001 181 #define ADSP2_RAM_RDY_SHIFT 0 182 #define ADSP2_RAM_RDY_WIDTH 1 183 184 /* 185 * ADSP2 Lock support 186 */ 187 #define ADSP2_LOCK_CODE_0 0x5555 188 #define ADSP2_LOCK_CODE_1 0xAAAA 189 190 #define ADSP2_WATCHDOG 0x0A 191 #define ADSP2_BUS_ERR_ADDR 0x52 192 #define ADSP2_REGION_LOCK_STATUS 0x64 193 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 194 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 195 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A 196 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C 197 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E 198 #define ADSP2_LOCK_REGION_CTRL 0x7A 199 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C 200 201 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000 202 #define ADSP2_ADDR_ERR_MASK 0x4000 203 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 204 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 205 #define ADSP2_CTRL_ERR_EINT 0x0001 206 207 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF 208 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF 209 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 210 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16 211 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD 212 213 #define ADSP2_LOCK_REGION_SHIFT 16 214 215 #define ADSP_MAX_STD_CTRL_SIZE 512 216 217 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 218 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 219 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0 220 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF 221 222 /* 223 * Event control messages 224 */ 225 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 226 227 /* 228 * HALO system info 229 */ 230 #define HALO_AHBM_WINDOW_DEBUG_0 0x02040 231 #define HALO_AHBM_WINDOW_DEBUG_1 0x02044 232 233 /* 234 * HALO core 235 */ 236 #define HALO_SCRATCH1 0x005c0 237 #define HALO_SCRATCH2 0x005c8 238 #define HALO_SCRATCH3 0x005d0 239 #define HALO_SCRATCH4 0x005d8 240 #define HALO_CCM_CORE_CONTROL 0x41000 241 #define HALO_CORE_SOFT_RESET 0x00010 242 #define HALO_WDT_CONTROL 0x47000 243 244 /* 245 * HALO MPU banks 246 */ 247 #define HALO_MPU_XMEM_ACCESS_0 0x43000 248 #define HALO_MPU_YMEM_ACCESS_0 0x43004 249 #define HALO_MPU_WINDOW_ACCESS_0 0x43008 250 #define HALO_MPU_XREG_ACCESS_0 0x4300C 251 #define HALO_MPU_YREG_ACCESS_0 0x43014 252 #define HALO_MPU_XMEM_ACCESS_1 0x43018 253 #define HALO_MPU_YMEM_ACCESS_1 0x4301C 254 #define HALO_MPU_WINDOW_ACCESS_1 0x43020 255 #define HALO_MPU_XREG_ACCESS_1 0x43024 256 #define HALO_MPU_YREG_ACCESS_1 0x4302C 257 #define HALO_MPU_XMEM_ACCESS_2 0x43030 258 #define HALO_MPU_YMEM_ACCESS_2 0x43034 259 #define HALO_MPU_WINDOW_ACCESS_2 0x43038 260 #define HALO_MPU_XREG_ACCESS_2 0x4303C 261 #define HALO_MPU_YREG_ACCESS_2 0x43044 262 #define HALO_MPU_XMEM_ACCESS_3 0x43048 263 #define HALO_MPU_YMEM_ACCESS_3 0x4304C 264 #define HALO_MPU_WINDOW_ACCESS_3 0x43050 265 #define HALO_MPU_XREG_ACCESS_3 0x43054 266 #define HALO_MPU_YREG_ACCESS_3 0x4305C 267 #define HALO_MPU_XM_VIO_ADDR 0x43100 268 #define HALO_MPU_XM_VIO_STATUS 0x43104 269 #define HALO_MPU_YM_VIO_ADDR 0x43108 270 #define HALO_MPU_YM_VIO_STATUS 0x4310C 271 #define HALO_MPU_PM_VIO_ADDR 0x43110 272 #define HALO_MPU_PM_VIO_STATUS 0x43114 273 #define HALO_MPU_LOCK_CONFIG 0x43140 274 275 /* 276 * HALO_AHBM_WINDOW_DEBUG_1 277 */ 278 #define HALO_AHBM_CORE_ERR_ADDR_MASK 0x0fffff00 279 #define HALO_AHBM_CORE_ERR_ADDR_SHIFT 8 280 #define HALO_AHBM_FLAGS_ERR_MASK 0x000000ff 281 282 /* 283 * HALO_CCM_CORE_CONTROL 284 */ 285 #define HALO_CORE_RESET 0x00000200 286 #define HALO_CORE_EN 0x00000001 287 288 /* 289 * HALO_CORE_SOFT_RESET 290 */ 291 #define HALO_CORE_SOFT_RESET_MASK 0x00000001 292 293 /* 294 * HALO_WDT_CONTROL 295 */ 296 #define HALO_WDT_EN_MASK 0x00000001 297 298 /* 299 * HALO_MPU_?M_VIO_STATUS 300 */ 301 #define HALO_MPU_VIO_STS_MASK 0x007e0000 302 #define HALO_MPU_VIO_STS_SHIFT 17 303 #define HALO_MPU_VIO_ERR_WR_MASK 0x00008000 304 #define HALO_MPU_VIO_ERR_SRC_MASK 0x00007fff 305 #define HALO_MPU_VIO_ERR_SRC_SHIFT 0 306 307 static const struct wm_adsp_ops wm_adsp1_ops; 308 static const struct wm_adsp_ops wm_adsp2_ops[]; 309 static const struct wm_adsp_ops wm_halo_ops; 310 311 struct wm_adsp_buf { 312 struct list_head list; 313 void *buf; 314 }; 315 316 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, 317 struct list_head *list) 318 { 319 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); 320 321 if (buf == NULL) 322 return NULL; 323 324 buf->buf = vmalloc(len); 325 if (!buf->buf) { 326 kfree(buf); 327 return NULL; 328 } 329 memcpy(buf->buf, src, len); 330 331 if (list) 332 list_add_tail(&buf->list, list); 333 334 return buf; 335 } 336 337 static void wm_adsp_buf_free(struct list_head *list) 338 { 339 while (!list_empty(list)) { 340 struct wm_adsp_buf *buf = list_first_entry(list, 341 struct wm_adsp_buf, 342 list); 343 list_del(&buf->list); 344 vfree(buf->buf); 345 kfree(buf); 346 } 347 } 348 349 #define WM_ADSP_FW_MBC_VSS 0 350 #define WM_ADSP_FW_HIFI 1 351 #define WM_ADSP_FW_TX 2 352 #define WM_ADSP_FW_TX_SPK 3 353 #define WM_ADSP_FW_RX 4 354 #define WM_ADSP_FW_RX_ANC 5 355 #define WM_ADSP_FW_CTRL 6 356 #define WM_ADSP_FW_ASR 7 357 #define WM_ADSP_FW_TRACE 8 358 #define WM_ADSP_FW_SPK_PROT 9 359 #define WM_ADSP_FW_SPK_CALI 10 360 #define WM_ADSP_FW_SPK_DIAG 11 361 #define WM_ADSP_FW_MISC 12 362 363 #define WM_ADSP_NUM_FW 13 364 365 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { 366 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", 367 [WM_ADSP_FW_HIFI] = "MasterHiFi", 368 [WM_ADSP_FW_TX] = "Tx", 369 [WM_ADSP_FW_TX_SPK] = "Tx Speaker", 370 [WM_ADSP_FW_RX] = "Rx", 371 [WM_ADSP_FW_RX_ANC] = "Rx ANC", 372 [WM_ADSP_FW_CTRL] = "Voice Ctrl", 373 [WM_ADSP_FW_ASR] = "ASR Assist", 374 [WM_ADSP_FW_TRACE] = "Dbg Trace", 375 [WM_ADSP_FW_SPK_PROT] = "Protection", 376 [WM_ADSP_FW_SPK_CALI] = "Calibration", 377 [WM_ADSP_FW_SPK_DIAG] = "Diagnostic", 378 [WM_ADSP_FW_MISC] = "Misc", 379 }; 380 381 struct wm_adsp_system_config_xm_hdr { 382 __be32 sys_enable; 383 __be32 fw_id; 384 __be32 fw_rev; 385 __be32 boot_status; 386 __be32 watchdog; 387 __be32 dma_buffer_size; 388 __be32 rdma[6]; 389 __be32 wdma[8]; 390 __be32 build_job_name[3]; 391 __be32 build_job_number; 392 }; 393 394 struct wm_halo_system_config_xm_hdr { 395 __be32 halo_heartbeat; 396 __be32 build_job_name[3]; 397 __be32 build_job_number; 398 }; 399 400 struct wm_adsp_alg_xm_struct { 401 __be32 magic; 402 __be32 smoothing; 403 __be32 threshold; 404 __be32 host_buf_ptr; 405 __be32 start_seq; 406 __be32 high_water_mark; 407 __be32 low_water_mark; 408 __be64 smoothed_power; 409 }; 410 411 struct wm_adsp_host_buf_coeff_v1 { 412 __be32 host_buf_ptr; /* Host buffer pointer */ 413 __be32 versions; /* Version numbers */ 414 __be32 name[4]; /* The buffer name */ 415 }; 416 417 struct wm_adsp_buffer { 418 __be32 buf1_base; /* Base addr of first buffer area */ 419 __be32 buf1_size; /* Size of buf1 area in DSP words */ 420 __be32 buf2_base; /* Base addr of 2nd buffer area */ 421 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */ 422 __be32 buf3_base; /* Base addr of buf3 area */ 423 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */ 424 __be32 high_water_mark; /* Point at which IRQ is asserted */ 425 __be32 irq_count; /* bits 1-31 count IRQ assertions */ 426 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ 427 __be32 next_write_index; /* word index of next write */ 428 __be32 next_read_index; /* word index of next read */ 429 __be32 error; /* error if any */ 430 __be32 oldest_block_index; /* word index of oldest surviving */ 431 __be32 requested_rewind; /* how many blocks rewind was done */ 432 __be32 reserved_space; /* internal */ 433 __be32 min_free; /* min free space since stream start */ 434 __be32 blocks_written[2]; /* total blocks written (64 bit) */ 435 __be32 words_written[2]; /* total words written (64 bit) */ 436 }; 437 438 struct wm_adsp_compr; 439 440 struct wm_adsp_compr_buf { 441 struct list_head list; 442 struct wm_adsp *dsp; 443 struct wm_adsp_compr *compr; 444 445 struct wm_adsp_buffer_region *regions; 446 u32 host_buf_ptr; 447 448 u32 error; 449 u32 irq_count; 450 int read_index; 451 int avail; 452 int host_buf_mem_type; 453 454 char *name; 455 }; 456 457 struct wm_adsp_compr { 458 struct list_head list; 459 struct wm_adsp *dsp; 460 struct wm_adsp_compr_buf *buf; 461 462 struct snd_compr_stream *stream; 463 struct snd_compressed_buffer size; 464 465 u32 *raw_buf; 466 unsigned int copied_total; 467 468 unsigned int sample_rate; 469 470 const char *name; 471 }; 472 473 #define WM_ADSP_DATA_WORD_SIZE 3 474 475 #define WM_ADSP_MIN_FRAGMENTS 1 476 #define WM_ADSP_MAX_FRAGMENTS 256 477 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE) 478 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE) 479 480 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 481 482 #define HOST_BUFFER_FIELD(field) \ 483 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32)) 484 485 #define ALG_XM_FIELD(field) \ 486 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) 487 488 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1 489 490 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00 491 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8 492 493 static int wm_adsp_buffer_init(struct wm_adsp *dsp); 494 static int wm_adsp_buffer_free(struct wm_adsp *dsp); 495 496 struct wm_adsp_buffer_region { 497 unsigned int offset; 498 unsigned int cumulative_size; 499 unsigned int mem_type; 500 unsigned int base_addr; 501 }; 502 503 struct wm_adsp_buffer_region_def { 504 unsigned int mem_type; 505 unsigned int base_offset; 506 unsigned int size_offset; 507 }; 508 509 static const struct wm_adsp_buffer_region_def default_regions[] = { 510 { 511 .mem_type = WMFW_ADSP2_XM, 512 .base_offset = HOST_BUFFER_FIELD(buf1_base), 513 .size_offset = HOST_BUFFER_FIELD(buf1_size), 514 }, 515 { 516 .mem_type = WMFW_ADSP2_XM, 517 .base_offset = HOST_BUFFER_FIELD(buf2_base), 518 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), 519 }, 520 { 521 .mem_type = WMFW_ADSP2_YM, 522 .base_offset = HOST_BUFFER_FIELD(buf3_base), 523 .size_offset = HOST_BUFFER_FIELD(buf_total_size), 524 }, 525 }; 526 527 struct wm_adsp_fw_caps { 528 u32 id; 529 struct snd_codec_desc desc; 530 int num_regions; 531 const struct wm_adsp_buffer_region_def *region_defs; 532 }; 533 534 static const struct wm_adsp_fw_caps ctrl_caps[] = { 535 { 536 .id = SND_AUDIOCODEC_BESPOKE, 537 .desc = { 538 .max_ch = 8, 539 .sample_rates = { 16000 }, 540 .num_sample_rates = 1, 541 .formats = SNDRV_PCM_FMTBIT_S16_LE, 542 }, 543 .num_regions = ARRAY_SIZE(default_regions), 544 .region_defs = default_regions, 545 }, 546 }; 547 548 static const struct wm_adsp_fw_caps trace_caps[] = { 549 { 550 .id = SND_AUDIOCODEC_BESPOKE, 551 .desc = { 552 .max_ch = 8, 553 .sample_rates = { 554 4000, 8000, 11025, 12000, 16000, 22050, 555 24000, 32000, 44100, 48000, 64000, 88200, 556 96000, 176400, 192000 557 }, 558 .num_sample_rates = 15, 559 .formats = SNDRV_PCM_FMTBIT_S16_LE, 560 }, 561 .num_regions = ARRAY_SIZE(default_regions), 562 .region_defs = default_regions, 563 }, 564 }; 565 566 static const struct { 567 const char *file; 568 int compr_direction; 569 int num_caps; 570 const struct wm_adsp_fw_caps *caps; 571 bool voice_trigger; 572 } wm_adsp_fw[WM_ADSP_NUM_FW] = { 573 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, 574 [WM_ADSP_FW_HIFI] = { .file = "hifi" }, 575 [WM_ADSP_FW_TX] = { .file = "tx" }, 576 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, 577 [WM_ADSP_FW_RX] = { .file = "rx" }, 578 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, 579 [WM_ADSP_FW_CTRL] = { 580 .file = "ctrl", 581 .compr_direction = SND_COMPRESS_CAPTURE, 582 .num_caps = ARRAY_SIZE(ctrl_caps), 583 .caps = ctrl_caps, 584 .voice_trigger = true, 585 }, 586 [WM_ADSP_FW_ASR] = { .file = "asr" }, 587 [WM_ADSP_FW_TRACE] = { 588 .file = "trace", 589 .compr_direction = SND_COMPRESS_CAPTURE, 590 .num_caps = ARRAY_SIZE(trace_caps), 591 .caps = trace_caps, 592 }, 593 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, 594 [WM_ADSP_FW_SPK_CALI] = { .file = "spk-cali" }, 595 [WM_ADSP_FW_SPK_DIAG] = { .file = "spk-diag" }, 596 [WM_ADSP_FW_MISC] = { .file = "misc" }, 597 }; 598 599 struct wm_coeff_ctl { 600 const char *name; 601 const char *fw_name; 602 /* Subname is needed to match with firmware */ 603 const char *subname; 604 unsigned int subname_len; 605 struct wm_adsp_alg_region alg_region; 606 struct wm_adsp *dsp; 607 unsigned int enabled:1; 608 struct list_head list; 609 void *cache; 610 unsigned int offset; 611 size_t len; 612 unsigned int set:1; 613 struct soc_bytes_ext bytes_ext; 614 unsigned int flags; 615 snd_ctl_elem_type_t type; 616 }; 617 618 static const char *wm_adsp_mem_region_name(unsigned int type) 619 { 620 switch (type) { 621 case WMFW_ADSP1_PM: 622 return "PM"; 623 case WMFW_HALO_PM_PACKED: 624 return "PM_PACKED"; 625 case WMFW_ADSP1_DM: 626 return "DM"; 627 case WMFW_ADSP2_XM: 628 return "XM"; 629 case WMFW_HALO_XM_PACKED: 630 return "XM_PACKED"; 631 case WMFW_ADSP2_YM: 632 return "YM"; 633 case WMFW_HALO_YM_PACKED: 634 return "YM_PACKED"; 635 case WMFW_ADSP1_ZM: 636 return "ZM"; 637 default: 638 return NULL; 639 } 640 } 641 642 #ifdef CONFIG_DEBUG_FS 643 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) 644 { 645 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); 646 647 kfree(dsp->wmfw_file_name); 648 dsp->wmfw_file_name = tmp; 649 } 650 651 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) 652 { 653 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); 654 655 kfree(dsp->bin_file_name); 656 dsp->bin_file_name = tmp; 657 } 658 659 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) 660 { 661 kfree(dsp->wmfw_file_name); 662 kfree(dsp->bin_file_name); 663 dsp->wmfw_file_name = NULL; 664 dsp->bin_file_name = NULL; 665 } 666 667 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, 668 char __user *user_buf, 669 size_t count, loff_t *ppos) 670 { 671 struct wm_adsp *dsp = file->private_data; 672 ssize_t ret; 673 674 mutex_lock(&dsp->pwr_lock); 675 676 if (!dsp->wmfw_file_name || !dsp->booted) 677 ret = 0; 678 else 679 ret = simple_read_from_buffer(user_buf, count, ppos, 680 dsp->wmfw_file_name, 681 strlen(dsp->wmfw_file_name)); 682 683 mutex_unlock(&dsp->pwr_lock); 684 return ret; 685 } 686 687 static ssize_t wm_adsp_debugfs_bin_read(struct file *file, 688 char __user *user_buf, 689 size_t count, loff_t *ppos) 690 { 691 struct wm_adsp *dsp = file->private_data; 692 ssize_t ret; 693 694 mutex_lock(&dsp->pwr_lock); 695 696 if (!dsp->bin_file_name || !dsp->booted) 697 ret = 0; 698 else 699 ret = simple_read_from_buffer(user_buf, count, ppos, 700 dsp->bin_file_name, 701 strlen(dsp->bin_file_name)); 702 703 mutex_unlock(&dsp->pwr_lock); 704 return ret; 705 } 706 707 static const struct { 708 const char *name; 709 const struct file_operations fops; 710 } wm_adsp_debugfs_fops[] = { 711 { 712 .name = "wmfw_file_name", 713 .fops = { 714 .open = simple_open, 715 .read = wm_adsp_debugfs_wmfw_read, 716 }, 717 }, 718 { 719 .name = "bin_file_name", 720 .fops = { 721 .open = simple_open, 722 .read = wm_adsp_debugfs_bin_read, 723 }, 724 }, 725 }; 726 727 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, 728 struct snd_soc_component *component) 729 { 730 struct dentry *root = NULL; 731 int i; 732 733 root = debugfs_create_dir(dsp->name, component->debugfs_root); 734 735 debugfs_create_bool("booted", 0444, root, &dsp->booted); 736 debugfs_create_bool("running", 0444, root, &dsp->running); 737 debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id); 738 debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version); 739 740 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) 741 debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root, 742 dsp, &wm_adsp_debugfs_fops[i].fops); 743 744 dsp->debugfs_root = root; 745 } 746 747 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) 748 { 749 wm_adsp_debugfs_clear(dsp); 750 debugfs_remove_recursive(dsp->debugfs_root); 751 dsp->debugfs_root = NULL; 752 } 753 #else 754 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, 755 struct snd_soc_component *component) 756 { 757 } 758 759 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) 760 { 761 } 762 763 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, 764 const char *s) 765 { 766 } 767 768 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, 769 const char *s) 770 { 771 } 772 773 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) 774 { 775 } 776 #endif 777 778 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, 779 struct snd_ctl_elem_value *ucontrol) 780 { 781 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 782 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 783 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); 784 785 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw; 786 787 return 0; 788 } 789 EXPORT_SYMBOL_GPL(wm_adsp_fw_get); 790 791 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, 792 struct snd_ctl_elem_value *ucontrol) 793 { 794 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 795 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 796 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); 797 int ret = 0; 798 799 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw) 800 return 0; 801 802 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW) 803 return -EINVAL; 804 805 mutex_lock(&dsp[e->shift_l].pwr_lock); 806 807 if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list)) 808 ret = -EBUSY; 809 else 810 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; 811 812 mutex_unlock(&dsp[e->shift_l].pwr_lock); 813 814 return ret; 815 } 816 EXPORT_SYMBOL_GPL(wm_adsp_fw_put); 817 818 const struct soc_enum wm_adsp_fw_enum[] = { 819 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 820 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 821 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 822 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 823 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 824 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 825 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), 826 }; 827 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum); 828 829 static const struct wm_adsp_region *wm_adsp_find_region(struct wm_adsp *dsp, 830 int type) 831 { 832 int i; 833 834 for (i = 0; i < dsp->num_mems; i++) 835 if (dsp->mem[i].type == type) 836 return &dsp->mem[i]; 837 838 return NULL; 839 } 840 841 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, 842 unsigned int offset) 843 { 844 switch (mem->type) { 845 case WMFW_ADSP1_PM: 846 return mem->base + (offset * 3); 847 case WMFW_ADSP1_DM: 848 case WMFW_ADSP2_XM: 849 case WMFW_ADSP2_YM: 850 case WMFW_ADSP1_ZM: 851 return mem->base + (offset * 2); 852 default: 853 WARN(1, "Unknown memory region type"); 854 return offset; 855 } 856 } 857 858 static unsigned int wm_halo_region_to_reg(struct wm_adsp_region const *mem, 859 unsigned int offset) 860 { 861 switch (mem->type) { 862 case WMFW_ADSP2_XM: 863 case WMFW_ADSP2_YM: 864 return mem->base + (offset * 4); 865 case WMFW_HALO_XM_PACKED: 866 case WMFW_HALO_YM_PACKED: 867 return (mem->base + (offset * 3)) & ~0x3; 868 case WMFW_HALO_PM_PACKED: 869 return mem->base + (offset * 5); 870 default: 871 WARN(1, "Unknown memory region type"); 872 return offset; 873 } 874 } 875 876 static void wm_adsp_read_fw_status(struct wm_adsp *dsp, 877 int noffs, unsigned int *offs) 878 { 879 unsigned int i; 880 int ret; 881 882 for (i = 0; i < noffs; ++i) { 883 ret = regmap_read(dsp->regmap, dsp->base + offs[i], &offs[i]); 884 if (ret) { 885 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); 886 return; 887 } 888 } 889 } 890 891 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) 892 { 893 unsigned int offs[] = { 894 ADSP2_SCRATCH0, ADSP2_SCRATCH1, ADSP2_SCRATCH2, ADSP2_SCRATCH3, 895 }; 896 897 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 898 899 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 900 offs[0], offs[1], offs[2], offs[3]); 901 } 902 903 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) 904 { 905 unsigned int offs[] = { ADSP2V2_SCRATCH0_1, ADSP2V2_SCRATCH2_3 }; 906 907 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 908 909 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 910 offs[0] & 0xFFFF, offs[0] >> 16, 911 offs[1] & 0xFFFF, offs[1] >> 16); 912 } 913 914 static void wm_halo_show_fw_status(struct wm_adsp *dsp) 915 { 916 unsigned int offs[] = { 917 HALO_SCRATCH1, HALO_SCRATCH2, HALO_SCRATCH3, HALO_SCRATCH4, 918 }; 919 920 wm_adsp_read_fw_status(dsp, ARRAY_SIZE(offs), offs); 921 922 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", 923 offs[0], offs[1], offs[2], offs[3]); 924 } 925 926 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) 927 { 928 return container_of(ext, struct wm_coeff_ctl, bytes_ext); 929 } 930 931 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) 932 { 933 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; 934 struct wm_adsp *dsp = ctl->dsp; 935 const struct wm_adsp_region *mem; 936 937 mem = wm_adsp_find_region(dsp, alg_region->type); 938 if (!mem) { 939 adsp_err(dsp, "No base for region %x\n", 940 alg_region->type); 941 return -EINVAL; 942 } 943 944 *reg = dsp->ops->region_to_reg(mem, ctl->alg_region.base + ctl->offset); 945 946 return 0; 947 } 948 949 static int wm_coeff_info(struct snd_kcontrol *kctl, 950 struct snd_ctl_elem_info *uinfo) 951 { 952 struct soc_bytes_ext *bytes_ext = 953 (struct soc_bytes_ext *)kctl->private_value; 954 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 955 956 switch (ctl->type) { 957 case WMFW_CTL_TYPE_ACKED: 958 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 959 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; 960 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; 961 uinfo->value.integer.step = 1; 962 uinfo->count = 1; 963 break; 964 default: 965 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 966 uinfo->count = ctl->len; 967 break; 968 } 969 970 return 0; 971 } 972 973 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, 974 unsigned int event_id) 975 { 976 struct wm_adsp *dsp = ctl->dsp; 977 __be32 val = cpu_to_be32(event_id); 978 unsigned int reg; 979 int i, ret; 980 981 ret = wm_coeff_base_reg(ctl, ®); 982 if (ret) 983 return ret; 984 985 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", 986 event_id, ctl->alg_region.alg, 987 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); 988 989 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 990 if (ret) { 991 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); 992 return ret; 993 } 994 995 /* 996 * Poll for ack, we initially poll at ~1ms intervals for firmwares 997 * that respond quickly, then go to ~10ms polls. A firmware is unlikely 998 * to ack instantly so we do the first 1ms delay before reading the 999 * control to avoid a pointless bus transaction 1000 */ 1001 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { 1002 switch (i) { 1003 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: 1004 usleep_range(1000, 2000); 1005 i++; 1006 break; 1007 default: 1008 usleep_range(10000, 20000); 1009 i += 10; 1010 break; 1011 } 1012 1013 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 1014 if (ret) { 1015 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); 1016 return ret; 1017 } 1018 1019 if (val == 0) { 1020 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); 1021 return 0; 1022 } 1023 } 1024 1025 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", 1026 reg, ctl->alg_region.alg, 1027 wm_adsp_mem_region_name(ctl->alg_region.type), 1028 ctl->offset); 1029 1030 return -ETIMEDOUT; 1031 } 1032 1033 static int wm_coeff_write_ctrl_raw(struct wm_coeff_ctl *ctl, 1034 const void *buf, size_t len) 1035 { 1036 struct wm_adsp *dsp = ctl->dsp; 1037 void *scratch; 1038 int ret; 1039 unsigned int reg; 1040 1041 ret = wm_coeff_base_reg(ctl, ®); 1042 if (ret) 1043 return ret; 1044 1045 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); 1046 if (!scratch) 1047 return -ENOMEM; 1048 1049 ret = regmap_raw_write(dsp->regmap, reg, scratch, 1050 len); 1051 if (ret) { 1052 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", 1053 len, reg, ret); 1054 kfree(scratch); 1055 return ret; 1056 } 1057 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); 1058 1059 kfree(scratch); 1060 1061 return 0; 1062 } 1063 1064 static int wm_coeff_write_ctrl(struct wm_coeff_ctl *ctl, 1065 const void *buf, size_t len) 1066 { 1067 int ret = 0; 1068 1069 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) 1070 ret = -EPERM; 1071 else if (buf != ctl->cache) 1072 memcpy(ctl->cache, buf, len); 1073 1074 ctl->set = 1; 1075 if (ctl->enabled && ctl->dsp->running) 1076 ret = wm_coeff_write_ctrl_raw(ctl, buf, len); 1077 1078 return ret; 1079 } 1080 1081 static int wm_coeff_put(struct snd_kcontrol *kctl, 1082 struct snd_ctl_elem_value *ucontrol) 1083 { 1084 struct soc_bytes_ext *bytes_ext = 1085 (struct soc_bytes_ext *)kctl->private_value; 1086 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 1087 char *p = ucontrol->value.bytes.data; 1088 int ret = 0; 1089 1090 mutex_lock(&ctl->dsp->pwr_lock); 1091 ret = wm_coeff_write_ctrl(ctl, p, ctl->len); 1092 mutex_unlock(&ctl->dsp->pwr_lock); 1093 1094 return ret; 1095 } 1096 1097 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, 1098 const unsigned int __user *bytes, unsigned int size) 1099 { 1100 struct soc_bytes_ext *bytes_ext = 1101 (struct soc_bytes_ext *)kctl->private_value; 1102 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 1103 int ret = 0; 1104 1105 mutex_lock(&ctl->dsp->pwr_lock); 1106 1107 if (copy_from_user(ctl->cache, bytes, size)) 1108 ret = -EFAULT; 1109 else 1110 ret = wm_coeff_write_ctrl(ctl, ctl->cache, size); 1111 1112 mutex_unlock(&ctl->dsp->pwr_lock); 1113 1114 return ret; 1115 } 1116 1117 static int wm_coeff_put_acked(struct snd_kcontrol *kctl, 1118 struct snd_ctl_elem_value *ucontrol) 1119 { 1120 struct soc_bytes_ext *bytes_ext = 1121 (struct soc_bytes_ext *)kctl->private_value; 1122 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 1123 unsigned int val = ucontrol->value.integer.value[0]; 1124 int ret; 1125 1126 if (val == 0) 1127 return 0; /* 0 means no event */ 1128 1129 mutex_lock(&ctl->dsp->pwr_lock); 1130 1131 if (ctl->enabled && ctl->dsp->running) 1132 ret = wm_coeff_write_acked_control(ctl, val); 1133 else 1134 ret = -EPERM; 1135 1136 mutex_unlock(&ctl->dsp->pwr_lock); 1137 1138 return ret; 1139 } 1140 1141 static int wm_coeff_read_ctrl_raw(struct wm_coeff_ctl *ctl, 1142 void *buf, size_t len) 1143 { 1144 struct wm_adsp *dsp = ctl->dsp; 1145 void *scratch; 1146 int ret; 1147 unsigned int reg; 1148 1149 ret = wm_coeff_base_reg(ctl, ®); 1150 if (ret) 1151 return ret; 1152 1153 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); 1154 if (!scratch) 1155 return -ENOMEM; 1156 1157 ret = regmap_raw_read(dsp->regmap, reg, scratch, len); 1158 if (ret) { 1159 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", 1160 len, reg, ret); 1161 kfree(scratch); 1162 return ret; 1163 } 1164 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); 1165 1166 memcpy(buf, scratch, len); 1167 kfree(scratch); 1168 1169 return 0; 1170 } 1171 1172 static int wm_coeff_read_ctrl(struct wm_coeff_ctl *ctl, void *buf, size_t len) 1173 { 1174 int ret = 0; 1175 1176 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { 1177 if (ctl->enabled && ctl->dsp->running) 1178 return wm_coeff_read_ctrl_raw(ctl, buf, len); 1179 else 1180 return -EPERM; 1181 } else { 1182 if (!ctl->flags && ctl->enabled && ctl->dsp->running) 1183 ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len); 1184 1185 if (buf != ctl->cache) 1186 memcpy(buf, ctl->cache, len); 1187 } 1188 1189 return ret; 1190 } 1191 1192 static int wm_coeff_get(struct snd_kcontrol *kctl, 1193 struct snd_ctl_elem_value *ucontrol) 1194 { 1195 struct soc_bytes_ext *bytes_ext = 1196 (struct soc_bytes_ext *)kctl->private_value; 1197 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 1198 char *p = ucontrol->value.bytes.data; 1199 int ret; 1200 1201 mutex_lock(&ctl->dsp->pwr_lock); 1202 ret = wm_coeff_read_ctrl(ctl, p, ctl->len); 1203 mutex_unlock(&ctl->dsp->pwr_lock); 1204 1205 return ret; 1206 } 1207 1208 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, 1209 unsigned int __user *bytes, unsigned int size) 1210 { 1211 struct soc_bytes_ext *bytes_ext = 1212 (struct soc_bytes_ext *)kctl->private_value; 1213 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); 1214 int ret = 0; 1215 1216 mutex_lock(&ctl->dsp->pwr_lock); 1217 1218 ret = wm_coeff_read_ctrl(ctl, ctl->cache, size); 1219 1220 if (!ret && copy_to_user(bytes, ctl->cache, size)) 1221 ret = -EFAULT; 1222 1223 mutex_unlock(&ctl->dsp->pwr_lock); 1224 1225 return ret; 1226 } 1227 1228 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, 1229 struct snd_ctl_elem_value *ucontrol) 1230 { 1231 /* 1232 * Although it's not useful to read an acked control, we must satisfy 1233 * user-side assumptions that all controls are readable and that a 1234 * write of the same value should be filtered out (it's valid to send 1235 * the same event number again to the firmware). We therefore return 0, 1236 * meaning "no event" so valid event numbers will always be a change 1237 */ 1238 ucontrol->value.integer.value[0] = 0; 1239 1240 return 0; 1241 } 1242 1243 struct wmfw_ctl_work { 1244 struct wm_adsp *dsp; 1245 struct wm_coeff_ctl *ctl; 1246 struct work_struct work; 1247 }; 1248 1249 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len) 1250 { 1251 unsigned int out, rd, wr, vol; 1252 1253 if (len > ADSP_MAX_STD_CTRL_SIZE) { 1254 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ; 1255 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE; 1256 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; 1257 1258 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK; 1259 } else { 1260 rd = SNDRV_CTL_ELEM_ACCESS_READ; 1261 wr = SNDRV_CTL_ELEM_ACCESS_WRITE; 1262 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; 1263 1264 out = 0; 1265 } 1266 1267 if (in) { 1268 out |= rd; 1269 if (in & WMFW_CTL_FLAG_WRITEABLE) 1270 out |= wr; 1271 if (in & WMFW_CTL_FLAG_VOLATILE) 1272 out |= vol; 1273 } else { 1274 out |= rd | wr | vol; 1275 } 1276 1277 return out; 1278 } 1279 1280 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) 1281 { 1282 struct snd_kcontrol_new *kcontrol; 1283 int ret; 1284 1285 if (!ctl || !ctl->name) 1286 return -EINVAL; 1287 1288 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); 1289 if (!kcontrol) 1290 return -ENOMEM; 1291 1292 kcontrol->name = ctl->name; 1293 kcontrol->info = wm_coeff_info; 1294 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; 1295 kcontrol->tlv.c = snd_soc_bytes_tlv_callback; 1296 kcontrol->private_value = (unsigned long)&ctl->bytes_ext; 1297 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); 1298 1299 switch (ctl->type) { 1300 case WMFW_CTL_TYPE_ACKED: 1301 kcontrol->get = wm_coeff_get_acked; 1302 kcontrol->put = wm_coeff_put_acked; 1303 break; 1304 default: 1305 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { 1306 ctl->bytes_ext.max = ctl->len; 1307 ctl->bytes_ext.get = wm_coeff_tlv_get; 1308 ctl->bytes_ext.put = wm_coeff_tlv_put; 1309 } else { 1310 kcontrol->get = wm_coeff_get; 1311 kcontrol->put = wm_coeff_put; 1312 } 1313 break; 1314 } 1315 1316 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1); 1317 if (ret < 0) 1318 goto err_kcontrol; 1319 1320 kfree(kcontrol); 1321 1322 return 0; 1323 1324 err_kcontrol: 1325 kfree(kcontrol); 1326 return ret; 1327 } 1328 1329 static int wm_coeff_init_control_caches(struct wm_adsp *dsp) 1330 { 1331 struct wm_coeff_ctl *ctl; 1332 int ret; 1333 1334 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1335 if (!ctl->enabled || ctl->set) 1336 continue; 1337 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) 1338 continue; 1339 1340 /* 1341 * For readable controls populate the cache from the DSP memory. 1342 * For non-readable controls the cache was zero-filled when 1343 * created so we don't need to do anything. 1344 */ 1345 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { 1346 ret = wm_coeff_read_ctrl_raw(ctl, ctl->cache, ctl->len); 1347 if (ret < 0) 1348 return ret; 1349 } 1350 } 1351 1352 return 0; 1353 } 1354 1355 static int wm_coeff_sync_controls(struct wm_adsp *dsp) 1356 { 1357 struct wm_coeff_ctl *ctl; 1358 int ret; 1359 1360 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1361 if (!ctl->enabled) 1362 continue; 1363 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { 1364 ret = wm_coeff_write_ctrl_raw(ctl, ctl->cache, 1365 ctl->len); 1366 if (ret < 0) 1367 return ret; 1368 } 1369 } 1370 1371 return 0; 1372 } 1373 1374 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, 1375 unsigned int event) 1376 { 1377 struct wm_coeff_ctl *ctl; 1378 int ret; 1379 1380 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1381 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) 1382 continue; 1383 1384 if (!ctl->enabled) 1385 continue; 1386 1387 ret = wm_coeff_write_acked_control(ctl, event); 1388 if (ret) 1389 adsp_warn(dsp, 1390 "Failed to send 0x%x event to alg 0x%x (%d)\n", 1391 event, ctl->alg_region.alg, ret); 1392 } 1393 } 1394 1395 static void wm_adsp_ctl_work(struct work_struct *work) 1396 { 1397 struct wmfw_ctl_work *ctl_work = container_of(work, 1398 struct wmfw_ctl_work, 1399 work); 1400 1401 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); 1402 kfree(ctl_work); 1403 } 1404 1405 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) 1406 { 1407 kfree(ctl->cache); 1408 kfree(ctl->name); 1409 kfree(ctl->subname); 1410 kfree(ctl); 1411 } 1412 1413 static int wm_adsp_create_control(struct wm_adsp *dsp, 1414 const struct wm_adsp_alg_region *alg_region, 1415 unsigned int offset, unsigned int len, 1416 const char *subname, unsigned int subname_len, 1417 unsigned int flags, snd_ctl_elem_type_t type) 1418 { 1419 struct wm_coeff_ctl *ctl; 1420 struct wmfw_ctl_work *ctl_work; 1421 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 1422 const char *region_name; 1423 int ret; 1424 1425 region_name = wm_adsp_mem_region_name(alg_region->type); 1426 if (!region_name) { 1427 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); 1428 return -EINVAL; 1429 } 1430 1431 switch (dsp->fw_ver) { 1432 case 0: 1433 case 1: 1434 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x", 1435 dsp->name, region_name, alg_region->alg); 1436 subname = NULL; /* don't append subname */ 1437 break; 1438 case 2: 1439 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, 1440 "%s%c %.12s %x", dsp->name, *region_name, 1441 wm_adsp_fw_text[dsp->fw], alg_region->alg); 1442 break; 1443 default: 1444 ret = scnprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, 1445 "%s %.12s %x", dsp->name, 1446 wm_adsp_fw_text[dsp->fw], alg_region->alg); 1447 break; 1448 } 1449 1450 if (subname) { 1451 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2; 1452 int skip = 0; 1453 1454 if (dsp->component->name_prefix) 1455 avail -= strlen(dsp->component->name_prefix) + 1; 1456 1457 /* Truncate the subname from the start if it is too long */ 1458 if (subname_len > avail) 1459 skip = subname_len - avail; 1460 1461 snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, 1462 " %.*s", subname_len - skip, subname + skip); 1463 } 1464 1465 list_for_each_entry(ctl, &dsp->ctl_list, list) { 1466 if (!strcmp(ctl->name, name)) { 1467 if (!ctl->enabled) 1468 ctl->enabled = 1; 1469 return 0; 1470 } 1471 } 1472 1473 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); 1474 if (!ctl) 1475 return -ENOMEM; 1476 ctl->fw_name = wm_adsp_fw_text[dsp->fw]; 1477 ctl->alg_region = *alg_region; 1478 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); 1479 if (!ctl->name) { 1480 ret = -ENOMEM; 1481 goto err_ctl; 1482 } 1483 if (subname) { 1484 ctl->subname_len = subname_len; 1485 ctl->subname = kmemdup(subname, 1486 strlen(subname) + 1, GFP_KERNEL); 1487 if (!ctl->subname) { 1488 ret = -ENOMEM; 1489 goto err_ctl_name; 1490 } 1491 } 1492 ctl->enabled = 1; 1493 ctl->set = 0; 1494 ctl->dsp = dsp; 1495 1496 ctl->flags = flags; 1497 ctl->type = type; 1498 ctl->offset = offset; 1499 ctl->len = len; 1500 ctl->cache = kzalloc(ctl->len, GFP_KERNEL); 1501 if (!ctl->cache) { 1502 ret = -ENOMEM; 1503 goto err_ctl_subname; 1504 } 1505 1506 list_add(&ctl->list, &dsp->ctl_list); 1507 1508 if (flags & WMFW_CTL_FLAG_SYS) 1509 return 0; 1510 1511 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); 1512 if (!ctl_work) { 1513 ret = -ENOMEM; 1514 goto err_list_del; 1515 } 1516 1517 ctl_work->dsp = dsp; 1518 ctl_work->ctl = ctl; 1519 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); 1520 schedule_work(&ctl_work->work); 1521 1522 return 0; 1523 1524 err_list_del: 1525 list_del(&ctl->list); 1526 kfree(ctl->cache); 1527 err_ctl_subname: 1528 kfree(ctl->subname); 1529 err_ctl_name: 1530 kfree(ctl->name); 1531 err_ctl: 1532 kfree(ctl); 1533 1534 return ret; 1535 } 1536 1537 struct wm_coeff_parsed_alg { 1538 int id; 1539 const u8 *name; 1540 int name_len; 1541 int ncoeff; 1542 }; 1543 1544 struct wm_coeff_parsed_coeff { 1545 int offset; 1546 int mem_type; 1547 const u8 *name; 1548 int name_len; 1549 snd_ctl_elem_type_t ctl_type; 1550 int flags; 1551 int len; 1552 }; 1553 1554 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) 1555 { 1556 int length; 1557 1558 switch (bytes) { 1559 case 1: 1560 length = **pos; 1561 break; 1562 case 2: 1563 length = le16_to_cpu(*((__le16 *)*pos)); 1564 break; 1565 default: 1566 return 0; 1567 } 1568 1569 if (str) 1570 *str = *pos + bytes; 1571 1572 *pos += ((length + bytes) + 3) & ~0x03; 1573 1574 return length; 1575 } 1576 1577 static int wm_coeff_parse_int(int bytes, const u8 **pos) 1578 { 1579 int val = 0; 1580 1581 switch (bytes) { 1582 case 2: 1583 val = le16_to_cpu(*((__le16 *)*pos)); 1584 break; 1585 case 4: 1586 val = le32_to_cpu(*((__le32 *)*pos)); 1587 break; 1588 default: 1589 break; 1590 } 1591 1592 *pos += bytes; 1593 1594 return val; 1595 } 1596 1597 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, 1598 struct wm_coeff_parsed_alg *blk) 1599 { 1600 const struct wmfw_adsp_alg_data *raw; 1601 1602 switch (dsp->fw_ver) { 1603 case 0: 1604 case 1: 1605 raw = (const struct wmfw_adsp_alg_data *)*data; 1606 *data = raw->data; 1607 1608 blk->id = le32_to_cpu(raw->id); 1609 blk->name = raw->name; 1610 blk->name_len = strlen(raw->name); 1611 blk->ncoeff = le32_to_cpu(raw->ncoeff); 1612 break; 1613 default: 1614 blk->id = wm_coeff_parse_int(sizeof(raw->id), data); 1615 blk->name_len = wm_coeff_parse_string(sizeof(u8), data, 1616 &blk->name); 1617 wm_coeff_parse_string(sizeof(u16), data, NULL); 1618 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); 1619 break; 1620 } 1621 1622 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); 1623 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); 1624 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); 1625 } 1626 1627 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, 1628 struct wm_coeff_parsed_coeff *blk) 1629 { 1630 const struct wmfw_adsp_coeff_data *raw; 1631 const u8 *tmp; 1632 int length; 1633 1634 switch (dsp->fw_ver) { 1635 case 0: 1636 case 1: 1637 raw = (const struct wmfw_adsp_coeff_data *)*data; 1638 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); 1639 1640 blk->offset = le16_to_cpu(raw->hdr.offset); 1641 blk->mem_type = le16_to_cpu(raw->hdr.type); 1642 blk->name = raw->name; 1643 blk->name_len = strlen(raw->name); 1644 blk->ctl_type = (__force snd_ctl_elem_type_t)le16_to_cpu(raw->ctl_type); 1645 blk->flags = le16_to_cpu(raw->flags); 1646 blk->len = le32_to_cpu(raw->len); 1647 break; 1648 default: 1649 tmp = *data; 1650 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); 1651 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); 1652 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); 1653 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp, 1654 &blk->name); 1655 wm_coeff_parse_string(sizeof(u8), &tmp, NULL); 1656 wm_coeff_parse_string(sizeof(u16), &tmp, NULL); 1657 blk->ctl_type = 1658 (__force snd_ctl_elem_type_t)wm_coeff_parse_int(sizeof(raw->ctl_type), 1659 &tmp); 1660 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); 1661 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); 1662 1663 *data = *data + sizeof(raw->hdr) + length; 1664 break; 1665 } 1666 1667 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); 1668 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); 1669 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); 1670 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); 1671 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); 1672 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); 1673 } 1674 1675 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp, 1676 const struct wm_coeff_parsed_coeff *coeff_blk, 1677 unsigned int f_required, 1678 unsigned int f_illegal) 1679 { 1680 if ((coeff_blk->flags & f_illegal) || 1681 ((coeff_blk->flags & f_required) != f_required)) { 1682 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", 1683 coeff_blk->flags, coeff_blk->ctl_type); 1684 return -EINVAL; 1685 } 1686 1687 return 0; 1688 } 1689 1690 static int wm_adsp_parse_coeff(struct wm_adsp *dsp, 1691 const struct wmfw_region *region) 1692 { 1693 struct wm_adsp_alg_region alg_region = {}; 1694 struct wm_coeff_parsed_alg alg_blk; 1695 struct wm_coeff_parsed_coeff coeff_blk; 1696 const u8 *data = region->data; 1697 int i, ret; 1698 1699 wm_coeff_parse_alg(dsp, &data, &alg_blk); 1700 for (i = 0; i < alg_blk.ncoeff; i++) { 1701 wm_coeff_parse_coeff(dsp, &data, &coeff_blk); 1702 1703 switch (coeff_blk.ctl_type) { 1704 case SNDRV_CTL_ELEM_TYPE_BYTES: 1705 break; 1706 case WMFW_CTL_TYPE_ACKED: 1707 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) 1708 continue; /* ignore */ 1709 1710 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, 1711 WMFW_CTL_FLAG_VOLATILE | 1712 WMFW_CTL_FLAG_WRITEABLE | 1713 WMFW_CTL_FLAG_READABLE, 1714 0); 1715 if (ret) 1716 return -EINVAL; 1717 break; 1718 case WMFW_CTL_TYPE_HOSTEVENT: 1719 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, 1720 WMFW_CTL_FLAG_SYS | 1721 WMFW_CTL_FLAG_VOLATILE | 1722 WMFW_CTL_FLAG_WRITEABLE | 1723 WMFW_CTL_FLAG_READABLE, 1724 0); 1725 if (ret) 1726 return -EINVAL; 1727 break; 1728 case WMFW_CTL_TYPE_HOST_BUFFER: 1729 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, 1730 WMFW_CTL_FLAG_SYS | 1731 WMFW_CTL_FLAG_VOLATILE | 1732 WMFW_CTL_FLAG_READABLE, 1733 0); 1734 if (ret) 1735 return -EINVAL; 1736 break; 1737 default: 1738 adsp_err(dsp, "Unknown control type: %d\n", 1739 coeff_blk.ctl_type); 1740 return -EINVAL; 1741 } 1742 1743 alg_region.type = coeff_blk.mem_type; 1744 alg_region.alg = alg_blk.id; 1745 1746 ret = wm_adsp_create_control(dsp, &alg_region, 1747 coeff_blk.offset, 1748 coeff_blk.len, 1749 coeff_blk.name, 1750 coeff_blk.name_len, 1751 coeff_blk.flags, 1752 coeff_blk.ctl_type); 1753 if (ret < 0) 1754 adsp_err(dsp, "Failed to create control: %.*s, %d\n", 1755 coeff_blk.name_len, coeff_blk.name, ret); 1756 } 1757 1758 return 0; 1759 } 1760 1761 static unsigned int wm_adsp1_parse_sizes(struct wm_adsp *dsp, 1762 const char * const file, 1763 unsigned int pos, 1764 const struct firmware *firmware) 1765 { 1766 const struct wmfw_adsp1_sizes *adsp1_sizes; 1767 1768 adsp1_sizes = (void *)&firmware->data[pos]; 1769 1770 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, 1771 le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), 1772 le32_to_cpu(adsp1_sizes->zm)); 1773 1774 return pos + sizeof(*adsp1_sizes); 1775 } 1776 1777 static unsigned int wm_adsp2_parse_sizes(struct wm_adsp *dsp, 1778 const char * const file, 1779 unsigned int pos, 1780 const struct firmware *firmware) 1781 { 1782 const struct wmfw_adsp2_sizes *adsp2_sizes; 1783 1784 adsp2_sizes = (void *)&firmware->data[pos]; 1785 1786 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, 1787 le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), 1788 le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); 1789 1790 return pos + sizeof(*adsp2_sizes); 1791 } 1792 1793 static bool wm_adsp_validate_version(struct wm_adsp *dsp, unsigned int version) 1794 { 1795 switch (version) { 1796 case 0: 1797 adsp_warn(dsp, "Deprecated file format %d\n", version); 1798 return true; 1799 case 1: 1800 case 2: 1801 return true; 1802 default: 1803 return false; 1804 } 1805 } 1806 1807 static bool wm_halo_validate_version(struct wm_adsp *dsp, unsigned int version) 1808 { 1809 switch (version) { 1810 case 3: 1811 return true; 1812 default: 1813 return false; 1814 } 1815 } 1816 1817 static int wm_adsp_load(struct wm_adsp *dsp) 1818 { 1819 LIST_HEAD(buf_list); 1820 const struct firmware *firmware; 1821 struct regmap *regmap = dsp->regmap; 1822 unsigned int pos = 0; 1823 const struct wmfw_header *header; 1824 const struct wmfw_adsp1_sizes *adsp1_sizes; 1825 const struct wmfw_footer *footer; 1826 const struct wmfw_region *region; 1827 const struct wm_adsp_region *mem; 1828 const char *region_name; 1829 char *file, *text = NULL; 1830 struct wm_adsp_buf *buf; 1831 unsigned int reg; 1832 int regions = 0; 1833 int ret, offset, type; 1834 1835 file = kzalloc(PAGE_SIZE, GFP_KERNEL); 1836 if (file == NULL) 1837 return -ENOMEM; 1838 1839 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name, 1840 wm_adsp_fw[dsp->fw].file); 1841 file[PAGE_SIZE - 1] = '\0'; 1842 1843 ret = request_firmware(&firmware, file, dsp->dev); 1844 if (ret != 0) { 1845 adsp_err(dsp, "Failed to request '%s'\n", file); 1846 goto out; 1847 } 1848 ret = -EINVAL; 1849 1850 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); 1851 if (pos >= firmware->size) { 1852 adsp_err(dsp, "%s: file too short, %zu bytes\n", 1853 file, firmware->size); 1854 goto out_fw; 1855 } 1856 1857 header = (void *)&firmware->data[0]; 1858 1859 if (memcmp(&header->magic[0], "WMFW", 4) != 0) { 1860 adsp_err(dsp, "%s: invalid magic\n", file); 1861 goto out_fw; 1862 } 1863 1864 if (!dsp->ops->validate_version(dsp, header->ver)) { 1865 adsp_err(dsp, "%s: unknown file format %d\n", 1866 file, header->ver); 1867 goto out_fw; 1868 } 1869 1870 adsp_info(dsp, "Firmware version: %d\n", header->ver); 1871 dsp->fw_ver = header->ver; 1872 1873 if (header->core != dsp->type) { 1874 adsp_err(dsp, "%s: invalid core %d != %d\n", 1875 file, header->core, dsp->type); 1876 goto out_fw; 1877 } 1878 1879 pos = sizeof(*header); 1880 pos = dsp->ops->parse_sizes(dsp, file, pos, firmware); 1881 1882 footer = (void *)&firmware->data[pos]; 1883 pos += sizeof(*footer); 1884 1885 if (le32_to_cpu(header->len) != pos) { 1886 adsp_err(dsp, "%s: unexpected header length %d\n", 1887 file, le32_to_cpu(header->len)); 1888 goto out_fw; 1889 } 1890 1891 adsp_dbg(dsp, "%s: timestamp %llu\n", file, 1892 le64_to_cpu(footer->timestamp)); 1893 1894 while (pos < firmware->size && 1895 sizeof(*region) < firmware->size - pos) { 1896 region = (void *)&(firmware->data[pos]); 1897 region_name = "Unknown"; 1898 reg = 0; 1899 text = NULL; 1900 offset = le32_to_cpu(region->offset) & 0xffffff; 1901 type = be32_to_cpu(region->type) & 0xff; 1902 1903 switch (type) { 1904 case WMFW_NAME_TEXT: 1905 region_name = "Firmware name"; 1906 text = kzalloc(le32_to_cpu(region->len) + 1, 1907 GFP_KERNEL); 1908 break; 1909 case WMFW_ALGORITHM_DATA: 1910 region_name = "Algorithm"; 1911 ret = wm_adsp_parse_coeff(dsp, region); 1912 if (ret != 0) 1913 goto out_fw; 1914 break; 1915 case WMFW_INFO_TEXT: 1916 region_name = "Information"; 1917 text = kzalloc(le32_to_cpu(region->len) + 1, 1918 GFP_KERNEL); 1919 break; 1920 case WMFW_ABSOLUTE: 1921 region_name = "Absolute"; 1922 reg = offset; 1923 break; 1924 case WMFW_ADSP1_PM: 1925 case WMFW_ADSP1_DM: 1926 case WMFW_ADSP2_XM: 1927 case WMFW_ADSP2_YM: 1928 case WMFW_ADSP1_ZM: 1929 case WMFW_HALO_PM_PACKED: 1930 case WMFW_HALO_XM_PACKED: 1931 case WMFW_HALO_YM_PACKED: 1932 mem = wm_adsp_find_region(dsp, type); 1933 if (!mem) { 1934 adsp_err(dsp, "No region of type: %x\n", type); 1935 ret = -EINVAL; 1936 goto out_fw; 1937 } 1938 1939 region_name = wm_adsp_mem_region_name(type); 1940 reg = dsp->ops->region_to_reg(mem, offset); 1941 break; 1942 default: 1943 adsp_warn(dsp, 1944 "%s.%d: Unknown region type %x at %d(%x)\n", 1945 file, regions, type, pos, pos); 1946 break; 1947 } 1948 1949 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, 1950 regions, le32_to_cpu(region->len), offset, 1951 region_name); 1952 1953 if (le32_to_cpu(region->len) > 1954 firmware->size - pos - sizeof(*region)) { 1955 adsp_err(dsp, 1956 "%s.%d: %s region len %d bytes exceeds file length %zu\n", 1957 file, regions, region_name, 1958 le32_to_cpu(region->len), firmware->size); 1959 ret = -EINVAL; 1960 goto out_fw; 1961 } 1962 1963 if (text) { 1964 memcpy(text, region->data, le32_to_cpu(region->len)); 1965 adsp_info(dsp, "%s: %s\n", file, text); 1966 kfree(text); 1967 text = NULL; 1968 } 1969 1970 if (reg) { 1971 buf = wm_adsp_buf_alloc(region->data, 1972 le32_to_cpu(region->len), 1973 &buf_list); 1974 if (!buf) { 1975 adsp_err(dsp, "Out of memory\n"); 1976 ret = -ENOMEM; 1977 goto out_fw; 1978 } 1979 1980 ret = regmap_raw_write_async(regmap, reg, buf->buf, 1981 le32_to_cpu(region->len)); 1982 if (ret != 0) { 1983 adsp_err(dsp, 1984 "%s.%d: Failed to write %d bytes at %d in %s: %d\n", 1985 file, regions, 1986 le32_to_cpu(region->len), offset, 1987 region_name, ret); 1988 goto out_fw; 1989 } 1990 } 1991 1992 pos += le32_to_cpu(region->len) + sizeof(*region); 1993 regions++; 1994 } 1995 1996 ret = regmap_async_complete(regmap); 1997 if (ret != 0) { 1998 adsp_err(dsp, "Failed to complete async write: %d\n", ret); 1999 goto out_fw; 2000 } 2001 2002 if (pos > firmware->size) 2003 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 2004 file, regions, pos - firmware->size); 2005 2006 wm_adsp_debugfs_save_wmfwname(dsp, file); 2007 2008 out_fw: 2009 regmap_async_complete(regmap); 2010 wm_adsp_buf_free(&buf_list); 2011 release_firmware(firmware); 2012 kfree(text); 2013 out: 2014 kfree(file); 2015 2016 return ret; 2017 } 2018 2019 /* 2020 * Find wm_coeff_ctl with input name as its subname 2021 * If not found, return NULL 2022 */ 2023 static struct wm_coeff_ctl *wm_adsp_get_ctl(struct wm_adsp *dsp, 2024 const char *name, int type, 2025 unsigned int alg) 2026 { 2027 struct wm_coeff_ctl *pos, *rslt = NULL; 2028 const char *fw_txt = wm_adsp_fw_text[dsp->fw]; 2029 2030 list_for_each_entry(pos, &dsp->ctl_list, list) { 2031 if (!pos->subname) 2032 continue; 2033 if (strncmp(pos->subname, name, pos->subname_len) == 0 && 2034 pos->fw_name == fw_txt && 2035 pos->alg_region.alg == alg && 2036 pos->alg_region.type == type) { 2037 rslt = pos; 2038 break; 2039 } 2040 } 2041 2042 return rslt; 2043 } 2044 2045 int wm_adsp_write_ctl(struct wm_adsp *dsp, const char *name, int type, 2046 unsigned int alg, void *buf, size_t len) 2047 { 2048 struct wm_coeff_ctl *ctl; 2049 struct snd_kcontrol *kcontrol; 2050 char ctl_name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 2051 int ret; 2052 2053 ctl = wm_adsp_get_ctl(dsp, name, type, alg); 2054 if (!ctl) 2055 return -EINVAL; 2056 2057 if (len > ctl->len) 2058 return -EINVAL; 2059 2060 ret = wm_coeff_write_ctrl(ctl, buf, len); 2061 if (ret) 2062 return ret; 2063 2064 if (ctl->flags & WMFW_CTL_FLAG_SYS) 2065 return 0; 2066 2067 if (dsp->component->name_prefix) 2068 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s", 2069 dsp->component->name_prefix, ctl->name); 2070 else 2071 snprintf(ctl_name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s", 2072 ctl->name); 2073 2074 kcontrol = snd_soc_card_get_kcontrol(dsp->component->card, ctl_name); 2075 if (!kcontrol) { 2076 adsp_err(dsp, "Can't find kcontrol %s\n", ctl_name); 2077 return -EINVAL; 2078 } 2079 2080 snd_ctl_notify(dsp->component->card->snd_card, 2081 SNDRV_CTL_EVENT_MASK_VALUE, &kcontrol->id); 2082 2083 return 0; 2084 } 2085 EXPORT_SYMBOL_GPL(wm_adsp_write_ctl); 2086 2087 int wm_adsp_read_ctl(struct wm_adsp *dsp, const char *name, int type, 2088 unsigned int alg, void *buf, size_t len) 2089 { 2090 struct wm_coeff_ctl *ctl; 2091 2092 ctl = wm_adsp_get_ctl(dsp, name, type, alg); 2093 if (!ctl) 2094 return -EINVAL; 2095 2096 if (len > ctl->len) 2097 return -EINVAL; 2098 2099 return wm_coeff_read_ctrl(ctl, buf, len); 2100 } 2101 EXPORT_SYMBOL_GPL(wm_adsp_read_ctl); 2102 2103 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, 2104 const struct wm_adsp_alg_region *alg_region) 2105 { 2106 struct wm_coeff_ctl *ctl; 2107 2108 list_for_each_entry(ctl, &dsp->ctl_list, list) { 2109 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && 2110 alg_region->alg == ctl->alg_region.alg && 2111 alg_region->type == ctl->alg_region.type) { 2112 ctl->alg_region.base = alg_region->base; 2113 } 2114 } 2115 } 2116 2117 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, 2118 const struct wm_adsp_region *mem, 2119 unsigned int pos, unsigned int len) 2120 { 2121 void *alg; 2122 unsigned int reg; 2123 int ret; 2124 __be32 val; 2125 2126 if (n_algs == 0) { 2127 adsp_err(dsp, "No algorithms\n"); 2128 return ERR_PTR(-EINVAL); 2129 } 2130 2131 if (n_algs > 1024) { 2132 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); 2133 return ERR_PTR(-EINVAL); 2134 } 2135 2136 /* Read the terminator first to validate the length */ 2137 reg = dsp->ops->region_to_reg(mem, pos + len); 2138 2139 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); 2140 if (ret != 0) { 2141 adsp_err(dsp, "Failed to read algorithm list end: %d\n", 2142 ret); 2143 return ERR_PTR(ret); 2144 } 2145 2146 if (be32_to_cpu(val) != 0xbedead) 2147 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", 2148 reg, be32_to_cpu(val)); 2149 2150 /* Convert length from DSP words to bytes */ 2151 len *= sizeof(u32); 2152 2153 alg = kzalloc(len, GFP_KERNEL | GFP_DMA); 2154 if (!alg) 2155 return ERR_PTR(-ENOMEM); 2156 2157 reg = dsp->ops->region_to_reg(mem, pos); 2158 2159 ret = regmap_raw_read(dsp->regmap, reg, alg, len); 2160 if (ret != 0) { 2161 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); 2162 kfree(alg); 2163 return ERR_PTR(ret); 2164 } 2165 2166 return alg; 2167 } 2168 2169 static struct wm_adsp_alg_region * 2170 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) 2171 { 2172 struct wm_adsp_alg_region *alg_region; 2173 2174 list_for_each_entry(alg_region, &dsp->alg_regions, list) { 2175 if (id == alg_region->alg && type == alg_region->type) 2176 return alg_region; 2177 } 2178 2179 return NULL; 2180 } 2181 2182 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp, 2183 int type, __be32 id, 2184 __be32 base) 2185 { 2186 struct wm_adsp_alg_region *alg_region; 2187 2188 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); 2189 if (!alg_region) 2190 return ERR_PTR(-ENOMEM); 2191 2192 alg_region->type = type; 2193 alg_region->alg = be32_to_cpu(id); 2194 alg_region->base = be32_to_cpu(base); 2195 2196 list_add_tail(&alg_region->list, &dsp->alg_regions); 2197 2198 if (dsp->fw_ver > 0) 2199 wm_adsp_ctl_fixup_base(dsp, alg_region); 2200 2201 return alg_region; 2202 } 2203 2204 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) 2205 { 2206 struct wm_adsp_alg_region *alg_region; 2207 2208 while (!list_empty(&dsp->alg_regions)) { 2209 alg_region = list_first_entry(&dsp->alg_regions, 2210 struct wm_adsp_alg_region, 2211 list); 2212 list_del(&alg_region->list); 2213 kfree(alg_region); 2214 } 2215 } 2216 2217 static void wmfw_parse_id_header(struct wm_adsp *dsp, 2218 struct wmfw_id_hdr *fw, int nalgs) 2219 { 2220 dsp->fw_id = be32_to_cpu(fw->id); 2221 dsp->fw_id_version = be32_to_cpu(fw->ver); 2222 2223 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %d algorithms\n", 2224 dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, 2225 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 2226 nalgs); 2227 } 2228 2229 static void wmfw_v3_parse_id_header(struct wm_adsp *dsp, 2230 struct wmfw_v3_id_hdr *fw, int nalgs) 2231 { 2232 dsp->fw_id = be32_to_cpu(fw->id); 2233 dsp->fw_id_version = be32_to_cpu(fw->ver); 2234 dsp->fw_vendor_id = be32_to_cpu(fw->vendor_id); 2235 2236 adsp_info(dsp, "Firmware: %x vendor: 0x%x v%d.%d.%d, %d algorithms\n", 2237 dsp->fw_id, dsp->fw_vendor_id, 2238 (dsp->fw_id_version & 0xff0000) >> 16, 2239 (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, 2240 nalgs); 2241 } 2242 2243 static int wm_adsp_create_regions(struct wm_adsp *dsp, __be32 id, int nregions, 2244 const int *type, __be32 *base) 2245 { 2246 struct wm_adsp_alg_region *alg_region; 2247 int i; 2248 2249 for (i = 0; i < nregions; i++) { 2250 alg_region = wm_adsp_create_region(dsp, type[i], id, base[i]); 2251 if (IS_ERR(alg_region)) 2252 return PTR_ERR(alg_region); 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int wm_adsp1_setup_algs(struct wm_adsp *dsp) 2259 { 2260 struct wmfw_adsp1_id_hdr adsp1_id; 2261 struct wmfw_adsp1_alg_hdr *adsp1_alg; 2262 struct wm_adsp_alg_region *alg_region; 2263 const struct wm_adsp_region *mem; 2264 unsigned int pos, len; 2265 size_t n_algs; 2266 int i, ret; 2267 2268 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); 2269 if (WARN_ON(!mem)) 2270 return -EINVAL; 2271 2272 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, 2273 sizeof(adsp1_id)); 2274 if (ret != 0) { 2275 adsp_err(dsp, "Failed to read algorithm info: %d\n", 2276 ret); 2277 return ret; 2278 } 2279 2280 n_algs = be32_to_cpu(adsp1_id.n_algs); 2281 2282 wmfw_parse_id_header(dsp, &adsp1_id.fw, n_algs); 2283 2284 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, 2285 adsp1_id.fw.id, adsp1_id.zm); 2286 if (IS_ERR(alg_region)) 2287 return PTR_ERR(alg_region); 2288 2289 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, 2290 adsp1_id.fw.id, adsp1_id.dm); 2291 if (IS_ERR(alg_region)) 2292 return PTR_ERR(alg_region); 2293 2294 /* Calculate offset and length in DSP words */ 2295 pos = sizeof(adsp1_id) / sizeof(u32); 2296 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); 2297 2298 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); 2299 if (IS_ERR(adsp1_alg)) 2300 return PTR_ERR(adsp1_alg); 2301 2302 for (i = 0; i < n_algs; i++) { 2303 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", 2304 i, be32_to_cpu(adsp1_alg[i].alg.id), 2305 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, 2306 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, 2307 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, 2308 be32_to_cpu(adsp1_alg[i].dm), 2309 be32_to_cpu(adsp1_alg[i].zm)); 2310 2311 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, 2312 adsp1_alg[i].alg.id, 2313 adsp1_alg[i].dm); 2314 if (IS_ERR(alg_region)) { 2315 ret = PTR_ERR(alg_region); 2316 goto out; 2317 } 2318 if (dsp->fw_ver == 0) { 2319 if (i + 1 < n_algs) { 2320 len = be32_to_cpu(adsp1_alg[i + 1].dm); 2321 len -= be32_to_cpu(adsp1_alg[i].dm); 2322 len *= 4; 2323 wm_adsp_create_control(dsp, alg_region, 0, 2324 len, NULL, 0, 0, 2325 SNDRV_CTL_ELEM_TYPE_BYTES); 2326 } else { 2327 adsp_warn(dsp, "Missing length info for region DM with ID %x\n", 2328 be32_to_cpu(adsp1_alg[i].alg.id)); 2329 } 2330 } 2331 2332 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, 2333 adsp1_alg[i].alg.id, 2334 adsp1_alg[i].zm); 2335 if (IS_ERR(alg_region)) { 2336 ret = PTR_ERR(alg_region); 2337 goto out; 2338 } 2339 if (dsp->fw_ver == 0) { 2340 if (i + 1 < n_algs) { 2341 len = be32_to_cpu(adsp1_alg[i + 1].zm); 2342 len -= be32_to_cpu(adsp1_alg[i].zm); 2343 len *= 4; 2344 wm_adsp_create_control(dsp, alg_region, 0, 2345 len, NULL, 0, 0, 2346 SNDRV_CTL_ELEM_TYPE_BYTES); 2347 } else { 2348 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 2349 be32_to_cpu(adsp1_alg[i].alg.id)); 2350 } 2351 } 2352 } 2353 2354 out: 2355 kfree(adsp1_alg); 2356 return ret; 2357 } 2358 2359 static int wm_adsp2_setup_algs(struct wm_adsp *dsp) 2360 { 2361 struct wmfw_adsp2_id_hdr adsp2_id; 2362 struct wmfw_adsp2_alg_hdr *adsp2_alg; 2363 struct wm_adsp_alg_region *alg_region; 2364 const struct wm_adsp_region *mem; 2365 unsigned int pos, len; 2366 size_t n_algs; 2367 int i, ret; 2368 2369 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); 2370 if (WARN_ON(!mem)) 2371 return -EINVAL; 2372 2373 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, 2374 sizeof(adsp2_id)); 2375 if (ret != 0) { 2376 adsp_err(dsp, "Failed to read algorithm info: %d\n", 2377 ret); 2378 return ret; 2379 } 2380 2381 n_algs = be32_to_cpu(adsp2_id.n_algs); 2382 2383 wmfw_parse_id_header(dsp, &adsp2_id.fw, n_algs); 2384 2385 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, 2386 adsp2_id.fw.id, adsp2_id.xm); 2387 if (IS_ERR(alg_region)) 2388 return PTR_ERR(alg_region); 2389 2390 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, 2391 adsp2_id.fw.id, adsp2_id.ym); 2392 if (IS_ERR(alg_region)) 2393 return PTR_ERR(alg_region); 2394 2395 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, 2396 adsp2_id.fw.id, adsp2_id.zm); 2397 if (IS_ERR(alg_region)) 2398 return PTR_ERR(alg_region); 2399 2400 /* Calculate offset and length in DSP words */ 2401 pos = sizeof(adsp2_id) / sizeof(u32); 2402 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); 2403 2404 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); 2405 if (IS_ERR(adsp2_alg)) 2406 return PTR_ERR(adsp2_alg); 2407 2408 for (i = 0; i < n_algs; i++) { 2409 adsp_info(dsp, 2410 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", 2411 i, be32_to_cpu(adsp2_alg[i].alg.id), 2412 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, 2413 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, 2414 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, 2415 be32_to_cpu(adsp2_alg[i].xm), 2416 be32_to_cpu(adsp2_alg[i].ym), 2417 be32_to_cpu(adsp2_alg[i].zm)); 2418 2419 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, 2420 adsp2_alg[i].alg.id, 2421 adsp2_alg[i].xm); 2422 if (IS_ERR(alg_region)) { 2423 ret = PTR_ERR(alg_region); 2424 goto out; 2425 } 2426 if (dsp->fw_ver == 0) { 2427 if (i + 1 < n_algs) { 2428 len = be32_to_cpu(adsp2_alg[i + 1].xm); 2429 len -= be32_to_cpu(adsp2_alg[i].xm); 2430 len *= 4; 2431 wm_adsp_create_control(dsp, alg_region, 0, 2432 len, NULL, 0, 0, 2433 SNDRV_CTL_ELEM_TYPE_BYTES); 2434 } else { 2435 adsp_warn(dsp, "Missing length info for region XM with ID %x\n", 2436 be32_to_cpu(adsp2_alg[i].alg.id)); 2437 } 2438 } 2439 2440 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, 2441 adsp2_alg[i].alg.id, 2442 adsp2_alg[i].ym); 2443 if (IS_ERR(alg_region)) { 2444 ret = PTR_ERR(alg_region); 2445 goto out; 2446 } 2447 if (dsp->fw_ver == 0) { 2448 if (i + 1 < n_algs) { 2449 len = be32_to_cpu(adsp2_alg[i + 1].ym); 2450 len -= be32_to_cpu(adsp2_alg[i].ym); 2451 len *= 4; 2452 wm_adsp_create_control(dsp, alg_region, 0, 2453 len, NULL, 0, 0, 2454 SNDRV_CTL_ELEM_TYPE_BYTES); 2455 } else { 2456 adsp_warn(dsp, "Missing length info for region YM with ID %x\n", 2457 be32_to_cpu(adsp2_alg[i].alg.id)); 2458 } 2459 } 2460 2461 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, 2462 adsp2_alg[i].alg.id, 2463 adsp2_alg[i].zm); 2464 if (IS_ERR(alg_region)) { 2465 ret = PTR_ERR(alg_region); 2466 goto out; 2467 } 2468 if (dsp->fw_ver == 0) { 2469 if (i + 1 < n_algs) { 2470 len = be32_to_cpu(adsp2_alg[i + 1].zm); 2471 len -= be32_to_cpu(adsp2_alg[i].zm); 2472 len *= 4; 2473 wm_adsp_create_control(dsp, alg_region, 0, 2474 len, NULL, 0, 0, 2475 SNDRV_CTL_ELEM_TYPE_BYTES); 2476 } else { 2477 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", 2478 be32_to_cpu(adsp2_alg[i].alg.id)); 2479 } 2480 } 2481 } 2482 2483 out: 2484 kfree(adsp2_alg); 2485 return ret; 2486 } 2487 2488 static int wm_halo_create_regions(struct wm_adsp *dsp, __be32 id, 2489 __be32 xm_base, __be32 ym_base) 2490 { 2491 static const int types[] = { 2492 WMFW_ADSP2_XM, WMFW_HALO_XM_PACKED, 2493 WMFW_ADSP2_YM, WMFW_HALO_YM_PACKED 2494 }; 2495 __be32 bases[] = { xm_base, xm_base, ym_base, ym_base }; 2496 2497 return wm_adsp_create_regions(dsp, id, ARRAY_SIZE(types), types, bases); 2498 } 2499 2500 static int wm_halo_setup_algs(struct wm_adsp *dsp) 2501 { 2502 struct wmfw_halo_id_hdr halo_id; 2503 struct wmfw_halo_alg_hdr *halo_alg; 2504 const struct wm_adsp_region *mem; 2505 unsigned int pos, len; 2506 size_t n_algs; 2507 int i, ret; 2508 2509 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); 2510 if (WARN_ON(!mem)) 2511 return -EINVAL; 2512 2513 ret = regmap_raw_read(dsp->regmap, mem->base, &halo_id, 2514 sizeof(halo_id)); 2515 if (ret != 0) { 2516 adsp_err(dsp, "Failed to read algorithm info: %d\n", 2517 ret); 2518 return ret; 2519 } 2520 2521 n_algs = be32_to_cpu(halo_id.n_algs); 2522 2523 wmfw_v3_parse_id_header(dsp, &halo_id.fw, n_algs); 2524 2525 ret = wm_halo_create_regions(dsp, halo_id.fw.id, 2526 halo_id.xm_base, halo_id.ym_base); 2527 if (ret) 2528 return ret; 2529 2530 /* Calculate offset and length in DSP words */ 2531 pos = sizeof(halo_id) / sizeof(u32); 2532 len = (sizeof(*halo_alg) * n_algs) / sizeof(u32); 2533 2534 halo_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); 2535 if (IS_ERR(halo_alg)) 2536 return PTR_ERR(halo_alg); 2537 2538 for (i = 0; i < n_algs; i++) { 2539 adsp_info(dsp, 2540 "%d: ID %x v%d.%d.%d XM@%x YM@%x\n", 2541 i, be32_to_cpu(halo_alg[i].alg.id), 2542 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff0000) >> 16, 2543 (be32_to_cpu(halo_alg[i].alg.ver) & 0xff00) >> 8, 2544 be32_to_cpu(halo_alg[i].alg.ver) & 0xff, 2545 be32_to_cpu(halo_alg[i].xm_base), 2546 be32_to_cpu(halo_alg[i].ym_base)); 2547 2548 ret = wm_halo_create_regions(dsp, halo_alg[i].alg.id, 2549 halo_alg[i].xm_base, 2550 halo_alg[i].ym_base); 2551 if (ret) 2552 goto out; 2553 } 2554 2555 out: 2556 kfree(halo_alg); 2557 return ret; 2558 } 2559 2560 static int wm_adsp_load_coeff(struct wm_adsp *dsp) 2561 { 2562 LIST_HEAD(buf_list); 2563 struct regmap *regmap = dsp->regmap; 2564 struct wmfw_coeff_hdr *hdr; 2565 struct wmfw_coeff_item *blk; 2566 const struct firmware *firmware; 2567 const struct wm_adsp_region *mem; 2568 struct wm_adsp_alg_region *alg_region; 2569 const char *region_name; 2570 int ret, pos, blocks, type, offset, reg; 2571 char *file; 2572 struct wm_adsp_buf *buf; 2573 2574 file = kzalloc(PAGE_SIZE, GFP_KERNEL); 2575 if (file == NULL) 2576 return -ENOMEM; 2577 2578 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name, 2579 wm_adsp_fw[dsp->fw].file); 2580 file[PAGE_SIZE - 1] = '\0'; 2581 2582 ret = request_firmware(&firmware, file, dsp->dev); 2583 if (ret != 0) { 2584 adsp_warn(dsp, "Failed to request '%s'\n", file); 2585 ret = 0; 2586 goto out; 2587 } 2588 ret = -EINVAL; 2589 2590 if (sizeof(*hdr) >= firmware->size) { 2591 adsp_err(dsp, "%s: file too short, %zu bytes\n", 2592 file, firmware->size); 2593 goto out_fw; 2594 } 2595 2596 hdr = (void *)&firmware->data[0]; 2597 if (memcmp(hdr->magic, "WMDR", 4) != 0) { 2598 adsp_err(dsp, "%s: invalid magic\n", file); 2599 goto out_fw; 2600 } 2601 2602 switch (be32_to_cpu(hdr->rev) & 0xff) { 2603 case 1: 2604 break; 2605 default: 2606 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", 2607 file, be32_to_cpu(hdr->rev) & 0xff); 2608 ret = -EINVAL; 2609 goto out_fw; 2610 } 2611 2612 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, 2613 (le32_to_cpu(hdr->ver) >> 16) & 0xff, 2614 (le32_to_cpu(hdr->ver) >> 8) & 0xff, 2615 le32_to_cpu(hdr->ver) & 0xff); 2616 2617 pos = le32_to_cpu(hdr->len); 2618 2619 blocks = 0; 2620 while (pos < firmware->size && 2621 sizeof(*blk) < firmware->size - pos) { 2622 blk = (void *)(&firmware->data[pos]); 2623 2624 type = le16_to_cpu(blk->type); 2625 offset = le16_to_cpu(blk->offset); 2626 2627 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", 2628 file, blocks, le32_to_cpu(blk->id), 2629 (le32_to_cpu(blk->ver) >> 16) & 0xff, 2630 (le32_to_cpu(blk->ver) >> 8) & 0xff, 2631 le32_to_cpu(blk->ver) & 0xff); 2632 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", 2633 file, blocks, le32_to_cpu(blk->len), offset, type); 2634 2635 reg = 0; 2636 region_name = "Unknown"; 2637 switch (type) { 2638 case (WMFW_NAME_TEXT << 8): 2639 case (WMFW_INFO_TEXT << 8): 2640 case (WMFW_METADATA << 8): 2641 break; 2642 case (WMFW_ABSOLUTE << 8): 2643 /* 2644 * Old files may use this for global 2645 * coefficients. 2646 */ 2647 if (le32_to_cpu(blk->id) == dsp->fw_id && 2648 offset == 0) { 2649 region_name = "global coefficients"; 2650 mem = wm_adsp_find_region(dsp, type); 2651 if (!mem) { 2652 adsp_err(dsp, "No ZM\n"); 2653 break; 2654 } 2655 reg = dsp->ops->region_to_reg(mem, 0); 2656 2657 } else { 2658 region_name = "register"; 2659 reg = offset; 2660 } 2661 break; 2662 2663 case WMFW_ADSP1_DM: 2664 case WMFW_ADSP1_ZM: 2665 case WMFW_ADSP2_XM: 2666 case WMFW_ADSP2_YM: 2667 case WMFW_HALO_XM_PACKED: 2668 case WMFW_HALO_YM_PACKED: 2669 case WMFW_HALO_PM_PACKED: 2670 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", 2671 file, blocks, le32_to_cpu(blk->len), 2672 type, le32_to_cpu(blk->id)); 2673 2674 mem = wm_adsp_find_region(dsp, type); 2675 if (!mem) { 2676 adsp_err(dsp, "No base for region %x\n", type); 2677 break; 2678 } 2679 2680 alg_region = wm_adsp_find_alg_region(dsp, type, 2681 le32_to_cpu(blk->id)); 2682 if (alg_region) { 2683 reg = alg_region->base; 2684 reg = dsp->ops->region_to_reg(mem, reg); 2685 reg += offset; 2686 } else { 2687 adsp_err(dsp, "No %x for algorithm %x\n", 2688 type, le32_to_cpu(blk->id)); 2689 } 2690 break; 2691 2692 default: 2693 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", 2694 file, blocks, type, pos); 2695 break; 2696 } 2697 2698 if (reg) { 2699 if (le32_to_cpu(blk->len) > 2700 firmware->size - pos - sizeof(*blk)) { 2701 adsp_err(dsp, 2702 "%s.%d: %s region len %d bytes exceeds file length %zu\n", 2703 file, blocks, region_name, 2704 le32_to_cpu(blk->len), 2705 firmware->size); 2706 ret = -EINVAL; 2707 goto out_fw; 2708 } 2709 2710 buf = wm_adsp_buf_alloc(blk->data, 2711 le32_to_cpu(blk->len), 2712 &buf_list); 2713 if (!buf) { 2714 adsp_err(dsp, "Out of memory\n"); 2715 ret = -ENOMEM; 2716 goto out_fw; 2717 } 2718 2719 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", 2720 file, blocks, le32_to_cpu(blk->len), 2721 reg); 2722 ret = regmap_raw_write_async(regmap, reg, buf->buf, 2723 le32_to_cpu(blk->len)); 2724 if (ret != 0) { 2725 adsp_err(dsp, 2726 "%s.%d: Failed to write to %x in %s: %d\n", 2727 file, blocks, reg, region_name, ret); 2728 } 2729 } 2730 2731 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; 2732 blocks++; 2733 } 2734 2735 ret = regmap_async_complete(regmap); 2736 if (ret != 0) 2737 adsp_err(dsp, "Failed to complete async write: %d\n", ret); 2738 2739 if (pos > firmware->size) 2740 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", 2741 file, blocks, pos - firmware->size); 2742 2743 wm_adsp_debugfs_save_binname(dsp, file); 2744 2745 out_fw: 2746 regmap_async_complete(regmap); 2747 release_firmware(firmware); 2748 wm_adsp_buf_free(&buf_list); 2749 out: 2750 kfree(file); 2751 return ret; 2752 } 2753 2754 static int wm_adsp_create_name(struct wm_adsp *dsp) 2755 { 2756 char *p; 2757 2758 if (!dsp->name) { 2759 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", 2760 dsp->num); 2761 if (!dsp->name) 2762 return -ENOMEM; 2763 } 2764 2765 if (!dsp->fwf_name) { 2766 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL); 2767 if (!p) 2768 return -ENOMEM; 2769 2770 dsp->fwf_name = p; 2771 for (; *p != 0; ++p) 2772 *p = tolower(*p); 2773 } 2774 2775 return 0; 2776 } 2777 2778 static int wm_adsp_common_init(struct wm_adsp *dsp) 2779 { 2780 int ret; 2781 2782 ret = wm_adsp_create_name(dsp); 2783 if (ret) 2784 return ret; 2785 2786 INIT_LIST_HEAD(&dsp->alg_regions); 2787 INIT_LIST_HEAD(&dsp->ctl_list); 2788 INIT_LIST_HEAD(&dsp->compr_list); 2789 INIT_LIST_HEAD(&dsp->buffer_list); 2790 2791 mutex_init(&dsp->pwr_lock); 2792 2793 return 0; 2794 } 2795 2796 int wm_adsp1_init(struct wm_adsp *dsp) 2797 { 2798 dsp->ops = &wm_adsp1_ops; 2799 2800 return wm_adsp_common_init(dsp); 2801 } 2802 EXPORT_SYMBOL_GPL(wm_adsp1_init); 2803 2804 int wm_adsp1_event(struct snd_soc_dapm_widget *w, 2805 struct snd_kcontrol *kcontrol, 2806 int event) 2807 { 2808 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2809 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 2810 struct wm_adsp *dsp = &dsps[w->shift]; 2811 struct wm_coeff_ctl *ctl; 2812 int ret; 2813 unsigned int val; 2814 2815 dsp->component = component; 2816 2817 mutex_lock(&dsp->pwr_lock); 2818 2819 switch (event) { 2820 case SND_SOC_DAPM_POST_PMU: 2821 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2822 ADSP1_SYS_ENA, ADSP1_SYS_ENA); 2823 2824 /* 2825 * For simplicity set the DSP clock rate to be the 2826 * SYSCLK rate rather than making it configurable. 2827 */ 2828 if (dsp->sysclk_reg) { 2829 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); 2830 if (ret != 0) { 2831 adsp_err(dsp, "Failed to read SYSCLK state: %d\n", 2832 ret); 2833 goto err_mutex; 2834 } 2835 2836 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; 2837 2838 ret = regmap_update_bits(dsp->regmap, 2839 dsp->base + ADSP1_CONTROL_31, 2840 ADSP1_CLK_SEL_MASK, val); 2841 if (ret != 0) { 2842 adsp_err(dsp, "Failed to set clock rate: %d\n", 2843 ret); 2844 goto err_mutex; 2845 } 2846 } 2847 2848 ret = wm_adsp_load(dsp); 2849 if (ret != 0) 2850 goto err_ena; 2851 2852 ret = wm_adsp1_setup_algs(dsp); 2853 if (ret != 0) 2854 goto err_ena; 2855 2856 ret = wm_adsp_load_coeff(dsp); 2857 if (ret != 0) 2858 goto err_ena; 2859 2860 /* Initialize caches for enabled and unset controls */ 2861 ret = wm_coeff_init_control_caches(dsp); 2862 if (ret != 0) 2863 goto err_ena; 2864 2865 /* Sync set controls */ 2866 ret = wm_coeff_sync_controls(dsp); 2867 if (ret != 0) 2868 goto err_ena; 2869 2870 dsp->booted = true; 2871 2872 /* Start the core running */ 2873 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2874 ADSP1_CORE_ENA | ADSP1_START, 2875 ADSP1_CORE_ENA | ADSP1_START); 2876 2877 dsp->running = true; 2878 break; 2879 2880 case SND_SOC_DAPM_PRE_PMD: 2881 dsp->running = false; 2882 dsp->booted = false; 2883 2884 /* Halt the core */ 2885 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2886 ADSP1_CORE_ENA | ADSP1_START, 0); 2887 2888 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, 2889 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); 2890 2891 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2892 ADSP1_SYS_ENA, 0); 2893 2894 list_for_each_entry(ctl, &dsp->ctl_list, list) 2895 ctl->enabled = 0; 2896 2897 2898 wm_adsp_free_alg_regions(dsp); 2899 break; 2900 2901 default: 2902 break; 2903 } 2904 2905 mutex_unlock(&dsp->pwr_lock); 2906 2907 return 0; 2908 2909 err_ena: 2910 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, 2911 ADSP1_SYS_ENA, 0); 2912 err_mutex: 2913 mutex_unlock(&dsp->pwr_lock); 2914 2915 return ret; 2916 } 2917 EXPORT_SYMBOL_GPL(wm_adsp1_event); 2918 2919 static int wm_adsp2v2_enable_core(struct wm_adsp *dsp) 2920 { 2921 unsigned int val; 2922 int ret, count; 2923 2924 /* Wait for the RAM to start, should be near instantaneous */ 2925 for (count = 0; count < 10; ++count) { 2926 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); 2927 if (ret != 0) 2928 return ret; 2929 2930 if (val & ADSP2_RAM_RDY) 2931 break; 2932 2933 usleep_range(250, 500); 2934 } 2935 2936 if (!(val & ADSP2_RAM_RDY)) { 2937 adsp_err(dsp, "Failed to start DSP RAM\n"); 2938 return -EBUSY; 2939 } 2940 2941 adsp_dbg(dsp, "RAM ready after %d polls\n", count); 2942 2943 return 0; 2944 } 2945 2946 static int wm_adsp2_enable_core(struct wm_adsp *dsp) 2947 { 2948 int ret; 2949 2950 ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, 2951 ADSP2_SYS_ENA, ADSP2_SYS_ENA); 2952 if (ret != 0) 2953 return ret; 2954 2955 return wm_adsp2v2_enable_core(dsp); 2956 } 2957 2958 static int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) 2959 { 2960 struct regmap *regmap = dsp->regmap; 2961 unsigned int code0, code1, lock_reg; 2962 2963 if (!(lock_regions & WM_ADSP2_REGION_ALL)) 2964 return 0; 2965 2966 lock_regions &= WM_ADSP2_REGION_ALL; 2967 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; 2968 2969 while (lock_regions) { 2970 code0 = code1 = 0; 2971 if (lock_regions & BIT(0)) { 2972 code0 = ADSP2_LOCK_CODE_0; 2973 code1 = ADSP2_LOCK_CODE_1; 2974 } 2975 if (lock_regions & BIT(1)) { 2976 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; 2977 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; 2978 } 2979 regmap_write(regmap, lock_reg, code0); 2980 regmap_write(regmap, lock_reg, code1); 2981 lock_regions >>= 2; 2982 lock_reg += 2; 2983 } 2984 2985 return 0; 2986 } 2987 2988 static int wm_adsp2_enable_memory(struct wm_adsp *dsp) 2989 { 2990 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2991 ADSP2_MEM_ENA, ADSP2_MEM_ENA); 2992 } 2993 2994 static void wm_adsp2_disable_memory(struct wm_adsp *dsp) 2995 { 2996 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 2997 ADSP2_MEM_ENA, 0); 2998 } 2999 3000 static void wm_adsp2_disable_core(struct wm_adsp *dsp) 3001 { 3002 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 3003 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 3004 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); 3005 3006 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 3007 ADSP2_SYS_ENA, 0); 3008 } 3009 3010 static void wm_adsp2v2_disable_core(struct wm_adsp *dsp) 3011 { 3012 regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); 3013 regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); 3014 regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); 3015 } 3016 3017 static void wm_adsp_boot_work(struct work_struct *work) 3018 { 3019 struct wm_adsp *dsp = container_of(work, 3020 struct wm_adsp, 3021 boot_work); 3022 int ret; 3023 3024 mutex_lock(&dsp->pwr_lock); 3025 3026 if (dsp->ops->enable_memory) { 3027 ret = dsp->ops->enable_memory(dsp); 3028 if (ret != 0) 3029 goto err_mutex; 3030 } 3031 3032 if (dsp->ops->enable_core) { 3033 ret = dsp->ops->enable_core(dsp); 3034 if (ret != 0) 3035 goto err_mem; 3036 } 3037 3038 ret = wm_adsp_load(dsp); 3039 if (ret != 0) 3040 goto err_ena; 3041 3042 ret = dsp->ops->setup_algs(dsp); 3043 if (ret != 0) 3044 goto err_ena; 3045 3046 ret = wm_adsp_load_coeff(dsp); 3047 if (ret != 0) 3048 goto err_ena; 3049 3050 /* Initialize caches for enabled and unset controls */ 3051 ret = wm_coeff_init_control_caches(dsp); 3052 if (ret != 0) 3053 goto err_ena; 3054 3055 if (dsp->ops->disable_core) 3056 dsp->ops->disable_core(dsp); 3057 3058 dsp->booted = true; 3059 3060 mutex_unlock(&dsp->pwr_lock); 3061 3062 return; 3063 3064 err_ena: 3065 if (dsp->ops->disable_core) 3066 dsp->ops->disable_core(dsp); 3067 err_mem: 3068 if (dsp->ops->disable_memory) 3069 dsp->ops->disable_memory(dsp); 3070 err_mutex: 3071 mutex_unlock(&dsp->pwr_lock); 3072 } 3073 3074 static int wm_halo_configure_mpu(struct wm_adsp *dsp, unsigned int lock_regions) 3075 { 3076 struct reg_sequence config[] = { 3077 { dsp->base + HALO_MPU_LOCK_CONFIG, 0x5555 }, 3078 { dsp->base + HALO_MPU_LOCK_CONFIG, 0xAAAA }, 3079 { dsp->base + HALO_MPU_XMEM_ACCESS_0, 0xFFFFFFFF }, 3080 { dsp->base + HALO_MPU_YMEM_ACCESS_0, 0xFFFFFFFF }, 3081 { dsp->base + HALO_MPU_WINDOW_ACCESS_0, lock_regions }, 3082 { dsp->base + HALO_MPU_XREG_ACCESS_0, lock_regions }, 3083 { dsp->base + HALO_MPU_YREG_ACCESS_0, lock_regions }, 3084 { dsp->base + HALO_MPU_XMEM_ACCESS_1, 0xFFFFFFFF }, 3085 { dsp->base + HALO_MPU_YMEM_ACCESS_1, 0xFFFFFFFF }, 3086 { dsp->base + HALO_MPU_WINDOW_ACCESS_1, lock_regions }, 3087 { dsp->base + HALO_MPU_XREG_ACCESS_1, lock_regions }, 3088 { dsp->base + HALO_MPU_YREG_ACCESS_1, lock_regions }, 3089 { dsp->base + HALO_MPU_XMEM_ACCESS_2, 0xFFFFFFFF }, 3090 { dsp->base + HALO_MPU_YMEM_ACCESS_2, 0xFFFFFFFF }, 3091 { dsp->base + HALO_MPU_WINDOW_ACCESS_2, lock_regions }, 3092 { dsp->base + HALO_MPU_XREG_ACCESS_2, lock_regions }, 3093 { dsp->base + HALO_MPU_YREG_ACCESS_2, lock_regions }, 3094 { dsp->base + HALO_MPU_XMEM_ACCESS_3, 0xFFFFFFFF }, 3095 { dsp->base + HALO_MPU_YMEM_ACCESS_3, 0xFFFFFFFF }, 3096 { dsp->base + HALO_MPU_WINDOW_ACCESS_3, lock_regions }, 3097 { dsp->base + HALO_MPU_XREG_ACCESS_3, lock_regions }, 3098 { dsp->base + HALO_MPU_YREG_ACCESS_3, lock_regions }, 3099 { dsp->base + HALO_MPU_LOCK_CONFIG, 0 }, 3100 }; 3101 3102 return regmap_multi_reg_write(dsp->regmap, config, ARRAY_SIZE(config)); 3103 } 3104 3105 int wm_adsp2_set_dspclk(struct snd_soc_dapm_widget *w, unsigned int freq) 3106 { 3107 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 3108 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 3109 struct wm_adsp *dsp = &dsps[w->shift]; 3110 int ret; 3111 3112 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CLOCKING, 3113 ADSP2_CLK_SEL_MASK, 3114 freq << ADSP2_CLK_SEL_SHIFT); 3115 if (ret) 3116 adsp_err(dsp, "Failed to set clock rate: %d\n", ret); 3117 3118 return ret; 3119 } 3120 EXPORT_SYMBOL_GPL(wm_adsp2_set_dspclk); 3121 3122 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, 3123 struct snd_ctl_elem_value *ucontrol) 3124 { 3125 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3126 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 3127 struct soc_mixer_control *mc = 3128 (struct soc_mixer_control *)kcontrol->private_value; 3129 struct wm_adsp *dsp = &dsps[mc->shift - 1]; 3130 3131 ucontrol->value.integer.value[0] = dsp->preloaded; 3132 3133 return 0; 3134 } 3135 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); 3136 3137 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, 3138 struct snd_ctl_elem_value *ucontrol) 3139 { 3140 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 3141 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 3142 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3143 struct soc_mixer_control *mc = 3144 (struct soc_mixer_control *)kcontrol->private_value; 3145 struct wm_adsp *dsp = &dsps[mc->shift - 1]; 3146 char preload[32]; 3147 3148 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); 3149 3150 dsp->preloaded = ucontrol->value.integer.value[0]; 3151 3152 if (ucontrol->value.integer.value[0]) 3153 snd_soc_component_force_enable_pin(component, preload); 3154 else 3155 snd_soc_component_disable_pin(component, preload); 3156 3157 snd_soc_dapm_sync(dapm); 3158 3159 flush_work(&dsp->boot_work); 3160 3161 return 0; 3162 } 3163 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); 3164 3165 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) 3166 { 3167 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, 3168 ADSP2_WDT_ENA_MASK, 0); 3169 } 3170 3171 static void wm_halo_stop_watchdog(struct wm_adsp *dsp) 3172 { 3173 regmap_update_bits(dsp->regmap, dsp->base + HALO_WDT_CONTROL, 3174 HALO_WDT_EN_MASK, 0); 3175 } 3176 3177 int wm_adsp_early_event(struct snd_soc_dapm_widget *w, 3178 struct snd_kcontrol *kcontrol, int event) 3179 { 3180 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 3181 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 3182 struct wm_adsp *dsp = &dsps[w->shift]; 3183 struct wm_coeff_ctl *ctl; 3184 3185 switch (event) { 3186 case SND_SOC_DAPM_PRE_PMU: 3187 queue_work(system_unbound_wq, &dsp->boot_work); 3188 break; 3189 case SND_SOC_DAPM_PRE_PMD: 3190 mutex_lock(&dsp->pwr_lock); 3191 3192 wm_adsp_debugfs_clear(dsp); 3193 3194 dsp->fw_id = 0; 3195 dsp->fw_id_version = 0; 3196 3197 dsp->booted = false; 3198 3199 if (dsp->ops->disable_memory) 3200 dsp->ops->disable_memory(dsp); 3201 3202 list_for_each_entry(ctl, &dsp->ctl_list, list) 3203 ctl->enabled = 0; 3204 3205 wm_adsp_free_alg_regions(dsp); 3206 3207 mutex_unlock(&dsp->pwr_lock); 3208 3209 adsp_dbg(dsp, "Shutdown complete\n"); 3210 break; 3211 default: 3212 break; 3213 } 3214 3215 return 0; 3216 } 3217 EXPORT_SYMBOL_GPL(wm_adsp_early_event); 3218 3219 static int wm_adsp2_start_core(struct wm_adsp *dsp) 3220 { 3221 return regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 3222 ADSP2_CORE_ENA | ADSP2_START, 3223 ADSP2_CORE_ENA | ADSP2_START); 3224 } 3225 3226 static void wm_adsp2_stop_core(struct wm_adsp *dsp) 3227 { 3228 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 3229 ADSP2_CORE_ENA | ADSP2_START, 0); 3230 } 3231 3232 int wm_adsp_event(struct snd_soc_dapm_widget *w, 3233 struct snd_kcontrol *kcontrol, int event) 3234 { 3235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 3236 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); 3237 struct wm_adsp *dsp = &dsps[w->shift]; 3238 int ret; 3239 3240 switch (event) { 3241 case SND_SOC_DAPM_POST_PMU: 3242 flush_work(&dsp->boot_work); 3243 3244 mutex_lock(&dsp->pwr_lock); 3245 3246 if (!dsp->booted) { 3247 ret = -EIO; 3248 goto err; 3249 } 3250 3251 if (dsp->ops->enable_core) { 3252 ret = dsp->ops->enable_core(dsp); 3253 if (ret != 0) 3254 goto err; 3255 } 3256 3257 /* Sync set controls */ 3258 ret = wm_coeff_sync_controls(dsp); 3259 if (ret != 0) 3260 goto err; 3261 3262 if (dsp->ops->lock_memory) { 3263 ret = dsp->ops->lock_memory(dsp, dsp->lock_regions); 3264 if (ret != 0) { 3265 adsp_err(dsp, "Error configuring MPU: %d\n", 3266 ret); 3267 goto err; 3268 } 3269 } 3270 3271 if (dsp->ops->start_core) { 3272 ret = dsp->ops->start_core(dsp); 3273 if (ret != 0) 3274 goto err; 3275 } 3276 3277 if (wm_adsp_fw[dsp->fw].num_caps != 0) { 3278 ret = wm_adsp_buffer_init(dsp); 3279 if (ret < 0) 3280 goto err; 3281 } 3282 3283 dsp->running = true; 3284 3285 mutex_unlock(&dsp->pwr_lock); 3286 break; 3287 3288 case SND_SOC_DAPM_PRE_PMD: 3289 /* Tell the firmware to cleanup */ 3290 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); 3291 3292 if (dsp->ops->stop_watchdog) 3293 dsp->ops->stop_watchdog(dsp); 3294 3295 /* Log firmware state, it can be useful for analysis */ 3296 if (dsp->ops->show_fw_status) 3297 dsp->ops->show_fw_status(dsp); 3298 3299 mutex_lock(&dsp->pwr_lock); 3300 3301 dsp->running = false; 3302 3303 if (dsp->ops->stop_core) 3304 dsp->ops->stop_core(dsp); 3305 if (dsp->ops->disable_core) 3306 dsp->ops->disable_core(dsp); 3307 3308 if (wm_adsp_fw[dsp->fw].num_caps != 0) 3309 wm_adsp_buffer_free(dsp); 3310 3311 dsp->fatal_error = false; 3312 3313 mutex_unlock(&dsp->pwr_lock); 3314 3315 adsp_dbg(dsp, "Execution stopped\n"); 3316 break; 3317 3318 default: 3319 break; 3320 } 3321 3322 return 0; 3323 err: 3324 if (dsp->ops->stop_core) 3325 dsp->ops->stop_core(dsp); 3326 if (dsp->ops->disable_core) 3327 dsp->ops->disable_core(dsp); 3328 mutex_unlock(&dsp->pwr_lock); 3329 return ret; 3330 } 3331 EXPORT_SYMBOL_GPL(wm_adsp_event); 3332 3333 static int wm_halo_start_core(struct wm_adsp *dsp) 3334 { 3335 return regmap_update_bits(dsp->regmap, 3336 dsp->base + HALO_CCM_CORE_CONTROL, 3337 HALO_CORE_RESET | HALO_CORE_EN, 3338 HALO_CORE_RESET | HALO_CORE_EN); 3339 } 3340 3341 static void wm_halo_stop_core(struct wm_adsp *dsp) 3342 { 3343 regmap_update_bits(dsp->regmap, dsp->base + HALO_CCM_CORE_CONTROL, 3344 HALO_CORE_EN, 0); 3345 3346 /* reset halo core with CORE_SOFT_RESET */ 3347 regmap_update_bits(dsp->regmap, dsp->base + HALO_CORE_SOFT_RESET, 3348 HALO_CORE_SOFT_RESET_MASK, 1); 3349 } 3350 3351 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component) 3352 { 3353 char preload[32]; 3354 3355 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); 3356 snd_soc_component_disable_pin(component, preload); 3357 3358 wm_adsp2_init_debugfs(dsp, component); 3359 3360 dsp->component = component; 3361 3362 return 0; 3363 } 3364 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe); 3365 3366 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component) 3367 { 3368 wm_adsp2_cleanup_debugfs(dsp); 3369 3370 return 0; 3371 } 3372 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove); 3373 3374 int wm_adsp2_init(struct wm_adsp *dsp) 3375 { 3376 int ret; 3377 3378 ret = wm_adsp_common_init(dsp); 3379 if (ret) 3380 return ret; 3381 3382 switch (dsp->rev) { 3383 case 0: 3384 /* 3385 * Disable the DSP memory by default when in reset for a small 3386 * power saving. 3387 */ 3388 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, 3389 ADSP2_MEM_ENA, 0); 3390 if (ret) { 3391 adsp_err(dsp, 3392 "Failed to clear memory retention: %d\n", ret); 3393 return ret; 3394 } 3395 3396 dsp->ops = &wm_adsp2_ops[0]; 3397 break; 3398 case 1: 3399 dsp->ops = &wm_adsp2_ops[1]; 3400 break; 3401 default: 3402 dsp->ops = &wm_adsp2_ops[2]; 3403 break; 3404 } 3405 3406 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); 3407 3408 return 0; 3409 } 3410 EXPORT_SYMBOL_GPL(wm_adsp2_init); 3411 3412 int wm_halo_init(struct wm_adsp *dsp) 3413 { 3414 int ret; 3415 3416 ret = wm_adsp_common_init(dsp); 3417 if (ret) 3418 return ret; 3419 3420 dsp->ops = &wm_halo_ops; 3421 3422 INIT_WORK(&dsp->boot_work, wm_adsp_boot_work); 3423 3424 return 0; 3425 } 3426 EXPORT_SYMBOL_GPL(wm_halo_init); 3427 3428 void wm_adsp2_remove(struct wm_adsp *dsp) 3429 { 3430 struct wm_coeff_ctl *ctl; 3431 3432 while (!list_empty(&dsp->ctl_list)) { 3433 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, 3434 list); 3435 list_del(&ctl->list); 3436 wm_adsp_free_ctl_blk(ctl); 3437 } 3438 } 3439 EXPORT_SYMBOL_GPL(wm_adsp2_remove); 3440 3441 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr) 3442 { 3443 return compr->buf != NULL; 3444 } 3445 3446 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr) 3447 { 3448 struct wm_adsp_compr_buf *buf = NULL, *tmp; 3449 3450 if (compr->dsp->fatal_error) 3451 return -EINVAL; 3452 3453 list_for_each_entry(tmp, &compr->dsp->buffer_list, list) { 3454 if (!tmp->name || !strcmp(compr->name, tmp->name)) { 3455 buf = tmp; 3456 break; 3457 } 3458 } 3459 3460 if (!buf) 3461 return -EINVAL; 3462 3463 compr->buf = buf; 3464 buf->compr = compr; 3465 3466 return 0; 3467 } 3468 3469 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr) 3470 { 3471 if (!compr) 3472 return; 3473 3474 /* Wake the poll so it can see buffer is no longer attached */ 3475 if (compr->stream) 3476 snd_compr_fragment_elapsed(compr->stream); 3477 3478 if (wm_adsp_compr_attached(compr)) { 3479 compr->buf->compr = NULL; 3480 compr->buf = NULL; 3481 } 3482 } 3483 3484 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream) 3485 { 3486 struct wm_adsp_compr *compr, *tmp; 3487 struct snd_soc_pcm_runtime *rtd = stream->private_data; 3488 int ret = 0; 3489 3490 mutex_lock(&dsp->pwr_lock); 3491 3492 if (wm_adsp_fw[dsp->fw].num_caps == 0) { 3493 adsp_err(dsp, "%s: Firmware does not support compressed API\n", 3494 asoc_rtd_to_codec(rtd, 0)->name); 3495 ret = -ENXIO; 3496 goto out; 3497 } 3498 3499 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { 3500 adsp_err(dsp, "%s: Firmware does not support stream direction\n", 3501 asoc_rtd_to_codec(rtd, 0)->name); 3502 ret = -EINVAL; 3503 goto out; 3504 } 3505 3506 list_for_each_entry(tmp, &dsp->compr_list, list) { 3507 if (!strcmp(tmp->name, asoc_rtd_to_codec(rtd, 0)->name)) { 3508 adsp_err(dsp, "%s: Only a single stream supported per dai\n", 3509 asoc_rtd_to_codec(rtd, 0)->name); 3510 ret = -EBUSY; 3511 goto out; 3512 } 3513 } 3514 3515 compr = kzalloc(sizeof(*compr), GFP_KERNEL); 3516 if (!compr) { 3517 ret = -ENOMEM; 3518 goto out; 3519 } 3520 3521 compr->dsp = dsp; 3522 compr->stream = stream; 3523 compr->name = asoc_rtd_to_codec(rtd, 0)->name; 3524 3525 list_add_tail(&compr->list, &dsp->compr_list); 3526 3527 stream->runtime->private_data = compr; 3528 3529 out: 3530 mutex_unlock(&dsp->pwr_lock); 3531 3532 return ret; 3533 } 3534 EXPORT_SYMBOL_GPL(wm_adsp_compr_open); 3535 3536 int wm_adsp_compr_free(struct snd_soc_component *component, 3537 struct snd_compr_stream *stream) 3538 { 3539 struct wm_adsp_compr *compr = stream->runtime->private_data; 3540 struct wm_adsp *dsp = compr->dsp; 3541 3542 mutex_lock(&dsp->pwr_lock); 3543 3544 wm_adsp_compr_detach(compr); 3545 list_del(&compr->list); 3546 3547 kfree(compr->raw_buf); 3548 kfree(compr); 3549 3550 mutex_unlock(&dsp->pwr_lock); 3551 3552 return 0; 3553 } 3554 EXPORT_SYMBOL_GPL(wm_adsp_compr_free); 3555 3556 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, 3557 struct snd_compr_params *params) 3558 { 3559 struct wm_adsp_compr *compr = stream->runtime->private_data; 3560 struct wm_adsp *dsp = compr->dsp; 3561 const struct wm_adsp_fw_caps *caps; 3562 const struct snd_codec_desc *desc; 3563 int i, j; 3564 3565 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE || 3566 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE || 3567 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || 3568 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || 3569 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) { 3570 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n", 3571 params->buffer.fragment_size, 3572 params->buffer.fragments); 3573 3574 return -EINVAL; 3575 } 3576 3577 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { 3578 caps = &wm_adsp_fw[dsp->fw].caps[i]; 3579 desc = &caps->desc; 3580 3581 if (caps->id != params->codec.id) 3582 continue; 3583 3584 if (stream->direction == SND_COMPRESS_PLAYBACK) { 3585 if (desc->max_ch < params->codec.ch_out) 3586 continue; 3587 } else { 3588 if (desc->max_ch < params->codec.ch_in) 3589 continue; 3590 } 3591 3592 if (!(desc->formats & (1 << params->codec.format))) 3593 continue; 3594 3595 for (j = 0; j < desc->num_sample_rates; ++j) 3596 if (desc->sample_rates[j] == params->codec.sample_rate) 3597 return 0; 3598 } 3599 3600 compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", 3601 params->codec.id, params->codec.ch_in, params->codec.ch_out, 3602 params->codec.sample_rate, params->codec.format); 3603 return -EINVAL; 3604 } 3605 3606 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr) 3607 { 3608 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE; 3609 } 3610 3611 int wm_adsp_compr_set_params(struct snd_soc_component *component, 3612 struct snd_compr_stream *stream, 3613 struct snd_compr_params *params) 3614 { 3615 struct wm_adsp_compr *compr = stream->runtime->private_data; 3616 unsigned int size; 3617 int ret; 3618 3619 ret = wm_adsp_compr_check_params(stream, params); 3620 if (ret) 3621 return ret; 3622 3623 compr->size = params->buffer; 3624 3625 compr_dbg(compr, "fragment_size=%d fragments=%d\n", 3626 compr->size.fragment_size, compr->size.fragments); 3627 3628 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf); 3629 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); 3630 if (!compr->raw_buf) 3631 return -ENOMEM; 3632 3633 compr->sample_rate = params->codec.sample_rate; 3634 3635 return 0; 3636 } 3637 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); 3638 3639 int wm_adsp_compr_get_caps(struct snd_soc_component *component, 3640 struct snd_compr_stream *stream, 3641 struct snd_compr_caps *caps) 3642 { 3643 struct wm_adsp_compr *compr = stream->runtime->private_data; 3644 int fw = compr->dsp->fw; 3645 int i; 3646 3647 if (wm_adsp_fw[fw].caps) { 3648 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) 3649 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; 3650 3651 caps->num_codecs = i; 3652 caps->direction = wm_adsp_fw[fw].compr_direction; 3653 3654 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE; 3655 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE; 3656 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; 3657 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; 3658 } 3659 3660 return 0; 3661 } 3662 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); 3663 3664 static int wm_adsp_read_raw_data_block(struct wm_adsp *dsp, int mem_type, 3665 unsigned int mem_addr, 3666 unsigned int num_words, __be32 *data) 3667 { 3668 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); 3669 unsigned int reg; 3670 int ret; 3671 3672 if (!mem) 3673 return -EINVAL; 3674 3675 reg = dsp->ops->region_to_reg(mem, mem_addr); 3676 3677 ret = regmap_raw_read(dsp->regmap, reg, data, 3678 sizeof(*data) * num_words); 3679 if (ret < 0) 3680 return ret; 3681 3682 return 0; 3683 } 3684 3685 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, 3686 unsigned int mem_addr, u32 *data) 3687 { 3688 __be32 raw; 3689 int ret; 3690 3691 ret = wm_adsp_read_raw_data_block(dsp, mem_type, mem_addr, 1, &raw); 3692 if (ret < 0) 3693 return ret; 3694 3695 *data = be32_to_cpu(raw) & 0x00ffffffu; 3696 3697 return 0; 3698 } 3699 3700 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, 3701 unsigned int mem_addr, u32 data) 3702 { 3703 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); 3704 __be32 val = cpu_to_be32(data & 0x00ffffffu); 3705 unsigned int reg; 3706 3707 if (!mem) 3708 return -EINVAL; 3709 3710 reg = dsp->ops->region_to_reg(mem, mem_addr); 3711 3712 return regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); 3713 } 3714 3715 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf, 3716 unsigned int field_offset, u32 *data) 3717 { 3718 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type, 3719 buf->host_buf_ptr + field_offset, data); 3720 } 3721 3722 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf, 3723 unsigned int field_offset, u32 data) 3724 { 3725 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type, 3726 buf->host_buf_ptr + field_offset, data); 3727 } 3728 3729 static void wm_adsp_remove_padding(u32 *buf, int nwords) 3730 { 3731 const __be32 *pack_in = (__be32 *)buf; 3732 u8 *pack_out = (u8 *)buf; 3733 int i; 3734 3735 /* 3736 * DSP words from the register map have pad bytes and the data bytes 3737 * are in swapped order. This swaps back to the original little-endian 3738 * order and strips the pad bytes. 3739 */ 3740 for (i = 0; i < nwords; i++) { 3741 u32 word = be32_to_cpu(*pack_in++); 3742 *pack_out++ = (u8)word; 3743 *pack_out++ = (u8)(word >> 8); 3744 *pack_out++ = (u8)(word >> 16); 3745 } 3746 } 3747 3748 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) 3749 { 3750 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps; 3751 struct wm_adsp_buffer_region *region; 3752 u32 offset = 0; 3753 int i, ret; 3754 3755 buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions), 3756 GFP_KERNEL); 3757 if (!buf->regions) 3758 return -ENOMEM; 3759 3760 for (i = 0; i < caps->num_regions; ++i) { 3761 region = &buf->regions[i]; 3762 3763 region->offset = offset; 3764 region->mem_type = caps->region_defs[i].mem_type; 3765 3766 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset, 3767 ®ion->base_addr); 3768 if (ret < 0) 3769 return ret; 3770 3771 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset, 3772 &offset); 3773 if (ret < 0) 3774 return ret; 3775 3776 region->cumulative_size = offset; 3777 3778 compr_dbg(buf, 3779 "region=%d type=%d base=%08x off=%08x size=%08x\n", 3780 i, region->mem_type, region->base_addr, 3781 region->offset, region->cumulative_size); 3782 } 3783 3784 return 0; 3785 } 3786 3787 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf) 3788 { 3789 buf->irq_count = 0xFFFFFFFF; 3790 buf->read_index = -1; 3791 buf->avail = 0; 3792 } 3793 3794 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp) 3795 { 3796 struct wm_adsp_compr_buf *buf; 3797 3798 buf = kzalloc(sizeof(*buf), GFP_KERNEL); 3799 if (!buf) 3800 return NULL; 3801 3802 buf->dsp = dsp; 3803 3804 wm_adsp_buffer_clear(buf); 3805 3806 list_add_tail(&buf->list, &dsp->buffer_list); 3807 3808 return buf; 3809 } 3810 3811 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp) 3812 { 3813 struct wm_adsp_alg_region *alg_region; 3814 struct wm_adsp_compr_buf *buf; 3815 u32 xmalg, addr, magic; 3816 int i, ret; 3817 3818 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); 3819 if (!alg_region) { 3820 adsp_err(dsp, "No algorithm region found\n"); 3821 return -EINVAL; 3822 } 3823 3824 buf = wm_adsp_buffer_alloc(dsp); 3825 if (!buf) 3826 return -ENOMEM; 3827 3828 xmalg = dsp->ops->sys_config_size / sizeof(__be32); 3829 3830 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); 3831 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); 3832 if (ret < 0) 3833 return ret; 3834 3835 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) 3836 return -ENODEV; 3837 3838 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); 3839 for (i = 0; i < 5; ++i) { 3840 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, 3841 &buf->host_buf_ptr); 3842 if (ret < 0) 3843 return ret; 3844 3845 if (buf->host_buf_ptr) 3846 break; 3847 3848 usleep_range(1000, 2000); 3849 } 3850 3851 if (!buf->host_buf_ptr) 3852 return -EIO; 3853 3854 buf->host_buf_mem_type = WMFW_ADSP2_XM; 3855 3856 ret = wm_adsp_buffer_populate(buf); 3857 if (ret < 0) 3858 return ret; 3859 3860 compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr); 3861 3862 return 0; 3863 } 3864 3865 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl) 3866 { 3867 struct wm_adsp_host_buf_coeff_v1 coeff_v1; 3868 struct wm_adsp_compr_buf *buf; 3869 unsigned int reg, version; 3870 __be32 bufp; 3871 int ret, i; 3872 3873 ret = wm_coeff_base_reg(ctl, ®); 3874 if (ret) 3875 return ret; 3876 3877 for (i = 0; i < 5; ++i) { 3878 ret = regmap_raw_read(ctl->dsp->regmap, reg, &bufp, sizeof(bufp)); 3879 if (ret < 0) 3880 return ret; 3881 3882 if (bufp) 3883 break; 3884 3885 usleep_range(1000, 2000); 3886 } 3887 3888 if (!bufp) { 3889 adsp_err(ctl->dsp, "Failed to acquire host buffer\n"); 3890 return -EIO; 3891 } 3892 3893 buf = wm_adsp_buffer_alloc(ctl->dsp); 3894 if (!buf) 3895 return -ENOMEM; 3896 3897 buf->host_buf_mem_type = ctl->alg_region.type; 3898 buf->host_buf_ptr = be32_to_cpu(bufp); 3899 3900 ret = wm_adsp_buffer_populate(buf); 3901 if (ret < 0) 3902 return ret; 3903 3904 /* 3905 * v0 host_buffer coefficients didn't have versioning, so if the 3906 * control is one word, assume version 0. 3907 */ 3908 if (ctl->len == 4) { 3909 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr); 3910 return 0; 3911 } 3912 3913 ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1, 3914 sizeof(coeff_v1)); 3915 if (ret < 0) 3916 return ret; 3917 3918 version = be32_to_cpu(coeff_v1.versions) & HOST_BUF_COEFF_COMPAT_VER_MASK; 3919 version >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT; 3920 3921 if (version > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) { 3922 adsp_err(ctl->dsp, 3923 "Host buffer coeff ver %u > supported version %u\n", 3924 version, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER); 3925 return -EINVAL; 3926 } 3927 3928 wm_adsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name)); 3929 3930 buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part, 3931 (char *)&coeff_v1.name); 3932 3933 compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n", 3934 buf->host_buf_ptr, version); 3935 3936 return version; 3937 } 3938 3939 static int wm_adsp_buffer_init(struct wm_adsp *dsp) 3940 { 3941 struct wm_coeff_ctl *ctl; 3942 int ret; 3943 3944 list_for_each_entry(ctl, &dsp->ctl_list, list) { 3945 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER) 3946 continue; 3947 3948 if (!ctl->enabled) 3949 continue; 3950 3951 ret = wm_adsp_buffer_parse_coeff(ctl); 3952 if (ret < 0) { 3953 adsp_err(dsp, "Failed to parse coeff: %d\n", ret); 3954 goto error; 3955 } else if (ret == 0) { 3956 /* Only one buffer supported for version 0 */ 3957 return 0; 3958 } 3959 } 3960 3961 if (list_empty(&dsp->buffer_list)) { 3962 /* Fall back to legacy support */ 3963 ret = wm_adsp_buffer_parse_legacy(dsp); 3964 if (ret) { 3965 adsp_err(dsp, "Failed to parse legacy: %d\n", ret); 3966 goto error; 3967 } 3968 } 3969 3970 return 0; 3971 3972 error: 3973 wm_adsp_buffer_free(dsp); 3974 return ret; 3975 } 3976 3977 static int wm_adsp_buffer_free(struct wm_adsp *dsp) 3978 { 3979 struct wm_adsp_compr_buf *buf, *tmp; 3980 3981 list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) { 3982 wm_adsp_compr_detach(buf->compr); 3983 3984 kfree(buf->name); 3985 kfree(buf->regions); 3986 list_del(&buf->list); 3987 kfree(buf); 3988 } 3989 3990 return 0; 3991 } 3992 3993 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf) 3994 { 3995 int ret; 3996 3997 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error); 3998 if (ret < 0) { 3999 compr_err(buf, "Failed to check buffer error: %d\n", ret); 4000 return ret; 4001 } 4002 if (buf->error != 0) { 4003 compr_err(buf, "Buffer error occurred: %d\n", buf->error); 4004 return -EIO; 4005 } 4006 4007 return 0; 4008 } 4009 4010 int wm_adsp_compr_trigger(struct snd_soc_component *component, 4011 struct snd_compr_stream *stream, int cmd) 4012 { 4013 struct wm_adsp_compr *compr = stream->runtime->private_data; 4014 struct wm_adsp *dsp = compr->dsp; 4015 int ret = 0; 4016 4017 compr_dbg(compr, "Trigger: %d\n", cmd); 4018 4019 mutex_lock(&dsp->pwr_lock); 4020 4021 switch (cmd) { 4022 case SNDRV_PCM_TRIGGER_START: 4023 if (!wm_adsp_compr_attached(compr)) { 4024 ret = wm_adsp_compr_attach(compr); 4025 if (ret < 0) { 4026 compr_err(compr, "Failed to link buffer and stream: %d\n", 4027 ret); 4028 break; 4029 } 4030 } 4031 4032 ret = wm_adsp_buffer_get_error(compr->buf); 4033 if (ret < 0) 4034 break; 4035 4036 /* Trigger the IRQ at one fragment of data */ 4037 ret = wm_adsp_buffer_write(compr->buf, 4038 HOST_BUFFER_FIELD(high_water_mark), 4039 wm_adsp_compr_frag_words(compr)); 4040 if (ret < 0) { 4041 compr_err(compr, "Failed to set high water mark: %d\n", 4042 ret); 4043 break; 4044 } 4045 break; 4046 case SNDRV_PCM_TRIGGER_STOP: 4047 if (wm_adsp_compr_attached(compr)) 4048 wm_adsp_buffer_clear(compr->buf); 4049 break; 4050 default: 4051 ret = -EINVAL; 4052 break; 4053 } 4054 4055 mutex_unlock(&dsp->pwr_lock); 4056 4057 return ret; 4058 } 4059 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); 4060 4061 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) 4062 { 4063 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1; 4064 4065 return buf->regions[last_region].cumulative_size; 4066 } 4067 4068 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) 4069 { 4070 u32 next_read_index, next_write_index; 4071 int write_index, read_index, avail; 4072 int ret; 4073 4074 /* Only sync read index if we haven't already read a valid index */ 4075 if (buf->read_index < 0) { 4076 ret = wm_adsp_buffer_read(buf, 4077 HOST_BUFFER_FIELD(next_read_index), 4078 &next_read_index); 4079 if (ret < 0) 4080 return ret; 4081 4082 read_index = sign_extend32(next_read_index, 23); 4083 4084 if (read_index < 0) { 4085 compr_dbg(buf, "Avail check on unstarted stream\n"); 4086 return 0; 4087 } 4088 4089 buf->read_index = read_index; 4090 } 4091 4092 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index), 4093 &next_write_index); 4094 if (ret < 0) 4095 return ret; 4096 4097 write_index = sign_extend32(next_write_index, 23); 4098 4099 avail = write_index - buf->read_index; 4100 if (avail < 0) 4101 avail += wm_adsp_buffer_size(buf); 4102 4103 compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n", 4104 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE); 4105 4106 buf->avail = avail; 4107 4108 return 0; 4109 } 4110 4111 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp) 4112 { 4113 struct wm_adsp_compr_buf *buf; 4114 struct wm_adsp_compr *compr; 4115 int ret = 0; 4116 4117 mutex_lock(&dsp->pwr_lock); 4118 4119 if (list_empty(&dsp->buffer_list)) { 4120 ret = -ENODEV; 4121 goto out; 4122 } 4123 4124 adsp_dbg(dsp, "Handling buffer IRQ\n"); 4125 4126 list_for_each_entry(buf, &dsp->buffer_list, list) { 4127 compr = buf->compr; 4128 4129 ret = wm_adsp_buffer_get_error(buf); 4130 if (ret < 0) 4131 goto out_notify; /* Wake poll to report error */ 4132 4133 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), 4134 &buf->irq_count); 4135 if (ret < 0) { 4136 compr_err(buf, "Failed to get irq_count: %d\n", ret); 4137 goto out; 4138 } 4139 4140 ret = wm_adsp_buffer_update_avail(buf); 4141 if (ret < 0) { 4142 compr_err(buf, "Error reading avail: %d\n", ret); 4143 goto out; 4144 } 4145 4146 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2) 4147 ret = WM_ADSP_COMPR_VOICE_TRIGGER; 4148 4149 out_notify: 4150 if (compr && compr->stream) 4151 snd_compr_fragment_elapsed(compr->stream); 4152 } 4153 4154 out: 4155 mutex_unlock(&dsp->pwr_lock); 4156 4157 return ret; 4158 } 4159 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq); 4160 4161 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf) 4162 { 4163 if (buf->irq_count & 0x01) 4164 return 0; 4165 4166 compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count); 4167 4168 buf->irq_count |= 0x01; 4169 4170 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), 4171 buf->irq_count); 4172 } 4173 4174 int wm_adsp_compr_pointer(struct snd_soc_component *component, 4175 struct snd_compr_stream *stream, 4176 struct snd_compr_tstamp *tstamp) 4177 { 4178 struct wm_adsp_compr *compr = stream->runtime->private_data; 4179 struct wm_adsp *dsp = compr->dsp; 4180 struct wm_adsp_compr_buf *buf; 4181 int ret = 0; 4182 4183 compr_dbg(compr, "Pointer request\n"); 4184 4185 mutex_lock(&dsp->pwr_lock); 4186 4187 buf = compr->buf; 4188 4189 if (dsp->fatal_error || !buf || buf->error) { 4190 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); 4191 ret = -EIO; 4192 goto out; 4193 } 4194 4195 if (buf->avail < wm_adsp_compr_frag_words(compr)) { 4196 ret = wm_adsp_buffer_update_avail(buf); 4197 if (ret < 0) { 4198 compr_err(compr, "Error reading avail: %d\n", ret); 4199 goto out; 4200 } 4201 4202 /* 4203 * If we really have less than 1 fragment available tell the 4204 * DSP to inform us once a whole fragment is available. 4205 */ 4206 if (buf->avail < wm_adsp_compr_frag_words(compr)) { 4207 ret = wm_adsp_buffer_get_error(buf); 4208 if (ret < 0) { 4209 if (buf->error) 4210 snd_compr_stop_error(stream, 4211 SNDRV_PCM_STATE_XRUN); 4212 goto out; 4213 } 4214 4215 ret = wm_adsp_buffer_reenable_irq(buf); 4216 if (ret < 0) { 4217 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n", 4218 ret); 4219 goto out; 4220 } 4221 } 4222 } 4223 4224 tstamp->copied_total = compr->copied_total; 4225 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE; 4226 tstamp->sampling_rate = compr->sample_rate; 4227 4228 out: 4229 mutex_unlock(&dsp->pwr_lock); 4230 4231 return ret; 4232 } 4233 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); 4234 4235 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) 4236 { 4237 struct wm_adsp_compr_buf *buf = compr->buf; 4238 unsigned int adsp_addr; 4239 int mem_type, nwords, max_read; 4240 int i, ret; 4241 4242 /* Calculate read parameters */ 4243 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i) 4244 if (buf->read_index < buf->regions[i].cumulative_size) 4245 break; 4246 4247 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions) 4248 return -EINVAL; 4249 4250 mem_type = buf->regions[i].mem_type; 4251 adsp_addr = buf->regions[i].base_addr + 4252 (buf->read_index - buf->regions[i].offset); 4253 4254 max_read = wm_adsp_compr_frag_words(compr); 4255 nwords = buf->regions[i].cumulative_size - buf->read_index; 4256 4257 if (nwords > target) 4258 nwords = target; 4259 if (nwords > buf->avail) 4260 nwords = buf->avail; 4261 if (nwords > max_read) 4262 nwords = max_read; 4263 if (!nwords) 4264 return 0; 4265 4266 /* Read data from DSP */ 4267 ret = wm_adsp_read_raw_data_block(buf->dsp, mem_type, adsp_addr, 4268 nwords, (__be32 *)compr->raw_buf); 4269 if (ret < 0) 4270 return ret; 4271 4272 wm_adsp_remove_padding(compr->raw_buf, nwords); 4273 4274 /* update read index to account for words read */ 4275 buf->read_index += nwords; 4276 if (buf->read_index == wm_adsp_buffer_size(buf)) 4277 buf->read_index = 0; 4278 4279 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), 4280 buf->read_index); 4281 if (ret < 0) 4282 return ret; 4283 4284 /* update avail to account for words read */ 4285 buf->avail -= nwords; 4286 4287 return nwords; 4288 } 4289 4290 static int wm_adsp_compr_read(struct wm_adsp_compr *compr, 4291 char __user *buf, size_t count) 4292 { 4293 struct wm_adsp *dsp = compr->dsp; 4294 int ntotal = 0; 4295 int nwords, nbytes; 4296 4297 compr_dbg(compr, "Requested read of %zu bytes\n", count); 4298 4299 if (dsp->fatal_error || !compr->buf || compr->buf->error) { 4300 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); 4301 return -EIO; 4302 } 4303 4304 count /= WM_ADSP_DATA_WORD_SIZE; 4305 4306 do { 4307 nwords = wm_adsp_buffer_capture_block(compr, count); 4308 if (nwords < 0) { 4309 compr_err(compr, "Failed to capture block: %d\n", 4310 nwords); 4311 return nwords; 4312 } 4313 4314 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE; 4315 4316 compr_dbg(compr, "Read %d bytes\n", nbytes); 4317 4318 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) { 4319 compr_err(compr, "Failed to copy data to user: %d, %d\n", 4320 ntotal, nbytes); 4321 return -EFAULT; 4322 } 4323 4324 count -= nwords; 4325 ntotal += nbytes; 4326 } while (nwords > 0 && count > 0); 4327 4328 compr->copied_total += ntotal; 4329 4330 return ntotal; 4331 } 4332 4333 int wm_adsp_compr_copy(struct snd_soc_component *component, 4334 struct snd_compr_stream *stream, char __user *buf, 4335 size_t count) 4336 { 4337 struct wm_adsp_compr *compr = stream->runtime->private_data; 4338 struct wm_adsp *dsp = compr->dsp; 4339 int ret; 4340 4341 mutex_lock(&dsp->pwr_lock); 4342 4343 if (stream->direction == SND_COMPRESS_CAPTURE) 4344 ret = wm_adsp_compr_read(compr, buf, count); 4345 else 4346 ret = -ENOTSUPP; 4347 4348 mutex_unlock(&dsp->pwr_lock); 4349 4350 return ret; 4351 } 4352 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); 4353 4354 static void wm_adsp_fatal_error(struct wm_adsp *dsp) 4355 { 4356 struct wm_adsp_compr *compr; 4357 4358 dsp->fatal_error = true; 4359 4360 list_for_each_entry(compr, &dsp->compr_list, list) { 4361 if (compr->stream) 4362 snd_compr_fragment_elapsed(compr->stream); 4363 } 4364 } 4365 4366 irqreturn_t wm_adsp2_bus_error(int irq, void *data) 4367 { 4368 struct wm_adsp *dsp = (struct wm_adsp *)data; 4369 unsigned int val; 4370 struct regmap *regmap = dsp->regmap; 4371 int ret = 0; 4372 4373 mutex_lock(&dsp->pwr_lock); 4374 4375 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); 4376 if (ret) { 4377 adsp_err(dsp, 4378 "Failed to read Region Lock Ctrl register: %d\n", ret); 4379 goto error; 4380 } 4381 4382 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { 4383 adsp_err(dsp, "watchdog timeout error\n"); 4384 dsp->ops->stop_watchdog(dsp); 4385 wm_adsp_fatal_error(dsp); 4386 } 4387 4388 if (val & (ADSP2_ADDR_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { 4389 if (val & ADSP2_ADDR_ERR_MASK) 4390 adsp_err(dsp, "bus error: address error\n"); 4391 else 4392 adsp_err(dsp, "bus error: region lock error\n"); 4393 4394 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); 4395 if (ret) { 4396 adsp_err(dsp, 4397 "Failed to read Bus Err Addr register: %d\n", 4398 ret); 4399 goto error; 4400 } 4401 4402 adsp_err(dsp, "bus error address = 0x%x\n", 4403 val & ADSP2_BUS_ERR_ADDR_MASK); 4404 4405 ret = regmap_read(regmap, 4406 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, 4407 &val); 4408 if (ret) { 4409 adsp_err(dsp, 4410 "Failed to read Pmem Xmem Err Addr register: %d\n", 4411 ret); 4412 goto error; 4413 } 4414 4415 adsp_err(dsp, "xmem error address = 0x%x\n", 4416 val & ADSP2_XMEM_ERR_ADDR_MASK); 4417 adsp_err(dsp, "pmem error address = 0x%x\n", 4418 (val & ADSP2_PMEM_ERR_ADDR_MASK) >> 4419 ADSP2_PMEM_ERR_ADDR_SHIFT); 4420 } 4421 4422 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, 4423 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); 4424 4425 error: 4426 mutex_unlock(&dsp->pwr_lock); 4427 4428 return IRQ_HANDLED; 4429 } 4430 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); 4431 4432 irqreturn_t wm_halo_bus_error(int irq, void *data) 4433 { 4434 struct wm_adsp *dsp = (struct wm_adsp *)data; 4435 struct regmap *regmap = dsp->regmap; 4436 unsigned int fault[6]; 4437 struct reg_sequence clear[] = { 4438 { dsp->base + HALO_MPU_XM_VIO_STATUS, 0x0 }, 4439 { dsp->base + HALO_MPU_YM_VIO_STATUS, 0x0 }, 4440 { dsp->base + HALO_MPU_PM_VIO_STATUS, 0x0 }, 4441 }; 4442 int ret; 4443 4444 mutex_lock(&dsp->pwr_lock); 4445 4446 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_1, 4447 fault); 4448 if (ret) { 4449 adsp_warn(dsp, "Failed to read AHB DEBUG_1: %d\n", ret); 4450 goto exit_unlock; 4451 } 4452 4453 adsp_warn(dsp, "AHB: STATUS: 0x%x ADDR: 0x%x\n", 4454 *fault & HALO_AHBM_FLAGS_ERR_MASK, 4455 (*fault & HALO_AHBM_CORE_ERR_ADDR_MASK) >> 4456 HALO_AHBM_CORE_ERR_ADDR_SHIFT); 4457 4458 ret = regmap_read(regmap, dsp->base_sysinfo + HALO_AHBM_WINDOW_DEBUG_0, 4459 fault); 4460 if (ret) { 4461 adsp_warn(dsp, "Failed to read AHB DEBUG_0: %d\n", ret); 4462 goto exit_unlock; 4463 } 4464 4465 adsp_warn(dsp, "AHB: SYS_ADDR: 0x%x\n", *fault); 4466 4467 ret = regmap_bulk_read(regmap, dsp->base + HALO_MPU_XM_VIO_ADDR, 4468 fault, ARRAY_SIZE(fault)); 4469 if (ret) { 4470 adsp_warn(dsp, "Failed to read MPU fault info: %d\n", ret); 4471 goto exit_unlock; 4472 } 4473 4474 adsp_warn(dsp, "XM: STATUS:0x%x ADDR:0x%x\n", fault[1], fault[0]); 4475 adsp_warn(dsp, "YM: STATUS:0x%x ADDR:0x%x\n", fault[3], fault[2]); 4476 adsp_warn(dsp, "PM: STATUS:0x%x ADDR:0x%x\n", fault[5], fault[4]); 4477 4478 ret = regmap_multi_reg_write(dsp->regmap, clear, ARRAY_SIZE(clear)); 4479 if (ret) 4480 adsp_warn(dsp, "Failed to clear MPU status: %d\n", ret); 4481 4482 exit_unlock: 4483 mutex_unlock(&dsp->pwr_lock); 4484 4485 return IRQ_HANDLED; 4486 } 4487 EXPORT_SYMBOL_GPL(wm_halo_bus_error); 4488 4489 irqreturn_t wm_halo_wdt_expire(int irq, void *data) 4490 { 4491 struct wm_adsp *dsp = data; 4492 4493 mutex_lock(&dsp->pwr_lock); 4494 4495 adsp_warn(dsp, "WDT Expiry Fault\n"); 4496 dsp->ops->stop_watchdog(dsp); 4497 wm_adsp_fatal_error(dsp); 4498 4499 mutex_unlock(&dsp->pwr_lock); 4500 4501 return IRQ_HANDLED; 4502 } 4503 EXPORT_SYMBOL_GPL(wm_halo_wdt_expire); 4504 4505 static const struct wm_adsp_ops wm_adsp1_ops = { 4506 .validate_version = wm_adsp_validate_version, 4507 .parse_sizes = wm_adsp1_parse_sizes, 4508 .region_to_reg = wm_adsp_region_to_reg, 4509 }; 4510 4511 static const struct wm_adsp_ops wm_adsp2_ops[] = { 4512 { 4513 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), 4514 .parse_sizes = wm_adsp2_parse_sizes, 4515 .validate_version = wm_adsp_validate_version, 4516 .setup_algs = wm_adsp2_setup_algs, 4517 .region_to_reg = wm_adsp_region_to_reg, 4518 4519 .show_fw_status = wm_adsp2_show_fw_status, 4520 4521 .enable_memory = wm_adsp2_enable_memory, 4522 .disable_memory = wm_adsp2_disable_memory, 4523 4524 .enable_core = wm_adsp2_enable_core, 4525 .disable_core = wm_adsp2_disable_core, 4526 4527 .start_core = wm_adsp2_start_core, 4528 .stop_core = wm_adsp2_stop_core, 4529 4530 }, 4531 { 4532 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), 4533 .parse_sizes = wm_adsp2_parse_sizes, 4534 .validate_version = wm_adsp_validate_version, 4535 .setup_algs = wm_adsp2_setup_algs, 4536 .region_to_reg = wm_adsp_region_to_reg, 4537 4538 .show_fw_status = wm_adsp2v2_show_fw_status, 4539 4540 .enable_memory = wm_adsp2_enable_memory, 4541 .disable_memory = wm_adsp2_disable_memory, 4542 .lock_memory = wm_adsp2_lock, 4543 4544 .enable_core = wm_adsp2v2_enable_core, 4545 .disable_core = wm_adsp2v2_disable_core, 4546 4547 .start_core = wm_adsp2_start_core, 4548 .stop_core = wm_adsp2_stop_core, 4549 }, 4550 { 4551 .sys_config_size = sizeof(struct wm_adsp_system_config_xm_hdr), 4552 .parse_sizes = wm_adsp2_parse_sizes, 4553 .validate_version = wm_adsp_validate_version, 4554 .setup_algs = wm_adsp2_setup_algs, 4555 .region_to_reg = wm_adsp_region_to_reg, 4556 4557 .show_fw_status = wm_adsp2v2_show_fw_status, 4558 .stop_watchdog = wm_adsp_stop_watchdog, 4559 4560 .enable_memory = wm_adsp2_enable_memory, 4561 .disable_memory = wm_adsp2_disable_memory, 4562 .lock_memory = wm_adsp2_lock, 4563 4564 .enable_core = wm_adsp2v2_enable_core, 4565 .disable_core = wm_adsp2v2_disable_core, 4566 4567 .start_core = wm_adsp2_start_core, 4568 .stop_core = wm_adsp2_stop_core, 4569 }, 4570 }; 4571 4572 static const struct wm_adsp_ops wm_halo_ops = { 4573 .sys_config_size = sizeof(struct wm_halo_system_config_xm_hdr), 4574 .parse_sizes = wm_adsp2_parse_sizes, 4575 .validate_version = wm_halo_validate_version, 4576 .setup_algs = wm_halo_setup_algs, 4577 .region_to_reg = wm_halo_region_to_reg, 4578 4579 .show_fw_status = wm_halo_show_fw_status, 4580 .stop_watchdog = wm_halo_stop_watchdog, 4581 4582 .lock_memory = wm_halo_configure_mpu, 4583 4584 .start_core = wm_halo_start_core, 4585 .stop_core = wm_halo_stop_core, 4586 }; 4587 4588 MODULE_LICENSE("GPL v2"); 4589