1 /* 2 * wm8996.c - WM8996 audio codec interface 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/workqueue.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <trace/events/asoc.h> 34 35 #include <sound/wm8996.h> 36 #include "wm8996.h" 37 38 #define WM8996_AIFS 2 39 40 #define HPOUT1L 1 41 #define HPOUT1R 2 42 #define HPOUT2L 4 43 #define HPOUT2R 8 44 45 #define WM8996_NUM_SUPPLIES 3 46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { 47 "DBVDD", 48 "AVDD1", 49 "AVDD2", 50 }; 51 52 struct wm8996_priv { 53 struct device *dev; 54 struct regmap *regmap; 55 struct snd_soc_codec *codec; 56 57 int ldo1ena; 58 59 int sysclk; 60 int sysclk_src; 61 62 int fll_src; 63 int fll_fref; 64 int fll_fout; 65 66 struct completion fll_lock; 67 68 u16 dcs_pending; 69 struct completion dcs_done; 70 71 u16 hpout_ena; 72 u16 hpout_pending; 73 74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; 75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; 76 int bg_ena; 77 78 struct wm8996_pdata pdata; 79 80 int rx_rate[WM8996_AIFS]; 81 int bclk_rate[WM8996_AIFS]; 82 83 /* Platform dependant ReTune mobile configuration */ 84 int num_retune_mobile_texts; 85 const char **retune_mobile_texts; 86 int retune_mobile_cfg[2]; 87 struct soc_enum retune_mobile_enum; 88 89 struct snd_soc_jack *jack; 90 bool detecting; 91 bool jack_mic; 92 int jack_flips; 93 wm8996_polarity_fn polarity_cb; 94 95 #ifdef CONFIG_GPIOLIB 96 struct gpio_chip gpio_chip; 97 #endif 98 }; 99 100 /* We can't use the same notifier block for more than one supply and 101 * there's no way I can see to get from a callback to the caller 102 * except container_of(). 103 */ 104 #define WM8996_REGULATOR_EVENT(n) \ 105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \ 106 unsigned long event, void *data) \ 107 { \ 108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ 109 disable_nb[n]); \ 110 if (event & REGULATOR_EVENT_DISABLE) { \ 111 regcache_mark_dirty(wm8996->regmap); \ 112 } \ 113 return 0; \ 114 } 115 116 WM8996_REGULATOR_EVENT(0) 117 WM8996_REGULATOR_EVENT(1) 118 WM8996_REGULATOR_EVENT(2) 119 120 static struct reg_default wm8996_reg[] = { 121 { WM8996_POWER_MANAGEMENT_1, 0x0 }, 122 { WM8996_POWER_MANAGEMENT_2, 0x0 }, 123 { WM8996_POWER_MANAGEMENT_3, 0x0 }, 124 { WM8996_POWER_MANAGEMENT_4, 0x0 }, 125 { WM8996_POWER_MANAGEMENT_5, 0x0 }, 126 { WM8996_POWER_MANAGEMENT_6, 0x0 }, 127 { WM8996_POWER_MANAGEMENT_7, 0x10 }, 128 { WM8996_POWER_MANAGEMENT_8, 0x0 }, 129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 }, 130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 }, 131 { WM8996_LINE_INPUT_CONTROL, 0x0 }, 132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 }, 133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 }, 134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 }, 135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 }, 136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 }, 137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 }, 138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 }, 139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 }, 140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 }, 141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 }, 142 { WM8996_MICBIAS_1, 0x39 }, 143 { WM8996_MICBIAS_2, 0x39 }, 144 { WM8996_LDO_1, 0x3 }, 145 { WM8996_LDO_2, 0x13 }, 146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 }, 147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 }, 148 { WM8996_HEADPHONE_DETECT_1, 0x20 }, 149 { WM8996_HEADPHONE_DETECT_2, 0x0 }, 150 { WM8996_MIC_DETECT_1, 0x7600 }, 151 { WM8996_MIC_DETECT_2, 0xbf }, 152 { WM8996_CHARGE_PUMP_1, 0x1f25 }, 153 { WM8996_CHARGE_PUMP_2, 0xab19 }, 154 { WM8996_DC_SERVO_1, 0x0 }, 155 { WM8996_DC_SERVO_3, 0x0 }, 156 { WM8996_DC_SERVO_5, 0x2a2a }, 157 { WM8996_DC_SERVO_6, 0x0 }, 158 { WM8996_DC_SERVO_7, 0x0 }, 159 { WM8996_ANALOGUE_HP_1, 0x0 }, 160 { WM8996_ANALOGUE_HP_2, 0x0 }, 161 { WM8996_CONTROL_INTERFACE_1, 0x8004 }, 162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 }, 163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 }, 164 { WM8996_AIF_CLOCKING_1, 0x0 }, 165 { WM8996_AIF_CLOCKING_2, 0x0 }, 166 { WM8996_CLOCKING_1, 0x10 }, 167 { WM8996_CLOCKING_2, 0x0 }, 168 { WM8996_AIF_RATE, 0x83 }, 169 { WM8996_FLL_CONTROL_1, 0x0 }, 170 { WM8996_FLL_CONTROL_2, 0x0 }, 171 { WM8996_FLL_CONTROL_3, 0x0 }, 172 { WM8996_FLL_CONTROL_4, 0x5dc0 }, 173 { WM8996_FLL_CONTROL_5, 0xc84 }, 174 { WM8996_FLL_EFS_1, 0x0 }, 175 { WM8996_FLL_EFS_2, 0x2 }, 176 { WM8996_AIF1_CONTROL, 0x0 }, 177 { WM8996_AIF1_BCLK, 0x0 }, 178 { WM8996_AIF1_TX_LRCLK_1, 0x80 }, 179 { WM8996_AIF1_TX_LRCLK_2, 0x8 }, 180 { WM8996_AIF1_RX_LRCLK_1, 0x80 }, 181 { WM8996_AIF1_RX_LRCLK_2, 0x0 }, 182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 }, 183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 }, 184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 }, 185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 }, 186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 }, 187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 }, 188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 }, 189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 }, 190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 }, 191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 }, 192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 }, 193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 }, 194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 }, 195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 }, 196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 }, 197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 }, 198 { WM8996_AIF1TX_TEST, 0x7 }, 199 { WM8996_AIF2_CONTROL, 0x0 }, 200 { WM8996_AIF2_BCLK, 0x0 }, 201 { WM8996_AIF2_TX_LRCLK_1, 0x80 }, 202 { WM8996_AIF2_TX_LRCLK_2, 0x8 }, 203 { WM8996_AIF2_RX_LRCLK_1, 0x80 }, 204 { WM8996_AIF2_RX_LRCLK_2, 0x0 }, 205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 }, 206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 }, 207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 }, 208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 }, 209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 }, 210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 }, 211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 }, 212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 }, 213 { WM8996_AIF2TX_TEST, 0x1 }, 214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 }, 215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 }, 216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 }, 217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 }, 218 { WM8996_DSP1_TX_FILTERS, 0x2000 }, 219 { WM8996_DSP1_RX_FILTERS_1, 0x200 }, 220 { WM8996_DSP1_RX_FILTERS_2, 0x10 }, 221 { WM8996_DSP1_DRC_1, 0x98 }, 222 { WM8996_DSP1_DRC_2, 0x845 }, 223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 }, 224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 }, 225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca }, 226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 }, 227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 }, 228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 }, 229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 }, 230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 }, 231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 }, 232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 }, 233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 }, 234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 }, 235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 }, 236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e }, 237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 }, 238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad }, 239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 }, 240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 }, 241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 }, 242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 }, 243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 }, 244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 }, 245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 }, 246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 }, 247 { WM8996_DSP2_TX_FILTERS, 0x2000 }, 248 { WM8996_DSP2_RX_FILTERS_1, 0x200 }, 249 { WM8996_DSP2_RX_FILTERS_2, 0x10 }, 250 { WM8996_DSP2_DRC_1, 0x98 }, 251 { WM8996_DSP2_DRC_2, 0x845 }, 252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 }, 253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 }, 254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca }, 255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 }, 256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 }, 257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 }, 258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 }, 259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 }, 260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 }, 261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 }, 262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 }, 263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 }, 264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 }, 265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e }, 266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 }, 267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad }, 268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 }, 269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 }, 270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 }, 271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 }, 272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 }, 273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 }, 274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 }, 275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 }, 276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 }, 277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 }, 278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 }, 279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 }, 280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 }, 281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 }, 282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 }, 283 { WM8996_DAC_SOFTMUTE, 0x0 }, 284 { WM8996_OVERSAMPLING, 0xd }, 285 { WM8996_SIDETONE, 0x1040 }, 286 { WM8996_GPIO_1, 0xa101 }, 287 { WM8996_GPIO_2, 0xa101 }, 288 { WM8996_GPIO_3, 0xa101 }, 289 { WM8996_GPIO_4, 0xa101 }, 290 { WM8996_GPIO_5, 0xa101 }, 291 { WM8996_PULL_CONTROL_1, 0x0 }, 292 { WM8996_PULL_CONTROL_2, 0x140 }, 293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f }, 294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf }, 295 { WM8996_LEFT_PDM_SPEAKER, 0x0 }, 296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 }, 297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 }, 298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 }, 299 }; 300 301 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); 302 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 303 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 304 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); 305 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); 306 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); 307 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 308 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); 309 310 static const char *sidetone_hpf_text[] = { 311 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" 312 }; 313 314 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 315 WM8996_SIDETONE, 7, sidetone_hpf_text); 316 317 static const char *hpf_mode_text[] = { 318 "HiFi", "Custom", "Voice" 319 }; 320 321 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode, 322 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text); 323 324 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode, 325 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text); 326 327 static const char *hpf_cutoff_text[] = { 328 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 329 }; 330 331 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff, 332 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text); 333 334 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff, 335 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text); 336 337 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) 338 { 339 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 340 struct wm8996_pdata *pdata = &wm8996->pdata; 341 int base, best, best_val, save, i, cfg, iface; 342 343 if (!wm8996->num_retune_mobile_texts) 344 return; 345 346 switch (block) { 347 case 0: 348 base = WM8996_DSP1_RX_EQ_GAINS_1; 349 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 350 WM8996_DSP1RX_SRC) 351 iface = 1; 352 else 353 iface = 0; 354 break; 355 case 1: 356 base = WM8996_DSP1_RX_EQ_GAINS_2; 357 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 358 WM8996_DSP2RX_SRC) 359 iface = 1; 360 else 361 iface = 0; 362 break; 363 default: 364 return; 365 } 366 367 /* Find the version of the currently selected configuration 368 * with the nearest sample rate. */ 369 cfg = wm8996->retune_mobile_cfg[block]; 370 best = 0; 371 best_val = INT_MAX; 372 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 373 if (strcmp(pdata->retune_mobile_cfgs[i].name, 374 wm8996->retune_mobile_texts[cfg]) == 0 && 375 abs(pdata->retune_mobile_cfgs[i].rate 376 - wm8996->rx_rate[iface]) < best_val) { 377 best = i; 378 best_val = abs(pdata->retune_mobile_cfgs[i].rate 379 - wm8996->rx_rate[iface]); 380 } 381 } 382 383 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 384 block, 385 pdata->retune_mobile_cfgs[best].name, 386 pdata->retune_mobile_cfgs[best].rate, 387 wm8996->rx_rate[iface]); 388 389 /* The EQ will be disabled while reconfiguring it, remember the 390 * current configuration. 391 */ 392 save = snd_soc_read(codec, base); 393 save &= WM8996_DSP1RX_EQ_ENA; 394 395 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) 396 snd_soc_update_bits(codec, base + i, 0xffff, 397 pdata->retune_mobile_cfgs[best].regs[i]); 398 399 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); 400 } 401 402 /* Icky as hell but saves code duplication */ 403 static int wm8996_get_retune_mobile_block(const char *name) 404 { 405 if (strcmp(name, "DSP1 EQ Mode") == 0) 406 return 0; 407 if (strcmp(name, "DSP2 EQ Mode") == 0) 408 return 1; 409 return -EINVAL; 410 } 411 412 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 413 struct snd_ctl_elem_value *ucontrol) 414 { 415 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 417 struct wm8996_pdata *pdata = &wm8996->pdata; 418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 419 int value = ucontrol->value.integer.value[0]; 420 421 if (block < 0) 422 return block; 423 424 if (value >= pdata->num_retune_mobile_cfgs) 425 return -EINVAL; 426 427 wm8996->retune_mobile_cfg[block] = value; 428 429 wm8996_set_retune_mobile(codec, block); 430 431 return 0; 432 } 433 434 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 435 struct snd_ctl_elem_value *ucontrol) 436 { 437 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 440 441 if (block < 0) 442 return block; 443 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; 444 445 return 0; 446 } 447 448 static const struct snd_kcontrol_new wm8996_snd_controls[] = { 449 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, 450 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), 451 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, 452 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), 453 454 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, 455 0, 5, 24, 0, sidetone_tlv), 456 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, 457 0, 5, 24, 0, sidetone_tlv), 458 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), 459 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), 460 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), 461 462 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, 463 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 464 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, 465 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 466 467 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, 468 13, 1, 0), 469 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), 470 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), 471 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), 472 473 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, 474 13, 1, 0), 475 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), 476 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), 477 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), 478 479 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, 480 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 481 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), 482 483 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, 484 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 485 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), 486 487 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, 488 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 489 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, 490 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), 491 492 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, 493 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 494 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, 495 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), 496 497 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), 498 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), 499 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), 500 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), 501 502 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), 503 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), 504 505 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), 506 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), 507 508 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, 509 0, threedstereo_tlv), 510 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, 511 0, threedstereo_tlv), 512 513 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, 514 8, 0, out_digital_tlv), 515 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, 516 8, 0, out_digital_tlv), 517 518 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, 519 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), 520 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, 521 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), 522 523 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, 524 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), 525 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, 526 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), 527 528 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, 529 spk_tlv), 530 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, 531 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), 532 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, 533 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), 534 535 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), 536 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), 537 538 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0), 539 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0), 540 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0), 541 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5, 542 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA | 543 WM8996_DSP1TXR_DRC_ENA), 544 545 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0), 546 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0), 547 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0), 548 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5, 549 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA | 550 WM8996_DSP2TXR_DRC_ENA), 551 }; 552 553 static const struct snd_kcontrol_new wm8996_eq_controls[] = { 554 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, 555 eq_tlv), 556 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, 557 eq_tlv), 558 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, 559 eq_tlv), 560 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, 561 eq_tlv), 562 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, 563 eq_tlv), 564 565 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, 566 eq_tlv), 567 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, 568 eq_tlv), 569 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, 570 eq_tlv), 571 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, 572 eq_tlv), 573 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, 574 eq_tlv), 575 }; 576 577 static void wm8996_bg_enable(struct snd_soc_codec *codec) 578 { 579 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 580 581 wm8996->bg_ena++; 582 if (wm8996->bg_ena == 1) { 583 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 584 WM8996_BG_ENA, WM8996_BG_ENA); 585 msleep(2); 586 } 587 } 588 589 static void wm8996_bg_disable(struct snd_soc_codec *codec) 590 { 591 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 592 593 wm8996->bg_ena--; 594 if (!wm8996->bg_ena) 595 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 596 WM8996_BG_ENA, 0); 597 } 598 599 static int bg_event(struct snd_soc_dapm_widget *w, 600 struct snd_kcontrol *kcontrol, int event) 601 { 602 struct snd_soc_codec *codec = w->codec; 603 int ret = 0; 604 605 switch (event) { 606 case SND_SOC_DAPM_PRE_PMU: 607 wm8996_bg_enable(codec); 608 break; 609 case SND_SOC_DAPM_POST_PMD: 610 wm8996_bg_disable(codec); 611 break; 612 default: 613 WARN(1, "Invalid event %d\n", event); 614 ret = -EINVAL; 615 } 616 617 return ret; 618 } 619 620 static int cp_event(struct snd_soc_dapm_widget *w, 621 struct snd_kcontrol *kcontrol, int event) 622 { 623 int ret = 0; 624 625 switch (event) { 626 case SND_SOC_DAPM_POST_PMU: 627 msleep(5); 628 break; 629 default: 630 WARN(1, "Invalid event %d\n", event); 631 ret = -EINVAL; 632 } 633 634 return 0; 635 } 636 637 static int rmv_short_event(struct snd_soc_dapm_widget *w, 638 struct snd_kcontrol *kcontrol, int event) 639 { 640 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 641 642 /* Record which outputs we enabled */ 643 switch (event) { 644 case SND_SOC_DAPM_PRE_PMD: 645 wm8996->hpout_pending &= ~w->shift; 646 break; 647 case SND_SOC_DAPM_PRE_PMU: 648 wm8996->hpout_pending |= w->shift; 649 break; 650 default: 651 WARN(1, "Invalid event %d\n", event); 652 return -EINVAL; 653 } 654 655 return 0; 656 } 657 658 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) 659 { 660 struct i2c_client *i2c = to_i2c_client(codec->dev); 661 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 662 int ret; 663 unsigned long timeout = 200; 664 665 snd_soc_write(codec, WM8996_DC_SERVO_2, mask); 666 667 /* Use the interrupt if possible */ 668 do { 669 if (i2c->irq) { 670 timeout = wait_for_completion_timeout(&wm8996->dcs_done, 671 msecs_to_jiffies(200)); 672 if (timeout == 0) 673 dev_err(codec->dev, "DC servo timed out\n"); 674 675 } else { 676 msleep(1); 677 timeout--; 678 } 679 680 ret = snd_soc_read(codec, WM8996_DC_SERVO_2); 681 dev_dbg(codec->dev, "DC servo state: %x\n", ret); 682 } while (timeout && ret & mask); 683 684 if (timeout == 0) 685 dev_err(codec->dev, "DC servo timed out for %x\n", mask); 686 else 687 dev_dbg(codec->dev, "DC servo complete for %x\n", mask); 688 } 689 690 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, 691 enum snd_soc_dapm_type event, int subseq) 692 { 693 struct snd_soc_codec *codec = container_of(dapm, 694 struct snd_soc_codec, dapm); 695 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 696 u16 val, mask; 697 698 /* Complete any pending DC servo starts */ 699 if (wm8996->dcs_pending) { 700 dev_dbg(codec->dev, "Starting DC servo for %x\n", 701 wm8996->dcs_pending); 702 703 /* Trigger a startup sequence */ 704 wait_for_dc_servo(codec, wm8996->dcs_pending 705 << WM8996_DCS_TRIG_STARTUP_0_SHIFT); 706 707 wm8996->dcs_pending = 0; 708 } 709 710 if (wm8996->hpout_pending != wm8996->hpout_ena) { 711 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", 712 wm8996->hpout_ena, wm8996->hpout_pending); 713 714 val = 0; 715 mask = 0; 716 if (wm8996->hpout_pending & HPOUT1L) { 717 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 718 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 719 } else { 720 mask |= WM8996_HPOUT1L_RMV_SHORT | 721 WM8996_HPOUT1L_OUTP | 722 WM8996_HPOUT1L_DLY; 723 } 724 725 if (wm8996->hpout_pending & HPOUT1R) { 726 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 727 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 728 } else { 729 mask |= WM8996_HPOUT1R_RMV_SHORT | 730 WM8996_HPOUT1R_OUTP | 731 WM8996_HPOUT1R_DLY; 732 } 733 734 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); 735 736 val = 0; 737 mask = 0; 738 if (wm8996->hpout_pending & HPOUT2L) { 739 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 740 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 741 } else { 742 mask |= WM8996_HPOUT2L_RMV_SHORT | 743 WM8996_HPOUT2L_OUTP | 744 WM8996_HPOUT2L_DLY; 745 } 746 747 if (wm8996->hpout_pending & HPOUT2R) { 748 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 749 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 750 } else { 751 mask |= WM8996_HPOUT2R_RMV_SHORT | 752 WM8996_HPOUT2R_OUTP | 753 WM8996_HPOUT2R_DLY; 754 } 755 756 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); 757 758 wm8996->hpout_ena = wm8996->hpout_pending; 759 } 760 } 761 762 static int dcs_start(struct snd_soc_dapm_widget *w, 763 struct snd_kcontrol *kcontrol, int event) 764 { 765 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 766 767 switch (event) { 768 case SND_SOC_DAPM_POST_PMU: 769 wm8996->dcs_pending |= 1 << w->shift; 770 break; 771 default: 772 WARN(1, "Invalid event %d\n", event); 773 return -EINVAL; 774 } 775 776 return 0; 777 } 778 779 static const char *sidetone_text[] = { 780 "IN1", "IN2", 781 }; 782 783 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum, 784 WM8996_SIDETONE, 0, sidetone_text); 785 786 static const struct snd_kcontrol_new left_sidetone = 787 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); 788 789 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum, 790 WM8996_SIDETONE, 1, sidetone_text); 791 792 static const struct snd_kcontrol_new right_sidetone = 793 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); 794 795 static const char *spk_text[] = { 796 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 797 }; 798 799 static SOC_ENUM_SINGLE_DECL(spkl_enum, 800 WM8996_LEFT_PDM_SPEAKER, 0, spk_text); 801 802 static const struct snd_kcontrol_new spkl_mux = 803 SOC_DAPM_ENUM("SPKL", spkl_enum); 804 805 static SOC_ENUM_SINGLE_DECL(spkr_enum, 806 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text); 807 808 static const struct snd_kcontrol_new spkr_mux = 809 SOC_DAPM_ENUM("SPKR", spkr_enum); 810 811 static const char *dsp1rx_text[] = { 812 "AIF1", "AIF2" 813 }; 814 815 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum, 816 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text); 817 818 static const struct snd_kcontrol_new dsp1rx = 819 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 820 821 static const char *dsp2rx_text[] = { 822 "AIF2", "AIF1" 823 }; 824 825 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum, 826 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text); 827 828 static const struct snd_kcontrol_new dsp2rx = 829 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 830 831 static const char *aif2tx_text[] = { 832 "DSP2", "DSP1", "AIF1" 833 }; 834 835 static SOC_ENUM_SINGLE_DECL(aif2tx_enum, 836 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text); 837 838 static const struct snd_kcontrol_new aif2tx = 839 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 840 841 static const char *inmux_text[] = { 842 "ADC", "DMIC1", "DMIC2" 843 }; 844 845 static SOC_ENUM_SINGLE_DECL(in1_enum, 846 WM8996_POWER_MANAGEMENT_7, 0, inmux_text); 847 848 static const struct snd_kcontrol_new in1_mux = 849 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 850 851 static SOC_ENUM_SINGLE_DECL(in2_enum, 852 WM8996_POWER_MANAGEMENT_7, 4, inmux_text); 853 854 static const struct snd_kcontrol_new in2_mux = 855 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 856 857 static const struct snd_kcontrol_new dac2r_mix[] = { 858 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 859 5, 1, 0), 860 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 861 4, 1, 0), 862 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), 863 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), 864 }; 865 866 static const struct snd_kcontrol_new dac2l_mix[] = { 867 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 868 5, 1, 0), 869 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 870 4, 1, 0), 871 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), 872 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), 873 }; 874 875 static const struct snd_kcontrol_new dac1r_mix[] = { 876 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 877 5, 1, 0), 878 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 879 4, 1, 0), 880 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), 881 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), 882 }; 883 884 static const struct snd_kcontrol_new dac1l_mix[] = { 885 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 886 5, 1, 0), 887 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 888 4, 1, 0), 889 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), 890 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), 891 }; 892 893 static const struct snd_kcontrol_new dsp1txl[] = { 894 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 895 1, 1, 0), 896 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 897 0, 1, 0), 898 }; 899 900 static const struct snd_kcontrol_new dsp1txr[] = { 901 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 902 1, 1, 0), 903 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 904 0, 1, 0), 905 }; 906 907 static const struct snd_kcontrol_new dsp2txl[] = { 908 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 909 1, 1, 0), 910 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 911 0, 1, 0), 912 }; 913 914 static const struct snd_kcontrol_new dsp2txr[] = { 915 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 916 1, 1, 0), 917 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 918 0, 1, 0), 919 }; 920 921 922 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { 923 SND_SOC_DAPM_INPUT("IN1LN"), 924 SND_SOC_DAPM_INPUT("IN1LP"), 925 SND_SOC_DAPM_INPUT("IN1RN"), 926 SND_SOC_DAPM_INPUT("IN1RP"), 927 928 SND_SOC_DAPM_INPUT("IN2LN"), 929 SND_SOC_DAPM_INPUT("IN2LP"), 930 SND_SOC_DAPM_INPUT("IN2RN"), 931 SND_SOC_DAPM_INPUT("IN2RP"), 932 933 SND_SOC_DAPM_INPUT("DMIC1DAT"), 934 SND_SOC_DAPM_INPUT("DMIC2DAT"), 935 936 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), 937 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), 938 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), 939 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), 940 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, 941 SND_SOC_DAPM_POST_PMU), 942 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event, 943 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 944 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 945 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), 946 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), 947 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), 948 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), 949 950 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 951 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 952 953 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), 954 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), 955 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), 956 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), 957 958 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), 959 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), 960 961 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), 962 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), 963 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), 964 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), 965 966 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), 967 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), 968 969 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), 970 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), 971 972 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), 973 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), 974 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), 975 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), 976 977 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, 978 dsp2txl, ARRAY_SIZE(dsp2txl)), 979 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, 980 dsp2txr, ARRAY_SIZE(dsp2txr)), 981 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, 982 dsp1txl, ARRAY_SIZE(dsp1txl)), 983 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, 984 dsp1txr, ARRAY_SIZE(dsp1txr)), 985 986 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, 987 dac2l_mix, ARRAY_SIZE(dac2l_mix)), 988 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, 989 dac2r_mix, ARRAY_SIZE(dac2r_mix)), 990 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 991 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 992 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 993 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 994 995 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), 996 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), 997 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), 998 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), 999 1000 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0), 1001 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0), 1002 1003 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0), 1004 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0), 1005 1006 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0), 1007 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0), 1008 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0), 1009 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0), 1010 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0), 1011 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0), 1012 1013 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0), 1014 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0), 1015 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0), 1016 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0), 1017 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0), 1018 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0), 1019 1020 /* We route as stereo pairs so define some dummy widgets to squash 1021 * things down for now. RXA = 0,1, RXB = 2,3 and so on */ 1022 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), 1024 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), 1025 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), 1026 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), 1027 1028 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), 1029 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), 1030 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), 1031 1032 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), 1033 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), 1034 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), 1035 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), 1036 1037 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), 1038 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), 1039 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, 1040 SND_SOC_DAPM_POST_PMU), 1041 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, 1042 rmv_short_event, 1043 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1044 1045 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), 1046 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), 1047 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, 1048 SND_SOC_DAPM_POST_PMU), 1049 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, 1050 rmv_short_event, 1051 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1052 1053 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 1054 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), 1055 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, 1056 SND_SOC_DAPM_POST_PMU), 1057 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, 1058 rmv_short_event, 1059 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1060 1061 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 1062 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), 1063 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, 1064 SND_SOC_DAPM_POST_PMU), 1065 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, 1066 rmv_short_event, 1067 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1068 1069 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1070 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1071 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1072 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1073 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1074 }; 1075 1076 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { 1077 { "AIFCLK", NULL, "SYSCLK" }, 1078 { "SYSDSPCLK", NULL, "SYSCLK" }, 1079 { "Charge Pump", NULL, "SYSCLK" }, 1080 { "Charge Pump", NULL, "CPVDD" }, 1081 1082 { "MICB1", NULL, "LDO2" }, 1083 { "MICB1", NULL, "MICB1 Audio" }, 1084 { "MICB1", NULL, "Bandgap" }, 1085 { "MICB2", NULL, "LDO2" }, 1086 { "MICB2", NULL, "MICB2 Audio" }, 1087 { "MICB2", NULL, "Bandgap" }, 1088 1089 { "AIF1RX0", NULL, "AIF1 Playback" }, 1090 { "AIF1RX1", NULL, "AIF1 Playback" }, 1091 { "AIF1RX2", NULL, "AIF1 Playback" }, 1092 { "AIF1RX3", NULL, "AIF1 Playback" }, 1093 { "AIF1RX4", NULL, "AIF1 Playback" }, 1094 { "AIF1RX5", NULL, "AIF1 Playback" }, 1095 1096 { "AIF2RX0", NULL, "AIF2 Playback" }, 1097 { "AIF2RX1", NULL, "AIF2 Playback" }, 1098 1099 { "AIF1 Capture", NULL, "AIF1TX0" }, 1100 { "AIF1 Capture", NULL, "AIF1TX1" }, 1101 { "AIF1 Capture", NULL, "AIF1TX2" }, 1102 { "AIF1 Capture", NULL, "AIF1TX3" }, 1103 { "AIF1 Capture", NULL, "AIF1TX4" }, 1104 { "AIF1 Capture", NULL, "AIF1TX5" }, 1105 1106 { "AIF2 Capture", NULL, "AIF2TX0" }, 1107 { "AIF2 Capture", NULL, "AIF2TX1" }, 1108 1109 { "IN1L PGA", NULL, "IN2LN" }, 1110 { "IN1L PGA", NULL, "IN2LP" }, 1111 { "IN1L PGA", NULL, "IN1LN" }, 1112 { "IN1L PGA", NULL, "IN1LP" }, 1113 { "IN1L PGA", NULL, "Bandgap" }, 1114 1115 { "IN1R PGA", NULL, "IN2RN" }, 1116 { "IN1R PGA", NULL, "IN2RP" }, 1117 { "IN1R PGA", NULL, "IN1RN" }, 1118 { "IN1R PGA", NULL, "IN1RP" }, 1119 { "IN1R PGA", NULL, "Bandgap" }, 1120 1121 { "ADCL", NULL, "IN1L PGA" }, 1122 1123 { "ADCR", NULL, "IN1R PGA" }, 1124 1125 { "DMIC1L", NULL, "DMIC1DAT" }, 1126 { "DMIC1R", NULL, "DMIC1DAT" }, 1127 { "DMIC2L", NULL, "DMIC2DAT" }, 1128 { "DMIC2R", NULL, "DMIC2DAT" }, 1129 1130 { "DMIC2L", NULL, "DMIC2" }, 1131 { "DMIC2R", NULL, "DMIC2" }, 1132 { "DMIC1L", NULL, "DMIC1" }, 1133 { "DMIC1R", NULL, "DMIC1" }, 1134 1135 { "IN1L Mux", "ADC", "ADCL" }, 1136 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1137 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1138 1139 { "IN1R Mux", "ADC", "ADCR" }, 1140 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1141 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1142 1143 { "IN2L Mux", "ADC", "ADCL" }, 1144 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1145 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1146 1147 { "IN2R Mux", "ADC", "ADCR" }, 1148 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1149 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1150 1151 { "Left Sidetone", "IN1", "IN1L Mux" }, 1152 { "Left Sidetone", "IN2", "IN2L Mux" }, 1153 1154 { "Right Sidetone", "IN1", "IN1R Mux" }, 1155 { "Right Sidetone", "IN2", "IN2R Mux" }, 1156 1157 { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, 1158 { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, 1159 1160 { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, 1161 { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, 1162 1163 { "AIF1TX0", NULL, "DSP1TXL" }, 1164 { "AIF1TX1", NULL, "DSP1TXR" }, 1165 { "AIF1TX2", NULL, "DSP2TXL" }, 1166 { "AIF1TX3", NULL, "DSP2TXR" }, 1167 { "AIF1TX4", NULL, "AIF2RX0" }, 1168 { "AIF1TX5", NULL, "AIF2RX1" }, 1169 1170 { "AIF1RX0", NULL, "AIFCLK" }, 1171 { "AIF1RX1", NULL, "AIFCLK" }, 1172 { "AIF1RX2", NULL, "AIFCLK" }, 1173 { "AIF1RX3", NULL, "AIFCLK" }, 1174 { "AIF1RX4", NULL, "AIFCLK" }, 1175 { "AIF1RX5", NULL, "AIFCLK" }, 1176 1177 { "AIF2RX0", NULL, "AIFCLK" }, 1178 { "AIF2RX1", NULL, "AIFCLK" }, 1179 1180 { "AIF1TX0", NULL, "AIFCLK" }, 1181 { "AIF1TX1", NULL, "AIFCLK" }, 1182 { "AIF1TX2", NULL, "AIFCLK" }, 1183 { "AIF1TX3", NULL, "AIFCLK" }, 1184 { "AIF1TX4", NULL, "AIFCLK" }, 1185 { "AIF1TX5", NULL, "AIFCLK" }, 1186 1187 { "AIF2TX0", NULL, "AIFCLK" }, 1188 { "AIF2TX1", NULL, "AIFCLK" }, 1189 1190 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1191 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1192 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1193 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1194 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1195 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1196 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1197 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1198 1199 { "AIF1RXA", NULL, "AIF1RX0" }, 1200 { "AIF1RXA", NULL, "AIF1RX1" }, 1201 { "AIF1RXB", NULL, "AIF1RX2" }, 1202 { "AIF1RXB", NULL, "AIF1RX3" }, 1203 { "AIF1RXC", NULL, "AIF1RX4" }, 1204 { "AIF1RXC", NULL, "AIF1RX5" }, 1205 1206 { "AIF2RX", NULL, "AIF2RX0" }, 1207 { "AIF2RX", NULL, "AIF2RX1" }, 1208 1209 { "AIF2TX", "DSP2", "DSP2TX" }, 1210 { "AIF2TX", "DSP1", "DSP1RX" }, 1211 { "AIF2TX", "AIF1", "AIF1RXC" }, 1212 1213 { "DSP1RXL", NULL, "DSP1RX" }, 1214 { "DSP1RXR", NULL, "DSP1RX" }, 1215 { "DSP2RXL", NULL, "DSP2RX" }, 1216 { "DSP2RXR", NULL, "DSP2RX" }, 1217 1218 { "DSP2TX", NULL, "DSP2TXL" }, 1219 { "DSP2TX", NULL, "DSP2TXR" }, 1220 1221 { "DSP1RX", "AIF1", "AIF1RXA" }, 1222 { "DSP1RX", "AIF2", "AIF2RX" }, 1223 1224 { "DSP2RX", "AIF1", "AIF1RXB" }, 1225 { "DSP2RX", "AIF2", "AIF2RX" }, 1226 1227 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, 1228 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, 1229 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1230 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1231 1232 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, 1233 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, 1234 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1235 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1236 1237 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, 1238 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, 1239 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1240 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1241 1242 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, 1243 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, 1244 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1245 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1246 1247 { "DAC1L", NULL, "DAC1L Mixer" }, 1248 { "DAC1R", NULL, "DAC1R Mixer" }, 1249 { "DAC2L", NULL, "DAC2L Mixer" }, 1250 { "DAC2R", NULL, "DAC2R Mixer" }, 1251 1252 { "HPOUT2L PGA", NULL, "Charge Pump" }, 1253 { "HPOUT2L PGA", NULL, "Bandgap" }, 1254 { "HPOUT2L PGA", NULL, "DAC2L" }, 1255 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, 1256 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, 1257 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" }, 1258 1259 { "HPOUT2R PGA", NULL, "Charge Pump" }, 1260 { "HPOUT2R PGA", NULL, "Bandgap" }, 1261 { "HPOUT2R PGA", NULL, "DAC2R" }, 1262 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, 1263 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, 1264 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" }, 1265 1266 { "HPOUT1L PGA", NULL, "Charge Pump" }, 1267 { "HPOUT1L PGA", NULL, "Bandgap" }, 1268 { "HPOUT1L PGA", NULL, "DAC1L" }, 1269 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, 1270 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, 1271 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" }, 1272 1273 { "HPOUT1R PGA", NULL, "Charge Pump" }, 1274 { "HPOUT1R PGA", NULL, "Bandgap" }, 1275 { "HPOUT1R PGA", NULL, "DAC1R" }, 1276 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, 1277 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, 1278 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" }, 1279 1280 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, 1281 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, 1282 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, 1283 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, 1284 1285 { "SPKL", "DAC1L", "DAC1L" }, 1286 { "SPKL", "DAC1R", "DAC1R" }, 1287 { "SPKL", "DAC2L", "DAC2L" }, 1288 { "SPKL", "DAC2R", "DAC2R" }, 1289 1290 { "SPKR", "DAC1L", "DAC1L" }, 1291 { "SPKR", "DAC1R", "DAC1R" }, 1292 { "SPKR", "DAC2L", "DAC2L" }, 1293 { "SPKR", "DAC2R", "DAC2R" }, 1294 1295 { "SPKL PGA", NULL, "SPKL" }, 1296 { "SPKR PGA", NULL, "SPKR" }, 1297 1298 { "SPKDAT", NULL, "SPKL PGA" }, 1299 { "SPKDAT", NULL, "SPKR PGA" }, 1300 }; 1301 1302 static bool wm8996_readable_register(struct device *dev, unsigned int reg) 1303 { 1304 /* Due to the sparseness of the register map the compiler 1305 * output from an explicit switch statement ends up being much 1306 * more efficient than a table. 1307 */ 1308 switch (reg) { 1309 case WM8996_SOFTWARE_RESET: 1310 case WM8996_POWER_MANAGEMENT_1: 1311 case WM8996_POWER_MANAGEMENT_2: 1312 case WM8996_POWER_MANAGEMENT_3: 1313 case WM8996_POWER_MANAGEMENT_4: 1314 case WM8996_POWER_MANAGEMENT_5: 1315 case WM8996_POWER_MANAGEMENT_6: 1316 case WM8996_POWER_MANAGEMENT_7: 1317 case WM8996_POWER_MANAGEMENT_8: 1318 case WM8996_LEFT_LINE_INPUT_VOLUME: 1319 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1320 case WM8996_LINE_INPUT_CONTROL: 1321 case WM8996_DAC1_HPOUT1_VOLUME: 1322 case WM8996_DAC2_HPOUT2_VOLUME: 1323 case WM8996_DAC1_LEFT_VOLUME: 1324 case WM8996_DAC1_RIGHT_VOLUME: 1325 case WM8996_DAC2_LEFT_VOLUME: 1326 case WM8996_DAC2_RIGHT_VOLUME: 1327 case WM8996_OUTPUT1_LEFT_VOLUME: 1328 case WM8996_OUTPUT1_RIGHT_VOLUME: 1329 case WM8996_OUTPUT2_LEFT_VOLUME: 1330 case WM8996_OUTPUT2_RIGHT_VOLUME: 1331 case WM8996_MICBIAS_1: 1332 case WM8996_MICBIAS_2: 1333 case WM8996_LDO_1: 1334 case WM8996_LDO_2: 1335 case WM8996_ACCESSORY_DETECT_MODE_1: 1336 case WM8996_ACCESSORY_DETECT_MODE_2: 1337 case WM8996_HEADPHONE_DETECT_1: 1338 case WM8996_HEADPHONE_DETECT_2: 1339 case WM8996_MIC_DETECT_1: 1340 case WM8996_MIC_DETECT_2: 1341 case WM8996_MIC_DETECT_3: 1342 case WM8996_CHARGE_PUMP_1: 1343 case WM8996_CHARGE_PUMP_2: 1344 case WM8996_DC_SERVO_1: 1345 case WM8996_DC_SERVO_2: 1346 case WM8996_DC_SERVO_3: 1347 case WM8996_DC_SERVO_5: 1348 case WM8996_DC_SERVO_6: 1349 case WM8996_DC_SERVO_7: 1350 case WM8996_DC_SERVO_READBACK_0: 1351 case WM8996_ANALOGUE_HP_1: 1352 case WM8996_ANALOGUE_HP_2: 1353 case WM8996_CHIP_REVISION: 1354 case WM8996_CONTROL_INTERFACE_1: 1355 case WM8996_WRITE_SEQUENCER_CTRL_1: 1356 case WM8996_WRITE_SEQUENCER_CTRL_2: 1357 case WM8996_AIF_CLOCKING_1: 1358 case WM8996_AIF_CLOCKING_2: 1359 case WM8996_CLOCKING_1: 1360 case WM8996_CLOCKING_2: 1361 case WM8996_AIF_RATE: 1362 case WM8996_FLL_CONTROL_1: 1363 case WM8996_FLL_CONTROL_2: 1364 case WM8996_FLL_CONTROL_3: 1365 case WM8996_FLL_CONTROL_4: 1366 case WM8996_FLL_CONTROL_5: 1367 case WM8996_FLL_CONTROL_6: 1368 case WM8996_FLL_EFS_1: 1369 case WM8996_FLL_EFS_2: 1370 case WM8996_AIF1_CONTROL: 1371 case WM8996_AIF1_BCLK: 1372 case WM8996_AIF1_TX_LRCLK_1: 1373 case WM8996_AIF1_TX_LRCLK_2: 1374 case WM8996_AIF1_RX_LRCLK_1: 1375 case WM8996_AIF1_RX_LRCLK_2: 1376 case WM8996_AIF1TX_DATA_CONFIGURATION_1: 1377 case WM8996_AIF1TX_DATA_CONFIGURATION_2: 1378 case WM8996_AIF1RX_DATA_CONFIGURATION: 1379 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: 1380 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: 1381 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: 1382 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: 1383 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: 1384 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: 1385 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: 1386 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: 1387 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: 1388 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: 1389 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: 1390 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: 1391 case WM8996_AIF1RX_MONO_CONFIGURATION: 1392 case WM8996_AIF1TX_TEST: 1393 case WM8996_AIF2_CONTROL: 1394 case WM8996_AIF2_BCLK: 1395 case WM8996_AIF2_TX_LRCLK_1: 1396 case WM8996_AIF2_TX_LRCLK_2: 1397 case WM8996_AIF2_RX_LRCLK_1: 1398 case WM8996_AIF2_RX_LRCLK_2: 1399 case WM8996_AIF2TX_DATA_CONFIGURATION_1: 1400 case WM8996_AIF2TX_DATA_CONFIGURATION_2: 1401 case WM8996_AIF2RX_DATA_CONFIGURATION: 1402 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: 1403 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: 1404 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: 1405 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: 1406 case WM8996_AIF2RX_MONO_CONFIGURATION: 1407 case WM8996_AIF2TX_TEST: 1408 case WM8996_DSP1_TX_LEFT_VOLUME: 1409 case WM8996_DSP1_TX_RIGHT_VOLUME: 1410 case WM8996_DSP1_RX_LEFT_VOLUME: 1411 case WM8996_DSP1_RX_RIGHT_VOLUME: 1412 case WM8996_DSP1_TX_FILTERS: 1413 case WM8996_DSP1_RX_FILTERS_1: 1414 case WM8996_DSP1_RX_FILTERS_2: 1415 case WM8996_DSP1_DRC_1: 1416 case WM8996_DSP1_DRC_2: 1417 case WM8996_DSP1_DRC_3: 1418 case WM8996_DSP1_DRC_4: 1419 case WM8996_DSP1_DRC_5: 1420 case WM8996_DSP1_RX_EQ_GAINS_1: 1421 case WM8996_DSP1_RX_EQ_GAINS_2: 1422 case WM8996_DSP1_RX_EQ_BAND_1_A: 1423 case WM8996_DSP1_RX_EQ_BAND_1_B: 1424 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1425 case WM8996_DSP1_RX_EQ_BAND_2_A: 1426 case WM8996_DSP1_RX_EQ_BAND_2_B: 1427 case WM8996_DSP1_RX_EQ_BAND_2_C: 1428 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1429 case WM8996_DSP1_RX_EQ_BAND_3_A: 1430 case WM8996_DSP1_RX_EQ_BAND_3_B: 1431 case WM8996_DSP1_RX_EQ_BAND_3_C: 1432 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1433 case WM8996_DSP1_RX_EQ_BAND_4_A: 1434 case WM8996_DSP1_RX_EQ_BAND_4_B: 1435 case WM8996_DSP1_RX_EQ_BAND_4_C: 1436 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1437 case WM8996_DSP1_RX_EQ_BAND_5_A: 1438 case WM8996_DSP1_RX_EQ_BAND_5_B: 1439 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1440 case WM8996_DSP2_TX_LEFT_VOLUME: 1441 case WM8996_DSP2_TX_RIGHT_VOLUME: 1442 case WM8996_DSP2_RX_LEFT_VOLUME: 1443 case WM8996_DSP2_RX_RIGHT_VOLUME: 1444 case WM8996_DSP2_TX_FILTERS: 1445 case WM8996_DSP2_RX_FILTERS_1: 1446 case WM8996_DSP2_RX_FILTERS_2: 1447 case WM8996_DSP2_DRC_1: 1448 case WM8996_DSP2_DRC_2: 1449 case WM8996_DSP2_DRC_3: 1450 case WM8996_DSP2_DRC_4: 1451 case WM8996_DSP2_DRC_5: 1452 case WM8996_DSP2_RX_EQ_GAINS_1: 1453 case WM8996_DSP2_RX_EQ_GAINS_2: 1454 case WM8996_DSP2_RX_EQ_BAND_1_A: 1455 case WM8996_DSP2_RX_EQ_BAND_1_B: 1456 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1457 case WM8996_DSP2_RX_EQ_BAND_2_A: 1458 case WM8996_DSP2_RX_EQ_BAND_2_B: 1459 case WM8996_DSP2_RX_EQ_BAND_2_C: 1460 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1461 case WM8996_DSP2_RX_EQ_BAND_3_A: 1462 case WM8996_DSP2_RX_EQ_BAND_3_B: 1463 case WM8996_DSP2_RX_EQ_BAND_3_C: 1464 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1465 case WM8996_DSP2_RX_EQ_BAND_4_A: 1466 case WM8996_DSP2_RX_EQ_BAND_4_B: 1467 case WM8996_DSP2_RX_EQ_BAND_4_C: 1468 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1469 case WM8996_DSP2_RX_EQ_BAND_5_A: 1470 case WM8996_DSP2_RX_EQ_BAND_5_B: 1471 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1472 case WM8996_DAC1_MIXER_VOLUMES: 1473 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1474 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1475 case WM8996_DAC2_MIXER_VOLUMES: 1476 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1477 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1478 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: 1479 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: 1480 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: 1481 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: 1482 case WM8996_DSP_TX_MIXER_SELECT: 1483 case WM8996_DAC_SOFTMUTE: 1484 case WM8996_OVERSAMPLING: 1485 case WM8996_SIDETONE: 1486 case WM8996_GPIO_1: 1487 case WM8996_GPIO_2: 1488 case WM8996_GPIO_3: 1489 case WM8996_GPIO_4: 1490 case WM8996_GPIO_5: 1491 case WM8996_PULL_CONTROL_1: 1492 case WM8996_PULL_CONTROL_2: 1493 case WM8996_INTERRUPT_STATUS_1: 1494 case WM8996_INTERRUPT_STATUS_2: 1495 case WM8996_INTERRUPT_RAW_STATUS_2: 1496 case WM8996_INTERRUPT_STATUS_1_MASK: 1497 case WM8996_INTERRUPT_STATUS_2_MASK: 1498 case WM8996_INTERRUPT_CONTROL: 1499 case WM8996_LEFT_PDM_SPEAKER: 1500 case WM8996_RIGHT_PDM_SPEAKER: 1501 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: 1502 case WM8996_PDM_SPEAKER_VOLUME: 1503 return 1; 1504 default: 1505 return 0; 1506 } 1507 } 1508 1509 static bool wm8996_volatile_register(struct device *dev, unsigned int reg) 1510 { 1511 switch (reg) { 1512 case WM8996_SOFTWARE_RESET: 1513 case WM8996_CHIP_REVISION: 1514 case WM8996_LDO_1: 1515 case WM8996_LDO_2: 1516 case WM8996_INTERRUPT_STATUS_1: 1517 case WM8996_INTERRUPT_STATUS_2: 1518 case WM8996_INTERRUPT_RAW_STATUS_2: 1519 case WM8996_DC_SERVO_READBACK_0: 1520 case WM8996_DC_SERVO_2: 1521 case WM8996_DC_SERVO_6: 1522 case WM8996_DC_SERVO_7: 1523 case WM8996_FLL_CONTROL_6: 1524 case WM8996_MIC_DETECT_3: 1525 case WM8996_HEADPHONE_DETECT_1: 1526 case WM8996_HEADPHONE_DETECT_2: 1527 return 1; 1528 default: 1529 return 0; 1530 } 1531 } 1532 1533 static const int bclk_divs[] = { 1534 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 1535 }; 1536 1537 static void wm8996_update_bclk(struct snd_soc_codec *codec) 1538 { 1539 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1540 int aif, best, cur_val, bclk_rate, bclk_reg, i; 1541 1542 /* Don't bother if we're in a low frequency idle mode that 1543 * can't support audio. 1544 */ 1545 if (wm8996->sysclk < 64000) 1546 return; 1547 1548 for (aif = 0; aif < WM8996_AIFS; aif++) { 1549 switch (aif) { 1550 case 0: 1551 bclk_reg = WM8996_AIF1_BCLK; 1552 break; 1553 case 1: 1554 bclk_reg = WM8996_AIF2_BCLK; 1555 break; 1556 } 1557 1558 bclk_rate = wm8996->bclk_rate[aif]; 1559 1560 /* Pick a divisor for BCLK as close as we can get to ideal */ 1561 best = 0; 1562 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1563 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; 1564 if (cur_val < 0) /* BCLK table is sorted */ 1565 break; 1566 best = i; 1567 } 1568 bclk_rate = wm8996->sysclk / bclk_divs[best]; 1569 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1570 bclk_divs[best], bclk_rate); 1571 1572 snd_soc_update_bits(codec, bclk_reg, 1573 WM8996_AIF1_BCLK_DIV_MASK, best); 1574 } 1575 } 1576 1577 static int wm8996_set_bias_level(struct snd_soc_codec *codec, 1578 enum snd_soc_bias_level level) 1579 { 1580 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1581 int ret; 1582 1583 switch (level) { 1584 case SND_SOC_BIAS_ON: 1585 break; 1586 case SND_SOC_BIAS_PREPARE: 1587 /* Put the MICBIASes into regulating mode */ 1588 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1589 WM8996_MICB1_MODE, 0); 1590 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1591 WM8996_MICB2_MODE, 0); 1592 break; 1593 1594 case SND_SOC_BIAS_STANDBY: 1595 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1596 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 1597 wm8996->supplies); 1598 if (ret != 0) { 1599 dev_err(codec->dev, 1600 "Failed to enable supplies: %d\n", 1601 ret); 1602 return ret; 1603 } 1604 1605 if (wm8996->pdata.ldo_ena >= 0) { 1606 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1607 1); 1608 msleep(5); 1609 } 1610 1611 regcache_cache_only(wm8996->regmap, false); 1612 regcache_sync(wm8996->regmap); 1613 } 1614 1615 /* Bypass the MICBIASes for lowest power */ 1616 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1617 WM8996_MICB1_MODE, WM8996_MICB1_MODE); 1618 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1619 WM8996_MICB2_MODE, WM8996_MICB2_MODE); 1620 break; 1621 1622 case SND_SOC_BIAS_OFF: 1623 regcache_cache_only(wm8996->regmap, true); 1624 if (wm8996->pdata.ldo_ena >= 0) { 1625 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1626 regcache_cache_only(wm8996->regmap, true); 1627 } 1628 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), 1629 wm8996->supplies); 1630 break; 1631 } 1632 1633 codec->dapm.bias_level = level; 1634 1635 return 0; 1636 } 1637 1638 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1639 { 1640 struct snd_soc_codec *codec = dai->codec; 1641 int aifctrl = 0; 1642 int bclk = 0; 1643 int lrclk_tx = 0; 1644 int lrclk_rx = 0; 1645 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; 1646 1647 switch (dai->id) { 1648 case 0: 1649 aifctrl_reg = WM8996_AIF1_CONTROL; 1650 bclk_reg = WM8996_AIF1_BCLK; 1651 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; 1652 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; 1653 break; 1654 case 1: 1655 aifctrl_reg = WM8996_AIF2_CONTROL; 1656 bclk_reg = WM8996_AIF2_BCLK; 1657 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; 1658 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; 1659 break; 1660 default: 1661 WARN(1, "Invalid dai id %d\n", dai->id); 1662 return -EINVAL; 1663 } 1664 1665 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1666 case SND_SOC_DAIFMT_NB_NF: 1667 break; 1668 case SND_SOC_DAIFMT_IB_NF: 1669 bclk |= WM8996_AIF1_BCLK_INV; 1670 break; 1671 case SND_SOC_DAIFMT_NB_IF: 1672 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1673 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1674 break; 1675 case SND_SOC_DAIFMT_IB_IF: 1676 bclk |= WM8996_AIF1_BCLK_INV; 1677 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1678 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1679 break; 1680 } 1681 1682 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1683 case SND_SOC_DAIFMT_CBS_CFS: 1684 break; 1685 case SND_SOC_DAIFMT_CBS_CFM: 1686 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1687 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1688 break; 1689 case SND_SOC_DAIFMT_CBM_CFS: 1690 bclk |= WM8996_AIF1_BCLK_MSTR; 1691 break; 1692 case SND_SOC_DAIFMT_CBM_CFM: 1693 bclk |= WM8996_AIF1_BCLK_MSTR; 1694 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1695 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1696 break; 1697 default: 1698 return -EINVAL; 1699 } 1700 1701 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1702 case SND_SOC_DAIFMT_DSP_A: 1703 break; 1704 case SND_SOC_DAIFMT_DSP_B: 1705 aifctrl |= 1; 1706 break; 1707 case SND_SOC_DAIFMT_I2S: 1708 aifctrl |= 2; 1709 break; 1710 case SND_SOC_DAIFMT_LEFT_J: 1711 aifctrl |= 3; 1712 break; 1713 default: 1714 return -EINVAL; 1715 } 1716 1717 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); 1718 snd_soc_update_bits(codec, bclk_reg, 1719 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, 1720 bclk); 1721 snd_soc_update_bits(codec, lrclk_tx_reg, 1722 WM8996_AIF1TX_LRCLK_INV | 1723 WM8996_AIF1TX_LRCLK_MSTR, 1724 lrclk_tx); 1725 snd_soc_update_bits(codec, lrclk_rx_reg, 1726 WM8996_AIF1RX_LRCLK_INV | 1727 WM8996_AIF1RX_LRCLK_MSTR, 1728 lrclk_rx); 1729 1730 return 0; 1731 } 1732 1733 static const int dsp_divs[] = { 1734 48000, 32000, 16000, 8000 1735 }; 1736 1737 static int wm8996_hw_params(struct snd_pcm_substream *substream, 1738 struct snd_pcm_hw_params *params, 1739 struct snd_soc_dai *dai) 1740 { 1741 struct snd_soc_codec *codec = dai->codec; 1742 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1743 int bits, i, bclk_rate, best; 1744 int aifdata = 0; 1745 int lrclk = 0; 1746 int dsp = 0; 1747 int aifdata_reg, lrclk_reg, dsp_shift; 1748 1749 switch (dai->id) { 1750 case 0: 1751 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1752 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { 1753 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; 1754 lrclk_reg = WM8996_AIF1_RX_LRCLK_1; 1755 } else { 1756 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; 1757 lrclk_reg = WM8996_AIF1_TX_LRCLK_1; 1758 } 1759 dsp_shift = 0; 1760 break; 1761 case 1: 1762 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1763 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { 1764 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; 1765 lrclk_reg = WM8996_AIF2_RX_LRCLK_1; 1766 } else { 1767 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; 1768 lrclk_reg = WM8996_AIF2_TX_LRCLK_1; 1769 } 1770 dsp_shift = WM8996_DSP2_DIV_SHIFT; 1771 break; 1772 default: 1773 WARN(1, "Invalid dai id %d\n", dai->id); 1774 return -EINVAL; 1775 } 1776 1777 bclk_rate = snd_soc_params_to_bclk(params); 1778 if (bclk_rate < 0) { 1779 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); 1780 return bclk_rate; 1781 } 1782 1783 wm8996->bclk_rate[dai->id] = bclk_rate; 1784 wm8996->rx_rate[dai->id] = params_rate(params); 1785 1786 /* Needs looking at for TDM */ 1787 bits = snd_pcm_format_width(params_format(params)); 1788 if (bits < 0) 1789 return bits; 1790 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; 1791 1792 best = 0; 1793 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { 1794 if (abs(dsp_divs[i] - params_rate(params)) < 1795 abs(dsp_divs[best] - params_rate(params))) 1796 best = i; 1797 } 1798 dsp |= i << dsp_shift; 1799 1800 wm8996_update_bclk(codec); 1801 1802 lrclk = bclk_rate / params_rate(params); 1803 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1804 lrclk, bclk_rate / lrclk); 1805 1806 snd_soc_update_bits(codec, aifdata_reg, 1807 WM8996_AIF1TX_WL_MASK | 1808 WM8996_AIF1TX_SLOT_LEN_MASK, 1809 aifdata); 1810 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, 1811 lrclk); 1812 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, 1813 WM8996_DSP1_DIV_MASK << dsp_shift, dsp); 1814 1815 return 0; 1816 } 1817 1818 static int wm8996_set_sysclk(struct snd_soc_dai *dai, 1819 int clk_id, unsigned int freq, int dir) 1820 { 1821 struct snd_soc_codec *codec = dai->codec; 1822 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1823 int lfclk = 0; 1824 int ratediv = 0; 1825 int sync = WM8996_REG_SYNC; 1826 int src; 1827 int old; 1828 1829 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) 1830 return 0; 1831 1832 /* Disable SYSCLK while we reconfigure */ 1833 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; 1834 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1835 WM8996_SYSCLK_ENA, 0); 1836 1837 switch (clk_id) { 1838 case WM8996_SYSCLK_MCLK1: 1839 wm8996->sysclk = freq; 1840 src = 0; 1841 break; 1842 case WM8996_SYSCLK_MCLK2: 1843 wm8996->sysclk = freq; 1844 src = 1; 1845 break; 1846 case WM8996_SYSCLK_FLL: 1847 wm8996->sysclk = freq; 1848 src = 2; 1849 break; 1850 default: 1851 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); 1852 return -EINVAL; 1853 } 1854 1855 switch (wm8996->sysclk) { 1856 case 5644800: 1857 case 6144000: 1858 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1859 WM8996_SYSCLK_RATE, 0); 1860 break; 1861 case 22579200: 1862 case 24576000: 1863 ratediv = WM8996_SYSCLK_DIV; 1864 wm8996->sysclk /= 2; 1865 case 11289600: 1866 case 12288000: 1867 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1868 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); 1869 break; 1870 case 32000: 1871 case 32768: 1872 lfclk = WM8996_LFCLK_ENA; 1873 sync = 0; 1874 break; 1875 default: 1876 dev_warn(codec->dev, "Unsupported clock rate %dHz\n", 1877 wm8996->sysclk); 1878 return -EINVAL; 1879 } 1880 1881 wm8996_update_bclk(codec); 1882 1883 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1884 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, 1885 src << WM8996_SYSCLK_SRC_SHIFT | ratediv); 1886 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); 1887 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1, 1888 WM8996_REG_SYNC, sync); 1889 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1890 WM8996_SYSCLK_ENA, old); 1891 1892 wm8996->sysclk_src = clk_id; 1893 1894 return 0; 1895 } 1896 1897 struct _fll_div { 1898 u16 fll_fratio; 1899 u16 fll_outdiv; 1900 u16 fll_refclk_div; 1901 u16 fll_loop_gain; 1902 u16 fll_ref_freq; 1903 u16 n; 1904 u16 theta; 1905 u16 lambda; 1906 }; 1907 1908 static struct { 1909 unsigned int min; 1910 unsigned int max; 1911 u16 fll_fratio; 1912 int ratio; 1913 } fll_fratios[] = { 1914 { 0, 64000, 4, 16 }, 1915 { 64000, 128000, 3, 8 }, 1916 { 128000, 256000, 2, 4 }, 1917 { 256000, 1000000, 1, 2 }, 1918 { 1000000, 13500000, 0, 1 }, 1919 }; 1920 1921 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1922 unsigned int Fout) 1923 { 1924 unsigned int target; 1925 unsigned int div; 1926 unsigned int fratio, gcd_fll; 1927 int i; 1928 1929 /* Fref must be <=13.5MHz */ 1930 div = 1; 1931 fll_div->fll_refclk_div = 0; 1932 while ((Fref / div) > 13500000) { 1933 div *= 2; 1934 fll_div->fll_refclk_div++; 1935 1936 if (div > 8) { 1937 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1938 Fref); 1939 return -EINVAL; 1940 } 1941 } 1942 1943 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 1944 1945 /* Apply the division for our remaining calculations */ 1946 Fref /= div; 1947 1948 if (Fref >= 3000000) 1949 fll_div->fll_loop_gain = 5; 1950 else 1951 fll_div->fll_loop_gain = 0; 1952 1953 if (Fref >= 48000) 1954 fll_div->fll_ref_freq = 0; 1955 else 1956 fll_div->fll_ref_freq = 1; 1957 1958 /* Fvco should be 90-100MHz; don't check the upper bound */ 1959 div = 2; 1960 while (Fout * div < 90000000) { 1961 div++; 1962 if (div > 64) { 1963 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1964 Fout); 1965 return -EINVAL; 1966 } 1967 } 1968 target = Fout * div; 1969 fll_div->fll_outdiv = div - 1; 1970 1971 pr_debug("FLL Fvco=%dHz\n", target); 1972 1973 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1974 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1975 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1976 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1977 fratio = fll_fratios[i].ratio; 1978 break; 1979 } 1980 } 1981 if (i == ARRAY_SIZE(fll_fratios)) { 1982 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1983 return -EINVAL; 1984 } 1985 1986 fll_div->n = target / (fratio * Fref); 1987 1988 if (target % Fref == 0) { 1989 fll_div->theta = 0; 1990 fll_div->lambda = 0; 1991 } else { 1992 gcd_fll = gcd(target, fratio * Fref); 1993 1994 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 1995 / gcd_fll; 1996 fll_div->lambda = (fratio * Fref) / gcd_fll; 1997 } 1998 1999 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 2000 fll_div->n, fll_div->theta, fll_div->lambda); 2001 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 2002 fll_div->fll_fratio, fll_div->fll_outdiv, 2003 fll_div->fll_refclk_div); 2004 2005 return 0; 2006 } 2007 2008 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 2009 unsigned int Fref, unsigned int Fout) 2010 { 2011 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2012 struct i2c_client *i2c = to_i2c_client(codec->dev); 2013 struct _fll_div fll_div; 2014 unsigned long timeout; 2015 int ret, reg, retry; 2016 2017 /* Any change? */ 2018 if (source == wm8996->fll_src && Fref == wm8996->fll_fref && 2019 Fout == wm8996->fll_fout) 2020 return 0; 2021 2022 if (Fout == 0) { 2023 dev_dbg(codec->dev, "FLL disabled\n"); 2024 2025 wm8996->fll_fref = 0; 2026 wm8996->fll_fout = 0; 2027 2028 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2029 WM8996_FLL_ENA, 0); 2030 2031 wm8996_bg_disable(codec); 2032 2033 return 0; 2034 } 2035 2036 ret = fll_factors(&fll_div, Fref, Fout); 2037 if (ret != 0) 2038 return ret; 2039 2040 switch (source) { 2041 case WM8996_FLL_MCLK1: 2042 reg = 0; 2043 break; 2044 case WM8996_FLL_MCLK2: 2045 reg = 1; 2046 break; 2047 case WM8996_FLL_DACLRCLK1: 2048 reg = 2; 2049 break; 2050 case WM8996_FLL_BCLK1: 2051 reg = 3; 2052 break; 2053 default: 2054 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 2055 return -EINVAL; 2056 } 2057 2058 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; 2059 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; 2060 2061 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, 2062 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | 2063 WM8996_FLL_REFCLK_SRC_MASK, reg); 2064 2065 reg = 0; 2066 if (fll_div.theta || fll_div.lambda) 2067 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); 2068 else 2069 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; 2070 snd_soc_write(codec, WM8996_FLL_EFS_2, reg); 2071 2072 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, 2073 WM8996_FLL_OUTDIV_MASK | 2074 WM8996_FLL_FRATIO_MASK, 2075 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | 2076 (fll_div.fll_fratio)); 2077 2078 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); 2079 2080 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, 2081 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, 2082 (fll_div.n << WM8996_FLL_N_SHIFT) | 2083 fll_div.fll_loop_gain); 2084 2085 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); 2086 2087 /* Enable the bandgap if it's not already enabled */ 2088 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1); 2089 if (!(ret & WM8996_FLL_ENA)) 2090 wm8996_bg_enable(codec); 2091 2092 /* Clear any pending completions (eg, from failed startups) */ 2093 try_wait_for_completion(&wm8996->fll_lock); 2094 2095 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2096 WM8996_FLL_ENA, WM8996_FLL_ENA); 2097 2098 /* The FLL supports live reconfiguration - kick that in case we were 2099 * already enabled. 2100 */ 2101 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); 2102 2103 /* Wait for the FLL to lock, using the interrupt if possible */ 2104 if (Fref > 1000000) 2105 timeout = usecs_to_jiffies(300); 2106 else 2107 timeout = msecs_to_jiffies(2); 2108 2109 /* Allow substantially longer if we've actually got the IRQ, poll 2110 * at a slightly higher rate if we don't. 2111 */ 2112 if (i2c->irq) 2113 timeout *= 10; 2114 else 2115 timeout /= 2; 2116 2117 for (retry = 0; retry < 10; retry++) { 2118 ret = wait_for_completion_timeout(&wm8996->fll_lock, 2119 timeout); 2120 if (ret != 0) { 2121 WARN_ON(!i2c->irq); 2122 break; 2123 } 2124 2125 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2); 2126 if (ret & WM8996_FLL_LOCK_STS) 2127 break; 2128 } 2129 if (retry == 10) { 2130 dev_err(codec->dev, "Timed out waiting for FLL\n"); 2131 ret = -ETIMEDOUT; 2132 } 2133 2134 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2135 2136 wm8996->fll_fref = Fref; 2137 wm8996->fll_fout = Fout; 2138 wm8996->fll_src = source; 2139 2140 return ret; 2141 } 2142 2143 #ifdef CONFIG_GPIOLIB 2144 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) 2145 { 2146 return container_of(chip, struct wm8996_priv, gpio_chip); 2147 } 2148 2149 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2150 { 2151 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2152 2153 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2154 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); 2155 } 2156 2157 static int wm8996_gpio_direction_out(struct gpio_chip *chip, 2158 unsigned offset, int value) 2159 { 2160 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2161 int val; 2162 2163 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); 2164 2165 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2166 WM8996_GP1_FN_MASK | WM8996_GP1_DIR | 2167 WM8996_GP1_LVL, val); 2168 } 2169 2170 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) 2171 { 2172 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2173 unsigned int reg; 2174 int ret; 2175 2176 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®); 2177 if (ret < 0) 2178 return ret; 2179 2180 return (reg & WM8996_GP1_LVL) != 0; 2181 } 2182 2183 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 2184 { 2185 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2186 2187 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2188 WM8996_GP1_FN_MASK | WM8996_GP1_DIR, 2189 (1 << WM8996_GP1_FN_SHIFT) | 2190 (1 << WM8996_GP1_DIR_SHIFT)); 2191 } 2192 2193 static struct gpio_chip wm8996_template_chip = { 2194 .label = "wm8996", 2195 .owner = THIS_MODULE, 2196 .direction_output = wm8996_gpio_direction_out, 2197 .set = wm8996_gpio_set, 2198 .direction_input = wm8996_gpio_direction_in, 2199 .get = wm8996_gpio_get, 2200 .can_sleep = 1, 2201 }; 2202 2203 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2204 { 2205 int ret; 2206 2207 wm8996->gpio_chip = wm8996_template_chip; 2208 wm8996->gpio_chip.ngpio = 5; 2209 wm8996->gpio_chip.dev = wm8996->dev; 2210 2211 if (wm8996->pdata.gpio_base) 2212 wm8996->gpio_chip.base = wm8996->pdata.gpio_base; 2213 else 2214 wm8996->gpio_chip.base = -1; 2215 2216 ret = gpiochip_add(&wm8996->gpio_chip); 2217 if (ret != 0) 2218 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret); 2219 } 2220 2221 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2222 { 2223 int ret; 2224 2225 ret = gpiochip_remove(&wm8996->gpio_chip); 2226 if (ret != 0) 2227 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret); 2228 } 2229 #else 2230 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2231 { 2232 } 2233 2234 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2235 { 2236 } 2237 #endif 2238 2239 /** 2240 * wm8996_detect - Enable default WM8996 jack detection 2241 * 2242 * The WM8996 has advanced accessory detection support for headsets. 2243 * This function provides a default implementation which integrates 2244 * the majority of this functionality with minimal user configuration. 2245 * 2246 * This will detect headset, headphone and short circuit button and 2247 * will also detect inverted microphone ground connections and update 2248 * the polarity of the connections. 2249 */ 2250 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2251 wm8996_polarity_fn polarity_cb) 2252 { 2253 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2254 struct snd_soc_dapm_context *dapm = &codec->dapm; 2255 2256 wm8996->jack = jack; 2257 wm8996->detecting = true; 2258 wm8996->polarity_cb = polarity_cb; 2259 wm8996->jack_flips = 0; 2260 2261 if (wm8996->polarity_cb) 2262 wm8996->polarity_cb(codec, 0); 2263 2264 /* Clear discarge to avoid noise during detection */ 2265 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 2266 WM8996_MICB1_DISCH, 0); 2267 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 2268 WM8996_MICB2_DISCH, 0); 2269 2270 /* LDO2 powers the microphones, SYSCLK clocks detection */ 2271 snd_soc_dapm_mutex_lock(dapm); 2272 2273 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2"); 2274 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK"); 2275 2276 snd_soc_dapm_mutex_unlock(dapm); 2277 2278 /* We start off just enabling microphone detection - even a 2279 * plain headphone will trigger detection. 2280 */ 2281 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2282 WM8996_MICD_ENA, WM8996_MICD_ENA); 2283 2284 /* Slowest detection rate, gives debounce for initial detection */ 2285 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2286 WM8996_MICD_RATE_MASK, 2287 WM8996_MICD_RATE_MASK); 2288 2289 /* Enable interrupts and we're off */ 2290 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, 2291 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0); 2292 2293 return 0; 2294 } 2295 EXPORT_SYMBOL_GPL(wm8996_detect); 2296 2297 static void wm8996_hpdet_irq(struct snd_soc_codec *codec) 2298 { 2299 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2300 int val, reg, report; 2301 2302 /* Assume headphone in error conditions; we need to report 2303 * something or we stall our state machine. 2304 */ 2305 report = SND_JACK_HEADPHONE; 2306 2307 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2); 2308 if (reg < 0) { 2309 dev_err(codec->dev, "Failed to read HPDET status\n"); 2310 goto out; 2311 } 2312 2313 if (!(reg & WM8996_HP_DONE)) { 2314 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n"); 2315 goto out; 2316 } 2317 2318 val = reg & WM8996_HP_LVL_MASK; 2319 2320 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val); 2321 2322 /* If we've got high enough impedence then report as line, 2323 * otherwise assume headphone. 2324 */ 2325 if (val >= 126) 2326 report = SND_JACK_LINEOUT; 2327 else 2328 report = SND_JACK_HEADPHONE; 2329 2330 out: 2331 if (wm8996->jack_mic) 2332 report |= SND_JACK_MICROPHONE; 2333 2334 snd_soc_jack_report(wm8996->jack, report, 2335 SND_JACK_LINEOUT | SND_JACK_HEADSET); 2336 2337 wm8996->detecting = false; 2338 2339 /* If the output isn't running re-clamp it */ 2340 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) & 2341 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT))) 2342 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2343 WM8996_HPOUT1L_RMV_SHORT | 2344 WM8996_HPOUT1R_RMV_SHORT, 0); 2345 2346 /* Go back to looking at the microphone */ 2347 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2348 WM8996_JD_MODE_MASK, 0); 2349 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 2350 WM8996_MICD_ENA); 2351 2352 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap"); 2353 snd_soc_dapm_sync(&codec->dapm); 2354 } 2355 2356 static void wm8996_hpdet_start(struct snd_soc_codec *codec) 2357 { 2358 /* Unclamp the output, we can't measure while we're shorting it */ 2359 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2360 WM8996_HPOUT1L_RMV_SHORT | 2361 WM8996_HPOUT1R_RMV_SHORT, 2362 WM8996_HPOUT1L_RMV_SHORT | 2363 WM8996_HPOUT1R_RMV_SHORT); 2364 2365 /* We need bandgap for HPDET */ 2366 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap"); 2367 snd_soc_dapm_sync(&codec->dapm); 2368 2369 /* Go into headphone detect left mode */ 2370 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0); 2371 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2372 WM8996_JD_MODE_MASK, 1); 2373 2374 /* Trigger a measurement */ 2375 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1, 2376 WM8996_HP_POLL, WM8996_HP_POLL); 2377 } 2378 2379 static void wm8996_report_headphone(struct snd_soc_codec *codec) 2380 { 2381 dev_dbg(codec->dev, "Headphone detected\n"); 2382 wm8996_hpdet_start(codec); 2383 2384 /* Increase the detection rate a bit for responsiveness. */ 2385 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2386 WM8996_MICD_RATE_MASK | 2387 WM8996_MICD_BIAS_STARTTIME_MASK, 2388 7 << WM8996_MICD_RATE_SHIFT | 2389 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2390 } 2391 2392 static void wm8996_micd(struct snd_soc_codec *codec) 2393 { 2394 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2395 int val, reg; 2396 2397 val = snd_soc_read(codec, WM8996_MIC_DETECT_3); 2398 2399 dev_dbg(codec->dev, "Microphone event: %x\n", val); 2400 2401 if (!(val & WM8996_MICD_VALID)) { 2402 dev_warn(codec->dev, "Microphone detection state invalid\n"); 2403 return; 2404 } 2405 2406 /* No accessory, reset everything and report removal */ 2407 if (!(val & WM8996_MICD_STS)) { 2408 dev_dbg(codec->dev, "Jack removal detected\n"); 2409 wm8996->jack_mic = false; 2410 wm8996->detecting = true; 2411 wm8996->jack_flips = 0; 2412 snd_soc_jack_report(wm8996->jack, 0, 2413 SND_JACK_LINEOUT | SND_JACK_HEADSET | 2414 SND_JACK_BTN_0); 2415 2416 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2417 WM8996_MICD_RATE_MASK | 2418 WM8996_MICD_BIAS_STARTTIME_MASK, 2419 WM8996_MICD_RATE_MASK | 2420 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2421 return; 2422 } 2423 2424 /* If the measurement is very high we've got a microphone, 2425 * either we just detected one or if we already reported then 2426 * we've got a button release event. 2427 */ 2428 if (val & 0x400) { 2429 if (wm8996->detecting) { 2430 dev_dbg(codec->dev, "Microphone detected\n"); 2431 wm8996->jack_mic = true; 2432 wm8996_hpdet_start(codec); 2433 2434 /* Increase poll rate to give better responsiveness 2435 * for buttons */ 2436 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2437 WM8996_MICD_RATE_MASK | 2438 WM8996_MICD_BIAS_STARTTIME_MASK, 2439 5 << WM8996_MICD_RATE_SHIFT | 2440 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2441 } else { 2442 dev_dbg(codec->dev, "Mic button up\n"); 2443 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0); 2444 } 2445 2446 return; 2447 } 2448 2449 /* If we detected a lower impedence during initial startup 2450 * then we probably have the wrong polarity, flip it. Don't 2451 * do this for the lowest impedences to speed up detection of 2452 * plain headphones. If both polarities report a low 2453 * impedence then give up and report headphones. 2454 */ 2455 if (wm8996->detecting && (val & 0x3f0)) { 2456 wm8996->jack_flips++; 2457 2458 if (wm8996->jack_flips > 1) { 2459 wm8996_report_headphone(codec); 2460 return; 2461 } 2462 2463 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); 2464 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2465 WM8996_MICD_BIAS_SRC; 2466 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2467 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2468 WM8996_MICD_BIAS_SRC, reg); 2469 2470 if (wm8996->polarity_cb) 2471 wm8996->polarity_cb(codec, 2472 (reg & WM8996_MICD_SRC) != 0); 2473 2474 dev_dbg(codec->dev, "Set microphone polarity to %d\n", 2475 (reg & WM8996_MICD_SRC) != 0); 2476 2477 return; 2478 } 2479 2480 /* Don't distinguish between buttons, just report any low 2481 * impedence as BTN_0. 2482 */ 2483 if (val & 0x3fc) { 2484 if (wm8996->jack_mic) { 2485 dev_dbg(codec->dev, "Mic button detected\n"); 2486 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0, 2487 SND_JACK_BTN_0); 2488 } else if (wm8996->detecting) { 2489 wm8996_report_headphone(codec); 2490 } 2491 } 2492 } 2493 2494 static irqreturn_t wm8996_irq(int irq, void *data) 2495 { 2496 struct snd_soc_codec *codec = data; 2497 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2498 int irq_val; 2499 2500 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); 2501 if (irq_val < 0) { 2502 dev_err(codec->dev, "Failed to read IRQ status: %d\n", 2503 irq_val); 2504 return IRQ_NONE; 2505 } 2506 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); 2507 2508 if (!irq_val) 2509 return IRQ_NONE; 2510 2511 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); 2512 2513 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { 2514 dev_dbg(codec->dev, "DC servo IRQ\n"); 2515 complete(&wm8996->dcs_done); 2516 } 2517 2518 if (irq_val & WM8996_FIFOS_ERR_EINT) 2519 dev_err(codec->dev, "Digital core FIFO error\n"); 2520 2521 if (irq_val & WM8996_FLL_LOCK_EINT) { 2522 dev_dbg(codec->dev, "FLL locked\n"); 2523 complete(&wm8996->fll_lock); 2524 } 2525 2526 if (irq_val & WM8996_MICD_EINT) 2527 wm8996_micd(codec); 2528 2529 if (irq_val & WM8996_HP_DONE_EINT) 2530 wm8996_hpdet_irq(codec); 2531 2532 return IRQ_HANDLED; 2533 } 2534 2535 static irqreturn_t wm8996_edge_irq(int irq, void *data) 2536 { 2537 irqreturn_t ret = IRQ_NONE; 2538 irqreturn_t val; 2539 2540 do { 2541 val = wm8996_irq(irq, data); 2542 if (val != IRQ_NONE) 2543 ret = val; 2544 } while (val != IRQ_NONE); 2545 2546 return ret; 2547 } 2548 2549 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) 2550 { 2551 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2552 struct wm8996_pdata *pdata = &wm8996->pdata; 2553 2554 struct snd_kcontrol_new controls[] = { 2555 SOC_ENUM_EXT("DSP1 EQ Mode", 2556 wm8996->retune_mobile_enum, 2557 wm8996_get_retune_mobile_enum, 2558 wm8996_put_retune_mobile_enum), 2559 SOC_ENUM_EXT("DSP2 EQ Mode", 2560 wm8996->retune_mobile_enum, 2561 wm8996_get_retune_mobile_enum, 2562 wm8996_put_retune_mobile_enum), 2563 }; 2564 int ret, i, j; 2565 const char **t; 2566 2567 /* We need an array of texts for the enum API but the number 2568 * of texts is likely to be less than the number of 2569 * configurations due to the sample rate dependency of the 2570 * configurations. */ 2571 wm8996->num_retune_mobile_texts = 0; 2572 wm8996->retune_mobile_texts = NULL; 2573 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2574 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { 2575 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2576 wm8996->retune_mobile_texts[j]) == 0) 2577 break; 2578 } 2579 2580 if (j != wm8996->num_retune_mobile_texts) 2581 continue; 2582 2583 /* Expand the array... */ 2584 t = krealloc(wm8996->retune_mobile_texts, 2585 sizeof(char *) * 2586 (wm8996->num_retune_mobile_texts + 1), 2587 GFP_KERNEL); 2588 if (t == NULL) 2589 continue; 2590 2591 /* ...store the new entry... */ 2592 t[wm8996->num_retune_mobile_texts] = 2593 pdata->retune_mobile_cfgs[i].name; 2594 2595 /* ...and remember the new version. */ 2596 wm8996->num_retune_mobile_texts++; 2597 wm8996->retune_mobile_texts = t; 2598 } 2599 2600 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2601 wm8996->num_retune_mobile_texts); 2602 2603 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts; 2604 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; 2605 2606 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2607 if (ret != 0) 2608 dev_err(codec->dev, 2609 "Failed to add ReTune Mobile controls: %d\n", ret); 2610 } 2611 2612 static const struct regmap_config wm8996_regmap = { 2613 .reg_bits = 16, 2614 .val_bits = 16, 2615 2616 .max_register = WM8996_MAX_REGISTER, 2617 .reg_defaults = wm8996_reg, 2618 .num_reg_defaults = ARRAY_SIZE(wm8996_reg), 2619 .volatile_reg = wm8996_volatile_register, 2620 .readable_reg = wm8996_readable_register, 2621 .cache_type = REGCACHE_RBTREE, 2622 }; 2623 2624 static int wm8996_probe(struct snd_soc_codec *codec) 2625 { 2626 int ret; 2627 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2628 struct i2c_client *i2c = to_i2c_client(codec->dev); 2629 int irq_flags; 2630 2631 wm8996->codec = codec; 2632 2633 init_completion(&wm8996->dcs_done); 2634 init_completion(&wm8996->fll_lock); 2635 2636 if (wm8996->pdata.num_retune_mobile_cfgs) 2637 wm8996_retune_mobile_pdata(codec); 2638 else 2639 snd_soc_add_codec_controls(codec, wm8996_eq_controls, 2640 ARRAY_SIZE(wm8996_eq_controls)); 2641 2642 if (i2c->irq) { 2643 if (wm8996->pdata.irq_flags) 2644 irq_flags = wm8996->pdata.irq_flags; 2645 else 2646 irq_flags = IRQF_TRIGGER_LOW; 2647 2648 irq_flags |= IRQF_ONESHOT; 2649 2650 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) 2651 ret = request_threaded_irq(i2c->irq, NULL, 2652 wm8996_edge_irq, 2653 irq_flags, "wm8996", codec); 2654 else 2655 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, 2656 irq_flags, "wm8996", codec); 2657 2658 if (ret == 0) { 2659 /* Unmask the interrupt */ 2660 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 2661 WM8996_IM_IRQ, 0); 2662 2663 /* Enable error reporting and DC servo status */ 2664 snd_soc_update_bits(codec, 2665 WM8996_INTERRUPT_STATUS_2_MASK, 2666 WM8996_IM_DCS_DONE_23_EINT | 2667 WM8996_IM_DCS_DONE_01_EINT | 2668 WM8996_IM_FLL_LOCK_EINT | 2669 WM8996_IM_FIFOS_ERR_EINT, 2670 0); 2671 } else { 2672 dev_err(codec->dev, "Failed to request IRQ: %d\n", 2673 ret); 2674 return ret; 2675 } 2676 } 2677 2678 return 0; 2679 } 2680 2681 static int wm8996_remove(struct snd_soc_codec *codec) 2682 { 2683 struct i2c_client *i2c = to_i2c_client(codec->dev); 2684 2685 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 2686 WM8996_IM_IRQ, WM8996_IM_IRQ); 2687 2688 if (i2c->irq) 2689 free_irq(i2c->irq, codec); 2690 2691 return 0; 2692 } 2693 2694 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { 2695 .probe = wm8996_probe, 2696 .remove = wm8996_remove, 2697 .set_bias_level = wm8996_set_bias_level, 2698 .idle_bias_off = true, 2699 .seq_notifier = wm8996_seq_notifier, 2700 .controls = wm8996_snd_controls, 2701 .num_controls = ARRAY_SIZE(wm8996_snd_controls), 2702 .dapm_widgets = wm8996_dapm_widgets, 2703 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), 2704 .dapm_routes = wm8996_dapm_routes, 2705 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), 2706 .set_pll = wm8996_set_fll, 2707 }; 2708 2709 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 2710 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 2711 SNDRV_PCM_RATE_48000) 2712 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 2713 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 2714 SNDRV_PCM_FMTBIT_S32_LE) 2715 2716 static const struct snd_soc_dai_ops wm8996_dai_ops = { 2717 .set_fmt = wm8996_set_fmt, 2718 .hw_params = wm8996_hw_params, 2719 .set_sysclk = wm8996_set_sysclk, 2720 }; 2721 2722 static struct snd_soc_dai_driver wm8996_dai[] = { 2723 { 2724 .name = "wm8996-aif1", 2725 .playback = { 2726 .stream_name = "AIF1 Playback", 2727 .channels_min = 1, 2728 .channels_max = 6, 2729 .rates = WM8996_RATES, 2730 .formats = WM8996_FORMATS, 2731 .sig_bits = 24, 2732 }, 2733 .capture = { 2734 .stream_name = "AIF1 Capture", 2735 .channels_min = 1, 2736 .channels_max = 6, 2737 .rates = WM8996_RATES, 2738 .formats = WM8996_FORMATS, 2739 .sig_bits = 24, 2740 }, 2741 .ops = &wm8996_dai_ops, 2742 }, 2743 { 2744 .name = "wm8996-aif2", 2745 .playback = { 2746 .stream_name = "AIF2 Playback", 2747 .channels_min = 1, 2748 .channels_max = 2, 2749 .rates = WM8996_RATES, 2750 .formats = WM8996_FORMATS, 2751 .sig_bits = 24, 2752 }, 2753 .capture = { 2754 .stream_name = "AIF2 Capture", 2755 .channels_min = 1, 2756 .channels_max = 2, 2757 .rates = WM8996_RATES, 2758 .formats = WM8996_FORMATS, 2759 .sig_bits = 24, 2760 }, 2761 .ops = &wm8996_dai_ops, 2762 }, 2763 }; 2764 2765 static int wm8996_i2c_probe(struct i2c_client *i2c, 2766 const struct i2c_device_id *id) 2767 { 2768 struct wm8996_priv *wm8996; 2769 int ret, i; 2770 unsigned int reg; 2771 2772 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv), 2773 GFP_KERNEL); 2774 if (wm8996 == NULL) 2775 return -ENOMEM; 2776 2777 i2c_set_clientdata(i2c, wm8996); 2778 wm8996->dev = &i2c->dev; 2779 2780 if (dev_get_platdata(&i2c->dev)) 2781 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), 2782 sizeof(wm8996->pdata)); 2783 2784 if (wm8996->pdata.ldo_ena > 0) { 2785 ret = gpio_request_one(wm8996->pdata.ldo_ena, 2786 GPIOF_OUT_INIT_LOW, "WM8996 ENA"); 2787 if (ret < 0) { 2788 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", 2789 wm8996->pdata.ldo_ena, ret); 2790 goto err; 2791 } 2792 } 2793 2794 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 2795 wm8996->supplies[i].supply = wm8996_supply_names[i]; 2796 2797 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies), 2798 wm8996->supplies); 2799 if (ret != 0) { 2800 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2801 goto err_gpio; 2802 } 2803 2804 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; 2805 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; 2806 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; 2807 2808 /* This should really be moved into the regulator core */ 2809 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { 2810 ret = regulator_register_notifier(wm8996->supplies[i].consumer, 2811 &wm8996->disable_nb[i]); 2812 if (ret != 0) { 2813 dev_err(&i2c->dev, 2814 "Failed to register regulator notifier: %d\n", 2815 ret); 2816 } 2817 } 2818 2819 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 2820 wm8996->supplies); 2821 if (ret != 0) { 2822 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2823 goto err_gpio; 2824 } 2825 2826 if (wm8996->pdata.ldo_ena > 0) { 2827 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 2828 msleep(5); 2829 } 2830 2831 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap); 2832 if (IS_ERR(wm8996->regmap)) { 2833 ret = PTR_ERR(wm8996->regmap); 2834 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 2835 goto err_enable; 2836 } 2837 2838 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®); 2839 if (ret < 0) { 2840 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2841 goto err_regmap; 2842 } 2843 if (reg != 0x8915) { 2844 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg); 2845 ret = -EINVAL; 2846 goto err_regmap; 2847 } 2848 2849 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®); 2850 if (ret < 0) { 2851 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2852 ret); 2853 goto err_regmap; 2854 } 2855 2856 dev_info(&i2c->dev, "revision %c\n", 2857 (reg & WM8996_CHIP_REV_MASK) + 'A'); 2858 2859 if (wm8996->pdata.ldo_ena > 0) { 2860 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 2861 regcache_cache_only(wm8996->regmap, true); 2862 } else { 2863 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET, 2864 0x8915); 2865 if (ret != 0) { 2866 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2867 goto err_regmap; 2868 } 2869 } 2870 2871 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2872 2873 /* Apply platform data settings */ 2874 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL, 2875 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2876 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | 2877 wm8996->pdata.inr_mode); 2878 2879 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { 2880 if (!wm8996->pdata.gpio_default[i]) 2881 continue; 2882 2883 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i, 2884 wm8996->pdata.gpio_default[i] & 0xffff); 2885 } 2886 2887 if (wm8996->pdata.spkmute_seq) 2888 regmap_update_bits(wm8996->regmap, 2889 WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 2890 WM8996_SPK_MUTE_ENDIAN | 2891 WM8996_SPK_MUTE_SEQ1_MASK, 2892 wm8996->pdata.spkmute_seq); 2893 2894 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2, 2895 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | 2896 WM8996_MICD_SRC, wm8996->pdata.micdet_def); 2897 2898 /* Latch volume update bits */ 2899 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME, 2900 WM8996_IN1_VU, WM8996_IN1_VU); 2901 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME, 2902 WM8996_IN1_VU, WM8996_IN1_VU); 2903 2904 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME, 2905 WM8996_DAC1_VU, WM8996_DAC1_VU); 2906 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME, 2907 WM8996_DAC1_VU, WM8996_DAC1_VU); 2908 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME, 2909 WM8996_DAC2_VU, WM8996_DAC2_VU); 2910 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME, 2911 WM8996_DAC2_VU, WM8996_DAC2_VU); 2912 2913 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME, 2914 WM8996_DAC1_VU, WM8996_DAC1_VU); 2915 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME, 2916 WM8996_DAC1_VU, WM8996_DAC1_VU); 2917 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME, 2918 WM8996_DAC2_VU, WM8996_DAC2_VU); 2919 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME, 2920 WM8996_DAC2_VU, WM8996_DAC2_VU); 2921 2922 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME, 2923 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2924 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME, 2925 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2926 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME, 2927 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2928 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME, 2929 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2930 2931 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME, 2932 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2933 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME, 2934 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2935 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME, 2936 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2937 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME, 2938 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2939 2940 /* No support currently for the underclocked TDM modes and 2941 * pick a default TDM layout with each channel pair working with 2942 * slots 0 and 1. */ 2943 regmap_update_bits(wm8996->regmap, 2944 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 2945 WM8996_AIF1RX_CHAN0_SLOTS_MASK | 2946 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2947 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); 2948 regmap_update_bits(wm8996->regmap, 2949 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 2950 WM8996_AIF1RX_CHAN1_SLOTS_MASK | 2951 WM8996_AIF1RX_CHAN1_START_SLOT_MASK, 2952 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); 2953 regmap_update_bits(wm8996->regmap, 2954 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 2955 WM8996_AIF1RX_CHAN2_SLOTS_MASK | 2956 WM8996_AIF1RX_CHAN2_START_SLOT_MASK, 2957 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); 2958 regmap_update_bits(wm8996->regmap, 2959 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 2960 WM8996_AIF1RX_CHAN3_SLOTS_MASK | 2961 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2962 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); 2963 regmap_update_bits(wm8996->regmap, 2964 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 2965 WM8996_AIF1RX_CHAN4_SLOTS_MASK | 2966 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2967 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); 2968 regmap_update_bits(wm8996->regmap, 2969 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 2970 WM8996_AIF1RX_CHAN5_SLOTS_MASK | 2971 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2972 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); 2973 2974 regmap_update_bits(wm8996->regmap, 2975 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 2976 WM8996_AIF2RX_CHAN0_SLOTS_MASK | 2977 WM8996_AIF2RX_CHAN0_START_SLOT_MASK, 2978 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); 2979 regmap_update_bits(wm8996->regmap, 2980 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 2981 WM8996_AIF2RX_CHAN1_SLOTS_MASK | 2982 WM8996_AIF2RX_CHAN1_START_SLOT_MASK, 2983 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); 2984 2985 regmap_update_bits(wm8996->regmap, 2986 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 2987 WM8996_AIF1TX_CHAN0_SLOTS_MASK | 2988 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2989 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); 2990 regmap_update_bits(wm8996->regmap, 2991 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2992 WM8996_AIF1TX_CHAN1_SLOTS_MASK | 2993 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2994 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2995 regmap_update_bits(wm8996->regmap, 2996 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 2997 WM8996_AIF1TX_CHAN2_SLOTS_MASK | 2998 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2999 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); 3000 regmap_update_bits(wm8996->regmap, 3001 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 3002 WM8996_AIF1TX_CHAN3_SLOTS_MASK | 3003 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3004 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); 3005 regmap_update_bits(wm8996->regmap, 3006 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 3007 WM8996_AIF1TX_CHAN4_SLOTS_MASK | 3008 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3009 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); 3010 regmap_update_bits(wm8996->regmap, 3011 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 3012 WM8996_AIF1TX_CHAN5_SLOTS_MASK | 3013 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3014 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); 3015 3016 regmap_update_bits(wm8996->regmap, 3017 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 3018 WM8996_AIF2TX_CHAN0_SLOTS_MASK | 3019 WM8996_AIF2TX_CHAN0_START_SLOT_MASK, 3020 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); 3021 regmap_update_bits(wm8996->regmap, 3022 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 3023 WM8996_AIF2TX_CHAN1_SLOTS_MASK | 3024 WM8996_AIF2TX_CHAN1_START_SLOT_MASK, 3025 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 3026 3027 /* If the TX LRCLK pins are not in LRCLK mode configure the 3028 * AIFs to source their clocks from the RX LRCLKs. 3029 */ 3030 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®); 3031 if (ret != 0) { 3032 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret); 3033 goto err_regmap; 3034 } 3035 3036 if (reg & WM8996_GP1_FN_MASK) 3037 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2, 3038 WM8996_AIF1TX_LRCLK_MODE, 3039 WM8996_AIF1TX_LRCLK_MODE); 3040 3041 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®); 3042 if (ret != 0) { 3043 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret); 3044 goto err_regmap; 3045 } 3046 3047 if (reg & WM8996_GP2_FN_MASK) 3048 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2, 3049 WM8996_AIF2TX_LRCLK_MODE, 3050 WM8996_AIF2TX_LRCLK_MODE); 3051 3052 wm8996_init_gpio(wm8996); 3053 3054 ret = snd_soc_register_codec(&i2c->dev, 3055 &soc_codec_dev_wm8996, wm8996_dai, 3056 ARRAY_SIZE(wm8996_dai)); 3057 if (ret < 0) 3058 goto err_gpiolib; 3059 3060 return ret; 3061 3062 err_gpiolib: 3063 wm8996_free_gpio(wm8996); 3064 err_regmap: 3065 err_enable: 3066 if (wm8996->pdata.ldo_ena > 0) 3067 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3068 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3069 err_gpio: 3070 if (wm8996->pdata.ldo_ena > 0) 3071 gpio_free(wm8996->pdata.ldo_ena); 3072 err: 3073 3074 return ret; 3075 } 3076 3077 static int wm8996_i2c_remove(struct i2c_client *client) 3078 { 3079 struct wm8996_priv *wm8996 = i2c_get_clientdata(client); 3080 int i; 3081 3082 snd_soc_unregister_codec(&client->dev); 3083 wm8996_free_gpio(wm8996); 3084 if (wm8996->pdata.ldo_ena > 0) { 3085 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3086 gpio_free(wm8996->pdata.ldo_ena); 3087 } 3088 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3089 regulator_unregister_notifier(wm8996->supplies[i].consumer, 3090 &wm8996->disable_nb[i]); 3091 3092 return 0; 3093 } 3094 3095 static const struct i2c_device_id wm8996_i2c_id[] = { 3096 { "wm8996", 0 }, 3097 { } 3098 }; 3099 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3100 3101 static struct i2c_driver wm8996_i2c_driver = { 3102 .driver = { 3103 .name = "wm8996", 3104 .owner = THIS_MODULE, 3105 }, 3106 .probe = wm8996_i2c_probe, 3107 .remove = wm8996_i2c_remove, 3108 .id_table = wm8996_i2c_id, 3109 }; 3110 3111 module_i2c_driver(wm8996_i2c_driver); 3112 3113 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3114 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3115 MODULE_LICENSE("GPL"); 3116