1 /* 2 * wm8996.c - WM8996 audio codec interface 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/gpio.h> 22 #include <linux/i2c.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/jack.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <trace/events/asoc.h> 35 36 #include <sound/wm8996.h> 37 #include "wm8996.h" 38 39 #define WM8996_AIFS 2 40 41 #define HPOUT1L 1 42 #define HPOUT1R 2 43 #define HPOUT2L 4 44 #define HPOUT2R 8 45 46 #define WM8996_NUM_SUPPLIES 3 47 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { 48 "DBVDD", 49 "AVDD1", 50 "AVDD2", 51 }; 52 53 struct wm8996_priv { 54 struct device *dev; 55 struct regmap *regmap; 56 struct snd_soc_component *component; 57 58 int ldo1ena; 59 60 int sysclk; 61 int sysclk_src; 62 63 int fll_src; 64 int fll_fref; 65 int fll_fout; 66 67 struct completion fll_lock; 68 69 u16 dcs_pending; 70 struct completion dcs_done; 71 72 u16 hpout_ena; 73 u16 hpout_pending; 74 75 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; 76 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; 77 int bg_ena; 78 79 struct wm8996_pdata pdata; 80 81 int rx_rate[WM8996_AIFS]; 82 int bclk_rate[WM8996_AIFS]; 83 84 /* Platform dependant ReTune mobile configuration */ 85 int num_retune_mobile_texts; 86 const char **retune_mobile_texts; 87 int retune_mobile_cfg[2]; 88 struct soc_enum retune_mobile_enum; 89 90 struct snd_soc_jack *jack; 91 bool detecting; 92 bool jack_mic; 93 int jack_flips; 94 wm8996_polarity_fn polarity_cb; 95 96 #ifdef CONFIG_GPIOLIB 97 struct gpio_chip gpio_chip; 98 #endif 99 }; 100 101 /* We can't use the same notifier block for more than one supply and 102 * there's no way I can see to get from a callback to the caller 103 * except container_of(). 104 */ 105 #define WM8996_REGULATOR_EVENT(n) \ 106 static int wm8996_regulator_event_##n(struct notifier_block *nb, \ 107 unsigned long event, void *data) \ 108 { \ 109 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ 110 disable_nb[n]); \ 111 if (event & REGULATOR_EVENT_DISABLE) { \ 112 regcache_mark_dirty(wm8996->regmap); \ 113 } \ 114 return 0; \ 115 } 116 117 WM8996_REGULATOR_EVENT(0) 118 WM8996_REGULATOR_EVENT(1) 119 WM8996_REGULATOR_EVENT(2) 120 121 static const struct reg_default wm8996_reg[] = { 122 { WM8996_POWER_MANAGEMENT_1, 0x0 }, 123 { WM8996_POWER_MANAGEMENT_2, 0x0 }, 124 { WM8996_POWER_MANAGEMENT_3, 0x0 }, 125 { WM8996_POWER_MANAGEMENT_4, 0x0 }, 126 { WM8996_POWER_MANAGEMENT_5, 0x0 }, 127 { WM8996_POWER_MANAGEMENT_6, 0x0 }, 128 { WM8996_POWER_MANAGEMENT_7, 0x10 }, 129 { WM8996_POWER_MANAGEMENT_8, 0x0 }, 130 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 }, 131 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 }, 132 { WM8996_LINE_INPUT_CONTROL, 0x0 }, 133 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 }, 134 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 }, 135 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 }, 136 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 }, 137 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 }, 138 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 }, 139 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 }, 140 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 }, 141 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 }, 142 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 }, 143 { WM8996_MICBIAS_1, 0x39 }, 144 { WM8996_MICBIAS_2, 0x39 }, 145 { WM8996_LDO_1, 0x3 }, 146 { WM8996_LDO_2, 0x13 }, 147 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 }, 148 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 }, 149 { WM8996_HEADPHONE_DETECT_1, 0x20 }, 150 { WM8996_HEADPHONE_DETECT_2, 0x0 }, 151 { WM8996_MIC_DETECT_1, 0x7600 }, 152 { WM8996_MIC_DETECT_2, 0xbf }, 153 { WM8996_CHARGE_PUMP_1, 0x1f25 }, 154 { WM8996_CHARGE_PUMP_2, 0xab19 }, 155 { WM8996_DC_SERVO_1, 0x0 }, 156 { WM8996_DC_SERVO_3, 0x0 }, 157 { WM8996_DC_SERVO_5, 0x2a2a }, 158 { WM8996_DC_SERVO_6, 0x0 }, 159 { WM8996_DC_SERVO_7, 0x0 }, 160 { WM8996_ANALOGUE_HP_1, 0x0 }, 161 { WM8996_ANALOGUE_HP_2, 0x0 }, 162 { WM8996_CONTROL_INTERFACE_1, 0x8004 }, 163 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 }, 164 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 }, 165 { WM8996_AIF_CLOCKING_1, 0x0 }, 166 { WM8996_AIF_CLOCKING_2, 0x0 }, 167 { WM8996_CLOCKING_1, 0x10 }, 168 { WM8996_CLOCKING_2, 0x0 }, 169 { WM8996_AIF_RATE, 0x83 }, 170 { WM8996_FLL_CONTROL_1, 0x0 }, 171 { WM8996_FLL_CONTROL_2, 0x0 }, 172 { WM8996_FLL_CONTROL_3, 0x0 }, 173 { WM8996_FLL_CONTROL_4, 0x5dc0 }, 174 { WM8996_FLL_CONTROL_5, 0xc84 }, 175 { WM8996_FLL_EFS_1, 0x0 }, 176 { WM8996_FLL_EFS_2, 0x2 }, 177 { WM8996_AIF1_CONTROL, 0x0 }, 178 { WM8996_AIF1_BCLK, 0x0 }, 179 { WM8996_AIF1_TX_LRCLK_1, 0x80 }, 180 { WM8996_AIF1_TX_LRCLK_2, 0x8 }, 181 { WM8996_AIF1_RX_LRCLK_1, 0x80 }, 182 { WM8996_AIF1_RX_LRCLK_2, 0x0 }, 183 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 }, 184 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 }, 185 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 }, 186 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 }, 187 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 }, 188 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 }, 189 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 }, 190 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 }, 191 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 }, 192 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 }, 193 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 }, 194 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 }, 195 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 }, 196 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 }, 197 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 }, 198 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 }, 199 { WM8996_AIF1TX_TEST, 0x7 }, 200 { WM8996_AIF2_CONTROL, 0x0 }, 201 { WM8996_AIF2_BCLK, 0x0 }, 202 { WM8996_AIF2_TX_LRCLK_1, 0x80 }, 203 { WM8996_AIF2_TX_LRCLK_2, 0x8 }, 204 { WM8996_AIF2_RX_LRCLK_1, 0x80 }, 205 { WM8996_AIF2_RX_LRCLK_2, 0x0 }, 206 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 }, 207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 }, 208 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 }, 209 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 }, 210 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 }, 211 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 }, 212 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 }, 213 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 }, 214 { WM8996_AIF2TX_TEST, 0x1 }, 215 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 }, 216 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 }, 217 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 }, 218 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 }, 219 { WM8996_DSP1_TX_FILTERS, 0x2000 }, 220 { WM8996_DSP1_RX_FILTERS_1, 0x200 }, 221 { WM8996_DSP1_RX_FILTERS_2, 0x10 }, 222 { WM8996_DSP1_DRC_1, 0x98 }, 223 { WM8996_DSP1_DRC_2, 0x845 }, 224 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 }, 225 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 }, 226 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca }, 227 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 }, 228 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 }, 229 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 }, 230 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 }, 231 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 }, 232 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 }, 233 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 }, 234 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 }, 235 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 }, 236 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 }, 237 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e }, 238 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 }, 239 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad }, 240 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 }, 241 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 }, 242 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 }, 243 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 }, 244 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 }, 245 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 }, 246 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 }, 247 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 }, 248 { WM8996_DSP2_TX_FILTERS, 0x2000 }, 249 { WM8996_DSP2_RX_FILTERS_1, 0x200 }, 250 { WM8996_DSP2_RX_FILTERS_2, 0x10 }, 251 { WM8996_DSP2_DRC_1, 0x98 }, 252 { WM8996_DSP2_DRC_2, 0x845 }, 253 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 }, 254 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 }, 255 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca }, 256 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 }, 257 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 }, 258 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 }, 259 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 }, 260 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 }, 261 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 }, 262 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 }, 263 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 }, 264 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 }, 265 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 }, 266 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e }, 267 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 }, 268 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad }, 269 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 }, 270 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 }, 271 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 }, 272 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 }, 273 { WM8996_DAC1_MIXER_VOLUMES, 0x0 }, 274 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 }, 275 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 }, 276 { WM8996_DAC2_MIXER_VOLUMES, 0x0 }, 277 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 }, 278 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 }, 279 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 }, 280 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 }, 281 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 }, 282 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 }, 283 { WM8996_DSP_TX_MIXER_SELECT, 0x0 }, 284 { WM8996_DAC_SOFTMUTE, 0x0 }, 285 { WM8996_OVERSAMPLING, 0xd }, 286 { WM8996_SIDETONE, 0x1040 }, 287 { WM8996_GPIO_1, 0xa101 }, 288 { WM8996_GPIO_2, 0xa101 }, 289 { WM8996_GPIO_3, 0xa101 }, 290 { WM8996_GPIO_4, 0xa101 }, 291 { WM8996_GPIO_5, 0xa101 }, 292 { WM8996_PULL_CONTROL_1, 0x0 }, 293 { WM8996_PULL_CONTROL_2, 0x140 }, 294 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f }, 295 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf }, 296 { WM8996_LEFT_PDM_SPEAKER, 0x0 }, 297 { WM8996_RIGHT_PDM_SPEAKER, 0x1 }, 298 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 }, 299 { WM8996_PDM_SPEAKER_VOLUME, 0x66 }, 300 }; 301 302 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); 303 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 304 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 305 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); 306 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); 307 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); 308 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 309 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); 310 311 static const char *sidetone_hpf_text[] = { 312 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" 313 }; 314 315 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 316 WM8996_SIDETONE, 7, sidetone_hpf_text); 317 318 static const char *hpf_mode_text[] = { 319 "HiFi", "Custom", "Voice" 320 }; 321 322 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode, 323 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text); 324 325 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode, 326 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text); 327 328 static const char *hpf_cutoff_text[] = { 329 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 330 }; 331 332 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff, 333 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text); 334 335 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff, 336 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text); 337 338 static void wm8996_set_retune_mobile(struct snd_soc_component *component, int block) 339 { 340 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 341 struct wm8996_pdata *pdata = &wm8996->pdata; 342 int base, best, best_val, save, i, cfg, iface; 343 344 if (!wm8996->num_retune_mobile_texts) 345 return; 346 347 switch (block) { 348 case 0: 349 base = WM8996_DSP1_RX_EQ_GAINS_1; 350 if (snd_soc_component_read32(component, WM8996_POWER_MANAGEMENT_8) & 351 WM8996_DSP1RX_SRC) 352 iface = 1; 353 else 354 iface = 0; 355 break; 356 case 1: 357 base = WM8996_DSP1_RX_EQ_GAINS_2; 358 if (snd_soc_component_read32(component, WM8996_POWER_MANAGEMENT_8) & 359 WM8996_DSP2RX_SRC) 360 iface = 1; 361 else 362 iface = 0; 363 break; 364 default: 365 return; 366 } 367 368 /* Find the version of the currently selected configuration 369 * with the nearest sample rate. */ 370 cfg = wm8996->retune_mobile_cfg[block]; 371 best = 0; 372 best_val = INT_MAX; 373 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 374 if (strcmp(pdata->retune_mobile_cfgs[i].name, 375 wm8996->retune_mobile_texts[cfg]) == 0 && 376 abs(pdata->retune_mobile_cfgs[i].rate 377 - wm8996->rx_rate[iface]) < best_val) { 378 best = i; 379 best_val = abs(pdata->retune_mobile_cfgs[i].rate 380 - wm8996->rx_rate[iface]); 381 } 382 } 383 384 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 385 block, 386 pdata->retune_mobile_cfgs[best].name, 387 pdata->retune_mobile_cfgs[best].rate, 388 wm8996->rx_rate[iface]); 389 390 /* The EQ will be disabled while reconfiguring it, remember the 391 * current configuration. 392 */ 393 save = snd_soc_component_read32(component, base); 394 save &= WM8996_DSP1RX_EQ_ENA; 395 396 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) 397 snd_soc_component_update_bits(component, base + i, 0xffff, 398 pdata->retune_mobile_cfgs[best].regs[i]); 399 400 snd_soc_component_update_bits(component, base, WM8996_DSP1RX_EQ_ENA, save); 401 } 402 403 /* Icky as hell but saves code duplication */ 404 static int wm8996_get_retune_mobile_block(const char *name) 405 { 406 if (strcmp(name, "DSP1 EQ Mode") == 0) 407 return 0; 408 if (strcmp(name, "DSP2 EQ Mode") == 0) 409 return 1; 410 return -EINVAL; 411 } 412 413 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 414 struct snd_ctl_elem_value *ucontrol) 415 { 416 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 417 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 418 struct wm8996_pdata *pdata = &wm8996->pdata; 419 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 420 int value = ucontrol->value.enumerated.item[0]; 421 422 if (block < 0) 423 return block; 424 425 if (value >= pdata->num_retune_mobile_cfgs) 426 return -EINVAL; 427 428 wm8996->retune_mobile_cfg[block] = value; 429 430 wm8996_set_retune_mobile(component, block); 431 432 return 0; 433 } 434 435 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 436 struct snd_ctl_elem_value *ucontrol) 437 { 438 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 439 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 440 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 441 442 if (block < 0) 443 return block; 444 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; 445 446 return 0; 447 } 448 449 static const struct snd_kcontrol_new wm8996_snd_controls[] = { 450 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, 451 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), 452 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, 453 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), 454 455 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, 456 0, 5, 24, 0, sidetone_tlv), 457 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, 458 0, 5, 24, 0, sidetone_tlv), 459 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), 460 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), 461 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), 462 463 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, 464 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 465 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, 466 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 467 468 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, 469 13, 1, 0), 470 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), 471 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), 472 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), 473 474 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, 475 13, 1, 0), 476 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), 477 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), 478 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), 479 480 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, 481 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 482 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), 483 484 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, 485 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 486 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), 487 488 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, 489 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 490 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, 491 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), 492 493 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, 494 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 495 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, 496 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), 497 498 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), 499 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), 500 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), 501 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), 502 503 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), 504 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), 505 506 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), 507 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), 508 509 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, 510 0, threedstereo_tlv), 511 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, 512 0, threedstereo_tlv), 513 514 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, 515 8, 0, out_digital_tlv), 516 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, 517 8, 0, out_digital_tlv), 518 519 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, 520 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), 521 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, 522 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), 523 524 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, 525 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), 526 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, 527 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), 528 529 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, 530 spk_tlv), 531 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, 532 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), 533 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, 534 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), 535 536 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), 537 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), 538 539 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0), 540 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0), 541 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0), 542 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5, 543 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA | 544 WM8996_DSP1TXR_DRC_ENA), 545 546 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0), 547 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0), 548 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0), 549 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5, 550 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA | 551 WM8996_DSP2TXR_DRC_ENA), 552 }; 553 554 static const struct snd_kcontrol_new wm8996_eq_controls[] = { 555 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, 556 eq_tlv), 557 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, 558 eq_tlv), 559 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, 560 eq_tlv), 561 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, 562 eq_tlv), 563 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, 564 eq_tlv), 565 566 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, 567 eq_tlv), 568 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, 569 eq_tlv), 570 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, 571 eq_tlv), 572 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, 573 eq_tlv), 574 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, 575 eq_tlv), 576 }; 577 578 static void wm8996_bg_enable(struct snd_soc_component *component) 579 { 580 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 581 582 wm8996->bg_ena++; 583 if (wm8996->bg_ena == 1) { 584 snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1, 585 WM8996_BG_ENA, WM8996_BG_ENA); 586 msleep(2); 587 } 588 } 589 590 static void wm8996_bg_disable(struct snd_soc_component *component) 591 { 592 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 593 594 wm8996->bg_ena--; 595 if (!wm8996->bg_ena) 596 snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1, 597 WM8996_BG_ENA, 0); 598 } 599 600 static int bg_event(struct snd_soc_dapm_widget *w, 601 struct snd_kcontrol *kcontrol, int event) 602 { 603 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 604 int ret = 0; 605 606 switch (event) { 607 case SND_SOC_DAPM_PRE_PMU: 608 wm8996_bg_enable(component); 609 break; 610 case SND_SOC_DAPM_POST_PMD: 611 wm8996_bg_disable(component); 612 break; 613 default: 614 WARN(1, "Invalid event %d\n", event); 615 ret = -EINVAL; 616 } 617 618 return ret; 619 } 620 621 static int cp_event(struct snd_soc_dapm_widget *w, 622 struct snd_kcontrol *kcontrol, int event) 623 { 624 switch (event) { 625 case SND_SOC_DAPM_POST_PMU: 626 msleep(5); 627 break; 628 default: 629 WARN(1, "Invalid event %d\n", event); 630 } 631 632 return 0; 633 } 634 635 static int rmv_short_event(struct snd_soc_dapm_widget *w, 636 struct snd_kcontrol *kcontrol, int event) 637 { 638 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 639 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 640 641 /* Record which outputs we enabled */ 642 switch (event) { 643 case SND_SOC_DAPM_PRE_PMD: 644 wm8996->hpout_pending &= ~w->shift; 645 break; 646 case SND_SOC_DAPM_PRE_PMU: 647 wm8996->hpout_pending |= w->shift; 648 break; 649 default: 650 WARN(1, "Invalid event %d\n", event); 651 return -EINVAL; 652 } 653 654 return 0; 655 } 656 657 static void wait_for_dc_servo(struct snd_soc_component *component, u16 mask) 658 { 659 struct i2c_client *i2c = to_i2c_client(component->dev); 660 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 661 int ret; 662 unsigned long timeout = 200; 663 664 snd_soc_component_write(component, WM8996_DC_SERVO_2, mask); 665 666 /* Use the interrupt if possible */ 667 do { 668 if (i2c->irq) { 669 timeout = wait_for_completion_timeout(&wm8996->dcs_done, 670 msecs_to_jiffies(200)); 671 if (timeout == 0) 672 dev_err(component->dev, "DC servo timed out\n"); 673 674 } else { 675 msleep(1); 676 timeout--; 677 } 678 679 ret = snd_soc_component_read32(component, WM8996_DC_SERVO_2); 680 dev_dbg(component->dev, "DC servo state: %x\n", ret); 681 } while (timeout && ret & mask); 682 683 if (timeout == 0) 684 dev_err(component->dev, "DC servo timed out for %x\n", mask); 685 else 686 dev_dbg(component->dev, "DC servo complete for %x\n", mask); 687 } 688 689 static void wm8996_seq_notifier(struct snd_soc_component *component, 690 enum snd_soc_dapm_type event, int subseq) 691 { 692 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 693 u16 val, mask; 694 695 /* Complete any pending DC servo starts */ 696 if (wm8996->dcs_pending) { 697 dev_dbg(component->dev, "Starting DC servo for %x\n", 698 wm8996->dcs_pending); 699 700 /* Trigger a startup sequence */ 701 wait_for_dc_servo(component, wm8996->dcs_pending 702 << WM8996_DCS_TRIG_STARTUP_0_SHIFT); 703 704 wm8996->dcs_pending = 0; 705 } 706 707 if (wm8996->hpout_pending != wm8996->hpout_ena) { 708 dev_dbg(component->dev, "Applying RMV_SHORTs %x->%x\n", 709 wm8996->hpout_ena, wm8996->hpout_pending); 710 711 val = 0; 712 mask = 0; 713 if (wm8996->hpout_pending & HPOUT1L) { 714 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 715 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 716 } else { 717 mask |= WM8996_HPOUT1L_RMV_SHORT | 718 WM8996_HPOUT1L_OUTP | 719 WM8996_HPOUT1L_DLY; 720 } 721 722 if (wm8996->hpout_pending & HPOUT1R) { 723 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 724 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 725 } else { 726 mask |= WM8996_HPOUT1R_RMV_SHORT | 727 WM8996_HPOUT1R_OUTP | 728 WM8996_HPOUT1R_DLY; 729 } 730 731 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val); 732 733 val = 0; 734 mask = 0; 735 if (wm8996->hpout_pending & HPOUT2L) { 736 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 737 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 738 } else { 739 mask |= WM8996_HPOUT2L_RMV_SHORT | 740 WM8996_HPOUT2L_OUTP | 741 WM8996_HPOUT2L_DLY; 742 } 743 744 if (wm8996->hpout_pending & HPOUT2R) { 745 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 746 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 747 } else { 748 mask |= WM8996_HPOUT2R_RMV_SHORT | 749 WM8996_HPOUT2R_OUTP | 750 WM8996_HPOUT2R_DLY; 751 } 752 753 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val); 754 755 wm8996->hpout_ena = wm8996->hpout_pending; 756 } 757 } 758 759 static int dcs_start(struct snd_soc_dapm_widget *w, 760 struct snd_kcontrol *kcontrol, int event) 761 { 762 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 763 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 764 765 switch (event) { 766 case SND_SOC_DAPM_POST_PMU: 767 wm8996->dcs_pending |= 1 << w->shift; 768 break; 769 default: 770 WARN(1, "Invalid event %d\n", event); 771 return -EINVAL; 772 } 773 774 return 0; 775 } 776 777 static const char *sidetone_text[] = { 778 "IN1", "IN2", 779 }; 780 781 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum, 782 WM8996_SIDETONE, 0, sidetone_text); 783 784 static const struct snd_kcontrol_new left_sidetone = 785 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); 786 787 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum, 788 WM8996_SIDETONE, 1, sidetone_text); 789 790 static const struct snd_kcontrol_new right_sidetone = 791 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); 792 793 static const char *spk_text[] = { 794 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 795 }; 796 797 static SOC_ENUM_SINGLE_DECL(spkl_enum, 798 WM8996_LEFT_PDM_SPEAKER, 0, spk_text); 799 800 static const struct snd_kcontrol_new spkl_mux = 801 SOC_DAPM_ENUM("SPKL", spkl_enum); 802 803 static SOC_ENUM_SINGLE_DECL(spkr_enum, 804 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text); 805 806 static const struct snd_kcontrol_new spkr_mux = 807 SOC_DAPM_ENUM("SPKR", spkr_enum); 808 809 static const char *dsp1rx_text[] = { 810 "AIF1", "AIF2" 811 }; 812 813 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum, 814 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text); 815 816 static const struct snd_kcontrol_new dsp1rx = 817 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 818 819 static const char *dsp2rx_text[] = { 820 "AIF2", "AIF1" 821 }; 822 823 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum, 824 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text); 825 826 static const struct snd_kcontrol_new dsp2rx = 827 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 828 829 static const char *aif2tx_text[] = { 830 "DSP2", "DSP1", "AIF1" 831 }; 832 833 static SOC_ENUM_SINGLE_DECL(aif2tx_enum, 834 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text); 835 836 static const struct snd_kcontrol_new aif2tx = 837 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 838 839 static const char *inmux_text[] = { 840 "ADC", "DMIC1", "DMIC2" 841 }; 842 843 static SOC_ENUM_SINGLE_DECL(in1_enum, 844 WM8996_POWER_MANAGEMENT_7, 0, inmux_text); 845 846 static const struct snd_kcontrol_new in1_mux = 847 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 848 849 static SOC_ENUM_SINGLE_DECL(in2_enum, 850 WM8996_POWER_MANAGEMENT_7, 4, inmux_text); 851 852 static const struct snd_kcontrol_new in2_mux = 853 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 854 855 static const struct snd_kcontrol_new dac2r_mix[] = { 856 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 857 5, 1, 0), 858 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 859 4, 1, 0), 860 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), 861 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), 862 }; 863 864 static const struct snd_kcontrol_new dac2l_mix[] = { 865 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 866 5, 1, 0), 867 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 868 4, 1, 0), 869 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), 870 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), 871 }; 872 873 static const struct snd_kcontrol_new dac1r_mix[] = { 874 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 875 5, 1, 0), 876 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 877 4, 1, 0), 878 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), 879 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), 880 }; 881 882 static const struct snd_kcontrol_new dac1l_mix[] = { 883 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 884 5, 1, 0), 885 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 886 4, 1, 0), 887 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), 888 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), 889 }; 890 891 static const struct snd_kcontrol_new dsp1txl[] = { 892 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 893 1, 1, 0), 894 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 895 0, 1, 0), 896 }; 897 898 static const struct snd_kcontrol_new dsp1txr[] = { 899 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 900 1, 1, 0), 901 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 902 0, 1, 0), 903 }; 904 905 static const struct snd_kcontrol_new dsp2txl[] = { 906 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 907 1, 1, 0), 908 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 909 0, 1, 0), 910 }; 911 912 static const struct snd_kcontrol_new dsp2txr[] = { 913 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 914 1, 1, 0), 915 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 916 0, 1, 0), 917 }; 918 919 920 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { 921 SND_SOC_DAPM_INPUT("IN1LN"), 922 SND_SOC_DAPM_INPUT("IN1LP"), 923 SND_SOC_DAPM_INPUT("IN1RN"), 924 SND_SOC_DAPM_INPUT("IN1RP"), 925 926 SND_SOC_DAPM_INPUT("IN2LN"), 927 SND_SOC_DAPM_INPUT("IN2LP"), 928 SND_SOC_DAPM_INPUT("IN2RN"), 929 SND_SOC_DAPM_INPUT("IN2RP"), 930 931 SND_SOC_DAPM_INPUT("DMIC1DAT"), 932 SND_SOC_DAPM_INPUT("DMIC2DAT"), 933 934 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), 935 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), 936 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), 937 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), 938 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, 939 SND_SOC_DAPM_POST_PMU), 940 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event, 941 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 942 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 943 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), 944 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), 945 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), 946 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), 947 948 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 949 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 950 951 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), 952 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), 953 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), 954 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), 955 956 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), 957 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), 958 959 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), 960 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), 961 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), 962 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), 963 964 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), 965 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), 966 967 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), 968 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), 969 970 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), 971 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), 972 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), 973 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), 974 975 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, 976 dsp2txl, ARRAY_SIZE(dsp2txl)), 977 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, 978 dsp2txr, ARRAY_SIZE(dsp2txr)), 979 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, 980 dsp1txl, ARRAY_SIZE(dsp1txl)), 981 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, 982 dsp1txr, ARRAY_SIZE(dsp1txr)), 983 984 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, 985 dac2l_mix, ARRAY_SIZE(dac2l_mix)), 986 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, 987 dac2r_mix, ARRAY_SIZE(dac2r_mix)), 988 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 989 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 990 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 991 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 992 993 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), 994 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), 995 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), 996 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), 997 998 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0), 999 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0), 1000 1001 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0), 1002 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0), 1003 1004 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0), 1005 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0), 1006 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0), 1007 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0), 1008 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0), 1009 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0), 1010 1011 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0), 1012 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0), 1013 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0), 1014 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0), 1015 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0), 1016 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0), 1017 1018 /* We route as stereo pairs so define some dummy widgets to squash 1019 * things down for now. RXA = 0,1, RXB = 2,3 and so on */ 1020 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), 1021 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), 1022 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), 1024 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), 1025 1026 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), 1027 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), 1028 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), 1029 1030 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), 1031 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), 1032 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), 1033 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), 1034 1035 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), 1036 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), 1037 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, 1038 SND_SOC_DAPM_POST_PMU), 1039 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, 1040 rmv_short_event, 1041 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1042 1043 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), 1044 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), 1045 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, 1046 SND_SOC_DAPM_POST_PMU), 1047 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, 1048 rmv_short_event, 1049 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1050 1051 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 1052 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), 1053 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, 1054 SND_SOC_DAPM_POST_PMU), 1055 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, 1056 rmv_short_event, 1057 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1058 1059 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 1060 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), 1061 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, 1062 SND_SOC_DAPM_POST_PMU), 1063 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, 1064 rmv_short_event, 1065 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1066 1067 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1068 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1069 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1070 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1071 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1072 }; 1073 1074 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { 1075 { "AIFCLK", NULL, "SYSCLK" }, 1076 { "SYSDSPCLK", NULL, "SYSCLK" }, 1077 { "Charge Pump", NULL, "SYSCLK" }, 1078 { "Charge Pump", NULL, "CPVDD" }, 1079 1080 { "MICB1", NULL, "LDO2" }, 1081 { "MICB1", NULL, "MICB1 Audio" }, 1082 { "MICB1", NULL, "Bandgap" }, 1083 { "MICB2", NULL, "LDO2" }, 1084 { "MICB2", NULL, "MICB2 Audio" }, 1085 { "MICB2", NULL, "Bandgap" }, 1086 1087 { "AIF1RX0", NULL, "AIF1 Playback" }, 1088 { "AIF1RX1", NULL, "AIF1 Playback" }, 1089 { "AIF1RX2", NULL, "AIF1 Playback" }, 1090 { "AIF1RX3", NULL, "AIF1 Playback" }, 1091 { "AIF1RX4", NULL, "AIF1 Playback" }, 1092 { "AIF1RX5", NULL, "AIF1 Playback" }, 1093 1094 { "AIF2RX0", NULL, "AIF2 Playback" }, 1095 { "AIF2RX1", NULL, "AIF2 Playback" }, 1096 1097 { "AIF1 Capture", NULL, "AIF1TX0" }, 1098 { "AIF1 Capture", NULL, "AIF1TX1" }, 1099 { "AIF1 Capture", NULL, "AIF1TX2" }, 1100 { "AIF1 Capture", NULL, "AIF1TX3" }, 1101 { "AIF1 Capture", NULL, "AIF1TX4" }, 1102 { "AIF1 Capture", NULL, "AIF1TX5" }, 1103 1104 { "AIF2 Capture", NULL, "AIF2TX0" }, 1105 { "AIF2 Capture", NULL, "AIF2TX1" }, 1106 1107 { "IN1L PGA", NULL, "IN2LN" }, 1108 { "IN1L PGA", NULL, "IN2LP" }, 1109 { "IN1L PGA", NULL, "IN1LN" }, 1110 { "IN1L PGA", NULL, "IN1LP" }, 1111 { "IN1L PGA", NULL, "Bandgap" }, 1112 1113 { "IN1R PGA", NULL, "IN2RN" }, 1114 { "IN1R PGA", NULL, "IN2RP" }, 1115 { "IN1R PGA", NULL, "IN1RN" }, 1116 { "IN1R PGA", NULL, "IN1RP" }, 1117 { "IN1R PGA", NULL, "Bandgap" }, 1118 1119 { "ADCL", NULL, "IN1L PGA" }, 1120 1121 { "ADCR", NULL, "IN1R PGA" }, 1122 1123 { "DMIC1L", NULL, "DMIC1DAT" }, 1124 { "DMIC1R", NULL, "DMIC1DAT" }, 1125 { "DMIC2L", NULL, "DMIC2DAT" }, 1126 { "DMIC2R", NULL, "DMIC2DAT" }, 1127 1128 { "DMIC2L", NULL, "DMIC2" }, 1129 { "DMIC2R", NULL, "DMIC2" }, 1130 { "DMIC1L", NULL, "DMIC1" }, 1131 { "DMIC1R", NULL, "DMIC1" }, 1132 1133 { "IN1L Mux", "ADC", "ADCL" }, 1134 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1135 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1136 1137 { "IN1R Mux", "ADC", "ADCR" }, 1138 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1139 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1140 1141 { "IN2L Mux", "ADC", "ADCL" }, 1142 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1143 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1144 1145 { "IN2R Mux", "ADC", "ADCR" }, 1146 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1147 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1148 1149 { "Left Sidetone", "IN1", "IN1L Mux" }, 1150 { "Left Sidetone", "IN2", "IN2L Mux" }, 1151 1152 { "Right Sidetone", "IN1", "IN1R Mux" }, 1153 { "Right Sidetone", "IN2", "IN2R Mux" }, 1154 1155 { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, 1156 { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, 1157 1158 { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, 1159 { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, 1160 1161 { "AIF1TX0", NULL, "DSP1TXL" }, 1162 { "AIF1TX1", NULL, "DSP1TXR" }, 1163 { "AIF1TX2", NULL, "DSP2TXL" }, 1164 { "AIF1TX3", NULL, "DSP2TXR" }, 1165 { "AIF1TX4", NULL, "AIF2RX0" }, 1166 { "AIF1TX5", NULL, "AIF2RX1" }, 1167 1168 { "AIF1RX0", NULL, "AIFCLK" }, 1169 { "AIF1RX1", NULL, "AIFCLK" }, 1170 { "AIF1RX2", NULL, "AIFCLK" }, 1171 { "AIF1RX3", NULL, "AIFCLK" }, 1172 { "AIF1RX4", NULL, "AIFCLK" }, 1173 { "AIF1RX5", NULL, "AIFCLK" }, 1174 1175 { "AIF2RX0", NULL, "AIFCLK" }, 1176 { "AIF2RX1", NULL, "AIFCLK" }, 1177 1178 { "AIF1TX0", NULL, "AIFCLK" }, 1179 { "AIF1TX1", NULL, "AIFCLK" }, 1180 { "AIF1TX2", NULL, "AIFCLK" }, 1181 { "AIF1TX3", NULL, "AIFCLK" }, 1182 { "AIF1TX4", NULL, "AIFCLK" }, 1183 { "AIF1TX5", NULL, "AIFCLK" }, 1184 1185 { "AIF2TX0", NULL, "AIFCLK" }, 1186 { "AIF2TX1", NULL, "AIFCLK" }, 1187 1188 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1189 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1190 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1191 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1192 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1193 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1194 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1195 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1196 1197 { "AIF1RXA", NULL, "AIF1RX0" }, 1198 { "AIF1RXA", NULL, "AIF1RX1" }, 1199 { "AIF1RXB", NULL, "AIF1RX2" }, 1200 { "AIF1RXB", NULL, "AIF1RX3" }, 1201 { "AIF1RXC", NULL, "AIF1RX4" }, 1202 { "AIF1RXC", NULL, "AIF1RX5" }, 1203 1204 { "AIF2RX", NULL, "AIF2RX0" }, 1205 { "AIF2RX", NULL, "AIF2RX1" }, 1206 1207 { "AIF2TX", "DSP2", "DSP2TX" }, 1208 { "AIF2TX", "DSP1", "DSP1RX" }, 1209 { "AIF2TX", "AIF1", "AIF1RXC" }, 1210 1211 { "DSP1RXL", NULL, "DSP1RX" }, 1212 { "DSP1RXR", NULL, "DSP1RX" }, 1213 { "DSP2RXL", NULL, "DSP2RX" }, 1214 { "DSP2RXR", NULL, "DSP2RX" }, 1215 1216 { "DSP2TX", NULL, "DSP2TXL" }, 1217 { "DSP2TX", NULL, "DSP2TXR" }, 1218 1219 { "DSP1RX", "AIF1", "AIF1RXA" }, 1220 { "DSP1RX", "AIF2", "AIF2RX" }, 1221 1222 { "DSP2RX", "AIF1", "AIF1RXB" }, 1223 { "DSP2RX", "AIF2", "AIF2RX" }, 1224 1225 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, 1226 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, 1227 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1228 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1229 1230 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, 1231 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, 1232 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1233 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1234 1235 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, 1236 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, 1237 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1238 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1239 1240 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, 1241 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, 1242 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1243 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1244 1245 { "DAC1L", NULL, "DAC1L Mixer" }, 1246 { "DAC1R", NULL, "DAC1R Mixer" }, 1247 { "DAC2L", NULL, "DAC2L Mixer" }, 1248 { "DAC2R", NULL, "DAC2R Mixer" }, 1249 1250 { "HPOUT2L PGA", NULL, "Charge Pump" }, 1251 { "HPOUT2L PGA", NULL, "Bandgap" }, 1252 { "HPOUT2L PGA", NULL, "DAC2L" }, 1253 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, 1254 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, 1255 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" }, 1256 1257 { "HPOUT2R PGA", NULL, "Charge Pump" }, 1258 { "HPOUT2R PGA", NULL, "Bandgap" }, 1259 { "HPOUT2R PGA", NULL, "DAC2R" }, 1260 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, 1261 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, 1262 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" }, 1263 1264 { "HPOUT1L PGA", NULL, "Charge Pump" }, 1265 { "HPOUT1L PGA", NULL, "Bandgap" }, 1266 { "HPOUT1L PGA", NULL, "DAC1L" }, 1267 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, 1268 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, 1269 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" }, 1270 1271 { "HPOUT1R PGA", NULL, "Charge Pump" }, 1272 { "HPOUT1R PGA", NULL, "Bandgap" }, 1273 { "HPOUT1R PGA", NULL, "DAC1R" }, 1274 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, 1275 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, 1276 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" }, 1277 1278 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, 1279 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, 1280 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, 1281 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, 1282 1283 { "SPKL", "DAC1L", "DAC1L" }, 1284 { "SPKL", "DAC1R", "DAC1R" }, 1285 { "SPKL", "DAC2L", "DAC2L" }, 1286 { "SPKL", "DAC2R", "DAC2R" }, 1287 1288 { "SPKR", "DAC1L", "DAC1L" }, 1289 { "SPKR", "DAC1R", "DAC1R" }, 1290 { "SPKR", "DAC2L", "DAC2L" }, 1291 { "SPKR", "DAC2R", "DAC2R" }, 1292 1293 { "SPKL PGA", NULL, "SPKL" }, 1294 { "SPKR PGA", NULL, "SPKR" }, 1295 1296 { "SPKDAT", NULL, "SPKL PGA" }, 1297 { "SPKDAT", NULL, "SPKR PGA" }, 1298 }; 1299 1300 static bool wm8996_readable_register(struct device *dev, unsigned int reg) 1301 { 1302 /* Due to the sparseness of the register map the compiler 1303 * output from an explicit switch statement ends up being much 1304 * more efficient than a table. 1305 */ 1306 switch (reg) { 1307 case WM8996_SOFTWARE_RESET: 1308 case WM8996_POWER_MANAGEMENT_1: 1309 case WM8996_POWER_MANAGEMENT_2: 1310 case WM8996_POWER_MANAGEMENT_3: 1311 case WM8996_POWER_MANAGEMENT_4: 1312 case WM8996_POWER_MANAGEMENT_5: 1313 case WM8996_POWER_MANAGEMENT_6: 1314 case WM8996_POWER_MANAGEMENT_7: 1315 case WM8996_POWER_MANAGEMENT_8: 1316 case WM8996_LEFT_LINE_INPUT_VOLUME: 1317 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1318 case WM8996_LINE_INPUT_CONTROL: 1319 case WM8996_DAC1_HPOUT1_VOLUME: 1320 case WM8996_DAC2_HPOUT2_VOLUME: 1321 case WM8996_DAC1_LEFT_VOLUME: 1322 case WM8996_DAC1_RIGHT_VOLUME: 1323 case WM8996_DAC2_LEFT_VOLUME: 1324 case WM8996_DAC2_RIGHT_VOLUME: 1325 case WM8996_OUTPUT1_LEFT_VOLUME: 1326 case WM8996_OUTPUT1_RIGHT_VOLUME: 1327 case WM8996_OUTPUT2_LEFT_VOLUME: 1328 case WM8996_OUTPUT2_RIGHT_VOLUME: 1329 case WM8996_MICBIAS_1: 1330 case WM8996_MICBIAS_2: 1331 case WM8996_LDO_1: 1332 case WM8996_LDO_2: 1333 case WM8996_ACCESSORY_DETECT_MODE_1: 1334 case WM8996_ACCESSORY_DETECT_MODE_2: 1335 case WM8996_HEADPHONE_DETECT_1: 1336 case WM8996_HEADPHONE_DETECT_2: 1337 case WM8996_MIC_DETECT_1: 1338 case WM8996_MIC_DETECT_2: 1339 case WM8996_MIC_DETECT_3: 1340 case WM8996_CHARGE_PUMP_1: 1341 case WM8996_CHARGE_PUMP_2: 1342 case WM8996_DC_SERVO_1: 1343 case WM8996_DC_SERVO_2: 1344 case WM8996_DC_SERVO_3: 1345 case WM8996_DC_SERVO_5: 1346 case WM8996_DC_SERVO_6: 1347 case WM8996_DC_SERVO_7: 1348 case WM8996_DC_SERVO_READBACK_0: 1349 case WM8996_ANALOGUE_HP_1: 1350 case WM8996_ANALOGUE_HP_2: 1351 case WM8996_CHIP_REVISION: 1352 case WM8996_CONTROL_INTERFACE_1: 1353 case WM8996_WRITE_SEQUENCER_CTRL_1: 1354 case WM8996_WRITE_SEQUENCER_CTRL_2: 1355 case WM8996_AIF_CLOCKING_1: 1356 case WM8996_AIF_CLOCKING_2: 1357 case WM8996_CLOCKING_1: 1358 case WM8996_CLOCKING_2: 1359 case WM8996_AIF_RATE: 1360 case WM8996_FLL_CONTROL_1: 1361 case WM8996_FLL_CONTROL_2: 1362 case WM8996_FLL_CONTROL_3: 1363 case WM8996_FLL_CONTROL_4: 1364 case WM8996_FLL_CONTROL_5: 1365 case WM8996_FLL_CONTROL_6: 1366 case WM8996_FLL_EFS_1: 1367 case WM8996_FLL_EFS_2: 1368 case WM8996_AIF1_CONTROL: 1369 case WM8996_AIF1_BCLK: 1370 case WM8996_AIF1_TX_LRCLK_1: 1371 case WM8996_AIF1_TX_LRCLK_2: 1372 case WM8996_AIF1_RX_LRCLK_1: 1373 case WM8996_AIF1_RX_LRCLK_2: 1374 case WM8996_AIF1TX_DATA_CONFIGURATION_1: 1375 case WM8996_AIF1TX_DATA_CONFIGURATION_2: 1376 case WM8996_AIF1RX_DATA_CONFIGURATION: 1377 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: 1378 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: 1379 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: 1380 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: 1381 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: 1382 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: 1383 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: 1384 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: 1385 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: 1386 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: 1387 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: 1388 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: 1389 case WM8996_AIF1RX_MONO_CONFIGURATION: 1390 case WM8996_AIF1TX_TEST: 1391 case WM8996_AIF2_CONTROL: 1392 case WM8996_AIF2_BCLK: 1393 case WM8996_AIF2_TX_LRCLK_1: 1394 case WM8996_AIF2_TX_LRCLK_2: 1395 case WM8996_AIF2_RX_LRCLK_1: 1396 case WM8996_AIF2_RX_LRCLK_2: 1397 case WM8996_AIF2TX_DATA_CONFIGURATION_1: 1398 case WM8996_AIF2TX_DATA_CONFIGURATION_2: 1399 case WM8996_AIF2RX_DATA_CONFIGURATION: 1400 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: 1401 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: 1402 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: 1403 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: 1404 case WM8996_AIF2RX_MONO_CONFIGURATION: 1405 case WM8996_AIF2TX_TEST: 1406 case WM8996_DSP1_TX_LEFT_VOLUME: 1407 case WM8996_DSP1_TX_RIGHT_VOLUME: 1408 case WM8996_DSP1_RX_LEFT_VOLUME: 1409 case WM8996_DSP1_RX_RIGHT_VOLUME: 1410 case WM8996_DSP1_TX_FILTERS: 1411 case WM8996_DSP1_RX_FILTERS_1: 1412 case WM8996_DSP1_RX_FILTERS_2: 1413 case WM8996_DSP1_DRC_1: 1414 case WM8996_DSP1_DRC_2: 1415 case WM8996_DSP1_DRC_3: 1416 case WM8996_DSP1_DRC_4: 1417 case WM8996_DSP1_DRC_5: 1418 case WM8996_DSP1_RX_EQ_GAINS_1: 1419 case WM8996_DSP1_RX_EQ_GAINS_2: 1420 case WM8996_DSP1_RX_EQ_BAND_1_A: 1421 case WM8996_DSP1_RX_EQ_BAND_1_B: 1422 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1423 case WM8996_DSP1_RX_EQ_BAND_2_A: 1424 case WM8996_DSP1_RX_EQ_BAND_2_B: 1425 case WM8996_DSP1_RX_EQ_BAND_2_C: 1426 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1427 case WM8996_DSP1_RX_EQ_BAND_3_A: 1428 case WM8996_DSP1_RX_EQ_BAND_3_B: 1429 case WM8996_DSP1_RX_EQ_BAND_3_C: 1430 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1431 case WM8996_DSP1_RX_EQ_BAND_4_A: 1432 case WM8996_DSP1_RX_EQ_BAND_4_B: 1433 case WM8996_DSP1_RX_EQ_BAND_4_C: 1434 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1435 case WM8996_DSP1_RX_EQ_BAND_5_A: 1436 case WM8996_DSP1_RX_EQ_BAND_5_B: 1437 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1438 case WM8996_DSP2_TX_LEFT_VOLUME: 1439 case WM8996_DSP2_TX_RIGHT_VOLUME: 1440 case WM8996_DSP2_RX_LEFT_VOLUME: 1441 case WM8996_DSP2_RX_RIGHT_VOLUME: 1442 case WM8996_DSP2_TX_FILTERS: 1443 case WM8996_DSP2_RX_FILTERS_1: 1444 case WM8996_DSP2_RX_FILTERS_2: 1445 case WM8996_DSP2_DRC_1: 1446 case WM8996_DSP2_DRC_2: 1447 case WM8996_DSP2_DRC_3: 1448 case WM8996_DSP2_DRC_4: 1449 case WM8996_DSP2_DRC_5: 1450 case WM8996_DSP2_RX_EQ_GAINS_1: 1451 case WM8996_DSP2_RX_EQ_GAINS_2: 1452 case WM8996_DSP2_RX_EQ_BAND_1_A: 1453 case WM8996_DSP2_RX_EQ_BAND_1_B: 1454 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1455 case WM8996_DSP2_RX_EQ_BAND_2_A: 1456 case WM8996_DSP2_RX_EQ_BAND_2_B: 1457 case WM8996_DSP2_RX_EQ_BAND_2_C: 1458 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1459 case WM8996_DSP2_RX_EQ_BAND_3_A: 1460 case WM8996_DSP2_RX_EQ_BAND_3_B: 1461 case WM8996_DSP2_RX_EQ_BAND_3_C: 1462 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1463 case WM8996_DSP2_RX_EQ_BAND_4_A: 1464 case WM8996_DSP2_RX_EQ_BAND_4_B: 1465 case WM8996_DSP2_RX_EQ_BAND_4_C: 1466 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1467 case WM8996_DSP2_RX_EQ_BAND_5_A: 1468 case WM8996_DSP2_RX_EQ_BAND_5_B: 1469 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1470 case WM8996_DAC1_MIXER_VOLUMES: 1471 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1472 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1473 case WM8996_DAC2_MIXER_VOLUMES: 1474 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1475 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1476 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: 1477 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: 1478 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: 1479 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: 1480 case WM8996_DSP_TX_MIXER_SELECT: 1481 case WM8996_DAC_SOFTMUTE: 1482 case WM8996_OVERSAMPLING: 1483 case WM8996_SIDETONE: 1484 case WM8996_GPIO_1: 1485 case WM8996_GPIO_2: 1486 case WM8996_GPIO_3: 1487 case WM8996_GPIO_4: 1488 case WM8996_GPIO_5: 1489 case WM8996_PULL_CONTROL_1: 1490 case WM8996_PULL_CONTROL_2: 1491 case WM8996_INTERRUPT_STATUS_1: 1492 case WM8996_INTERRUPT_STATUS_2: 1493 case WM8996_INTERRUPT_RAW_STATUS_2: 1494 case WM8996_INTERRUPT_STATUS_1_MASK: 1495 case WM8996_INTERRUPT_STATUS_2_MASK: 1496 case WM8996_INTERRUPT_CONTROL: 1497 case WM8996_LEFT_PDM_SPEAKER: 1498 case WM8996_RIGHT_PDM_SPEAKER: 1499 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: 1500 case WM8996_PDM_SPEAKER_VOLUME: 1501 return true; 1502 default: 1503 return false; 1504 } 1505 } 1506 1507 static bool wm8996_volatile_register(struct device *dev, unsigned int reg) 1508 { 1509 switch (reg) { 1510 case WM8996_SOFTWARE_RESET: 1511 case WM8996_CHIP_REVISION: 1512 case WM8996_LDO_1: 1513 case WM8996_LDO_2: 1514 case WM8996_INTERRUPT_STATUS_1: 1515 case WM8996_INTERRUPT_STATUS_2: 1516 case WM8996_INTERRUPT_RAW_STATUS_2: 1517 case WM8996_DC_SERVO_READBACK_0: 1518 case WM8996_DC_SERVO_2: 1519 case WM8996_DC_SERVO_6: 1520 case WM8996_DC_SERVO_7: 1521 case WM8996_FLL_CONTROL_6: 1522 case WM8996_MIC_DETECT_3: 1523 case WM8996_HEADPHONE_DETECT_1: 1524 case WM8996_HEADPHONE_DETECT_2: 1525 return true; 1526 default: 1527 return false; 1528 } 1529 } 1530 1531 static const int bclk_divs[] = { 1532 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 1533 }; 1534 1535 static void wm8996_update_bclk(struct snd_soc_component *component) 1536 { 1537 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 1538 int aif, best, cur_val, bclk_rate, bclk_reg, i; 1539 1540 /* Don't bother if we're in a low frequency idle mode that 1541 * can't support audio. 1542 */ 1543 if (wm8996->sysclk < 64000) 1544 return; 1545 1546 for (aif = 0; aif < WM8996_AIFS; aif++) { 1547 switch (aif) { 1548 case 0: 1549 bclk_reg = WM8996_AIF1_BCLK; 1550 break; 1551 case 1: 1552 bclk_reg = WM8996_AIF2_BCLK; 1553 break; 1554 } 1555 1556 bclk_rate = wm8996->bclk_rate[aif]; 1557 1558 /* Pick a divisor for BCLK as close as we can get to ideal */ 1559 best = 0; 1560 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1561 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; 1562 if (cur_val < 0) /* BCLK table is sorted */ 1563 break; 1564 best = i; 1565 } 1566 bclk_rate = wm8996->sysclk / bclk_divs[best]; 1567 dev_dbg(component->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1568 bclk_divs[best], bclk_rate); 1569 1570 snd_soc_component_update_bits(component, bclk_reg, 1571 WM8996_AIF1_BCLK_DIV_MASK, best); 1572 } 1573 } 1574 1575 static int wm8996_set_bias_level(struct snd_soc_component *component, 1576 enum snd_soc_bias_level level) 1577 { 1578 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 1579 int ret; 1580 1581 switch (level) { 1582 case SND_SOC_BIAS_ON: 1583 break; 1584 case SND_SOC_BIAS_PREPARE: 1585 /* Put the MICBIASes into regulating mode */ 1586 snd_soc_component_update_bits(component, WM8996_MICBIAS_1, 1587 WM8996_MICB1_MODE, 0); 1588 snd_soc_component_update_bits(component, WM8996_MICBIAS_2, 1589 WM8996_MICB2_MODE, 0); 1590 break; 1591 1592 case SND_SOC_BIAS_STANDBY: 1593 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1594 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 1595 wm8996->supplies); 1596 if (ret != 0) { 1597 dev_err(component->dev, 1598 "Failed to enable supplies: %d\n", 1599 ret); 1600 return ret; 1601 } 1602 1603 if (wm8996->pdata.ldo_ena >= 0) { 1604 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1605 1); 1606 msleep(5); 1607 } 1608 1609 regcache_cache_only(wm8996->regmap, false); 1610 regcache_sync(wm8996->regmap); 1611 } 1612 1613 /* Bypass the MICBIASes for lowest power */ 1614 snd_soc_component_update_bits(component, WM8996_MICBIAS_1, 1615 WM8996_MICB1_MODE, WM8996_MICB1_MODE); 1616 snd_soc_component_update_bits(component, WM8996_MICBIAS_2, 1617 WM8996_MICB2_MODE, WM8996_MICB2_MODE); 1618 break; 1619 1620 case SND_SOC_BIAS_OFF: 1621 regcache_cache_only(wm8996->regmap, true); 1622 if (wm8996->pdata.ldo_ena >= 0) { 1623 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1624 regcache_cache_only(wm8996->regmap, true); 1625 } 1626 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), 1627 wm8996->supplies); 1628 break; 1629 } 1630 1631 return 0; 1632 } 1633 1634 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1635 { 1636 struct snd_soc_component *component = dai->component; 1637 int aifctrl = 0; 1638 int bclk = 0; 1639 int lrclk_tx = 0; 1640 int lrclk_rx = 0; 1641 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; 1642 1643 switch (dai->id) { 1644 case 0: 1645 aifctrl_reg = WM8996_AIF1_CONTROL; 1646 bclk_reg = WM8996_AIF1_BCLK; 1647 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; 1648 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; 1649 break; 1650 case 1: 1651 aifctrl_reg = WM8996_AIF2_CONTROL; 1652 bclk_reg = WM8996_AIF2_BCLK; 1653 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; 1654 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; 1655 break; 1656 default: 1657 WARN(1, "Invalid dai id %d\n", dai->id); 1658 return -EINVAL; 1659 } 1660 1661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1662 case SND_SOC_DAIFMT_NB_NF: 1663 break; 1664 case SND_SOC_DAIFMT_IB_NF: 1665 bclk |= WM8996_AIF1_BCLK_INV; 1666 break; 1667 case SND_SOC_DAIFMT_NB_IF: 1668 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1669 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1670 break; 1671 case SND_SOC_DAIFMT_IB_IF: 1672 bclk |= WM8996_AIF1_BCLK_INV; 1673 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1674 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1675 break; 1676 } 1677 1678 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1679 case SND_SOC_DAIFMT_CBS_CFS: 1680 break; 1681 case SND_SOC_DAIFMT_CBS_CFM: 1682 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1683 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1684 break; 1685 case SND_SOC_DAIFMT_CBM_CFS: 1686 bclk |= WM8996_AIF1_BCLK_MSTR; 1687 break; 1688 case SND_SOC_DAIFMT_CBM_CFM: 1689 bclk |= WM8996_AIF1_BCLK_MSTR; 1690 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1691 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1692 break; 1693 default: 1694 return -EINVAL; 1695 } 1696 1697 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1698 case SND_SOC_DAIFMT_DSP_A: 1699 break; 1700 case SND_SOC_DAIFMT_DSP_B: 1701 aifctrl |= 1; 1702 break; 1703 case SND_SOC_DAIFMT_I2S: 1704 aifctrl |= 2; 1705 break; 1706 case SND_SOC_DAIFMT_LEFT_J: 1707 aifctrl |= 3; 1708 break; 1709 default: 1710 return -EINVAL; 1711 } 1712 1713 snd_soc_component_update_bits(component, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); 1714 snd_soc_component_update_bits(component, bclk_reg, 1715 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, 1716 bclk); 1717 snd_soc_component_update_bits(component, lrclk_tx_reg, 1718 WM8996_AIF1TX_LRCLK_INV | 1719 WM8996_AIF1TX_LRCLK_MSTR, 1720 lrclk_tx); 1721 snd_soc_component_update_bits(component, lrclk_rx_reg, 1722 WM8996_AIF1RX_LRCLK_INV | 1723 WM8996_AIF1RX_LRCLK_MSTR, 1724 lrclk_rx); 1725 1726 return 0; 1727 } 1728 1729 static const int dsp_divs[] = { 1730 48000, 32000, 16000, 8000 1731 }; 1732 1733 static int wm8996_hw_params(struct snd_pcm_substream *substream, 1734 struct snd_pcm_hw_params *params, 1735 struct snd_soc_dai *dai) 1736 { 1737 struct snd_soc_component *component = dai->component; 1738 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 1739 int bits, i, bclk_rate, best; 1740 int aifdata = 0; 1741 int lrclk = 0; 1742 int dsp = 0; 1743 int aifdata_reg, lrclk_reg, dsp_shift; 1744 1745 switch (dai->id) { 1746 case 0: 1747 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1748 (snd_soc_component_read32(component, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { 1749 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; 1750 lrclk_reg = WM8996_AIF1_RX_LRCLK_1; 1751 } else { 1752 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; 1753 lrclk_reg = WM8996_AIF1_TX_LRCLK_1; 1754 } 1755 dsp_shift = 0; 1756 break; 1757 case 1: 1758 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1759 (snd_soc_component_read32(component, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { 1760 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; 1761 lrclk_reg = WM8996_AIF2_RX_LRCLK_1; 1762 } else { 1763 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; 1764 lrclk_reg = WM8996_AIF2_TX_LRCLK_1; 1765 } 1766 dsp_shift = WM8996_DSP2_DIV_SHIFT; 1767 break; 1768 default: 1769 WARN(1, "Invalid dai id %d\n", dai->id); 1770 return -EINVAL; 1771 } 1772 1773 bclk_rate = snd_soc_params_to_bclk(params); 1774 if (bclk_rate < 0) { 1775 dev_err(component->dev, "Unsupported BCLK rate: %d\n", bclk_rate); 1776 return bclk_rate; 1777 } 1778 1779 wm8996->bclk_rate[dai->id] = bclk_rate; 1780 wm8996->rx_rate[dai->id] = params_rate(params); 1781 1782 /* Needs looking at for TDM */ 1783 bits = params_width(params); 1784 if (bits < 0) 1785 return bits; 1786 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; 1787 1788 best = 0; 1789 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { 1790 if (abs(dsp_divs[i] - params_rate(params)) < 1791 abs(dsp_divs[best] - params_rate(params))) 1792 best = i; 1793 } 1794 dsp |= i << dsp_shift; 1795 1796 wm8996_update_bclk(component); 1797 1798 lrclk = bclk_rate / params_rate(params); 1799 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1800 lrclk, bclk_rate / lrclk); 1801 1802 snd_soc_component_update_bits(component, aifdata_reg, 1803 WM8996_AIF1TX_WL_MASK | 1804 WM8996_AIF1TX_SLOT_LEN_MASK, 1805 aifdata); 1806 snd_soc_component_update_bits(component, lrclk_reg, WM8996_AIF1RX_RATE_MASK, 1807 lrclk); 1808 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_2, 1809 WM8996_DSP1_DIV_MASK << dsp_shift, dsp); 1810 1811 return 0; 1812 } 1813 1814 static int wm8996_set_sysclk(struct snd_soc_dai *dai, 1815 int clk_id, unsigned int freq, int dir) 1816 { 1817 struct snd_soc_component *component = dai->component; 1818 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 1819 int lfclk = 0; 1820 int ratediv = 0; 1821 int sync = WM8996_REG_SYNC; 1822 int src; 1823 int old; 1824 1825 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) 1826 return 0; 1827 1828 /* Disable SYSCLK while we reconfigure */ 1829 old = snd_soc_component_read32(component, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; 1830 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1, 1831 WM8996_SYSCLK_ENA, 0); 1832 1833 switch (clk_id) { 1834 case WM8996_SYSCLK_MCLK1: 1835 wm8996->sysclk = freq; 1836 src = 0; 1837 break; 1838 case WM8996_SYSCLK_MCLK2: 1839 wm8996->sysclk = freq; 1840 src = 1; 1841 break; 1842 case WM8996_SYSCLK_FLL: 1843 wm8996->sysclk = freq; 1844 src = 2; 1845 break; 1846 default: 1847 dev_err(component->dev, "Unsupported clock source %d\n", clk_id); 1848 return -EINVAL; 1849 } 1850 1851 switch (wm8996->sysclk) { 1852 case 5644800: 1853 case 6144000: 1854 snd_soc_component_update_bits(component, WM8996_AIF_RATE, 1855 WM8996_SYSCLK_RATE, 0); 1856 break; 1857 case 22579200: 1858 case 24576000: 1859 ratediv = WM8996_SYSCLK_DIV; 1860 wm8996->sysclk /= 2; 1861 /* fall through */ 1862 case 11289600: 1863 case 12288000: 1864 snd_soc_component_update_bits(component, WM8996_AIF_RATE, 1865 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); 1866 break; 1867 case 32000: 1868 case 32768: 1869 lfclk = WM8996_LFCLK_ENA; 1870 sync = 0; 1871 break; 1872 default: 1873 dev_warn(component->dev, "Unsupported clock rate %dHz\n", 1874 wm8996->sysclk); 1875 return -EINVAL; 1876 } 1877 1878 wm8996_update_bclk(component); 1879 1880 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1, 1881 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, 1882 src << WM8996_SYSCLK_SRC_SHIFT | ratediv); 1883 snd_soc_component_update_bits(component, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); 1884 snd_soc_component_update_bits(component, WM8996_CONTROL_INTERFACE_1, 1885 WM8996_REG_SYNC, sync); 1886 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1, 1887 WM8996_SYSCLK_ENA, old); 1888 1889 wm8996->sysclk_src = clk_id; 1890 1891 return 0; 1892 } 1893 1894 struct _fll_div { 1895 u16 fll_fratio; 1896 u16 fll_outdiv; 1897 u16 fll_refclk_div; 1898 u16 fll_loop_gain; 1899 u16 fll_ref_freq; 1900 u16 n; 1901 u16 theta; 1902 u16 lambda; 1903 }; 1904 1905 static struct { 1906 unsigned int min; 1907 unsigned int max; 1908 u16 fll_fratio; 1909 int ratio; 1910 } fll_fratios[] = { 1911 { 0, 64000, 4, 16 }, 1912 { 64000, 128000, 3, 8 }, 1913 { 128000, 256000, 2, 4 }, 1914 { 256000, 1000000, 1, 2 }, 1915 { 1000000, 13500000, 0, 1 }, 1916 }; 1917 1918 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1919 unsigned int Fout) 1920 { 1921 unsigned int target; 1922 unsigned int div; 1923 unsigned int fratio, gcd_fll; 1924 int i; 1925 1926 /* Fref must be <=13.5MHz */ 1927 div = 1; 1928 fll_div->fll_refclk_div = 0; 1929 while ((Fref / div) > 13500000) { 1930 div *= 2; 1931 fll_div->fll_refclk_div++; 1932 1933 if (div > 8) { 1934 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1935 Fref); 1936 return -EINVAL; 1937 } 1938 } 1939 1940 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 1941 1942 /* Apply the division for our remaining calculations */ 1943 Fref /= div; 1944 1945 if (Fref >= 3000000) 1946 fll_div->fll_loop_gain = 5; 1947 else 1948 fll_div->fll_loop_gain = 0; 1949 1950 if (Fref >= 48000) 1951 fll_div->fll_ref_freq = 0; 1952 else 1953 fll_div->fll_ref_freq = 1; 1954 1955 /* Fvco should be 90-100MHz; don't check the upper bound */ 1956 div = 2; 1957 while (Fout * div < 90000000) { 1958 div++; 1959 if (div > 64) { 1960 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1961 Fout); 1962 return -EINVAL; 1963 } 1964 } 1965 target = Fout * div; 1966 fll_div->fll_outdiv = div - 1; 1967 1968 pr_debug("FLL Fvco=%dHz\n", target); 1969 1970 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1971 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1972 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1973 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1974 fratio = fll_fratios[i].ratio; 1975 break; 1976 } 1977 } 1978 if (i == ARRAY_SIZE(fll_fratios)) { 1979 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1980 return -EINVAL; 1981 } 1982 1983 fll_div->n = target / (fratio * Fref); 1984 1985 if (target % Fref == 0) { 1986 fll_div->theta = 0; 1987 fll_div->lambda = 0; 1988 } else { 1989 gcd_fll = gcd(target, fratio * Fref); 1990 1991 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 1992 / gcd_fll; 1993 fll_div->lambda = (fratio * Fref) / gcd_fll; 1994 } 1995 1996 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 1997 fll_div->n, fll_div->theta, fll_div->lambda); 1998 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 1999 fll_div->fll_fratio, fll_div->fll_outdiv, 2000 fll_div->fll_refclk_div); 2001 2002 return 0; 2003 } 2004 2005 static int wm8996_set_fll(struct snd_soc_component *component, int fll_id, int source, 2006 unsigned int Fref, unsigned int Fout) 2007 { 2008 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2009 struct i2c_client *i2c = to_i2c_client(component->dev); 2010 struct _fll_div fll_div; 2011 unsigned long timeout, time_left; 2012 int ret, reg, retry; 2013 2014 /* Any change? */ 2015 if (source == wm8996->fll_src && Fref == wm8996->fll_fref && 2016 Fout == wm8996->fll_fout) 2017 return 0; 2018 2019 if (Fout == 0) { 2020 dev_dbg(component->dev, "FLL disabled\n"); 2021 2022 wm8996->fll_fref = 0; 2023 wm8996->fll_fout = 0; 2024 2025 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1, 2026 WM8996_FLL_ENA, 0); 2027 2028 wm8996_bg_disable(component); 2029 2030 return 0; 2031 } 2032 2033 ret = fll_factors(&fll_div, Fref, Fout); 2034 if (ret != 0) 2035 return ret; 2036 2037 switch (source) { 2038 case WM8996_FLL_MCLK1: 2039 reg = 0; 2040 break; 2041 case WM8996_FLL_MCLK2: 2042 reg = 1; 2043 break; 2044 case WM8996_FLL_DACLRCLK1: 2045 reg = 2; 2046 break; 2047 case WM8996_FLL_BCLK1: 2048 reg = 3; 2049 break; 2050 default: 2051 dev_err(component->dev, "Unknown FLL source %d\n", ret); 2052 return -EINVAL; 2053 } 2054 2055 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; 2056 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; 2057 2058 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_5, 2059 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | 2060 WM8996_FLL_REFCLK_SRC_MASK, reg); 2061 2062 reg = 0; 2063 if (fll_div.theta || fll_div.lambda) 2064 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); 2065 else 2066 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; 2067 snd_soc_component_write(component, WM8996_FLL_EFS_2, reg); 2068 2069 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_2, 2070 WM8996_FLL_OUTDIV_MASK | 2071 WM8996_FLL_FRATIO_MASK, 2072 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | 2073 (fll_div.fll_fratio)); 2074 2075 snd_soc_component_write(component, WM8996_FLL_CONTROL_3, fll_div.theta); 2076 2077 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_4, 2078 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, 2079 (fll_div.n << WM8996_FLL_N_SHIFT) | 2080 fll_div.fll_loop_gain); 2081 2082 snd_soc_component_write(component, WM8996_FLL_EFS_1, fll_div.lambda); 2083 2084 /* Enable the bandgap if it's not already enabled */ 2085 ret = snd_soc_component_read32(component, WM8996_FLL_CONTROL_1); 2086 if (!(ret & WM8996_FLL_ENA)) 2087 wm8996_bg_enable(component); 2088 2089 /* Clear any pending completions (eg, from failed startups) */ 2090 try_wait_for_completion(&wm8996->fll_lock); 2091 2092 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1, 2093 WM8996_FLL_ENA, WM8996_FLL_ENA); 2094 2095 /* The FLL supports live reconfiguration - kick that in case we were 2096 * already enabled. 2097 */ 2098 snd_soc_component_write(component, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); 2099 2100 /* Wait for the FLL to lock, using the interrupt if possible */ 2101 if (Fref > 1000000) 2102 timeout = usecs_to_jiffies(300); 2103 else 2104 timeout = msecs_to_jiffies(2); 2105 2106 /* Allow substantially longer if we've actually got the IRQ, poll 2107 * at a slightly higher rate if we don't. 2108 */ 2109 if (i2c->irq) 2110 timeout *= 10; 2111 else 2112 /* ensure timeout of atleast 1 jiffies */ 2113 timeout = timeout/2 ? : 1; 2114 2115 for (retry = 0; retry < 10; retry++) { 2116 time_left = wait_for_completion_timeout(&wm8996->fll_lock, 2117 timeout); 2118 if (time_left != 0) { 2119 WARN_ON(!i2c->irq); 2120 ret = 1; 2121 break; 2122 } 2123 2124 ret = snd_soc_component_read32(component, WM8996_INTERRUPT_RAW_STATUS_2); 2125 if (ret & WM8996_FLL_LOCK_STS) 2126 break; 2127 } 2128 if (retry == 10) { 2129 dev_err(component->dev, "Timed out waiting for FLL\n"); 2130 ret = -ETIMEDOUT; 2131 } 2132 2133 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2134 2135 wm8996->fll_fref = Fref; 2136 wm8996->fll_fout = Fout; 2137 wm8996->fll_src = source; 2138 2139 return ret; 2140 } 2141 2142 #ifdef CONFIG_GPIOLIB 2143 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2144 { 2145 struct wm8996_priv *wm8996 = gpiochip_get_data(chip); 2146 2147 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2148 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); 2149 } 2150 2151 static int wm8996_gpio_direction_out(struct gpio_chip *chip, 2152 unsigned offset, int value) 2153 { 2154 struct wm8996_priv *wm8996 = gpiochip_get_data(chip); 2155 int val; 2156 2157 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); 2158 2159 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2160 WM8996_GP1_FN_MASK | WM8996_GP1_DIR | 2161 WM8996_GP1_LVL, val); 2162 } 2163 2164 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) 2165 { 2166 struct wm8996_priv *wm8996 = gpiochip_get_data(chip); 2167 unsigned int reg; 2168 int ret; 2169 2170 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®); 2171 if (ret < 0) 2172 return ret; 2173 2174 return (reg & WM8996_GP1_LVL) != 0; 2175 } 2176 2177 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 2178 { 2179 struct wm8996_priv *wm8996 = gpiochip_get_data(chip); 2180 2181 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2182 WM8996_GP1_FN_MASK | WM8996_GP1_DIR, 2183 (1 << WM8996_GP1_FN_SHIFT) | 2184 (1 << WM8996_GP1_DIR_SHIFT)); 2185 } 2186 2187 static const struct gpio_chip wm8996_template_chip = { 2188 .label = "wm8996", 2189 .owner = THIS_MODULE, 2190 .direction_output = wm8996_gpio_direction_out, 2191 .set = wm8996_gpio_set, 2192 .direction_input = wm8996_gpio_direction_in, 2193 .get = wm8996_gpio_get, 2194 .can_sleep = 1, 2195 }; 2196 2197 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2198 { 2199 int ret; 2200 2201 wm8996->gpio_chip = wm8996_template_chip; 2202 wm8996->gpio_chip.ngpio = 5; 2203 wm8996->gpio_chip.parent = wm8996->dev; 2204 2205 if (wm8996->pdata.gpio_base) 2206 wm8996->gpio_chip.base = wm8996->pdata.gpio_base; 2207 else 2208 wm8996->gpio_chip.base = -1; 2209 2210 ret = gpiochip_add_data(&wm8996->gpio_chip, wm8996); 2211 if (ret != 0) 2212 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret); 2213 } 2214 2215 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2216 { 2217 gpiochip_remove(&wm8996->gpio_chip); 2218 } 2219 #else 2220 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2221 { 2222 } 2223 2224 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2225 { 2226 } 2227 #endif 2228 2229 /** 2230 * wm8996_detect - Enable default WM8996 jack detection 2231 * 2232 * The WM8996 has advanced accessory detection support for headsets. 2233 * This function provides a default implementation which integrates 2234 * the majority of this functionality with minimal user configuration. 2235 * 2236 * This will detect headset, headphone and short circuit button and 2237 * will also detect inverted microphone ground connections and update 2238 * the polarity of the connections. 2239 */ 2240 int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack, 2241 wm8996_polarity_fn polarity_cb) 2242 { 2243 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2244 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2245 2246 wm8996->jack = jack; 2247 wm8996->detecting = true; 2248 wm8996->polarity_cb = polarity_cb; 2249 wm8996->jack_flips = 0; 2250 2251 if (wm8996->polarity_cb) 2252 wm8996->polarity_cb(component, 0); 2253 2254 /* Clear discarge to avoid noise during detection */ 2255 snd_soc_component_update_bits(component, WM8996_MICBIAS_1, 2256 WM8996_MICB1_DISCH, 0); 2257 snd_soc_component_update_bits(component, WM8996_MICBIAS_2, 2258 WM8996_MICB2_DISCH, 0); 2259 2260 /* LDO2 powers the microphones, SYSCLK clocks detection */ 2261 snd_soc_dapm_mutex_lock(dapm); 2262 2263 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2"); 2264 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK"); 2265 2266 snd_soc_dapm_mutex_unlock(dapm); 2267 2268 /* We start off just enabling microphone detection - even a 2269 * plain headphone will trigger detection. 2270 */ 2271 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, 2272 WM8996_MICD_ENA, WM8996_MICD_ENA); 2273 2274 /* Slowest detection rate, gives debounce for initial detection */ 2275 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, 2276 WM8996_MICD_RATE_MASK, 2277 WM8996_MICD_RATE_MASK); 2278 2279 /* Enable interrupts and we're off */ 2280 snd_soc_component_update_bits(component, WM8996_INTERRUPT_STATUS_2_MASK, 2281 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0); 2282 2283 return 0; 2284 } 2285 EXPORT_SYMBOL_GPL(wm8996_detect); 2286 2287 static void wm8996_hpdet_irq(struct snd_soc_component *component) 2288 { 2289 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2290 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2291 int val, reg, report; 2292 2293 /* Assume headphone in error conditions; we need to report 2294 * something or we stall our state machine. 2295 */ 2296 report = SND_JACK_HEADPHONE; 2297 2298 reg = snd_soc_component_read32(component, WM8996_HEADPHONE_DETECT_2); 2299 if (reg < 0) { 2300 dev_err(component->dev, "Failed to read HPDET status\n"); 2301 goto out; 2302 } 2303 2304 if (!(reg & WM8996_HP_DONE)) { 2305 dev_err(component->dev, "Got HPDET IRQ but HPDET is busy\n"); 2306 goto out; 2307 } 2308 2309 val = reg & WM8996_HP_LVL_MASK; 2310 2311 dev_dbg(component->dev, "HPDET measured %d ohms\n", val); 2312 2313 /* If we've got high enough impedence then report as line, 2314 * otherwise assume headphone. 2315 */ 2316 if (val >= 126) 2317 report = SND_JACK_LINEOUT; 2318 else 2319 report = SND_JACK_HEADPHONE; 2320 2321 out: 2322 if (wm8996->jack_mic) 2323 report |= SND_JACK_MICROPHONE; 2324 2325 snd_soc_jack_report(wm8996->jack, report, 2326 SND_JACK_LINEOUT | SND_JACK_HEADSET); 2327 2328 wm8996->detecting = false; 2329 2330 /* If the output isn't running re-clamp it */ 2331 if (!(snd_soc_component_read32(component, WM8996_POWER_MANAGEMENT_1) & 2332 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT))) 2333 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, 2334 WM8996_HPOUT1L_RMV_SHORT | 2335 WM8996_HPOUT1R_RMV_SHORT, 0); 2336 2337 /* Go back to looking at the microphone */ 2338 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1, 2339 WM8996_JD_MODE_MASK, 0); 2340 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 2341 WM8996_MICD_ENA); 2342 2343 snd_soc_dapm_disable_pin(dapm, "Bandgap"); 2344 snd_soc_dapm_sync(dapm); 2345 } 2346 2347 static void wm8996_hpdet_start(struct snd_soc_component *component) 2348 { 2349 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 2350 2351 /* Unclamp the output, we can't measure while we're shorting it */ 2352 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, 2353 WM8996_HPOUT1L_RMV_SHORT | 2354 WM8996_HPOUT1R_RMV_SHORT, 2355 WM8996_HPOUT1L_RMV_SHORT | 2356 WM8996_HPOUT1R_RMV_SHORT); 2357 2358 /* We need bandgap for HPDET */ 2359 snd_soc_dapm_force_enable_pin(dapm, "Bandgap"); 2360 snd_soc_dapm_sync(dapm); 2361 2362 /* Go into headphone detect left mode */ 2363 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0); 2364 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1, 2365 WM8996_JD_MODE_MASK, 1); 2366 2367 /* Trigger a measurement */ 2368 snd_soc_component_update_bits(component, WM8996_HEADPHONE_DETECT_1, 2369 WM8996_HP_POLL, WM8996_HP_POLL); 2370 } 2371 2372 static void wm8996_report_headphone(struct snd_soc_component *component) 2373 { 2374 dev_dbg(component->dev, "Headphone detected\n"); 2375 wm8996_hpdet_start(component); 2376 2377 /* Increase the detection rate a bit for responsiveness. */ 2378 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, 2379 WM8996_MICD_RATE_MASK | 2380 WM8996_MICD_BIAS_STARTTIME_MASK, 2381 7 << WM8996_MICD_RATE_SHIFT | 2382 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2383 } 2384 2385 static void wm8996_micd(struct snd_soc_component *component) 2386 { 2387 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2388 int val, reg; 2389 2390 val = snd_soc_component_read32(component, WM8996_MIC_DETECT_3); 2391 2392 dev_dbg(component->dev, "Microphone event: %x\n", val); 2393 2394 if (!(val & WM8996_MICD_VALID)) { 2395 dev_warn(component->dev, "Microphone detection state invalid\n"); 2396 return; 2397 } 2398 2399 /* No accessory, reset everything and report removal */ 2400 if (!(val & WM8996_MICD_STS)) { 2401 dev_dbg(component->dev, "Jack removal detected\n"); 2402 wm8996->jack_mic = false; 2403 wm8996->detecting = true; 2404 wm8996->jack_flips = 0; 2405 snd_soc_jack_report(wm8996->jack, 0, 2406 SND_JACK_LINEOUT | SND_JACK_HEADSET | 2407 SND_JACK_BTN_0); 2408 2409 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, 2410 WM8996_MICD_RATE_MASK | 2411 WM8996_MICD_BIAS_STARTTIME_MASK, 2412 WM8996_MICD_RATE_MASK | 2413 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2414 return; 2415 } 2416 2417 /* If the measurement is very high we've got a microphone, 2418 * either we just detected one or if we already reported then 2419 * we've got a button release event. 2420 */ 2421 if (val & 0x400) { 2422 if (wm8996->detecting) { 2423 dev_dbg(component->dev, "Microphone detected\n"); 2424 wm8996->jack_mic = true; 2425 wm8996_hpdet_start(component); 2426 2427 /* Increase poll rate to give better responsiveness 2428 * for buttons */ 2429 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, 2430 WM8996_MICD_RATE_MASK | 2431 WM8996_MICD_BIAS_STARTTIME_MASK, 2432 5 << WM8996_MICD_RATE_SHIFT | 2433 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2434 } else { 2435 dev_dbg(component->dev, "Mic button up\n"); 2436 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0); 2437 } 2438 2439 return; 2440 } 2441 2442 /* If we detected a lower impedence during initial startup 2443 * then we probably have the wrong polarity, flip it. Don't 2444 * do this for the lowest impedences to speed up detection of 2445 * plain headphones. If both polarities report a low 2446 * impedence then give up and report headphones. 2447 */ 2448 if (wm8996->detecting && (val & 0x3f0)) { 2449 wm8996->jack_flips++; 2450 2451 if (wm8996->jack_flips > 1) { 2452 wm8996_report_headphone(component); 2453 return; 2454 } 2455 2456 reg = snd_soc_component_read32(component, WM8996_ACCESSORY_DETECT_MODE_2); 2457 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2458 WM8996_MICD_BIAS_SRC; 2459 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_2, 2460 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2461 WM8996_MICD_BIAS_SRC, reg); 2462 2463 if (wm8996->polarity_cb) 2464 wm8996->polarity_cb(component, 2465 (reg & WM8996_MICD_SRC) != 0); 2466 2467 dev_dbg(component->dev, "Set microphone polarity to %d\n", 2468 (reg & WM8996_MICD_SRC) != 0); 2469 2470 return; 2471 } 2472 2473 /* Don't distinguish between buttons, just report any low 2474 * impedence as BTN_0. 2475 */ 2476 if (val & 0x3fc) { 2477 if (wm8996->jack_mic) { 2478 dev_dbg(component->dev, "Mic button detected\n"); 2479 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0, 2480 SND_JACK_BTN_0); 2481 } else if (wm8996->detecting) { 2482 wm8996_report_headphone(component); 2483 } 2484 } 2485 } 2486 2487 static irqreturn_t wm8996_irq(int irq, void *data) 2488 { 2489 struct snd_soc_component *component = data; 2490 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2491 int irq_val; 2492 2493 irq_val = snd_soc_component_read32(component, WM8996_INTERRUPT_STATUS_2); 2494 if (irq_val < 0) { 2495 dev_err(component->dev, "Failed to read IRQ status: %d\n", 2496 irq_val); 2497 return IRQ_NONE; 2498 } 2499 irq_val &= ~snd_soc_component_read32(component, WM8996_INTERRUPT_STATUS_2_MASK); 2500 2501 if (!irq_val) 2502 return IRQ_NONE; 2503 2504 snd_soc_component_write(component, WM8996_INTERRUPT_STATUS_2, irq_val); 2505 2506 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { 2507 dev_dbg(component->dev, "DC servo IRQ\n"); 2508 complete(&wm8996->dcs_done); 2509 } 2510 2511 if (irq_val & WM8996_FIFOS_ERR_EINT) 2512 dev_err(component->dev, "Digital core FIFO error\n"); 2513 2514 if (irq_val & WM8996_FLL_LOCK_EINT) { 2515 dev_dbg(component->dev, "FLL locked\n"); 2516 complete(&wm8996->fll_lock); 2517 } 2518 2519 if (irq_val & WM8996_MICD_EINT) 2520 wm8996_micd(component); 2521 2522 if (irq_val & WM8996_HP_DONE_EINT) 2523 wm8996_hpdet_irq(component); 2524 2525 return IRQ_HANDLED; 2526 } 2527 2528 static irqreturn_t wm8996_edge_irq(int irq, void *data) 2529 { 2530 irqreturn_t ret = IRQ_NONE; 2531 irqreturn_t val; 2532 2533 do { 2534 val = wm8996_irq(irq, data); 2535 if (val != IRQ_NONE) 2536 ret = val; 2537 } while (val != IRQ_NONE); 2538 2539 return ret; 2540 } 2541 2542 static void wm8996_retune_mobile_pdata(struct snd_soc_component *component) 2543 { 2544 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2545 struct wm8996_pdata *pdata = &wm8996->pdata; 2546 2547 struct snd_kcontrol_new controls[] = { 2548 SOC_ENUM_EXT("DSP1 EQ Mode", 2549 wm8996->retune_mobile_enum, 2550 wm8996_get_retune_mobile_enum, 2551 wm8996_put_retune_mobile_enum), 2552 SOC_ENUM_EXT("DSP2 EQ Mode", 2553 wm8996->retune_mobile_enum, 2554 wm8996_get_retune_mobile_enum, 2555 wm8996_put_retune_mobile_enum), 2556 }; 2557 int ret, i, j; 2558 const char **t; 2559 2560 /* We need an array of texts for the enum API but the number 2561 * of texts is likely to be less than the number of 2562 * configurations due to the sample rate dependency of the 2563 * configurations. */ 2564 wm8996->num_retune_mobile_texts = 0; 2565 wm8996->retune_mobile_texts = NULL; 2566 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2567 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { 2568 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2569 wm8996->retune_mobile_texts[j]) == 0) 2570 break; 2571 } 2572 2573 if (j != wm8996->num_retune_mobile_texts) 2574 continue; 2575 2576 /* Expand the array... */ 2577 t = krealloc(wm8996->retune_mobile_texts, 2578 sizeof(char *) * 2579 (wm8996->num_retune_mobile_texts + 1), 2580 GFP_KERNEL); 2581 if (t == NULL) 2582 continue; 2583 2584 /* ...store the new entry... */ 2585 t[wm8996->num_retune_mobile_texts] = 2586 pdata->retune_mobile_cfgs[i].name; 2587 2588 /* ...and remember the new version. */ 2589 wm8996->num_retune_mobile_texts++; 2590 wm8996->retune_mobile_texts = t; 2591 } 2592 2593 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", 2594 wm8996->num_retune_mobile_texts); 2595 2596 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts; 2597 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; 2598 2599 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 2600 if (ret != 0) 2601 dev_err(component->dev, 2602 "Failed to add ReTune Mobile controls: %d\n", ret); 2603 } 2604 2605 static const struct regmap_config wm8996_regmap = { 2606 .reg_bits = 16, 2607 .val_bits = 16, 2608 2609 .max_register = WM8996_MAX_REGISTER, 2610 .reg_defaults = wm8996_reg, 2611 .num_reg_defaults = ARRAY_SIZE(wm8996_reg), 2612 .volatile_reg = wm8996_volatile_register, 2613 .readable_reg = wm8996_readable_register, 2614 .cache_type = REGCACHE_RBTREE, 2615 }; 2616 2617 static int wm8996_probe(struct snd_soc_component *component) 2618 { 2619 int ret; 2620 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component); 2621 struct i2c_client *i2c = to_i2c_client(component->dev); 2622 int irq_flags; 2623 2624 wm8996->component = component; 2625 2626 init_completion(&wm8996->dcs_done); 2627 init_completion(&wm8996->fll_lock); 2628 2629 if (wm8996->pdata.num_retune_mobile_cfgs) 2630 wm8996_retune_mobile_pdata(component); 2631 else 2632 snd_soc_add_component_controls(component, wm8996_eq_controls, 2633 ARRAY_SIZE(wm8996_eq_controls)); 2634 2635 if (i2c->irq) { 2636 if (wm8996->pdata.irq_flags) 2637 irq_flags = wm8996->pdata.irq_flags; 2638 else 2639 irq_flags = IRQF_TRIGGER_LOW; 2640 2641 irq_flags |= IRQF_ONESHOT; 2642 2643 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) 2644 ret = request_threaded_irq(i2c->irq, NULL, 2645 wm8996_edge_irq, 2646 irq_flags, "wm8996", component); 2647 else 2648 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, 2649 irq_flags, "wm8996", component); 2650 2651 if (ret == 0) { 2652 /* Unmask the interrupt */ 2653 snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL, 2654 WM8996_IM_IRQ, 0); 2655 2656 /* Enable error reporting and DC servo status */ 2657 snd_soc_component_update_bits(component, 2658 WM8996_INTERRUPT_STATUS_2_MASK, 2659 WM8996_IM_DCS_DONE_23_EINT | 2660 WM8996_IM_DCS_DONE_01_EINT | 2661 WM8996_IM_FLL_LOCK_EINT | 2662 WM8996_IM_FIFOS_ERR_EINT, 2663 0); 2664 } else { 2665 dev_err(component->dev, "Failed to request IRQ: %d\n", 2666 ret); 2667 return ret; 2668 } 2669 } 2670 2671 return 0; 2672 } 2673 2674 static void wm8996_remove(struct snd_soc_component *component) 2675 { 2676 struct i2c_client *i2c = to_i2c_client(component->dev); 2677 2678 snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL, 2679 WM8996_IM_IRQ, WM8996_IM_IRQ); 2680 2681 if (i2c->irq) 2682 free_irq(i2c->irq, component); 2683 } 2684 2685 static const struct snd_soc_component_driver soc_component_dev_wm8996 = { 2686 .probe = wm8996_probe, 2687 .remove = wm8996_remove, 2688 .set_bias_level = wm8996_set_bias_level, 2689 .seq_notifier = wm8996_seq_notifier, 2690 .controls = wm8996_snd_controls, 2691 .num_controls = ARRAY_SIZE(wm8996_snd_controls), 2692 .dapm_widgets = wm8996_dapm_widgets, 2693 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), 2694 .dapm_routes = wm8996_dapm_routes, 2695 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), 2696 .set_pll = wm8996_set_fll, 2697 .use_pmdown_time = 1, 2698 .endianness = 1, 2699 .non_legacy_dai_naming = 1, 2700 2701 }; 2702 2703 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 2704 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 2705 SNDRV_PCM_RATE_48000) 2706 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 2707 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 2708 SNDRV_PCM_FMTBIT_S32_LE) 2709 2710 static const struct snd_soc_dai_ops wm8996_dai_ops = { 2711 .set_fmt = wm8996_set_fmt, 2712 .hw_params = wm8996_hw_params, 2713 .set_sysclk = wm8996_set_sysclk, 2714 }; 2715 2716 static struct snd_soc_dai_driver wm8996_dai[] = { 2717 { 2718 .name = "wm8996-aif1", 2719 .playback = { 2720 .stream_name = "AIF1 Playback", 2721 .channels_min = 1, 2722 .channels_max = 6, 2723 .rates = WM8996_RATES, 2724 .formats = WM8996_FORMATS, 2725 .sig_bits = 24, 2726 }, 2727 .capture = { 2728 .stream_name = "AIF1 Capture", 2729 .channels_min = 1, 2730 .channels_max = 6, 2731 .rates = WM8996_RATES, 2732 .formats = WM8996_FORMATS, 2733 .sig_bits = 24, 2734 }, 2735 .ops = &wm8996_dai_ops, 2736 }, 2737 { 2738 .name = "wm8996-aif2", 2739 .playback = { 2740 .stream_name = "AIF2 Playback", 2741 .channels_min = 1, 2742 .channels_max = 2, 2743 .rates = WM8996_RATES, 2744 .formats = WM8996_FORMATS, 2745 .sig_bits = 24, 2746 }, 2747 .capture = { 2748 .stream_name = "AIF2 Capture", 2749 .channels_min = 1, 2750 .channels_max = 2, 2751 .rates = WM8996_RATES, 2752 .formats = WM8996_FORMATS, 2753 .sig_bits = 24, 2754 }, 2755 .ops = &wm8996_dai_ops, 2756 }, 2757 }; 2758 2759 static int wm8996_i2c_probe(struct i2c_client *i2c, 2760 const struct i2c_device_id *id) 2761 { 2762 struct wm8996_priv *wm8996; 2763 int ret, i; 2764 unsigned int reg; 2765 2766 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv), 2767 GFP_KERNEL); 2768 if (wm8996 == NULL) 2769 return -ENOMEM; 2770 2771 i2c_set_clientdata(i2c, wm8996); 2772 wm8996->dev = &i2c->dev; 2773 2774 if (dev_get_platdata(&i2c->dev)) 2775 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), 2776 sizeof(wm8996->pdata)); 2777 2778 if (wm8996->pdata.ldo_ena > 0) { 2779 ret = gpio_request_one(wm8996->pdata.ldo_ena, 2780 GPIOF_OUT_INIT_LOW, "WM8996 ENA"); 2781 if (ret < 0) { 2782 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", 2783 wm8996->pdata.ldo_ena, ret); 2784 goto err; 2785 } 2786 } 2787 2788 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 2789 wm8996->supplies[i].supply = wm8996_supply_names[i]; 2790 2791 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies), 2792 wm8996->supplies); 2793 if (ret != 0) { 2794 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2795 goto err_gpio; 2796 } 2797 2798 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; 2799 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; 2800 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; 2801 2802 /* This should really be moved into the regulator core */ 2803 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { 2804 ret = devm_regulator_register_notifier( 2805 wm8996->supplies[i].consumer, 2806 &wm8996->disable_nb[i]); 2807 if (ret != 0) { 2808 dev_err(&i2c->dev, 2809 "Failed to register regulator notifier: %d\n", 2810 ret); 2811 } 2812 } 2813 2814 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 2815 wm8996->supplies); 2816 if (ret != 0) { 2817 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2818 goto err_gpio; 2819 } 2820 2821 if (wm8996->pdata.ldo_ena > 0) { 2822 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 2823 msleep(5); 2824 } 2825 2826 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap); 2827 if (IS_ERR(wm8996->regmap)) { 2828 ret = PTR_ERR(wm8996->regmap); 2829 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 2830 goto err_enable; 2831 } 2832 2833 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®); 2834 if (ret < 0) { 2835 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2836 goto err_regmap; 2837 } 2838 if (reg != 0x8915) { 2839 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg); 2840 ret = -EINVAL; 2841 goto err_regmap; 2842 } 2843 2844 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®); 2845 if (ret < 0) { 2846 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2847 ret); 2848 goto err_regmap; 2849 } 2850 2851 dev_info(&i2c->dev, "revision %c\n", 2852 (reg & WM8996_CHIP_REV_MASK) + 'A'); 2853 2854 if (wm8996->pdata.ldo_ena > 0) { 2855 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 2856 regcache_cache_only(wm8996->regmap, true); 2857 } else { 2858 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET, 2859 0x8915); 2860 if (ret != 0) { 2861 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2862 goto err_regmap; 2863 } 2864 } 2865 2866 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2867 2868 /* Apply platform data settings */ 2869 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL, 2870 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2871 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | 2872 wm8996->pdata.inr_mode); 2873 2874 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { 2875 if (!wm8996->pdata.gpio_default[i]) 2876 continue; 2877 2878 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i, 2879 wm8996->pdata.gpio_default[i] & 0xffff); 2880 } 2881 2882 if (wm8996->pdata.spkmute_seq) 2883 regmap_update_bits(wm8996->regmap, 2884 WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 2885 WM8996_SPK_MUTE_ENDIAN | 2886 WM8996_SPK_MUTE_SEQ1_MASK, 2887 wm8996->pdata.spkmute_seq); 2888 2889 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2, 2890 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | 2891 WM8996_MICD_SRC, wm8996->pdata.micdet_def); 2892 2893 /* Latch volume update bits */ 2894 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME, 2895 WM8996_IN1_VU, WM8996_IN1_VU); 2896 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME, 2897 WM8996_IN1_VU, WM8996_IN1_VU); 2898 2899 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME, 2900 WM8996_DAC1_VU, WM8996_DAC1_VU); 2901 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME, 2902 WM8996_DAC1_VU, WM8996_DAC1_VU); 2903 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME, 2904 WM8996_DAC2_VU, WM8996_DAC2_VU); 2905 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME, 2906 WM8996_DAC2_VU, WM8996_DAC2_VU); 2907 2908 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME, 2909 WM8996_DAC1_VU, WM8996_DAC1_VU); 2910 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME, 2911 WM8996_DAC1_VU, WM8996_DAC1_VU); 2912 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME, 2913 WM8996_DAC2_VU, WM8996_DAC2_VU); 2914 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME, 2915 WM8996_DAC2_VU, WM8996_DAC2_VU); 2916 2917 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME, 2918 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2919 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME, 2920 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2921 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME, 2922 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2923 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME, 2924 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2925 2926 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME, 2927 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2928 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME, 2929 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2930 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME, 2931 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2932 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME, 2933 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2934 2935 /* No support currently for the underclocked TDM modes and 2936 * pick a default TDM layout with each channel pair working with 2937 * slots 0 and 1. */ 2938 regmap_update_bits(wm8996->regmap, 2939 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 2940 WM8996_AIF1RX_CHAN0_SLOTS_MASK | 2941 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2942 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); 2943 regmap_update_bits(wm8996->regmap, 2944 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 2945 WM8996_AIF1RX_CHAN1_SLOTS_MASK | 2946 WM8996_AIF1RX_CHAN1_START_SLOT_MASK, 2947 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); 2948 regmap_update_bits(wm8996->regmap, 2949 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 2950 WM8996_AIF1RX_CHAN2_SLOTS_MASK | 2951 WM8996_AIF1RX_CHAN2_START_SLOT_MASK, 2952 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); 2953 regmap_update_bits(wm8996->regmap, 2954 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 2955 WM8996_AIF1RX_CHAN3_SLOTS_MASK | 2956 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2957 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); 2958 regmap_update_bits(wm8996->regmap, 2959 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 2960 WM8996_AIF1RX_CHAN4_SLOTS_MASK | 2961 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2962 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); 2963 regmap_update_bits(wm8996->regmap, 2964 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 2965 WM8996_AIF1RX_CHAN5_SLOTS_MASK | 2966 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2967 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); 2968 2969 regmap_update_bits(wm8996->regmap, 2970 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 2971 WM8996_AIF2RX_CHAN0_SLOTS_MASK | 2972 WM8996_AIF2RX_CHAN0_START_SLOT_MASK, 2973 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); 2974 regmap_update_bits(wm8996->regmap, 2975 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 2976 WM8996_AIF2RX_CHAN1_SLOTS_MASK | 2977 WM8996_AIF2RX_CHAN1_START_SLOT_MASK, 2978 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); 2979 2980 regmap_update_bits(wm8996->regmap, 2981 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 2982 WM8996_AIF1TX_CHAN0_SLOTS_MASK | 2983 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2984 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); 2985 regmap_update_bits(wm8996->regmap, 2986 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2987 WM8996_AIF1TX_CHAN1_SLOTS_MASK | 2988 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2989 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2990 regmap_update_bits(wm8996->regmap, 2991 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 2992 WM8996_AIF1TX_CHAN2_SLOTS_MASK | 2993 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2994 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); 2995 regmap_update_bits(wm8996->regmap, 2996 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 2997 WM8996_AIF1TX_CHAN3_SLOTS_MASK | 2998 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2999 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); 3000 regmap_update_bits(wm8996->regmap, 3001 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 3002 WM8996_AIF1TX_CHAN4_SLOTS_MASK | 3003 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3004 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); 3005 regmap_update_bits(wm8996->regmap, 3006 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 3007 WM8996_AIF1TX_CHAN5_SLOTS_MASK | 3008 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3009 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); 3010 3011 regmap_update_bits(wm8996->regmap, 3012 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 3013 WM8996_AIF2TX_CHAN0_SLOTS_MASK | 3014 WM8996_AIF2TX_CHAN0_START_SLOT_MASK, 3015 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); 3016 regmap_update_bits(wm8996->regmap, 3017 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 3018 WM8996_AIF2TX_CHAN1_SLOTS_MASK | 3019 WM8996_AIF2TX_CHAN1_START_SLOT_MASK, 3020 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 3021 3022 /* If the TX LRCLK pins are not in LRCLK mode configure the 3023 * AIFs to source their clocks from the RX LRCLKs. 3024 */ 3025 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®); 3026 if (ret != 0) { 3027 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret); 3028 goto err_regmap; 3029 } 3030 3031 if (reg & WM8996_GP1_FN_MASK) 3032 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2, 3033 WM8996_AIF1TX_LRCLK_MODE, 3034 WM8996_AIF1TX_LRCLK_MODE); 3035 3036 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®); 3037 if (ret != 0) { 3038 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret); 3039 goto err_regmap; 3040 } 3041 3042 if (reg & WM8996_GP2_FN_MASK) 3043 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2, 3044 WM8996_AIF2TX_LRCLK_MODE, 3045 WM8996_AIF2TX_LRCLK_MODE); 3046 3047 wm8996_init_gpio(wm8996); 3048 3049 ret = devm_snd_soc_register_component(&i2c->dev, 3050 &soc_component_dev_wm8996, wm8996_dai, 3051 ARRAY_SIZE(wm8996_dai)); 3052 if (ret < 0) 3053 goto err_gpiolib; 3054 3055 return ret; 3056 3057 err_gpiolib: 3058 wm8996_free_gpio(wm8996); 3059 err_regmap: 3060 err_enable: 3061 if (wm8996->pdata.ldo_ena > 0) 3062 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3063 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3064 err_gpio: 3065 if (wm8996->pdata.ldo_ena > 0) 3066 gpio_free(wm8996->pdata.ldo_ena); 3067 err: 3068 3069 return ret; 3070 } 3071 3072 static int wm8996_i2c_remove(struct i2c_client *client) 3073 { 3074 struct wm8996_priv *wm8996 = i2c_get_clientdata(client); 3075 3076 wm8996_free_gpio(wm8996); 3077 if (wm8996->pdata.ldo_ena > 0) { 3078 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3079 gpio_free(wm8996->pdata.ldo_ena); 3080 } 3081 3082 return 0; 3083 } 3084 3085 static const struct i2c_device_id wm8996_i2c_id[] = { 3086 { "wm8996", 0 }, 3087 { } 3088 }; 3089 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3090 3091 static struct i2c_driver wm8996_i2c_driver = { 3092 .driver = { 3093 .name = "wm8996", 3094 }, 3095 .probe = wm8996_i2c_probe, 3096 .remove = wm8996_i2c_remove, 3097 .id_table = wm8996_i2c_id, 3098 }; 3099 3100 module_i2c_driver(wm8996_i2c_driver); 3101 3102 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3103 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3104 MODULE_LICENSE("GPL"); 3105