1 /* 2 * wm8996.c - WM8996 audio codec interface 3 * 4 * Copyright 2011-2 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/moduleparam.h> 15 #include <linux/init.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/regmap.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/workqueue.h> 26 #include <sound/core.h> 27 #include <sound/jack.h> 28 #include <sound/pcm.h> 29 #include <sound/pcm_params.h> 30 #include <sound/soc.h> 31 #include <sound/initval.h> 32 #include <sound/tlv.h> 33 #include <trace/events/asoc.h> 34 35 #include <sound/wm8996.h> 36 #include "wm8996.h" 37 38 #define WM8996_AIFS 2 39 40 #define HPOUT1L 1 41 #define HPOUT1R 2 42 #define HPOUT2L 4 43 #define HPOUT2R 8 44 45 #define WM8996_NUM_SUPPLIES 3 46 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = { 47 "DBVDD", 48 "AVDD1", 49 "AVDD2", 50 }; 51 52 struct wm8996_priv { 53 struct device *dev; 54 struct regmap *regmap; 55 struct snd_soc_codec *codec; 56 57 int ldo1ena; 58 59 int sysclk; 60 int sysclk_src; 61 62 int fll_src; 63 int fll_fref; 64 int fll_fout; 65 66 struct completion fll_lock; 67 68 u16 dcs_pending; 69 struct completion dcs_done; 70 71 u16 hpout_ena; 72 u16 hpout_pending; 73 74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES]; 75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES]; 76 int bg_ena; 77 78 struct wm8996_pdata pdata; 79 80 int rx_rate[WM8996_AIFS]; 81 int bclk_rate[WM8996_AIFS]; 82 83 /* Platform dependant ReTune mobile configuration */ 84 int num_retune_mobile_texts; 85 const char **retune_mobile_texts; 86 int retune_mobile_cfg[2]; 87 struct soc_enum retune_mobile_enum; 88 89 struct snd_soc_jack *jack; 90 bool detecting; 91 bool jack_mic; 92 int jack_flips; 93 wm8996_polarity_fn polarity_cb; 94 95 #ifdef CONFIG_GPIOLIB 96 struct gpio_chip gpio_chip; 97 #endif 98 }; 99 100 /* We can't use the same notifier block for more than one supply and 101 * there's no way I can see to get from a callback to the caller 102 * except container_of(). 103 */ 104 #define WM8996_REGULATOR_EVENT(n) \ 105 static int wm8996_regulator_event_##n(struct notifier_block *nb, \ 106 unsigned long event, void *data) \ 107 { \ 108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \ 109 disable_nb[n]); \ 110 if (event & REGULATOR_EVENT_DISABLE) { \ 111 regcache_mark_dirty(wm8996->regmap); \ 112 } \ 113 return 0; \ 114 } 115 116 WM8996_REGULATOR_EVENT(0) 117 WM8996_REGULATOR_EVENT(1) 118 WM8996_REGULATOR_EVENT(2) 119 120 static struct reg_default wm8996_reg[] = { 121 { WM8996_POWER_MANAGEMENT_1, 0x0 }, 122 { WM8996_POWER_MANAGEMENT_2, 0x0 }, 123 { WM8996_POWER_MANAGEMENT_3, 0x0 }, 124 { WM8996_POWER_MANAGEMENT_4, 0x0 }, 125 { WM8996_POWER_MANAGEMENT_5, 0x0 }, 126 { WM8996_POWER_MANAGEMENT_6, 0x0 }, 127 { WM8996_POWER_MANAGEMENT_7, 0x10 }, 128 { WM8996_POWER_MANAGEMENT_8, 0x0 }, 129 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 }, 130 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 }, 131 { WM8996_LINE_INPUT_CONTROL, 0x0 }, 132 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 }, 133 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 }, 134 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 }, 135 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 }, 136 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 }, 137 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 }, 138 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 }, 139 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 }, 140 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 }, 141 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 }, 142 { WM8996_MICBIAS_1, 0x39 }, 143 { WM8996_MICBIAS_2, 0x39 }, 144 { WM8996_LDO_1, 0x3 }, 145 { WM8996_LDO_2, 0x13 }, 146 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 }, 147 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 }, 148 { WM8996_HEADPHONE_DETECT_1, 0x20 }, 149 { WM8996_HEADPHONE_DETECT_2, 0x0 }, 150 { WM8996_MIC_DETECT_1, 0x7600 }, 151 { WM8996_MIC_DETECT_2, 0xbf }, 152 { WM8996_CHARGE_PUMP_1, 0x1f25 }, 153 { WM8996_CHARGE_PUMP_2, 0xab19 }, 154 { WM8996_DC_SERVO_1, 0x0 }, 155 { WM8996_DC_SERVO_3, 0x0 }, 156 { WM8996_DC_SERVO_5, 0x2a2a }, 157 { WM8996_DC_SERVO_6, 0x0 }, 158 { WM8996_DC_SERVO_7, 0x0 }, 159 { WM8996_ANALOGUE_HP_1, 0x0 }, 160 { WM8996_ANALOGUE_HP_2, 0x0 }, 161 { WM8996_CONTROL_INTERFACE_1, 0x8004 }, 162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 }, 163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 }, 164 { WM8996_AIF_CLOCKING_1, 0x0 }, 165 { WM8996_AIF_CLOCKING_2, 0x0 }, 166 { WM8996_CLOCKING_1, 0x10 }, 167 { WM8996_CLOCKING_2, 0x0 }, 168 { WM8996_AIF_RATE, 0x83 }, 169 { WM8996_FLL_CONTROL_1, 0x0 }, 170 { WM8996_FLL_CONTROL_2, 0x0 }, 171 { WM8996_FLL_CONTROL_3, 0x0 }, 172 { WM8996_FLL_CONTROL_4, 0x5dc0 }, 173 { WM8996_FLL_CONTROL_5, 0xc84 }, 174 { WM8996_FLL_EFS_1, 0x0 }, 175 { WM8996_FLL_EFS_2, 0x2 }, 176 { WM8996_AIF1_CONTROL, 0x0 }, 177 { WM8996_AIF1_BCLK, 0x0 }, 178 { WM8996_AIF1_TX_LRCLK_1, 0x80 }, 179 { WM8996_AIF1_TX_LRCLK_2, 0x8 }, 180 { WM8996_AIF1_RX_LRCLK_1, 0x80 }, 181 { WM8996_AIF1_RX_LRCLK_2, 0x0 }, 182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 }, 183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 }, 184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 }, 185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 }, 186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 }, 187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 }, 188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 }, 189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 }, 190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 }, 191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 }, 192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 }, 193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 }, 194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 }, 195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 }, 196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 }, 197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 }, 198 { WM8996_AIF1TX_TEST, 0x7 }, 199 { WM8996_AIF2_CONTROL, 0x0 }, 200 { WM8996_AIF2_BCLK, 0x0 }, 201 { WM8996_AIF2_TX_LRCLK_1, 0x80 }, 202 { WM8996_AIF2_TX_LRCLK_2, 0x8 }, 203 { WM8996_AIF2_RX_LRCLK_1, 0x80 }, 204 { WM8996_AIF2_RX_LRCLK_2, 0x0 }, 205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 }, 206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 }, 207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 }, 208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 }, 209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 }, 210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 }, 211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 }, 212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 }, 213 { WM8996_AIF2TX_TEST, 0x1 }, 214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 }, 215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 }, 216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 }, 217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 }, 218 { WM8996_DSP1_TX_FILTERS, 0x2000 }, 219 { WM8996_DSP1_RX_FILTERS_1, 0x200 }, 220 { WM8996_DSP1_RX_FILTERS_2, 0x10 }, 221 { WM8996_DSP1_DRC_1, 0x98 }, 222 { WM8996_DSP1_DRC_2, 0x845 }, 223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 }, 224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 }, 225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca }, 226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 }, 227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 }, 228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 }, 229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 }, 230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 }, 231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 }, 232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 }, 233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 }, 234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 }, 235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 }, 236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e }, 237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 }, 238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad }, 239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 }, 240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 }, 241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 }, 242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 }, 243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 }, 244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 }, 245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 }, 246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 }, 247 { WM8996_DSP2_TX_FILTERS, 0x2000 }, 248 { WM8996_DSP2_RX_FILTERS_1, 0x200 }, 249 { WM8996_DSP2_RX_FILTERS_2, 0x10 }, 250 { WM8996_DSP2_DRC_1, 0x98 }, 251 { WM8996_DSP2_DRC_2, 0x845 }, 252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 }, 253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 }, 254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca }, 255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 }, 256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 }, 257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 }, 258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 }, 259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 }, 260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 }, 261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 }, 262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 }, 263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 }, 264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 }, 265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e }, 266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 }, 267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad }, 268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 }, 269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 }, 270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 }, 271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 }, 272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 }, 273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 }, 274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 }, 275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 }, 276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 }, 277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 }, 278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 }, 279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 }, 280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 }, 281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 }, 282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 }, 283 { WM8996_DAC_SOFTMUTE, 0x0 }, 284 { WM8996_OVERSAMPLING, 0xd }, 285 { WM8996_SIDETONE, 0x1040 }, 286 { WM8996_GPIO_1, 0xa101 }, 287 { WM8996_GPIO_2, 0xa101 }, 288 { WM8996_GPIO_3, 0xa101 }, 289 { WM8996_GPIO_4, 0xa101 }, 290 { WM8996_GPIO_5, 0xa101 }, 291 { WM8996_PULL_CONTROL_1, 0x0 }, 292 { WM8996_PULL_CONTROL_2, 0x140 }, 293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f }, 294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf }, 295 { WM8996_LEFT_PDM_SPEAKER, 0x0 }, 296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 }, 297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 }, 298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 }, 299 }; 300 301 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0); 302 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 303 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 304 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0); 305 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0); 306 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0); 307 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 308 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1); 309 310 static const char *sidetone_hpf_text[] = { 311 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz" 312 }; 313 314 static SOC_ENUM_SINGLE_DECL(sidetone_hpf, 315 WM8996_SIDETONE, 7, sidetone_hpf_text); 316 317 static const char *hpf_mode_text[] = { 318 "HiFi", "Custom", "Voice" 319 }; 320 321 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode, 322 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text); 323 324 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode, 325 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text); 326 327 static const char *hpf_cutoff_text[] = { 328 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 329 }; 330 331 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff, 332 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text); 333 334 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff, 335 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text); 336 337 static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block) 338 { 339 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 340 struct wm8996_pdata *pdata = &wm8996->pdata; 341 int base, best, best_val, save, i, cfg, iface; 342 343 if (!wm8996->num_retune_mobile_texts) 344 return; 345 346 switch (block) { 347 case 0: 348 base = WM8996_DSP1_RX_EQ_GAINS_1; 349 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 350 WM8996_DSP1RX_SRC) 351 iface = 1; 352 else 353 iface = 0; 354 break; 355 case 1: 356 base = WM8996_DSP1_RX_EQ_GAINS_2; 357 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) & 358 WM8996_DSP2RX_SRC) 359 iface = 1; 360 else 361 iface = 0; 362 break; 363 default: 364 return; 365 } 366 367 /* Find the version of the currently selected configuration 368 * with the nearest sample rate. */ 369 cfg = wm8996->retune_mobile_cfg[block]; 370 best = 0; 371 best_val = INT_MAX; 372 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 373 if (strcmp(pdata->retune_mobile_cfgs[i].name, 374 wm8996->retune_mobile_texts[cfg]) == 0 && 375 abs(pdata->retune_mobile_cfgs[i].rate 376 - wm8996->rx_rate[iface]) < best_val) { 377 best = i; 378 best_val = abs(pdata->retune_mobile_cfgs[i].rate 379 - wm8996->rx_rate[iface]); 380 } 381 } 382 383 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", 384 block, 385 pdata->retune_mobile_cfgs[best].name, 386 pdata->retune_mobile_cfgs[best].rate, 387 wm8996->rx_rate[iface]); 388 389 /* The EQ will be disabled while reconfiguring it, remember the 390 * current configuration. 391 */ 392 save = snd_soc_read(codec, base); 393 save &= WM8996_DSP1RX_EQ_ENA; 394 395 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++) 396 snd_soc_update_bits(codec, base + i, 0xffff, 397 pdata->retune_mobile_cfgs[best].regs[i]); 398 399 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save); 400 } 401 402 /* Icky as hell but saves code duplication */ 403 static int wm8996_get_retune_mobile_block(const char *name) 404 { 405 if (strcmp(name, "DSP1 EQ Mode") == 0) 406 return 0; 407 if (strcmp(name, "DSP2 EQ Mode") == 0) 408 return 1; 409 return -EINVAL; 410 } 411 412 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, 413 struct snd_ctl_elem_value *ucontrol) 414 { 415 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 416 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 417 struct wm8996_pdata *pdata = &wm8996->pdata; 418 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 419 int value = ucontrol->value.integer.value[0]; 420 421 if (block < 0) 422 return block; 423 424 if (value >= pdata->num_retune_mobile_cfgs) 425 return -EINVAL; 426 427 wm8996->retune_mobile_cfg[block] = value; 428 429 wm8996_set_retune_mobile(codec, block); 430 431 return 0; 432 } 433 434 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, 435 struct snd_ctl_elem_value *ucontrol) 436 { 437 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 438 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 439 int block = wm8996_get_retune_mobile_block(kcontrol->id.name); 440 441 if (block < 0) 442 return block; 443 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block]; 444 445 return 0; 446 } 447 448 static const struct snd_kcontrol_new wm8996_snd_controls[] = { 449 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME, 450 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv), 451 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME, 452 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0), 453 454 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES, 455 0, 5, 24, 0, sidetone_tlv), 456 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES, 457 0, 5, 24, 0, sidetone_tlv), 458 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0), 459 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf), 460 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0), 461 462 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME, 463 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 464 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME, 465 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv), 466 467 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS, 468 13, 1, 0), 469 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0), 470 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode), 471 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff), 472 473 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS, 474 13, 1, 0), 475 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0), 476 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode), 477 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff), 478 479 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME, 480 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 481 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1), 482 483 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME, 484 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 485 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1), 486 487 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME, 488 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 489 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME, 490 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1), 491 492 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME, 493 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv), 494 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME, 495 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1), 496 497 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0), 498 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0), 499 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0), 500 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0), 501 502 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0), 503 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0), 504 505 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0), 506 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0), 507 508 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15, 509 0, threedstereo_tlv), 510 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15, 511 0, threedstereo_tlv), 512 513 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4, 514 8, 0, out_digital_tlv), 515 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4, 516 8, 0, out_digital_tlv), 517 518 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME, 519 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv), 520 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME, 521 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0), 522 523 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME, 524 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv), 525 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME, 526 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0), 527 528 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0, 529 spk_tlv), 530 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER, 531 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1), 532 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER, 533 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0), 534 535 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0), 536 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0), 537 538 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0), 539 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0), 540 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0), 541 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5, 542 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA | 543 WM8996_DSP1TXR_DRC_ENA), 544 545 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0), 546 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0), 547 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0), 548 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5, 549 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA | 550 WM8996_DSP2TXR_DRC_ENA), 551 }; 552 553 static const struct snd_kcontrol_new wm8996_eq_controls[] = { 554 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0, 555 eq_tlv), 556 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0, 557 eq_tlv), 558 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0, 559 eq_tlv), 560 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0, 561 eq_tlv), 562 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0, 563 eq_tlv), 564 565 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0, 566 eq_tlv), 567 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0, 568 eq_tlv), 569 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0, 570 eq_tlv), 571 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0, 572 eq_tlv), 573 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0, 574 eq_tlv), 575 }; 576 577 static void wm8996_bg_enable(struct snd_soc_codec *codec) 578 { 579 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 580 581 wm8996->bg_ena++; 582 if (wm8996->bg_ena == 1) { 583 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 584 WM8996_BG_ENA, WM8996_BG_ENA); 585 msleep(2); 586 } 587 } 588 589 static void wm8996_bg_disable(struct snd_soc_codec *codec) 590 { 591 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 592 593 wm8996->bg_ena--; 594 if (!wm8996->bg_ena) 595 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1, 596 WM8996_BG_ENA, 0); 597 } 598 599 static int bg_event(struct snd_soc_dapm_widget *w, 600 struct snd_kcontrol *kcontrol, int event) 601 { 602 struct snd_soc_codec *codec = w->codec; 603 int ret = 0; 604 605 switch (event) { 606 case SND_SOC_DAPM_PRE_PMU: 607 wm8996_bg_enable(codec); 608 break; 609 case SND_SOC_DAPM_POST_PMD: 610 wm8996_bg_disable(codec); 611 break; 612 default: 613 WARN(1, "Invalid event %d\n", event); 614 ret = -EINVAL; 615 } 616 617 return ret; 618 } 619 620 static int cp_event(struct snd_soc_dapm_widget *w, 621 struct snd_kcontrol *kcontrol, int event) 622 { 623 switch (event) { 624 case SND_SOC_DAPM_POST_PMU: 625 msleep(5); 626 break; 627 default: 628 WARN(1, "Invalid event %d\n", event); 629 } 630 631 return 0; 632 } 633 634 static int rmv_short_event(struct snd_soc_dapm_widget *w, 635 struct snd_kcontrol *kcontrol, int event) 636 { 637 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 638 639 /* Record which outputs we enabled */ 640 switch (event) { 641 case SND_SOC_DAPM_PRE_PMD: 642 wm8996->hpout_pending &= ~w->shift; 643 break; 644 case SND_SOC_DAPM_PRE_PMU: 645 wm8996->hpout_pending |= w->shift; 646 break; 647 default: 648 WARN(1, "Invalid event %d\n", event); 649 return -EINVAL; 650 } 651 652 return 0; 653 } 654 655 static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask) 656 { 657 struct i2c_client *i2c = to_i2c_client(codec->dev); 658 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 659 int ret; 660 unsigned long timeout = 200; 661 662 snd_soc_write(codec, WM8996_DC_SERVO_2, mask); 663 664 /* Use the interrupt if possible */ 665 do { 666 if (i2c->irq) { 667 timeout = wait_for_completion_timeout(&wm8996->dcs_done, 668 msecs_to_jiffies(200)); 669 if (timeout == 0) 670 dev_err(codec->dev, "DC servo timed out\n"); 671 672 } else { 673 msleep(1); 674 timeout--; 675 } 676 677 ret = snd_soc_read(codec, WM8996_DC_SERVO_2); 678 dev_dbg(codec->dev, "DC servo state: %x\n", ret); 679 } while (timeout && ret & mask); 680 681 if (timeout == 0) 682 dev_err(codec->dev, "DC servo timed out for %x\n", mask); 683 else 684 dev_dbg(codec->dev, "DC servo complete for %x\n", mask); 685 } 686 687 static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm, 688 enum snd_soc_dapm_type event, int subseq) 689 { 690 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm); 691 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 692 u16 val, mask; 693 694 /* Complete any pending DC servo starts */ 695 if (wm8996->dcs_pending) { 696 dev_dbg(codec->dev, "Starting DC servo for %x\n", 697 wm8996->dcs_pending); 698 699 /* Trigger a startup sequence */ 700 wait_for_dc_servo(codec, wm8996->dcs_pending 701 << WM8996_DCS_TRIG_STARTUP_0_SHIFT); 702 703 wm8996->dcs_pending = 0; 704 } 705 706 if (wm8996->hpout_pending != wm8996->hpout_ena) { 707 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n", 708 wm8996->hpout_ena, wm8996->hpout_pending); 709 710 val = 0; 711 mask = 0; 712 if (wm8996->hpout_pending & HPOUT1L) { 713 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 714 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP; 715 } else { 716 mask |= WM8996_HPOUT1L_RMV_SHORT | 717 WM8996_HPOUT1L_OUTP | 718 WM8996_HPOUT1L_DLY; 719 } 720 721 if (wm8996->hpout_pending & HPOUT1R) { 722 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 723 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP; 724 } else { 725 mask |= WM8996_HPOUT1R_RMV_SHORT | 726 WM8996_HPOUT1R_OUTP | 727 WM8996_HPOUT1R_DLY; 728 } 729 730 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val); 731 732 val = 0; 733 mask = 0; 734 if (wm8996->hpout_pending & HPOUT2L) { 735 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 736 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP; 737 } else { 738 mask |= WM8996_HPOUT2L_RMV_SHORT | 739 WM8996_HPOUT2L_OUTP | 740 WM8996_HPOUT2L_DLY; 741 } 742 743 if (wm8996->hpout_pending & HPOUT2R) { 744 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 745 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP; 746 } else { 747 mask |= WM8996_HPOUT2R_RMV_SHORT | 748 WM8996_HPOUT2R_OUTP | 749 WM8996_HPOUT2R_DLY; 750 } 751 752 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val); 753 754 wm8996->hpout_ena = wm8996->hpout_pending; 755 } 756 } 757 758 static int dcs_start(struct snd_soc_dapm_widget *w, 759 struct snd_kcontrol *kcontrol, int event) 760 { 761 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec); 762 763 switch (event) { 764 case SND_SOC_DAPM_POST_PMU: 765 wm8996->dcs_pending |= 1 << w->shift; 766 break; 767 default: 768 WARN(1, "Invalid event %d\n", event); 769 return -EINVAL; 770 } 771 772 return 0; 773 } 774 775 static const char *sidetone_text[] = { 776 "IN1", "IN2", 777 }; 778 779 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum, 780 WM8996_SIDETONE, 0, sidetone_text); 781 782 static const struct snd_kcontrol_new left_sidetone = 783 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum); 784 785 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum, 786 WM8996_SIDETONE, 1, sidetone_text); 787 788 static const struct snd_kcontrol_new right_sidetone = 789 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum); 790 791 static const char *spk_text[] = { 792 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 793 }; 794 795 static SOC_ENUM_SINGLE_DECL(spkl_enum, 796 WM8996_LEFT_PDM_SPEAKER, 0, spk_text); 797 798 static const struct snd_kcontrol_new spkl_mux = 799 SOC_DAPM_ENUM("SPKL", spkl_enum); 800 801 static SOC_ENUM_SINGLE_DECL(spkr_enum, 802 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text); 803 804 static const struct snd_kcontrol_new spkr_mux = 805 SOC_DAPM_ENUM("SPKR", spkr_enum); 806 807 static const char *dsp1rx_text[] = { 808 "AIF1", "AIF2" 809 }; 810 811 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum, 812 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text); 813 814 static const struct snd_kcontrol_new dsp1rx = 815 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum); 816 817 static const char *dsp2rx_text[] = { 818 "AIF2", "AIF1" 819 }; 820 821 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum, 822 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text); 823 824 static const struct snd_kcontrol_new dsp2rx = 825 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum); 826 827 static const char *aif2tx_text[] = { 828 "DSP2", "DSP1", "AIF1" 829 }; 830 831 static SOC_ENUM_SINGLE_DECL(aif2tx_enum, 832 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text); 833 834 static const struct snd_kcontrol_new aif2tx = 835 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum); 836 837 static const char *inmux_text[] = { 838 "ADC", "DMIC1", "DMIC2" 839 }; 840 841 static SOC_ENUM_SINGLE_DECL(in1_enum, 842 WM8996_POWER_MANAGEMENT_7, 0, inmux_text); 843 844 static const struct snd_kcontrol_new in1_mux = 845 SOC_DAPM_ENUM("IN1 Mux", in1_enum); 846 847 static SOC_ENUM_SINGLE_DECL(in2_enum, 848 WM8996_POWER_MANAGEMENT_7, 4, inmux_text); 849 850 static const struct snd_kcontrol_new in2_mux = 851 SOC_DAPM_ENUM("IN2 Mux", in2_enum); 852 853 static const struct snd_kcontrol_new dac2r_mix[] = { 854 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 855 5, 1, 0), 856 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 857 4, 1, 0), 858 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0), 859 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0), 860 }; 861 862 static const struct snd_kcontrol_new dac2l_mix[] = { 863 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 864 5, 1, 0), 865 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 866 4, 1, 0), 867 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0), 868 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0), 869 }; 870 871 static const struct snd_kcontrol_new dac1r_mix[] = { 872 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 873 5, 1, 0), 874 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 875 4, 1, 0), 876 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0), 877 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0), 878 }; 879 880 static const struct snd_kcontrol_new dac1l_mix[] = { 881 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 882 5, 1, 0), 883 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 884 4, 1, 0), 885 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0), 886 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0), 887 }; 888 889 static const struct snd_kcontrol_new dsp1txl[] = { 890 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 891 1, 1, 0), 892 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 893 0, 1, 0), 894 }; 895 896 static const struct snd_kcontrol_new dsp1txr[] = { 897 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 898 1, 1, 0), 899 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 900 0, 1, 0), 901 }; 902 903 static const struct snd_kcontrol_new dsp2txl[] = { 904 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 905 1, 1, 0), 906 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 907 0, 1, 0), 908 }; 909 910 static const struct snd_kcontrol_new dsp2txr[] = { 911 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 912 1, 1, 0), 913 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 914 0, 1, 0), 915 }; 916 917 918 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = { 919 SND_SOC_DAPM_INPUT("IN1LN"), 920 SND_SOC_DAPM_INPUT("IN1LP"), 921 SND_SOC_DAPM_INPUT("IN1RN"), 922 SND_SOC_DAPM_INPUT("IN1RP"), 923 924 SND_SOC_DAPM_INPUT("IN2LN"), 925 SND_SOC_DAPM_INPUT("IN2LP"), 926 SND_SOC_DAPM_INPUT("IN2RN"), 927 SND_SOC_DAPM_INPUT("IN2RP"), 928 929 SND_SOC_DAPM_INPUT("DMIC1DAT"), 930 SND_SOC_DAPM_INPUT("DMIC2DAT"), 931 932 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0), 933 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0), 934 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0), 935 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0), 936 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event, 937 SND_SOC_DAPM_POST_PMU), 938 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event, 939 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 940 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 941 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0), 942 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0), 943 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0), 944 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0), 945 946 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 947 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 948 949 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux), 950 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux), 951 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux), 952 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux), 953 954 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0), 955 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0), 956 957 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0), 958 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0), 959 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0), 960 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0), 961 962 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0), 963 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0), 964 965 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone), 966 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone), 967 968 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0), 969 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0), 970 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0), 971 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0), 972 973 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0, 974 dsp2txl, ARRAY_SIZE(dsp2txl)), 975 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0, 976 dsp2txr, ARRAY_SIZE(dsp2txr)), 977 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0, 978 dsp1txl, ARRAY_SIZE(dsp1txl)), 979 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0, 980 dsp1txr, ARRAY_SIZE(dsp1txr)), 981 982 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0, 983 dac2l_mix, ARRAY_SIZE(dac2l_mix)), 984 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0, 985 dac2r_mix, ARRAY_SIZE(dac2r_mix)), 986 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, 987 dac1l_mix, ARRAY_SIZE(dac1l_mix)), 988 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, 989 dac1r_mix, ARRAY_SIZE(dac1r_mix)), 990 991 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0), 992 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0), 993 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0), 994 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0), 995 996 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0), 997 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0), 998 999 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0), 1000 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0), 1001 1002 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0), 1003 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0), 1004 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0), 1005 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0), 1006 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0), 1007 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0), 1008 1009 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0), 1010 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0), 1011 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0), 1012 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0), 1013 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0), 1014 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0), 1015 1016 /* We route as stereo pairs so define some dummy widgets to squash 1017 * things down for now. RXA = 0,1, RXB = 2,3 and so on */ 1018 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0), 1019 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0), 1020 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0), 1021 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0), 1022 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0), 1023 1024 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx), 1025 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx), 1026 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx), 1027 1028 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux), 1029 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux), 1030 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0), 1031 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0), 1032 1033 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0), 1034 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0), 1035 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start, 1036 SND_SOC_DAPM_POST_PMU), 1037 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0, 1038 rmv_short_event, 1039 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1040 1041 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0), 1042 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0), 1043 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start, 1044 SND_SOC_DAPM_POST_PMU), 1045 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0, 1046 rmv_short_event, 1047 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1048 1049 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 1050 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0), 1051 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start, 1052 SND_SOC_DAPM_POST_PMU), 1053 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0, 1054 rmv_short_event, 1055 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1056 1057 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 1058 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0), 1059 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start, 1060 SND_SOC_DAPM_POST_PMU), 1061 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0, 1062 rmv_short_event, 1063 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1064 1065 SND_SOC_DAPM_OUTPUT("HPOUT1L"), 1066 SND_SOC_DAPM_OUTPUT("HPOUT1R"), 1067 SND_SOC_DAPM_OUTPUT("HPOUT2L"), 1068 SND_SOC_DAPM_OUTPUT("HPOUT2R"), 1069 SND_SOC_DAPM_OUTPUT("SPKDAT"), 1070 }; 1071 1072 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = { 1073 { "AIFCLK", NULL, "SYSCLK" }, 1074 { "SYSDSPCLK", NULL, "SYSCLK" }, 1075 { "Charge Pump", NULL, "SYSCLK" }, 1076 { "Charge Pump", NULL, "CPVDD" }, 1077 1078 { "MICB1", NULL, "LDO2" }, 1079 { "MICB1", NULL, "MICB1 Audio" }, 1080 { "MICB1", NULL, "Bandgap" }, 1081 { "MICB2", NULL, "LDO2" }, 1082 { "MICB2", NULL, "MICB2 Audio" }, 1083 { "MICB2", NULL, "Bandgap" }, 1084 1085 { "AIF1RX0", NULL, "AIF1 Playback" }, 1086 { "AIF1RX1", NULL, "AIF1 Playback" }, 1087 { "AIF1RX2", NULL, "AIF1 Playback" }, 1088 { "AIF1RX3", NULL, "AIF1 Playback" }, 1089 { "AIF1RX4", NULL, "AIF1 Playback" }, 1090 { "AIF1RX5", NULL, "AIF1 Playback" }, 1091 1092 { "AIF2RX0", NULL, "AIF2 Playback" }, 1093 { "AIF2RX1", NULL, "AIF2 Playback" }, 1094 1095 { "AIF1 Capture", NULL, "AIF1TX0" }, 1096 { "AIF1 Capture", NULL, "AIF1TX1" }, 1097 { "AIF1 Capture", NULL, "AIF1TX2" }, 1098 { "AIF1 Capture", NULL, "AIF1TX3" }, 1099 { "AIF1 Capture", NULL, "AIF1TX4" }, 1100 { "AIF1 Capture", NULL, "AIF1TX5" }, 1101 1102 { "AIF2 Capture", NULL, "AIF2TX0" }, 1103 { "AIF2 Capture", NULL, "AIF2TX1" }, 1104 1105 { "IN1L PGA", NULL, "IN2LN" }, 1106 { "IN1L PGA", NULL, "IN2LP" }, 1107 { "IN1L PGA", NULL, "IN1LN" }, 1108 { "IN1L PGA", NULL, "IN1LP" }, 1109 { "IN1L PGA", NULL, "Bandgap" }, 1110 1111 { "IN1R PGA", NULL, "IN2RN" }, 1112 { "IN1R PGA", NULL, "IN2RP" }, 1113 { "IN1R PGA", NULL, "IN1RN" }, 1114 { "IN1R PGA", NULL, "IN1RP" }, 1115 { "IN1R PGA", NULL, "Bandgap" }, 1116 1117 { "ADCL", NULL, "IN1L PGA" }, 1118 1119 { "ADCR", NULL, "IN1R PGA" }, 1120 1121 { "DMIC1L", NULL, "DMIC1DAT" }, 1122 { "DMIC1R", NULL, "DMIC1DAT" }, 1123 { "DMIC2L", NULL, "DMIC2DAT" }, 1124 { "DMIC2R", NULL, "DMIC2DAT" }, 1125 1126 { "DMIC2L", NULL, "DMIC2" }, 1127 { "DMIC2R", NULL, "DMIC2" }, 1128 { "DMIC1L", NULL, "DMIC1" }, 1129 { "DMIC1R", NULL, "DMIC1" }, 1130 1131 { "IN1L Mux", "ADC", "ADCL" }, 1132 { "IN1L Mux", "DMIC1", "DMIC1L" }, 1133 { "IN1L Mux", "DMIC2", "DMIC2L" }, 1134 1135 { "IN1R Mux", "ADC", "ADCR" }, 1136 { "IN1R Mux", "DMIC1", "DMIC1R" }, 1137 { "IN1R Mux", "DMIC2", "DMIC2R" }, 1138 1139 { "IN2L Mux", "ADC", "ADCL" }, 1140 { "IN2L Mux", "DMIC1", "DMIC1L" }, 1141 { "IN2L Mux", "DMIC2", "DMIC2L" }, 1142 1143 { "IN2R Mux", "ADC", "ADCR" }, 1144 { "IN2R Mux", "DMIC1", "DMIC1R" }, 1145 { "IN2R Mux", "DMIC2", "DMIC2R" }, 1146 1147 { "Left Sidetone", "IN1", "IN1L Mux" }, 1148 { "Left Sidetone", "IN2", "IN2L Mux" }, 1149 1150 { "Right Sidetone", "IN1", "IN1R Mux" }, 1151 { "Right Sidetone", "IN2", "IN2R Mux" }, 1152 1153 { "DSP1TXL", "IN1 Switch", "IN1L Mux" }, 1154 { "DSP1TXR", "IN1 Switch", "IN1R Mux" }, 1155 1156 { "DSP2TXL", "IN1 Switch", "IN2L Mux" }, 1157 { "DSP2TXR", "IN1 Switch", "IN2R Mux" }, 1158 1159 { "AIF1TX0", NULL, "DSP1TXL" }, 1160 { "AIF1TX1", NULL, "DSP1TXR" }, 1161 { "AIF1TX2", NULL, "DSP2TXL" }, 1162 { "AIF1TX3", NULL, "DSP2TXR" }, 1163 { "AIF1TX4", NULL, "AIF2RX0" }, 1164 { "AIF1TX5", NULL, "AIF2RX1" }, 1165 1166 { "AIF1RX0", NULL, "AIFCLK" }, 1167 { "AIF1RX1", NULL, "AIFCLK" }, 1168 { "AIF1RX2", NULL, "AIFCLK" }, 1169 { "AIF1RX3", NULL, "AIFCLK" }, 1170 { "AIF1RX4", NULL, "AIFCLK" }, 1171 { "AIF1RX5", NULL, "AIFCLK" }, 1172 1173 { "AIF2RX0", NULL, "AIFCLK" }, 1174 { "AIF2RX1", NULL, "AIFCLK" }, 1175 1176 { "AIF1TX0", NULL, "AIFCLK" }, 1177 { "AIF1TX1", NULL, "AIFCLK" }, 1178 { "AIF1TX2", NULL, "AIFCLK" }, 1179 { "AIF1TX3", NULL, "AIFCLK" }, 1180 { "AIF1TX4", NULL, "AIFCLK" }, 1181 { "AIF1TX5", NULL, "AIFCLK" }, 1182 1183 { "AIF2TX0", NULL, "AIFCLK" }, 1184 { "AIF2TX1", NULL, "AIFCLK" }, 1185 1186 { "DSP1RXL", NULL, "SYSDSPCLK" }, 1187 { "DSP1RXR", NULL, "SYSDSPCLK" }, 1188 { "DSP2RXL", NULL, "SYSDSPCLK" }, 1189 { "DSP2RXR", NULL, "SYSDSPCLK" }, 1190 { "DSP1TXL", NULL, "SYSDSPCLK" }, 1191 { "DSP1TXR", NULL, "SYSDSPCLK" }, 1192 { "DSP2TXL", NULL, "SYSDSPCLK" }, 1193 { "DSP2TXR", NULL, "SYSDSPCLK" }, 1194 1195 { "AIF1RXA", NULL, "AIF1RX0" }, 1196 { "AIF1RXA", NULL, "AIF1RX1" }, 1197 { "AIF1RXB", NULL, "AIF1RX2" }, 1198 { "AIF1RXB", NULL, "AIF1RX3" }, 1199 { "AIF1RXC", NULL, "AIF1RX4" }, 1200 { "AIF1RXC", NULL, "AIF1RX5" }, 1201 1202 { "AIF2RX", NULL, "AIF2RX0" }, 1203 { "AIF2RX", NULL, "AIF2RX1" }, 1204 1205 { "AIF2TX", "DSP2", "DSP2TX" }, 1206 { "AIF2TX", "DSP1", "DSP1RX" }, 1207 { "AIF2TX", "AIF1", "AIF1RXC" }, 1208 1209 { "DSP1RXL", NULL, "DSP1RX" }, 1210 { "DSP1RXR", NULL, "DSP1RX" }, 1211 { "DSP2RXL", NULL, "DSP2RX" }, 1212 { "DSP2RXR", NULL, "DSP2RX" }, 1213 1214 { "DSP2TX", NULL, "DSP2TXL" }, 1215 { "DSP2TX", NULL, "DSP2TXR" }, 1216 1217 { "DSP1RX", "AIF1", "AIF1RXA" }, 1218 { "DSP1RX", "AIF2", "AIF2RX" }, 1219 1220 { "DSP2RX", "AIF1", "AIF1RXB" }, 1221 { "DSP2RX", "AIF2", "AIF2RX" }, 1222 1223 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" }, 1224 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" }, 1225 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1226 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1227 1228 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" }, 1229 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" }, 1230 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1231 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1232 1233 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" }, 1234 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" }, 1235 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1236 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1237 1238 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" }, 1239 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" }, 1240 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1241 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1242 1243 { "DAC1L", NULL, "DAC1L Mixer" }, 1244 { "DAC1R", NULL, "DAC1R Mixer" }, 1245 { "DAC2L", NULL, "DAC2L Mixer" }, 1246 { "DAC2R", NULL, "DAC2R Mixer" }, 1247 1248 { "HPOUT2L PGA", NULL, "Charge Pump" }, 1249 { "HPOUT2L PGA", NULL, "Bandgap" }, 1250 { "HPOUT2L PGA", NULL, "DAC2L" }, 1251 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" }, 1252 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" }, 1253 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" }, 1254 1255 { "HPOUT2R PGA", NULL, "Charge Pump" }, 1256 { "HPOUT2R PGA", NULL, "Bandgap" }, 1257 { "HPOUT2R PGA", NULL, "DAC2R" }, 1258 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" }, 1259 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" }, 1260 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" }, 1261 1262 { "HPOUT1L PGA", NULL, "Charge Pump" }, 1263 { "HPOUT1L PGA", NULL, "Bandgap" }, 1264 { "HPOUT1L PGA", NULL, "DAC1L" }, 1265 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" }, 1266 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" }, 1267 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" }, 1268 1269 { "HPOUT1R PGA", NULL, "Charge Pump" }, 1270 { "HPOUT1R PGA", NULL, "Bandgap" }, 1271 { "HPOUT1R PGA", NULL, "DAC1R" }, 1272 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" }, 1273 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" }, 1274 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" }, 1275 1276 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" }, 1277 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" }, 1278 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" }, 1279 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" }, 1280 1281 { "SPKL", "DAC1L", "DAC1L" }, 1282 { "SPKL", "DAC1R", "DAC1R" }, 1283 { "SPKL", "DAC2L", "DAC2L" }, 1284 { "SPKL", "DAC2R", "DAC2R" }, 1285 1286 { "SPKR", "DAC1L", "DAC1L" }, 1287 { "SPKR", "DAC1R", "DAC1R" }, 1288 { "SPKR", "DAC2L", "DAC2L" }, 1289 { "SPKR", "DAC2R", "DAC2R" }, 1290 1291 { "SPKL PGA", NULL, "SPKL" }, 1292 { "SPKR PGA", NULL, "SPKR" }, 1293 1294 { "SPKDAT", NULL, "SPKL PGA" }, 1295 { "SPKDAT", NULL, "SPKR PGA" }, 1296 }; 1297 1298 static bool wm8996_readable_register(struct device *dev, unsigned int reg) 1299 { 1300 /* Due to the sparseness of the register map the compiler 1301 * output from an explicit switch statement ends up being much 1302 * more efficient than a table. 1303 */ 1304 switch (reg) { 1305 case WM8996_SOFTWARE_RESET: 1306 case WM8996_POWER_MANAGEMENT_1: 1307 case WM8996_POWER_MANAGEMENT_2: 1308 case WM8996_POWER_MANAGEMENT_3: 1309 case WM8996_POWER_MANAGEMENT_4: 1310 case WM8996_POWER_MANAGEMENT_5: 1311 case WM8996_POWER_MANAGEMENT_6: 1312 case WM8996_POWER_MANAGEMENT_7: 1313 case WM8996_POWER_MANAGEMENT_8: 1314 case WM8996_LEFT_LINE_INPUT_VOLUME: 1315 case WM8996_RIGHT_LINE_INPUT_VOLUME: 1316 case WM8996_LINE_INPUT_CONTROL: 1317 case WM8996_DAC1_HPOUT1_VOLUME: 1318 case WM8996_DAC2_HPOUT2_VOLUME: 1319 case WM8996_DAC1_LEFT_VOLUME: 1320 case WM8996_DAC1_RIGHT_VOLUME: 1321 case WM8996_DAC2_LEFT_VOLUME: 1322 case WM8996_DAC2_RIGHT_VOLUME: 1323 case WM8996_OUTPUT1_LEFT_VOLUME: 1324 case WM8996_OUTPUT1_RIGHT_VOLUME: 1325 case WM8996_OUTPUT2_LEFT_VOLUME: 1326 case WM8996_OUTPUT2_RIGHT_VOLUME: 1327 case WM8996_MICBIAS_1: 1328 case WM8996_MICBIAS_2: 1329 case WM8996_LDO_1: 1330 case WM8996_LDO_2: 1331 case WM8996_ACCESSORY_DETECT_MODE_1: 1332 case WM8996_ACCESSORY_DETECT_MODE_2: 1333 case WM8996_HEADPHONE_DETECT_1: 1334 case WM8996_HEADPHONE_DETECT_2: 1335 case WM8996_MIC_DETECT_1: 1336 case WM8996_MIC_DETECT_2: 1337 case WM8996_MIC_DETECT_3: 1338 case WM8996_CHARGE_PUMP_1: 1339 case WM8996_CHARGE_PUMP_2: 1340 case WM8996_DC_SERVO_1: 1341 case WM8996_DC_SERVO_2: 1342 case WM8996_DC_SERVO_3: 1343 case WM8996_DC_SERVO_5: 1344 case WM8996_DC_SERVO_6: 1345 case WM8996_DC_SERVO_7: 1346 case WM8996_DC_SERVO_READBACK_0: 1347 case WM8996_ANALOGUE_HP_1: 1348 case WM8996_ANALOGUE_HP_2: 1349 case WM8996_CHIP_REVISION: 1350 case WM8996_CONTROL_INTERFACE_1: 1351 case WM8996_WRITE_SEQUENCER_CTRL_1: 1352 case WM8996_WRITE_SEQUENCER_CTRL_2: 1353 case WM8996_AIF_CLOCKING_1: 1354 case WM8996_AIF_CLOCKING_2: 1355 case WM8996_CLOCKING_1: 1356 case WM8996_CLOCKING_2: 1357 case WM8996_AIF_RATE: 1358 case WM8996_FLL_CONTROL_1: 1359 case WM8996_FLL_CONTROL_2: 1360 case WM8996_FLL_CONTROL_3: 1361 case WM8996_FLL_CONTROL_4: 1362 case WM8996_FLL_CONTROL_5: 1363 case WM8996_FLL_CONTROL_6: 1364 case WM8996_FLL_EFS_1: 1365 case WM8996_FLL_EFS_2: 1366 case WM8996_AIF1_CONTROL: 1367 case WM8996_AIF1_BCLK: 1368 case WM8996_AIF1_TX_LRCLK_1: 1369 case WM8996_AIF1_TX_LRCLK_2: 1370 case WM8996_AIF1_RX_LRCLK_1: 1371 case WM8996_AIF1_RX_LRCLK_2: 1372 case WM8996_AIF1TX_DATA_CONFIGURATION_1: 1373 case WM8996_AIF1TX_DATA_CONFIGURATION_2: 1374 case WM8996_AIF1RX_DATA_CONFIGURATION: 1375 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION: 1376 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION: 1377 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION: 1378 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION: 1379 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION: 1380 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION: 1381 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION: 1382 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION: 1383 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION: 1384 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION: 1385 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION: 1386 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION: 1387 case WM8996_AIF1RX_MONO_CONFIGURATION: 1388 case WM8996_AIF1TX_TEST: 1389 case WM8996_AIF2_CONTROL: 1390 case WM8996_AIF2_BCLK: 1391 case WM8996_AIF2_TX_LRCLK_1: 1392 case WM8996_AIF2_TX_LRCLK_2: 1393 case WM8996_AIF2_RX_LRCLK_1: 1394 case WM8996_AIF2_RX_LRCLK_2: 1395 case WM8996_AIF2TX_DATA_CONFIGURATION_1: 1396 case WM8996_AIF2TX_DATA_CONFIGURATION_2: 1397 case WM8996_AIF2RX_DATA_CONFIGURATION: 1398 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION: 1399 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION: 1400 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION: 1401 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION: 1402 case WM8996_AIF2RX_MONO_CONFIGURATION: 1403 case WM8996_AIF2TX_TEST: 1404 case WM8996_DSP1_TX_LEFT_VOLUME: 1405 case WM8996_DSP1_TX_RIGHT_VOLUME: 1406 case WM8996_DSP1_RX_LEFT_VOLUME: 1407 case WM8996_DSP1_RX_RIGHT_VOLUME: 1408 case WM8996_DSP1_TX_FILTERS: 1409 case WM8996_DSP1_RX_FILTERS_1: 1410 case WM8996_DSP1_RX_FILTERS_2: 1411 case WM8996_DSP1_DRC_1: 1412 case WM8996_DSP1_DRC_2: 1413 case WM8996_DSP1_DRC_3: 1414 case WM8996_DSP1_DRC_4: 1415 case WM8996_DSP1_DRC_5: 1416 case WM8996_DSP1_RX_EQ_GAINS_1: 1417 case WM8996_DSP1_RX_EQ_GAINS_2: 1418 case WM8996_DSP1_RX_EQ_BAND_1_A: 1419 case WM8996_DSP1_RX_EQ_BAND_1_B: 1420 case WM8996_DSP1_RX_EQ_BAND_1_PG: 1421 case WM8996_DSP1_RX_EQ_BAND_2_A: 1422 case WM8996_DSP1_RX_EQ_BAND_2_B: 1423 case WM8996_DSP1_RX_EQ_BAND_2_C: 1424 case WM8996_DSP1_RX_EQ_BAND_2_PG: 1425 case WM8996_DSP1_RX_EQ_BAND_3_A: 1426 case WM8996_DSP1_RX_EQ_BAND_3_B: 1427 case WM8996_DSP1_RX_EQ_BAND_3_C: 1428 case WM8996_DSP1_RX_EQ_BAND_3_PG: 1429 case WM8996_DSP1_RX_EQ_BAND_4_A: 1430 case WM8996_DSP1_RX_EQ_BAND_4_B: 1431 case WM8996_DSP1_RX_EQ_BAND_4_C: 1432 case WM8996_DSP1_RX_EQ_BAND_4_PG: 1433 case WM8996_DSP1_RX_EQ_BAND_5_A: 1434 case WM8996_DSP1_RX_EQ_BAND_5_B: 1435 case WM8996_DSP1_RX_EQ_BAND_5_PG: 1436 case WM8996_DSP2_TX_LEFT_VOLUME: 1437 case WM8996_DSP2_TX_RIGHT_VOLUME: 1438 case WM8996_DSP2_RX_LEFT_VOLUME: 1439 case WM8996_DSP2_RX_RIGHT_VOLUME: 1440 case WM8996_DSP2_TX_FILTERS: 1441 case WM8996_DSP2_RX_FILTERS_1: 1442 case WM8996_DSP2_RX_FILTERS_2: 1443 case WM8996_DSP2_DRC_1: 1444 case WM8996_DSP2_DRC_2: 1445 case WM8996_DSP2_DRC_3: 1446 case WM8996_DSP2_DRC_4: 1447 case WM8996_DSP2_DRC_5: 1448 case WM8996_DSP2_RX_EQ_GAINS_1: 1449 case WM8996_DSP2_RX_EQ_GAINS_2: 1450 case WM8996_DSP2_RX_EQ_BAND_1_A: 1451 case WM8996_DSP2_RX_EQ_BAND_1_B: 1452 case WM8996_DSP2_RX_EQ_BAND_1_PG: 1453 case WM8996_DSP2_RX_EQ_BAND_2_A: 1454 case WM8996_DSP2_RX_EQ_BAND_2_B: 1455 case WM8996_DSP2_RX_EQ_BAND_2_C: 1456 case WM8996_DSP2_RX_EQ_BAND_2_PG: 1457 case WM8996_DSP2_RX_EQ_BAND_3_A: 1458 case WM8996_DSP2_RX_EQ_BAND_3_B: 1459 case WM8996_DSP2_RX_EQ_BAND_3_C: 1460 case WM8996_DSP2_RX_EQ_BAND_3_PG: 1461 case WM8996_DSP2_RX_EQ_BAND_4_A: 1462 case WM8996_DSP2_RX_EQ_BAND_4_B: 1463 case WM8996_DSP2_RX_EQ_BAND_4_C: 1464 case WM8996_DSP2_RX_EQ_BAND_4_PG: 1465 case WM8996_DSP2_RX_EQ_BAND_5_A: 1466 case WM8996_DSP2_RX_EQ_BAND_5_B: 1467 case WM8996_DSP2_RX_EQ_BAND_5_PG: 1468 case WM8996_DAC1_MIXER_VOLUMES: 1469 case WM8996_DAC1_LEFT_MIXER_ROUTING: 1470 case WM8996_DAC1_RIGHT_MIXER_ROUTING: 1471 case WM8996_DAC2_MIXER_VOLUMES: 1472 case WM8996_DAC2_LEFT_MIXER_ROUTING: 1473 case WM8996_DAC2_RIGHT_MIXER_ROUTING: 1474 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING: 1475 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING: 1476 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING: 1477 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING: 1478 case WM8996_DSP_TX_MIXER_SELECT: 1479 case WM8996_DAC_SOFTMUTE: 1480 case WM8996_OVERSAMPLING: 1481 case WM8996_SIDETONE: 1482 case WM8996_GPIO_1: 1483 case WM8996_GPIO_2: 1484 case WM8996_GPIO_3: 1485 case WM8996_GPIO_4: 1486 case WM8996_GPIO_5: 1487 case WM8996_PULL_CONTROL_1: 1488 case WM8996_PULL_CONTROL_2: 1489 case WM8996_INTERRUPT_STATUS_1: 1490 case WM8996_INTERRUPT_STATUS_2: 1491 case WM8996_INTERRUPT_RAW_STATUS_2: 1492 case WM8996_INTERRUPT_STATUS_1_MASK: 1493 case WM8996_INTERRUPT_STATUS_2_MASK: 1494 case WM8996_INTERRUPT_CONTROL: 1495 case WM8996_LEFT_PDM_SPEAKER: 1496 case WM8996_RIGHT_PDM_SPEAKER: 1497 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE: 1498 case WM8996_PDM_SPEAKER_VOLUME: 1499 return 1; 1500 default: 1501 return 0; 1502 } 1503 } 1504 1505 static bool wm8996_volatile_register(struct device *dev, unsigned int reg) 1506 { 1507 switch (reg) { 1508 case WM8996_SOFTWARE_RESET: 1509 case WM8996_CHIP_REVISION: 1510 case WM8996_LDO_1: 1511 case WM8996_LDO_2: 1512 case WM8996_INTERRUPT_STATUS_1: 1513 case WM8996_INTERRUPT_STATUS_2: 1514 case WM8996_INTERRUPT_RAW_STATUS_2: 1515 case WM8996_DC_SERVO_READBACK_0: 1516 case WM8996_DC_SERVO_2: 1517 case WM8996_DC_SERVO_6: 1518 case WM8996_DC_SERVO_7: 1519 case WM8996_FLL_CONTROL_6: 1520 case WM8996_MIC_DETECT_3: 1521 case WM8996_HEADPHONE_DETECT_1: 1522 case WM8996_HEADPHONE_DETECT_2: 1523 return 1; 1524 default: 1525 return 0; 1526 } 1527 } 1528 1529 static const int bclk_divs[] = { 1530 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96 1531 }; 1532 1533 static void wm8996_update_bclk(struct snd_soc_codec *codec) 1534 { 1535 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1536 int aif, best, cur_val, bclk_rate, bclk_reg, i; 1537 1538 /* Don't bother if we're in a low frequency idle mode that 1539 * can't support audio. 1540 */ 1541 if (wm8996->sysclk < 64000) 1542 return; 1543 1544 for (aif = 0; aif < WM8996_AIFS; aif++) { 1545 switch (aif) { 1546 case 0: 1547 bclk_reg = WM8996_AIF1_BCLK; 1548 break; 1549 case 1: 1550 bclk_reg = WM8996_AIF2_BCLK; 1551 break; 1552 } 1553 1554 bclk_rate = wm8996->bclk_rate[aif]; 1555 1556 /* Pick a divisor for BCLK as close as we can get to ideal */ 1557 best = 0; 1558 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1559 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate; 1560 if (cur_val < 0) /* BCLK table is sorted */ 1561 break; 1562 best = i; 1563 } 1564 bclk_rate = wm8996->sysclk / bclk_divs[best]; 1565 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1566 bclk_divs[best], bclk_rate); 1567 1568 snd_soc_update_bits(codec, bclk_reg, 1569 WM8996_AIF1_BCLK_DIV_MASK, best); 1570 } 1571 } 1572 1573 static int wm8996_set_bias_level(struct snd_soc_codec *codec, 1574 enum snd_soc_bias_level level) 1575 { 1576 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1577 int ret; 1578 1579 switch (level) { 1580 case SND_SOC_BIAS_ON: 1581 break; 1582 case SND_SOC_BIAS_PREPARE: 1583 /* Put the MICBIASes into regulating mode */ 1584 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1585 WM8996_MICB1_MODE, 0); 1586 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1587 WM8996_MICB2_MODE, 0); 1588 break; 1589 1590 case SND_SOC_BIAS_STANDBY: 1591 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1592 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 1593 wm8996->supplies); 1594 if (ret != 0) { 1595 dev_err(codec->dev, 1596 "Failed to enable supplies: %d\n", 1597 ret); 1598 return ret; 1599 } 1600 1601 if (wm8996->pdata.ldo_ena >= 0) { 1602 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1603 1); 1604 msleep(5); 1605 } 1606 1607 regcache_cache_only(wm8996->regmap, false); 1608 regcache_sync(wm8996->regmap); 1609 } 1610 1611 /* Bypass the MICBIASes for lowest power */ 1612 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 1613 WM8996_MICB1_MODE, WM8996_MICB1_MODE); 1614 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 1615 WM8996_MICB2_MODE, WM8996_MICB2_MODE); 1616 break; 1617 1618 case SND_SOC_BIAS_OFF: 1619 regcache_cache_only(wm8996->regmap, true); 1620 if (wm8996->pdata.ldo_ena >= 0) { 1621 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 1622 regcache_cache_only(wm8996->regmap, true); 1623 } 1624 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), 1625 wm8996->supplies); 1626 break; 1627 } 1628 1629 codec->dapm.bias_level = level; 1630 1631 return 0; 1632 } 1633 1634 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1635 { 1636 struct snd_soc_codec *codec = dai->codec; 1637 int aifctrl = 0; 1638 int bclk = 0; 1639 int lrclk_tx = 0; 1640 int lrclk_rx = 0; 1641 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg; 1642 1643 switch (dai->id) { 1644 case 0: 1645 aifctrl_reg = WM8996_AIF1_CONTROL; 1646 bclk_reg = WM8996_AIF1_BCLK; 1647 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2; 1648 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2; 1649 break; 1650 case 1: 1651 aifctrl_reg = WM8996_AIF2_CONTROL; 1652 bclk_reg = WM8996_AIF2_BCLK; 1653 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2; 1654 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2; 1655 break; 1656 default: 1657 WARN(1, "Invalid dai id %d\n", dai->id); 1658 return -EINVAL; 1659 } 1660 1661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1662 case SND_SOC_DAIFMT_NB_NF: 1663 break; 1664 case SND_SOC_DAIFMT_IB_NF: 1665 bclk |= WM8996_AIF1_BCLK_INV; 1666 break; 1667 case SND_SOC_DAIFMT_NB_IF: 1668 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1669 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1670 break; 1671 case SND_SOC_DAIFMT_IB_IF: 1672 bclk |= WM8996_AIF1_BCLK_INV; 1673 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV; 1674 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV; 1675 break; 1676 } 1677 1678 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1679 case SND_SOC_DAIFMT_CBS_CFS: 1680 break; 1681 case SND_SOC_DAIFMT_CBS_CFM: 1682 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1683 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1684 break; 1685 case SND_SOC_DAIFMT_CBM_CFS: 1686 bclk |= WM8996_AIF1_BCLK_MSTR; 1687 break; 1688 case SND_SOC_DAIFMT_CBM_CFM: 1689 bclk |= WM8996_AIF1_BCLK_MSTR; 1690 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR; 1691 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR; 1692 break; 1693 default: 1694 return -EINVAL; 1695 } 1696 1697 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1698 case SND_SOC_DAIFMT_DSP_A: 1699 break; 1700 case SND_SOC_DAIFMT_DSP_B: 1701 aifctrl |= 1; 1702 break; 1703 case SND_SOC_DAIFMT_I2S: 1704 aifctrl |= 2; 1705 break; 1706 case SND_SOC_DAIFMT_LEFT_J: 1707 aifctrl |= 3; 1708 break; 1709 default: 1710 return -EINVAL; 1711 } 1712 1713 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl); 1714 snd_soc_update_bits(codec, bclk_reg, 1715 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR, 1716 bclk); 1717 snd_soc_update_bits(codec, lrclk_tx_reg, 1718 WM8996_AIF1TX_LRCLK_INV | 1719 WM8996_AIF1TX_LRCLK_MSTR, 1720 lrclk_tx); 1721 snd_soc_update_bits(codec, lrclk_rx_reg, 1722 WM8996_AIF1RX_LRCLK_INV | 1723 WM8996_AIF1RX_LRCLK_MSTR, 1724 lrclk_rx); 1725 1726 return 0; 1727 } 1728 1729 static const int dsp_divs[] = { 1730 48000, 32000, 16000, 8000 1731 }; 1732 1733 static int wm8996_hw_params(struct snd_pcm_substream *substream, 1734 struct snd_pcm_hw_params *params, 1735 struct snd_soc_dai *dai) 1736 { 1737 struct snd_soc_codec *codec = dai->codec; 1738 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1739 int bits, i, bclk_rate, best; 1740 int aifdata = 0; 1741 int lrclk = 0; 1742 int dsp = 0; 1743 int aifdata_reg, lrclk_reg, dsp_shift; 1744 1745 switch (dai->id) { 1746 case 0: 1747 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1748 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) { 1749 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION; 1750 lrclk_reg = WM8996_AIF1_RX_LRCLK_1; 1751 } else { 1752 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1; 1753 lrclk_reg = WM8996_AIF1_TX_LRCLK_1; 1754 } 1755 dsp_shift = 0; 1756 break; 1757 case 1: 1758 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || 1759 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) { 1760 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION; 1761 lrclk_reg = WM8996_AIF2_RX_LRCLK_1; 1762 } else { 1763 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1; 1764 lrclk_reg = WM8996_AIF2_TX_LRCLK_1; 1765 } 1766 dsp_shift = WM8996_DSP2_DIV_SHIFT; 1767 break; 1768 default: 1769 WARN(1, "Invalid dai id %d\n", dai->id); 1770 return -EINVAL; 1771 } 1772 1773 bclk_rate = snd_soc_params_to_bclk(params); 1774 if (bclk_rate < 0) { 1775 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); 1776 return bclk_rate; 1777 } 1778 1779 wm8996->bclk_rate[dai->id] = bclk_rate; 1780 wm8996->rx_rate[dai->id] = params_rate(params); 1781 1782 /* Needs looking at for TDM */ 1783 bits = snd_pcm_format_width(params_format(params)); 1784 if (bits < 0) 1785 return bits; 1786 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits; 1787 1788 best = 0; 1789 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) { 1790 if (abs(dsp_divs[i] - params_rate(params)) < 1791 abs(dsp_divs[best] - params_rate(params))) 1792 best = i; 1793 } 1794 dsp |= i << dsp_shift; 1795 1796 wm8996_update_bclk(codec); 1797 1798 lrclk = bclk_rate / params_rate(params); 1799 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1800 lrclk, bclk_rate / lrclk); 1801 1802 snd_soc_update_bits(codec, aifdata_reg, 1803 WM8996_AIF1TX_WL_MASK | 1804 WM8996_AIF1TX_SLOT_LEN_MASK, 1805 aifdata); 1806 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK, 1807 lrclk); 1808 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2, 1809 WM8996_DSP1_DIV_MASK << dsp_shift, dsp); 1810 1811 return 0; 1812 } 1813 1814 static int wm8996_set_sysclk(struct snd_soc_dai *dai, 1815 int clk_id, unsigned int freq, int dir) 1816 { 1817 struct snd_soc_codec *codec = dai->codec; 1818 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 1819 int lfclk = 0; 1820 int ratediv = 0; 1821 int sync = WM8996_REG_SYNC; 1822 int src; 1823 int old; 1824 1825 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src) 1826 return 0; 1827 1828 /* Disable SYSCLK while we reconfigure */ 1829 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA; 1830 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1831 WM8996_SYSCLK_ENA, 0); 1832 1833 switch (clk_id) { 1834 case WM8996_SYSCLK_MCLK1: 1835 wm8996->sysclk = freq; 1836 src = 0; 1837 break; 1838 case WM8996_SYSCLK_MCLK2: 1839 wm8996->sysclk = freq; 1840 src = 1; 1841 break; 1842 case WM8996_SYSCLK_FLL: 1843 wm8996->sysclk = freq; 1844 src = 2; 1845 break; 1846 default: 1847 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id); 1848 return -EINVAL; 1849 } 1850 1851 switch (wm8996->sysclk) { 1852 case 5644800: 1853 case 6144000: 1854 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1855 WM8996_SYSCLK_RATE, 0); 1856 break; 1857 case 22579200: 1858 case 24576000: 1859 ratediv = WM8996_SYSCLK_DIV; 1860 wm8996->sysclk /= 2; 1861 case 11289600: 1862 case 12288000: 1863 snd_soc_update_bits(codec, WM8996_AIF_RATE, 1864 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE); 1865 break; 1866 case 32000: 1867 case 32768: 1868 lfclk = WM8996_LFCLK_ENA; 1869 sync = 0; 1870 break; 1871 default: 1872 dev_warn(codec->dev, "Unsupported clock rate %dHz\n", 1873 wm8996->sysclk); 1874 return -EINVAL; 1875 } 1876 1877 wm8996_update_bclk(codec); 1878 1879 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1880 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK, 1881 src << WM8996_SYSCLK_SRC_SHIFT | ratediv); 1882 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk); 1883 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1, 1884 WM8996_REG_SYNC, sync); 1885 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1, 1886 WM8996_SYSCLK_ENA, old); 1887 1888 wm8996->sysclk_src = clk_id; 1889 1890 return 0; 1891 } 1892 1893 struct _fll_div { 1894 u16 fll_fratio; 1895 u16 fll_outdiv; 1896 u16 fll_refclk_div; 1897 u16 fll_loop_gain; 1898 u16 fll_ref_freq; 1899 u16 n; 1900 u16 theta; 1901 u16 lambda; 1902 }; 1903 1904 static struct { 1905 unsigned int min; 1906 unsigned int max; 1907 u16 fll_fratio; 1908 int ratio; 1909 } fll_fratios[] = { 1910 { 0, 64000, 4, 16 }, 1911 { 64000, 128000, 3, 8 }, 1912 { 128000, 256000, 2, 4 }, 1913 { 256000, 1000000, 1, 2 }, 1914 { 1000000, 13500000, 0, 1 }, 1915 }; 1916 1917 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 1918 unsigned int Fout) 1919 { 1920 unsigned int target; 1921 unsigned int div; 1922 unsigned int fratio, gcd_fll; 1923 int i; 1924 1925 /* Fref must be <=13.5MHz */ 1926 div = 1; 1927 fll_div->fll_refclk_div = 0; 1928 while ((Fref / div) > 13500000) { 1929 div *= 2; 1930 fll_div->fll_refclk_div++; 1931 1932 if (div > 8) { 1933 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 1934 Fref); 1935 return -EINVAL; 1936 } 1937 } 1938 1939 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 1940 1941 /* Apply the division for our remaining calculations */ 1942 Fref /= div; 1943 1944 if (Fref >= 3000000) 1945 fll_div->fll_loop_gain = 5; 1946 else 1947 fll_div->fll_loop_gain = 0; 1948 1949 if (Fref >= 48000) 1950 fll_div->fll_ref_freq = 0; 1951 else 1952 fll_div->fll_ref_freq = 1; 1953 1954 /* Fvco should be 90-100MHz; don't check the upper bound */ 1955 div = 2; 1956 while (Fout * div < 90000000) { 1957 div++; 1958 if (div > 64) { 1959 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 1960 Fout); 1961 return -EINVAL; 1962 } 1963 } 1964 target = Fout * div; 1965 fll_div->fll_outdiv = div - 1; 1966 1967 pr_debug("FLL Fvco=%dHz\n", target); 1968 1969 /* Find an appropraite FLL_FRATIO and factor it out of the target */ 1970 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 1971 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 1972 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 1973 fratio = fll_fratios[i].ratio; 1974 break; 1975 } 1976 } 1977 if (i == ARRAY_SIZE(fll_fratios)) { 1978 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 1979 return -EINVAL; 1980 } 1981 1982 fll_div->n = target / (fratio * Fref); 1983 1984 if (target % Fref == 0) { 1985 fll_div->theta = 0; 1986 fll_div->lambda = 0; 1987 } else { 1988 gcd_fll = gcd(target, fratio * Fref); 1989 1990 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 1991 / gcd_fll; 1992 fll_div->lambda = (fratio * Fref) / gcd_fll; 1993 } 1994 1995 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 1996 fll_div->n, fll_div->theta, fll_div->lambda); 1997 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 1998 fll_div->fll_fratio, fll_div->fll_outdiv, 1999 fll_div->fll_refclk_div); 2000 2001 return 0; 2002 } 2003 2004 static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 2005 unsigned int Fref, unsigned int Fout) 2006 { 2007 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2008 struct i2c_client *i2c = to_i2c_client(codec->dev); 2009 struct _fll_div fll_div; 2010 unsigned long timeout; 2011 int ret, reg, retry; 2012 2013 /* Any change? */ 2014 if (source == wm8996->fll_src && Fref == wm8996->fll_fref && 2015 Fout == wm8996->fll_fout) 2016 return 0; 2017 2018 if (Fout == 0) { 2019 dev_dbg(codec->dev, "FLL disabled\n"); 2020 2021 wm8996->fll_fref = 0; 2022 wm8996->fll_fout = 0; 2023 2024 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2025 WM8996_FLL_ENA, 0); 2026 2027 wm8996_bg_disable(codec); 2028 2029 return 0; 2030 } 2031 2032 ret = fll_factors(&fll_div, Fref, Fout); 2033 if (ret != 0) 2034 return ret; 2035 2036 switch (source) { 2037 case WM8996_FLL_MCLK1: 2038 reg = 0; 2039 break; 2040 case WM8996_FLL_MCLK2: 2041 reg = 1; 2042 break; 2043 case WM8996_FLL_DACLRCLK1: 2044 reg = 2; 2045 break; 2046 case WM8996_FLL_BCLK1: 2047 reg = 3; 2048 break; 2049 default: 2050 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 2051 return -EINVAL; 2052 } 2053 2054 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT; 2055 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT; 2056 2057 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5, 2058 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ | 2059 WM8996_FLL_REFCLK_SRC_MASK, reg); 2060 2061 reg = 0; 2062 if (fll_div.theta || fll_div.lambda) 2063 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT); 2064 else 2065 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT; 2066 snd_soc_write(codec, WM8996_FLL_EFS_2, reg); 2067 2068 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2, 2069 WM8996_FLL_OUTDIV_MASK | 2070 WM8996_FLL_FRATIO_MASK, 2071 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) | 2072 (fll_div.fll_fratio)); 2073 2074 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta); 2075 2076 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4, 2077 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK, 2078 (fll_div.n << WM8996_FLL_N_SHIFT) | 2079 fll_div.fll_loop_gain); 2080 2081 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda); 2082 2083 /* Enable the bandgap if it's not already enabled */ 2084 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1); 2085 if (!(ret & WM8996_FLL_ENA)) 2086 wm8996_bg_enable(codec); 2087 2088 /* Clear any pending completions (eg, from failed startups) */ 2089 try_wait_for_completion(&wm8996->fll_lock); 2090 2091 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1, 2092 WM8996_FLL_ENA, WM8996_FLL_ENA); 2093 2094 /* The FLL supports live reconfiguration - kick that in case we were 2095 * already enabled. 2096 */ 2097 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK); 2098 2099 /* Wait for the FLL to lock, using the interrupt if possible */ 2100 if (Fref > 1000000) 2101 timeout = usecs_to_jiffies(300); 2102 else 2103 timeout = msecs_to_jiffies(2); 2104 2105 /* Allow substantially longer if we've actually got the IRQ, poll 2106 * at a slightly higher rate if we don't. 2107 */ 2108 if (i2c->irq) 2109 timeout *= 10; 2110 else 2111 timeout /= 2; 2112 2113 for (retry = 0; retry < 10; retry++) { 2114 ret = wait_for_completion_timeout(&wm8996->fll_lock, 2115 timeout); 2116 if (ret != 0) { 2117 WARN_ON(!i2c->irq); 2118 break; 2119 } 2120 2121 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2); 2122 if (ret & WM8996_FLL_LOCK_STS) 2123 break; 2124 } 2125 if (retry == 10) { 2126 dev_err(codec->dev, "Timed out waiting for FLL\n"); 2127 ret = -ETIMEDOUT; 2128 } 2129 2130 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 2131 2132 wm8996->fll_fref = Fref; 2133 wm8996->fll_fout = Fout; 2134 wm8996->fll_src = source; 2135 2136 return ret; 2137 } 2138 2139 #ifdef CONFIG_GPIOLIB 2140 static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip) 2141 { 2142 return container_of(chip, struct wm8996_priv, gpio_chip); 2143 } 2144 2145 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 2146 { 2147 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2148 2149 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2150 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT); 2151 } 2152 2153 static int wm8996_gpio_direction_out(struct gpio_chip *chip, 2154 unsigned offset, int value) 2155 { 2156 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2157 int val; 2158 2159 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT); 2160 2161 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2162 WM8996_GP1_FN_MASK | WM8996_GP1_DIR | 2163 WM8996_GP1_LVL, val); 2164 } 2165 2166 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset) 2167 { 2168 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2169 unsigned int reg; 2170 int ret; 2171 2172 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, ®); 2173 if (ret < 0) 2174 return ret; 2175 2176 return (reg & WM8996_GP1_LVL) != 0; 2177 } 2178 2179 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset) 2180 { 2181 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip); 2182 2183 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset, 2184 WM8996_GP1_FN_MASK | WM8996_GP1_DIR, 2185 (1 << WM8996_GP1_FN_SHIFT) | 2186 (1 << WM8996_GP1_DIR_SHIFT)); 2187 } 2188 2189 static struct gpio_chip wm8996_template_chip = { 2190 .label = "wm8996", 2191 .owner = THIS_MODULE, 2192 .direction_output = wm8996_gpio_direction_out, 2193 .set = wm8996_gpio_set, 2194 .direction_input = wm8996_gpio_direction_in, 2195 .get = wm8996_gpio_get, 2196 .can_sleep = 1, 2197 }; 2198 2199 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2200 { 2201 int ret; 2202 2203 wm8996->gpio_chip = wm8996_template_chip; 2204 wm8996->gpio_chip.ngpio = 5; 2205 wm8996->gpio_chip.dev = wm8996->dev; 2206 2207 if (wm8996->pdata.gpio_base) 2208 wm8996->gpio_chip.base = wm8996->pdata.gpio_base; 2209 else 2210 wm8996->gpio_chip.base = -1; 2211 2212 ret = gpiochip_add(&wm8996->gpio_chip); 2213 if (ret != 0) 2214 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret); 2215 } 2216 2217 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2218 { 2219 gpiochip_remove(&wm8996->gpio_chip); 2220 } 2221 #else 2222 static void wm8996_init_gpio(struct wm8996_priv *wm8996) 2223 { 2224 } 2225 2226 static void wm8996_free_gpio(struct wm8996_priv *wm8996) 2227 { 2228 } 2229 #endif 2230 2231 /** 2232 * wm8996_detect - Enable default WM8996 jack detection 2233 * 2234 * The WM8996 has advanced accessory detection support for headsets. 2235 * This function provides a default implementation which integrates 2236 * the majority of this functionality with minimal user configuration. 2237 * 2238 * This will detect headset, headphone and short circuit button and 2239 * will also detect inverted microphone ground connections and update 2240 * the polarity of the connections. 2241 */ 2242 int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, 2243 wm8996_polarity_fn polarity_cb) 2244 { 2245 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2246 struct snd_soc_dapm_context *dapm = &codec->dapm; 2247 2248 wm8996->jack = jack; 2249 wm8996->detecting = true; 2250 wm8996->polarity_cb = polarity_cb; 2251 wm8996->jack_flips = 0; 2252 2253 if (wm8996->polarity_cb) 2254 wm8996->polarity_cb(codec, 0); 2255 2256 /* Clear discarge to avoid noise during detection */ 2257 snd_soc_update_bits(codec, WM8996_MICBIAS_1, 2258 WM8996_MICB1_DISCH, 0); 2259 snd_soc_update_bits(codec, WM8996_MICBIAS_2, 2260 WM8996_MICB2_DISCH, 0); 2261 2262 /* LDO2 powers the microphones, SYSCLK clocks detection */ 2263 snd_soc_dapm_mutex_lock(dapm); 2264 2265 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2"); 2266 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK"); 2267 2268 snd_soc_dapm_mutex_unlock(dapm); 2269 2270 /* We start off just enabling microphone detection - even a 2271 * plain headphone will trigger detection. 2272 */ 2273 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2274 WM8996_MICD_ENA, WM8996_MICD_ENA); 2275 2276 /* Slowest detection rate, gives debounce for initial detection */ 2277 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2278 WM8996_MICD_RATE_MASK, 2279 WM8996_MICD_RATE_MASK); 2280 2281 /* Enable interrupts and we're off */ 2282 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK, 2283 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0); 2284 2285 return 0; 2286 } 2287 EXPORT_SYMBOL_GPL(wm8996_detect); 2288 2289 static void wm8996_hpdet_irq(struct snd_soc_codec *codec) 2290 { 2291 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2292 int val, reg, report; 2293 2294 /* Assume headphone in error conditions; we need to report 2295 * something or we stall our state machine. 2296 */ 2297 report = SND_JACK_HEADPHONE; 2298 2299 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2); 2300 if (reg < 0) { 2301 dev_err(codec->dev, "Failed to read HPDET status\n"); 2302 goto out; 2303 } 2304 2305 if (!(reg & WM8996_HP_DONE)) { 2306 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n"); 2307 goto out; 2308 } 2309 2310 val = reg & WM8996_HP_LVL_MASK; 2311 2312 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val); 2313 2314 /* If we've got high enough impedence then report as line, 2315 * otherwise assume headphone. 2316 */ 2317 if (val >= 126) 2318 report = SND_JACK_LINEOUT; 2319 else 2320 report = SND_JACK_HEADPHONE; 2321 2322 out: 2323 if (wm8996->jack_mic) 2324 report |= SND_JACK_MICROPHONE; 2325 2326 snd_soc_jack_report(wm8996->jack, report, 2327 SND_JACK_LINEOUT | SND_JACK_HEADSET); 2328 2329 wm8996->detecting = false; 2330 2331 /* If the output isn't running re-clamp it */ 2332 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) & 2333 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT))) 2334 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2335 WM8996_HPOUT1L_RMV_SHORT | 2336 WM8996_HPOUT1R_RMV_SHORT, 0); 2337 2338 /* Go back to looking at the microphone */ 2339 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2340 WM8996_JD_MODE_MASK, 0); 2341 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 2342 WM8996_MICD_ENA); 2343 2344 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap"); 2345 snd_soc_dapm_sync(&codec->dapm); 2346 } 2347 2348 static void wm8996_hpdet_start(struct snd_soc_codec *codec) 2349 { 2350 /* Unclamp the output, we can't measure while we're shorting it */ 2351 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, 2352 WM8996_HPOUT1L_RMV_SHORT | 2353 WM8996_HPOUT1R_RMV_SHORT, 2354 WM8996_HPOUT1L_RMV_SHORT | 2355 WM8996_HPOUT1R_RMV_SHORT); 2356 2357 /* We need bandgap for HPDET */ 2358 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap"); 2359 snd_soc_dapm_sync(&codec->dapm); 2360 2361 /* Go into headphone detect left mode */ 2362 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0); 2363 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1, 2364 WM8996_JD_MODE_MASK, 1); 2365 2366 /* Trigger a measurement */ 2367 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1, 2368 WM8996_HP_POLL, WM8996_HP_POLL); 2369 } 2370 2371 static void wm8996_report_headphone(struct snd_soc_codec *codec) 2372 { 2373 dev_dbg(codec->dev, "Headphone detected\n"); 2374 wm8996_hpdet_start(codec); 2375 2376 /* Increase the detection rate a bit for responsiveness. */ 2377 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2378 WM8996_MICD_RATE_MASK | 2379 WM8996_MICD_BIAS_STARTTIME_MASK, 2380 7 << WM8996_MICD_RATE_SHIFT | 2381 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2382 } 2383 2384 static void wm8996_micd(struct snd_soc_codec *codec) 2385 { 2386 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2387 int val, reg; 2388 2389 val = snd_soc_read(codec, WM8996_MIC_DETECT_3); 2390 2391 dev_dbg(codec->dev, "Microphone event: %x\n", val); 2392 2393 if (!(val & WM8996_MICD_VALID)) { 2394 dev_warn(codec->dev, "Microphone detection state invalid\n"); 2395 return; 2396 } 2397 2398 /* No accessory, reset everything and report removal */ 2399 if (!(val & WM8996_MICD_STS)) { 2400 dev_dbg(codec->dev, "Jack removal detected\n"); 2401 wm8996->jack_mic = false; 2402 wm8996->detecting = true; 2403 wm8996->jack_flips = 0; 2404 snd_soc_jack_report(wm8996->jack, 0, 2405 SND_JACK_LINEOUT | SND_JACK_HEADSET | 2406 SND_JACK_BTN_0); 2407 2408 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2409 WM8996_MICD_RATE_MASK | 2410 WM8996_MICD_BIAS_STARTTIME_MASK, 2411 WM8996_MICD_RATE_MASK | 2412 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2413 return; 2414 } 2415 2416 /* If the measurement is very high we've got a microphone, 2417 * either we just detected one or if we already reported then 2418 * we've got a button release event. 2419 */ 2420 if (val & 0x400) { 2421 if (wm8996->detecting) { 2422 dev_dbg(codec->dev, "Microphone detected\n"); 2423 wm8996->jack_mic = true; 2424 wm8996_hpdet_start(codec); 2425 2426 /* Increase poll rate to give better responsiveness 2427 * for buttons */ 2428 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, 2429 WM8996_MICD_RATE_MASK | 2430 WM8996_MICD_BIAS_STARTTIME_MASK, 2431 5 << WM8996_MICD_RATE_SHIFT | 2432 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT); 2433 } else { 2434 dev_dbg(codec->dev, "Mic button up\n"); 2435 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0); 2436 } 2437 2438 return; 2439 } 2440 2441 /* If we detected a lower impedence during initial startup 2442 * then we probably have the wrong polarity, flip it. Don't 2443 * do this for the lowest impedences to speed up detection of 2444 * plain headphones. If both polarities report a low 2445 * impedence then give up and report headphones. 2446 */ 2447 if (wm8996->detecting && (val & 0x3f0)) { 2448 wm8996->jack_flips++; 2449 2450 if (wm8996->jack_flips > 1) { 2451 wm8996_report_headphone(codec); 2452 return; 2453 } 2454 2455 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2); 2456 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2457 WM8996_MICD_BIAS_SRC; 2458 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2, 2459 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC | 2460 WM8996_MICD_BIAS_SRC, reg); 2461 2462 if (wm8996->polarity_cb) 2463 wm8996->polarity_cb(codec, 2464 (reg & WM8996_MICD_SRC) != 0); 2465 2466 dev_dbg(codec->dev, "Set microphone polarity to %d\n", 2467 (reg & WM8996_MICD_SRC) != 0); 2468 2469 return; 2470 } 2471 2472 /* Don't distinguish between buttons, just report any low 2473 * impedence as BTN_0. 2474 */ 2475 if (val & 0x3fc) { 2476 if (wm8996->jack_mic) { 2477 dev_dbg(codec->dev, "Mic button detected\n"); 2478 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0, 2479 SND_JACK_BTN_0); 2480 } else if (wm8996->detecting) { 2481 wm8996_report_headphone(codec); 2482 } 2483 } 2484 } 2485 2486 static irqreturn_t wm8996_irq(int irq, void *data) 2487 { 2488 struct snd_soc_codec *codec = data; 2489 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2490 int irq_val; 2491 2492 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2); 2493 if (irq_val < 0) { 2494 dev_err(codec->dev, "Failed to read IRQ status: %d\n", 2495 irq_val); 2496 return IRQ_NONE; 2497 } 2498 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK); 2499 2500 if (!irq_val) 2501 return IRQ_NONE; 2502 2503 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val); 2504 2505 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) { 2506 dev_dbg(codec->dev, "DC servo IRQ\n"); 2507 complete(&wm8996->dcs_done); 2508 } 2509 2510 if (irq_val & WM8996_FIFOS_ERR_EINT) 2511 dev_err(codec->dev, "Digital core FIFO error\n"); 2512 2513 if (irq_val & WM8996_FLL_LOCK_EINT) { 2514 dev_dbg(codec->dev, "FLL locked\n"); 2515 complete(&wm8996->fll_lock); 2516 } 2517 2518 if (irq_val & WM8996_MICD_EINT) 2519 wm8996_micd(codec); 2520 2521 if (irq_val & WM8996_HP_DONE_EINT) 2522 wm8996_hpdet_irq(codec); 2523 2524 return IRQ_HANDLED; 2525 } 2526 2527 static irqreturn_t wm8996_edge_irq(int irq, void *data) 2528 { 2529 irqreturn_t ret = IRQ_NONE; 2530 irqreturn_t val; 2531 2532 do { 2533 val = wm8996_irq(irq, data); 2534 if (val != IRQ_NONE) 2535 ret = val; 2536 } while (val != IRQ_NONE); 2537 2538 return ret; 2539 } 2540 2541 static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec) 2542 { 2543 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2544 struct wm8996_pdata *pdata = &wm8996->pdata; 2545 2546 struct snd_kcontrol_new controls[] = { 2547 SOC_ENUM_EXT("DSP1 EQ Mode", 2548 wm8996->retune_mobile_enum, 2549 wm8996_get_retune_mobile_enum, 2550 wm8996_put_retune_mobile_enum), 2551 SOC_ENUM_EXT("DSP2 EQ Mode", 2552 wm8996->retune_mobile_enum, 2553 wm8996_get_retune_mobile_enum, 2554 wm8996_put_retune_mobile_enum), 2555 }; 2556 int ret, i, j; 2557 const char **t; 2558 2559 /* We need an array of texts for the enum API but the number 2560 * of texts is likely to be less than the number of 2561 * configurations due to the sample rate dependency of the 2562 * configurations. */ 2563 wm8996->num_retune_mobile_texts = 0; 2564 wm8996->retune_mobile_texts = NULL; 2565 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { 2566 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) { 2567 if (strcmp(pdata->retune_mobile_cfgs[i].name, 2568 wm8996->retune_mobile_texts[j]) == 0) 2569 break; 2570 } 2571 2572 if (j != wm8996->num_retune_mobile_texts) 2573 continue; 2574 2575 /* Expand the array... */ 2576 t = krealloc(wm8996->retune_mobile_texts, 2577 sizeof(char *) * 2578 (wm8996->num_retune_mobile_texts + 1), 2579 GFP_KERNEL); 2580 if (t == NULL) 2581 continue; 2582 2583 /* ...store the new entry... */ 2584 t[wm8996->num_retune_mobile_texts] = 2585 pdata->retune_mobile_cfgs[i].name; 2586 2587 /* ...and remember the new version. */ 2588 wm8996->num_retune_mobile_texts++; 2589 wm8996->retune_mobile_texts = t; 2590 } 2591 2592 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", 2593 wm8996->num_retune_mobile_texts); 2594 2595 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts; 2596 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts; 2597 2598 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2599 if (ret != 0) 2600 dev_err(codec->dev, 2601 "Failed to add ReTune Mobile controls: %d\n", ret); 2602 } 2603 2604 static const struct regmap_config wm8996_regmap = { 2605 .reg_bits = 16, 2606 .val_bits = 16, 2607 2608 .max_register = WM8996_MAX_REGISTER, 2609 .reg_defaults = wm8996_reg, 2610 .num_reg_defaults = ARRAY_SIZE(wm8996_reg), 2611 .volatile_reg = wm8996_volatile_register, 2612 .readable_reg = wm8996_readable_register, 2613 .cache_type = REGCACHE_RBTREE, 2614 }; 2615 2616 static int wm8996_probe(struct snd_soc_codec *codec) 2617 { 2618 int ret; 2619 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec); 2620 struct i2c_client *i2c = to_i2c_client(codec->dev); 2621 int irq_flags; 2622 2623 wm8996->codec = codec; 2624 2625 init_completion(&wm8996->dcs_done); 2626 init_completion(&wm8996->fll_lock); 2627 2628 if (wm8996->pdata.num_retune_mobile_cfgs) 2629 wm8996_retune_mobile_pdata(codec); 2630 else 2631 snd_soc_add_codec_controls(codec, wm8996_eq_controls, 2632 ARRAY_SIZE(wm8996_eq_controls)); 2633 2634 if (i2c->irq) { 2635 if (wm8996->pdata.irq_flags) 2636 irq_flags = wm8996->pdata.irq_flags; 2637 else 2638 irq_flags = IRQF_TRIGGER_LOW; 2639 2640 irq_flags |= IRQF_ONESHOT; 2641 2642 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) 2643 ret = request_threaded_irq(i2c->irq, NULL, 2644 wm8996_edge_irq, 2645 irq_flags, "wm8996", codec); 2646 else 2647 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq, 2648 irq_flags, "wm8996", codec); 2649 2650 if (ret == 0) { 2651 /* Unmask the interrupt */ 2652 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 2653 WM8996_IM_IRQ, 0); 2654 2655 /* Enable error reporting and DC servo status */ 2656 snd_soc_update_bits(codec, 2657 WM8996_INTERRUPT_STATUS_2_MASK, 2658 WM8996_IM_DCS_DONE_23_EINT | 2659 WM8996_IM_DCS_DONE_01_EINT | 2660 WM8996_IM_FLL_LOCK_EINT | 2661 WM8996_IM_FIFOS_ERR_EINT, 2662 0); 2663 } else { 2664 dev_err(codec->dev, "Failed to request IRQ: %d\n", 2665 ret); 2666 return ret; 2667 } 2668 } 2669 2670 return 0; 2671 } 2672 2673 static int wm8996_remove(struct snd_soc_codec *codec) 2674 { 2675 struct i2c_client *i2c = to_i2c_client(codec->dev); 2676 2677 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL, 2678 WM8996_IM_IRQ, WM8996_IM_IRQ); 2679 2680 if (i2c->irq) 2681 free_irq(i2c->irq, codec); 2682 2683 return 0; 2684 } 2685 2686 static struct snd_soc_codec_driver soc_codec_dev_wm8996 = { 2687 .probe = wm8996_probe, 2688 .remove = wm8996_remove, 2689 .set_bias_level = wm8996_set_bias_level, 2690 .idle_bias_off = true, 2691 .seq_notifier = wm8996_seq_notifier, 2692 .controls = wm8996_snd_controls, 2693 .num_controls = ARRAY_SIZE(wm8996_snd_controls), 2694 .dapm_widgets = wm8996_dapm_widgets, 2695 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets), 2696 .dapm_routes = wm8996_dapm_routes, 2697 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes), 2698 .set_pll = wm8996_set_fll, 2699 }; 2700 2701 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 2702 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\ 2703 SNDRV_PCM_RATE_48000) 2704 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\ 2705 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\ 2706 SNDRV_PCM_FMTBIT_S32_LE) 2707 2708 static const struct snd_soc_dai_ops wm8996_dai_ops = { 2709 .set_fmt = wm8996_set_fmt, 2710 .hw_params = wm8996_hw_params, 2711 .set_sysclk = wm8996_set_sysclk, 2712 }; 2713 2714 static struct snd_soc_dai_driver wm8996_dai[] = { 2715 { 2716 .name = "wm8996-aif1", 2717 .playback = { 2718 .stream_name = "AIF1 Playback", 2719 .channels_min = 1, 2720 .channels_max = 6, 2721 .rates = WM8996_RATES, 2722 .formats = WM8996_FORMATS, 2723 .sig_bits = 24, 2724 }, 2725 .capture = { 2726 .stream_name = "AIF1 Capture", 2727 .channels_min = 1, 2728 .channels_max = 6, 2729 .rates = WM8996_RATES, 2730 .formats = WM8996_FORMATS, 2731 .sig_bits = 24, 2732 }, 2733 .ops = &wm8996_dai_ops, 2734 }, 2735 { 2736 .name = "wm8996-aif2", 2737 .playback = { 2738 .stream_name = "AIF2 Playback", 2739 .channels_min = 1, 2740 .channels_max = 2, 2741 .rates = WM8996_RATES, 2742 .formats = WM8996_FORMATS, 2743 .sig_bits = 24, 2744 }, 2745 .capture = { 2746 .stream_name = "AIF2 Capture", 2747 .channels_min = 1, 2748 .channels_max = 2, 2749 .rates = WM8996_RATES, 2750 .formats = WM8996_FORMATS, 2751 .sig_bits = 24, 2752 }, 2753 .ops = &wm8996_dai_ops, 2754 }, 2755 }; 2756 2757 static int wm8996_i2c_probe(struct i2c_client *i2c, 2758 const struct i2c_device_id *id) 2759 { 2760 struct wm8996_priv *wm8996; 2761 int ret, i; 2762 unsigned int reg; 2763 2764 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv), 2765 GFP_KERNEL); 2766 if (wm8996 == NULL) 2767 return -ENOMEM; 2768 2769 i2c_set_clientdata(i2c, wm8996); 2770 wm8996->dev = &i2c->dev; 2771 2772 if (dev_get_platdata(&i2c->dev)) 2773 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev), 2774 sizeof(wm8996->pdata)); 2775 2776 if (wm8996->pdata.ldo_ena > 0) { 2777 ret = gpio_request_one(wm8996->pdata.ldo_ena, 2778 GPIOF_OUT_INIT_LOW, "WM8996 ENA"); 2779 if (ret < 0) { 2780 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n", 2781 wm8996->pdata.ldo_ena, ret); 2782 goto err; 2783 } 2784 } 2785 2786 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 2787 wm8996->supplies[i].supply = wm8996_supply_names[i]; 2788 2789 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies), 2790 wm8996->supplies); 2791 if (ret != 0) { 2792 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 2793 goto err_gpio; 2794 } 2795 2796 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0; 2797 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1; 2798 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2; 2799 2800 /* This should really be moved into the regulator core */ 2801 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) { 2802 ret = regulator_register_notifier(wm8996->supplies[i].consumer, 2803 &wm8996->disable_nb[i]); 2804 if (ret != 0) { 2805 dev_err(&i2c->dev, 2806 "Failed to register regulator notifier: %d\n", 2807 ret); 2808 } 2809 } 2810 2811 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies), 2812 wm8996->supplies); 2813 if (ret != 0) { 2814 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 2815 goto err_gpio; 2816 } 2817 2818 if (wm8996->pdata.ldo_ena > 0) { 2819 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1); 2820 msleep(5); 2821 } 2822 2823 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap); 2824 if (IS_ERR(wm8996->regmap)) { 2825 ret = PTR_ERR(wm8996->regmap); 2826 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 2827 goto err_enable; 2828 } 2829 2830 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, ®); 2831 if (ret < 0) { 2832 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); 2833 goto err_regmap; 2834 } 2835 if (reg != 0x8915) { 2836 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg); 2837 ret = -EINVAL; 2838 goto err_regmap; 2839 } 2840 2841 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, ®); 2842 if (ret < 0) { 2843 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 2844 ret); 2845 goto err_regmap; 2846 } 2847 2848 dev_info(&i2c->dev, "revision %c\n", 2849 (reg & WM8996_CHIP_REV_MASK) + 'A'); 2850 2851 if (wm8996->pdata.ldo_ena > 0) { 2852 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 2853 regcache_cache_only(wm8996->regmap, true); 2854 } else { 2855 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET, 2856 0x8915); 2857 if (ret != 0) { 2858 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 2859 goto err_regmap; 2860 } 2861 } 2862 2863 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 2864 2865 /* Apply platform data settings */ 2866 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL, 2867 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK, 2868 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT | 2869 wm8996->pdata.inr_mode); 2870 2871 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) { 2872 if (!wm8996->pdata.gpio_default[i]) 2873 continue; 2874 2875 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i, 2876 wm8996->pdata.gpio_default[i] & 0xffff); 2877 } 2878 2879 if (wm8996->pdata.spkmute_seq) 2880 regmap_update_bits(wm8996->regmap, 2881 WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 2882 WM8996_SPK_MUTE_ENDIAN | 2883 WM8996_SPK_MUTE_SEQ1_MASK, 2884 wm8996->pdata.spkmute_seq); 2885 2886 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2, 2887 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC | 2888 WM8996_MICD_SRC, wm8996->pdata.micdet_def); 2889 2890 /* Latch volume update bits */ 2891 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME, 2892 WM8996_IN1_VU, WM8996_IN1_VU); 2893 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME, 2894 WM8996_IN1_VU, WM8996_IN1_VU); 2895 2896 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME, 2897 WM8996_DAC1_VU, WM8996_DAC1_VU); 2898 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME, 2899 WM8996_DAC1_VU, WM8996_DAC1_VU); 2900 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME, 2901 WM8996_DAC2_VU, WM8996_DAC2_VU); 2902 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME, 2903 WM8996_DAC2_VU, WM8996_DAC2_VU); 2904 2905 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME, 2906 WM8996_DAC1_VU, WM8996_DAC1_VU); 2907 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME, 2908 WM8996_DAC1_VU, WM8996_DAC1_VU); 2909 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME, 2910 WM8996_DAC2_VU, WM8996_DAC2_VU); 2911 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME, 2912 WM8996_DAC2_VU, WM8996_DAC2_VU); 2913 2914 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME, 2915 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2916 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME, 2917 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU); 2918 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME, 2919 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2920 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME, 2921 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU); 2922 2923 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME, 2924 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2925 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME, 2926 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU); 2927 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME, 2928 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2929 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME, 2930 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU); 2931 2932 /* No support currently for the underclocked TDM modes and 2933 * pick a default TDM layout with each channel pair working with 2934 * slots 0 and 1. */ 2935 regmap_update_bits(wm8996->regmap, 2936 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 2937 WM8996_AIF1RX_CHAN0_SLOTS_MASK | 2938 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2939 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0); 2940 regmap_update_bits(wm8996->regmap, 2941 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 2942 WM8996_AIF1RX_CHAN1_SLOTS_MASK | 2943 WM8996_AIF1RX_CHAN1_START_SLOT_MASK, 2944 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1); 2945 regmap_update_bits(wm8996->regmap, 2946 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 2947 WM8996_AIF1RX_CHAN2_SLOTS_MASK | 2948 WM8996_AIF1RX_CHAN2_START_SLOT_MASK, 2949 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0); 2950 regmap_update_bits(wm8996->regmap, 2951 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 2952 WM8996_AIF1RX_CHAN3_SLOTS_MASK | 2953 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2954 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1); 2955 regmap_update_bits(wm8996->regmap, 2956 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 2957 WM8996_AIF1RX_CHAN4_SLOTS_MASK | 2958 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2959 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0); 2960 regmap_update_bits(wm8996->regmap, 2961 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 2962 WM8996_AIF1RX_CHAN5_SLOTS_MASK | 2963 WM8996_AIF1RX_CHAN0_START_SLOT_MASK, 2964 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1); 2965 2966 regmap_update_bits(wm8996->regmap, 2967 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 2968 WM8996_AIF2RX_CHAN0_SLOTS_MASK | 2969 WM8996_AIF2RX_CHAN0_START_SLOT_MASK, 2970 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0); 2971 regmap_update_bits(wm8996->regmap, 2972 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 2973 WM8996_AIF2RX_CHAN1_SLOTS_MASK | 2974 WM8996_AIF2RX_CHAN1_START_SLOT_MASK, 2975 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1); 2976 2977 regmap_update_bits(wm8996->regmap, 2978 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 2979 WM8996_AIF1TX_CHAN0_SLOTS_MASK | 2980 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2981 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0); 2982 regmap_update_bits(wm8996->regmap, 2983 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 2984 WM8996_AIF1TX_CHAN1_SLOTS_MASK | 2985 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2986 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 2987 regmap_update_bits(wm8996->regmap, 2988 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 2989 WM8996_AIF1TX_CHAN2_SLOTS_MASK | 2990 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2991 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0); 2992 regmap_update_bits(wm8996->regmap, 2993 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 2994 WM8996_AIF1TX_CHAN3_SLOTS_MASK | 2995 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 2996 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1); 2997 regmap_update_bits(wm8996->regmap, 2998 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 2999 WM8996_AIF1TX_CHAN4_SLOTS_MASK | 3000 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3001 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0); 3002 regmap_update_bits(wm8996->regmap, 3003 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 3004 WM8996_AIF1TX_CHAN5_SLOTS_MASK | 3005 WM8996_AIF1TX_CHAN0_START_SLOT_MASK, 3006 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1); 3007 3008 regmap_update_bits(wm8996->regmap, 3009 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 3010 WM8996_AIF2TX_CHAN0_SLOTS_MASK | 3011 WM8996_AIF2TX_CHAN0_START_SLOT_MASK, 3012 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0); 3013 regmap_update_bits(wm8996->regmap, 3014 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 3015 WM8996_AIF2TX_CHAN1_SLOTS_MASK | 3016 WM8996_AIF2TX_CHAN1_START_SLOT_MASK, 3017 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1); 3018 3019 /* If the TX LRCLK pins are not in LRCLK mode configure the 3020 * AIFs to source their clocks from the RX LRCLKs. 3021 */ 3022 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, ®); 3023 if (ret != 0) { 3024 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret); 3025 goto err_regmap; 3026 } 3027 3028 if (reg & WM8996_GP1_FN_MASK) 3029 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2, 3030 WM8996_AIF1TX_LRCLK_MODE, 3031 WM8996_AIF1TX_LRCLK_MODE); 3032 3033 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, ®); 3034 if (ret != 0) { 3035 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret); 3036 goto err_regmap; 3037 } 3038 3039 if (reg & WM8996_GP2_FN_MASK) 3040 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2, 3041 WM8996_AIF2TX_LRCLK_MODE, 3042 WM8996_AIF2TX_LRCLK_MODE); 3043 3044 wm8996_init_gpio(wm8996); 3045 3046 ret = snd_soc_register_codec(&i2c->dev, 3047 &soc_codec_dev_wm8996, wm8996_dai, 3048 ARRAY_SIZE(wm8996_dai)); 3049 if (ret < 0) 3050 goto err_gpiolib; 3051 3052 return ret; 3053 3054 err_gpiolib: 3055 wm8996_free_gpio(wm8996); 3056 err_regmap: 3057 err_enable: 3058 if (wm8996->pdata.ldo_ena > 0) 3059 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3060 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies); 3061 err_gpio: 3062 if (wm8996->pdata.ldo_ena > 0) 3063 gpio_free(wm8996->pdata.ldo_ena); 3064 err: 3065 3066 return ret; 3067 } 3068 3069 static int wm8996_i2c_remove(struct i2c_client *client) 3070 { 3071 struct wm8996_priv *wm8996 = i2c_get_clientdata(client); 3072 int i; 3073 3074 snd_soc_unregister_codec(&client->dev); 3075 wm8996_free_gpio(wm8996); 3076 if (wm8996->pdata.ldo_ena > 0) { 3077 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0); 3078 gpio_free(wm8996->pdata.ldo_ena); 3079 } 3080 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) 3081 regulator_unregister_notifier(wm8996->supplies[i].consumer, 3082 &wm8996->disable_nb[i]); 3083 3084 return 0; 3085 } 3086 3087 static const struct i2c_device_id wm8996_i2c_id[] = { 3088 { "wm8996", 0 }, 3089 { } 3090 }; 3091 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id); 3092 3093 static struct i2c_driver wm8996_i2c_driver = { 3094 .driver = { 3095 .name = "wm8996", 3096 .owner = THIS_MODULE, 3097 }, 3098 .probe = wm8996_i2c_probe, 3099 .remove = wm8996_i2c_remove, 3100 .id_table = wm8996_i2c_id, 3101 }; 3102 3103 module_i2c_driver(wm8996_i2c_driver); 3104 3105 MODULE_DESCRIPTION("ASoC WM8996 driver"); 3106 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 3107 MODULE_LICENSE("GPL"); 3108