16a504a75SDimitris Papastamos /* 26a504a75SDimitris Papastamos * wm8995.h -- WM8995 ALSA SoC Audio driver 36a504a75SDimitris Papastamos * 46a504a75SDimitris Papastamos * Copyright 2010 Wolfson Microelectronics plc 56a504a75SDimitris Papastamos * 66a504a75SDimitris Papastamos * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 76a504a75SDimitris Papastamos * 86a504a75SDimitris Papastamos * This program is free software; you can redistribute it and/or modify 96a504a75SDimitris Papastamos * it under the terms of the GNU General Public License version 2 as 106a504a75SDimitris Papastamos * published by the Free Software Foundation. 116a504a75SDimitris Papastamos */ 126a504a75SDimitris Papastamos 136a504a75SDimitris Papastamos #ifndef _WM8995_H 146a504a75SDimitris Papastamos #define _WM8995_H 156a504a75SDimitris Papastamos 166a504a75SDimitris Papastamos #include <asm/types.h> 176a504a75SDimitris Papastamos 186a504a75SDimitris Papastamos /* 196a504a75SDimitris Papastamos * Register values. 206a504a75SDimitris Papastamos */ 216a504a75SDimitris Papastamos #define WM8995_SOFTWARE_RESET 0x00 226a504a75SDimitris Papastamos #define WM8995_POWER_MANAGEMENT_1 0x01 236a504a75SDimitris Papastamos #define WM8995_POWER_MANAGEMENT_2 0x02 246a504a75SDimitris Papastamos #define WM8995_POWER_MANAGEMENT_3 0x03 256a504a75SDimitris Papastamos #define WM8995_POWER_MANAGEMENT_4 0x04 266a504a75SDimitris Papastamos #define WM8995_POWER_MANAGEMENT_5 0x05 276a504a75SDimitris Papastamos #define WM8995_LEFT_LINE_INPUT_1_VOLUME 0x10 286a504a75SDimitris Papastamos #define WM8995_RIGHT_LINE_INPUT_1_VOLUME 0x11 296a504a75SDimitris Papastamos #define WM8995_LEFT_LINE_INPUT_CONTROL 0x12 306a504a75SDimitris Papastamos #define WM8995_DAC1_LEFT_VOLUME 0x18 316a504a75SDimitris Papastamos #define WM8995_DAC1_RIGHT_VOLUME 0x19 326a504a75SDimitris Papastamos #define WM8995_DAC2_LEFT_VOLUME 0x1A 336a504a75SDimitris Papastamos #define WM8995_DAC2_RIGHT_VOLUME 0x1B 346a504a75SDimitris Papastamos #define WM8995_OUTPUT_VOLUME_ZC_1 0x1C 356a504a75SDimitris Papastamos #define WM8995_MICBIAS_1 0x20 366a504a75SDimitris Papastamos #define WM8995_MICBIAS_2 0x21 376a504a75SDimitris Papastamos #define WM8995_LDO_1 0x28 386a504a75SDimitris Papastamos #define WM8995_LDO_2 0x29 396a504a75SDimitris Papastamos #define WM8995_ACCESSORY_DETECT_MODE1 0x30 406a504a75SDimitris Papastamos #define WM8995_ACCESSORY_DETECT_MODE2 0x31 416a504a75SDimitris Papastamos #define WM8995_HEADPHONE_DETECT1 0x34 426a504a75SDimitris Papastamos #define WM8995_HEADPHONE_DETECT2 0x35 436a504a75SDimitris Papastamos #define WM8995_MIC_DETECT_1 0x38 446a504a75SDimitris Papastamos #define WM8995_MIC_DETECT_2 0x39 456a504a75SDimitris Papastamos #define WM8995_CHARGE_PUMP_1 0x40 466a504a75SDimitris Papastamos #define WM8995_CLASS_W_1 0x45 476a504a75SDimitris Papastamos #define WM8995_DC_SERVO_1 0x50 486a504a75SDimitris Papastamos #define WM8995_DC_SERVO_2 0x51 496a504a75SDimitris Papastamos #define WM8995_DC_SERVO_3 0x52 506a504a75SDimitris Papastamos #define WM8995_DC_SERVO_5 0x54 516a504a75SDimitris Papastamos #define WM8995_DC_SERVO_6 0x55 526a504a75SDimitris Papastamos #define WM8995_DC_SERVO_7 0x56 536a504a75SDimitris Papastamos #define WM8995_DC_SERVO_READBACK_0 0x57 546a504a75SDimitris Papastamos #define WM8995_ANALOGUE_HP_1 0x60 556a504a75SDimitris Papastamos #define WM8995_ANALOGUE_HP_2 0x61 566a504a75SDimitris Papastamos #define WM8995_CHIP_REVISION 0x100 576a504a75SDimitris Papastamos #define WM8995_CONTROL_INTERFACE_1 0x101 586a504a75SDimitris Papastamos #define WM8995_CONTROL_INTERFACE_2 0x102 596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_CTRL_1 0x110 606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_CTRL_2 0x111 616a504a75SDimitris Papastamos #define WM8995_AIF1_CLOCKING_1 0x200 626a504a75SDimitris Papastamos #define WM8995_AIF1_CLOCKING_2 0x201 636a504a75SDimitris Papastamos #define WM8995_AIF2_CLOCKING_1 0x204 646a504a75SDimitris Papastamos #define WM8995_AIF2_CLOCKING_2 0x205 656a504a75SDimitris Papastamos #define WM8995_CLOCKING_1 0x208 666a504a75SDimitris Papastamos #define WM8995_CLOCKING_2 0x209 676a504a75SDimitris Papastamos #define WM8995_AIF1_RATE 0x210 686a504a75SDimitris Papastamos #define WM8995_AIF2_RATE 0x211 696a504a75SDimitris Papastamos #define WM8995_RATE_STATUS 0x212 706a504a75SDimitris Papastamos #define WM8995_FLL1_CONTROL_1 0x220 716a504a75SDimitris Papastamos #define WM8995_FLL1_CONTROL_2 0x221 726a504a75SDimitris Papastamos #define WM8995_FLL1_CONTROL_3 0x222 736a504a75SDimitris Papastamos #define WM8995_FLL1_CONTROL_4 0x223 746a504a75SDimitris Papastamos #define WM8995_FLL1_CONTROL_5 0x224 756a504a75SDimitris Papastamos #define WM8995_FLL2_CONTROL_1 0x240 766a504a75SDimitris Papastamos #define WM8995_FLL2_CONTROL_2 0x241 776a504a75SDimitris Papastamos #define WM8995_FLL2_CONTROL_3 0x242 786a504a75SDimitris Papastamos #define WM8995_FLL2_CONTROL_4 0x243 796a504a75SDimitris Papastamos #define WM8995_FLL2_CONTROL_5 0x244 806a504a75SDimitris Papastamos #define WM8995_AIF1_CONTROL_1 0x300 816a504a75SDimitris Papastamos #define WM8995_AIF1_CONTROL_2 0x301 826a504a75SDimitris Papastamos #define WM8995_AIF1_MASTER_SLAVE 0x302 836a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK 0x303 846a504a75SDimitris Papastamos #define WM8995_AIF1ADC_LRCLK 0x304 856a504a75SDimitris Papastamos #define WM8995_AIF1DAC_LRCLK 0x305 866a504a75SDimitris Papastamos #define WM8995_AIF1DAC_DATA 0x306 876a504a75SDimitris Papastamos #define WM8995_AIF1ADC_DATA 0x307 886a504a75SDimitris Papastamos #define WM8995_AIF2_CONTROL_1 0x310 896a504a75SDimitris Papastamos #define WM8995_AIF2_CONTROL_2 0x311 906a504a75SDimitris Papastamos #define WM8995_AIF2_MASTER_SLAVE 0x312 916a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK 0x313 926a504a75SDimitris Papastamos #define WM8995_AIF2ADC_LRCLK 0x314 936a504a75SDimitris Papastamos #define WM8995_AIF2DAC_LRCLK 0x315 946a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DATA 0x316 956a504a75SDimitris Papastamos #define WM8995_AIF2ADC_DATA 0x317 966a504a75SDimitris Papastamos #define WM8995_AIF1_ADC1_LEFT_VOLUME 0x400 976a504a75SDimitris Papastamos #define WM8995_AIF1_ADC1_RIGHT_VOLUME 0x401 986a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_LEFT_VOLUME 0x402 996a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_RIGHT_VOLUME 0x403 1006a504a75SDimitris Papastamos #define WM8995_AIF1_ADC2_LEFT_VOLUME 0x404 1016a504a75SDimitris Papastamos #define WM8995_AIF1_ADC2_RIGHT_VOLUME 0x405 1026a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_LEFT_VOLUME 0x406 1036a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_RIGHT_VOLUME 0x407 1046a504a75SDimitris Papastamos #define WM8995_AIF1_ADC1_FILTERS 0x410 1056a504a75SDimitris Papastamos #define WM8995_AIF1_ADC2_FILTERS 0x411 1066a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_FILTERS_1 0x420 1076a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_FILTERS_2 0x421 1086a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_FILTERS_1 0x422 1096a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_FILTERS_2 0x423 1106a504a75SDimitris Papastamos #define WM8995_AIF1_DRC1_1 0x440 1116a504a75SDimitris Papastamos #define WM8995_AIF1_DRC1_2 0x441 1126a504a75SDimitris Papastamos #define WM8995_AIF1_DRC1_3 0x442 1136a504a75SDimitris Papastamos #define WM8995_AIF1_DRC1_4 0x443 1146a504a75SDimitris Papastamos #define WM8995_AIF1_DRC1_5 0x444 1156a504a75SDimitris Papastamos #define WM8995_AIF1_DRC2_1 0x450 1166a504a75SDimitris Papastamos #define WM8995_AIF1_DRC2_2 0x451 1176a504a75SDimitris Papastamos #define WM8995_AIF1_DRC2_3 0x452 1186a504a75SDimitris Papastamos #define WM8995_AIF1_DRC2_4 0x453 1196a504a75SDimitris Papastamos #define WM8995_AIF1_DRC2_5 0x454 1206a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_GAINS_1 0x480 1216a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_GAINS_2 0x481 1226a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_1_A 0x482 1236a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_1_B 0x483 1246a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_1_PG 0x484 1256a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_2_A 0x485 1266a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_2_B 0x486 1276a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_2_C 0x487 1286a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_2_PG 0x488 1296a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_3_A 0x489 1306a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_3_B 0x48A 1316a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_3_C 0x48B 1326a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_3_PG 0x48C 1336a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_4_A 0x48D 1346a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_4_B 0x48E 1356a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_4_C 0x48F 1366a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_4_PG 0x490 1376a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_5_A 0x491 1386a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_5_B 0x492 1396a504a75SDimitris Papastamos #define WM8995_AIF1_DAC1_EQ_BAND_5_PG 0x493 1406a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_GAINS_1 0x4A0 1416a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_GAINS_2 0x4A1 1426a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_1_A 0x4A2 1436a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_1_B 0x4A3 1446a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_1_PG 0x4A4 1456a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_2_A 0x4A5 1466a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_2_B 0x4A6 1476a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_2_C 0x4A7 1486a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_2_PG 0x4A8 1496a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_3_A 0x4A9 1506a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_3_B 0x4AA 1516a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_3_C 0x4AB 1526a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_3_PG 0x4AC 1536a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_4_A 0x4AD 1546a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_4_B 0x4AE 1556a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_4_C 0x4AF 1566a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_4_PG 0x4B0 1576a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_5_A 0x4B1 1586a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_5_B 0x4B2 1596a504a75SDimitris Papastamos #define WM8995_AIF1_DAC2_EQ_BAND_5_PG 0x4B3 1606a504a75SDimitris Papastamos #define WM8995_AIF2_ADC_LEFT_VOLUME 0x500 1616a504a75SDimitris Papastamos #define WM8995_AIF2_ADC_RIGHT_VOLUME 0x501 1626a504a75SDimitris Papastamos #define WM8995_AIF2_DAC_LEFT_VOLUME 0x502 1636a504a75SDimitris Papastamos #define WM8995_AIF2_DAC_RIGHT_VOLUME 0x503 1646a504a75SDimitris Papastamos #define WM8995_AIF2_ADC_FILTERS 0x510 1656a504a75SDimitris Papastamos #define WM8995_AIF2_DAC_FILTERS_1 0x520 1666a504a75SDimitris Papastamos #define WM8995_AIF2_DAC_FILTERS_2 0x521 1676a504a75SDimitris Papastamos #define WM8995_AIF2_DRC_1 0x540 1686a504a75SDimitris Papastamos #define WM8995_AIF2_DRC_2 0x541 1696a504a75SDimitris Papastamos #define WM8995_AIF2_DRC_3 0x542 1706a504a75SDimitris Papastamos #define WM8995_AIF2_DRC_4 0x543 1716a504a75SDimitris Papastamos #define WM8995_AIF2_DRC_5 0x544 1726a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_GAINS_1 0x580 1736a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_GAINS_2 0x581 1746a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_1_A 0x582 1756a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_1_B 0x583 1766a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_1_PG 0x584 1776a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_2_A 0x585 1786a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_2_B 0x586 1796a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_2_C 0x587 1806a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_2_PG 0x588 1816a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_3_A 0x589 1826a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_3_B 0x58A 1836a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_3_C 0x58B 1846a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_3_PG 0x58C 1856a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_4_A 0x58D 1866a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_4_B 0x58E 1876a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_4_C 0x58F 1886a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_4_PG 0x590 1896a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_5_A 0x591 1906a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_5_B 0x592 1916a504a75SDimitris Papastamos #define WM8995_AIF2_EQ_BAND_5_PG 0x593 1926a504a75SDimitris Papastamos #define WM8995_DAC1_MIXER_VOLUMES 0x600 1936a504a75SDimitris Papastamos #define WM8995_DAC1_LEFT_MIXER_ROUTING 0x601 1946a504a75SDimitris Papastamos #define WM8995_DAC1_RIGHT_MIXER_ROUTING 0x602 1956a504a75SDimitris Papastamos #define WM8995_DAC2_MIXER_VOLUMES 0x603 1966a504a75SDimitris Papastamos #define WM8995_DAC2_LEFT_MIXER_ROUTING 0x604 1976a504a75SDimitris Papastamos #define WM8995_DAC2_RIGHT_MIXER_ROUTING 0x605 1986a504a75SDimitris Papastamos #define WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING 0x606 1996a504a75SDimitris Papastamos #define WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING 0x607 2006a504a75SDimitris Papastamos #define WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING 0x608 2016a504a75SDimitris Papastamos #define WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING 0x609 2026a504a75SDimitris Papastamos #define WM8995_DAC_SOFTMUTE 0x610 2036a504a75SDimitris Papastamos #define WM8995_OVERSAMPLING 0x620 2046a504a75SDimitris Papastamos #define WM8995_SIDETONE 0x621 2056a504a75SDimitris Papastamos #define WM8995_GPIO_1 0x700 2066a504a75SDimitris Papastamos #define WM8995_GPIO_2 0x701 2076a504a75SDimitris Papastamos #define WM8995_GPIO_3 0x702 2086a504a75SDimitris Papastamos #define WM8995_GPIO_4 0x703 2096a504a75SDimitris Papastamos #define WM8995_GPIO_5 0x704 2106a504a75SDimitris Papastamos #define WM8995_GPIO_6 0x705 2116a504a75SDimitris Papastamos #define WM8995_GPIO_7 0x706 2126a504a75SDimitris Papastamos #define WM8995_GPIO_8 0x707 2136a504a75SDimitris Papastamos #define WM8995_GPIO_9 0x708 2146a504a75SDimitris Papastamos #define WM8995_GPIO_10 0x709 2156a504a75SDimitris Papastamos #define WM8995_GPIO_11 0x70A 2166a504a75SDimitris Papastamos #define WM8995_GPIO_12 0x70B 2176a504a75SDimitris Papastamos #define WM8995_GPIO_13 0x70C 2186a504a75SDimitris Papastamos #define WM8995_GPIO_14 0x70D 2196a504a75SDimitris Papastamos #define WM8995_PULL_CONTROL_1 0x720 2206a504a75SDimitris Papastamos #define WM8995_PULL_CONTROL_2 0x721 2216a504a75SDimitris Papastamos #define WM8995_INTERRUPT_STATUS_1 0x730 2226a504a75SDimitris Papastamos #define WM8995_INTERRUPT_STATUS_2 0x731 2236a504a75SDimitris Papastamos #define WM8995_INTERRUPT_RAW_STATUS_2 0x732 2246a504a75SDimitris Papastamos #define WM8995_INTERRUPT_STATUS_1_MASK 0x738 2256a504a75SDimitris Papastamos #define WM8995_INTERRUPT_STATUS_2_MASK 0x739 2266a504a75SDimitris Papastamos #define WM8995_INTERRUPT_CONTROL 0x740 2276a504a75SDimitris Papastamos #define WM8995_LEFT_PDM_SPEAKER_1 0x800 2286a504a75SDimitris Papastamos #define WM8995_RIGHT_PDM_SPEAKER_1 0x801 2296a504a75SDimitris Papastamos #define WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE 0x802 2306a504a75SDimitris Papastamos #define WM8995_LEFT_PDM_SPEAKER_2 0x808 2316a504a75SDimitris Papastamos #define WM8995_RIGHT_PDM_SPEAKER_2 0x809 2326a504a75SDimitris Papastamos #define WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE 0x80A 2336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_0 0x3000 2346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_1 0x3001 2356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_2 0x3002 2366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_3 0x3003 2376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_4 0x3004 2386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_5 0x3005 2396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_6 0x3006 2406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_7 0x3007 2416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_8 0x3008 2426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_9 0x3009 2436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_10 0x300A 2446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_11 0x300B 2456a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_12 0x300C 2466a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_13 0x300D 2476a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_14 0x300E 2486a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_15 0x300F 2496a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_16 0x3010 2506a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_17 0x3011 2516a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_18 0x3012 2526a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_19 0x3013 2536a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_20 0x3014 2546a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_21 0x3015 2556a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_22 0x3016 2566a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_23 0x3017 2576a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_24 0x3018 2586a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_25 0x3019 2596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_26 0x301A 2606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_27 0x301B 2616a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_28 0x301C 2626a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_29 0x301D 2636a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_30 0x301E 2646a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_31 0x301F 2656a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_32 0x3020 2666a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_33 0x3021 2676a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_34 0x3022 2686a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_35 0x3023 2696a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_36 0x3024 2706a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_37 0x3025 2716a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_38 0x3026 2726a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_39 0x3027 2736a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_40 0x3028 2746a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_41 0x3029 2756a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_42 0x302A 2766a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_43 0x302B 2776a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_44 0x302C 2786a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_45 0x302D 2796a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_46 0x302E 2806a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_47 0x302F 2816a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_48 0x3030 2826a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_49 0x3031 2836a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_50 0x3032 2846a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_51 0x3033 2856a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_52 0x3034 2866a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_53 0x3035 2876a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_54 0x3036 2886a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_55 0x3037 2896a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_56 0x3038 2906a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_57 0x3039 2916a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_58 0x303A 2926a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_59 0x303B 2936a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_60 0x303C 2946a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_61 0x303D 2956a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_62 0x303E 2966a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_63 0x303F 2976a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_64 0x3040 2986a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_65 0x3041 2996a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_66 0x3042 3006a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_67 0x3043 3016a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_68 0x3044 3026a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_69 0x3045 3036a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_70 0x3046 3046a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_71 0x3047 3056a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_72 0x3048 3066a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_73 0x3049 3076a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_74 0x304A 3086a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_75 0x304B 3096a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_76 0x304C 3106a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_77 0x304D 3116a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_78 0x304E 3126a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_79 0x304F 3136a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_80 0x3050 3146a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_81 0x3051 3156a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_82 0x3052 3166a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_83 0x3053 3176a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_84 0x3054 3186a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_85 0x3055 3196a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_86 0x3056 3206a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_87 0x3057 3216a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_88 0x3058 3226a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_89 0x3059 3236a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_90 0x305A 3246a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_91 0x305B 3256a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_92 0x305C 3266a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_93 0x305D 3276a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_94 0x305E 3286a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_95 0x305F 3296a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_96 0x3060 3306a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_97 0x3061 3316a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_98 0x3062 3326a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_99 0x3063 3336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_100 0x3064 3346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_101 0x3065 3356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_102 0x3066 3366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_103 0x3067 3376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_104 0x3068 3386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_105 0x3069 3396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_106 0x306A 3406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_107 0x306B 3416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_108 0x306C 3426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_109 0x306D 3436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_110 0x306E 3446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_111 0x306F 3456a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_112 0x3070 3466a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_113 0x3071 3476a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_114 0x3072 3486a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_115 0x3073 3496a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_116 0x3074 3506a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_117 0x3075 3516a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_118 0x3076 3526a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_119 0x3077 3536a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_120 0x3078 3546a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_121 0x3079 3556a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_122 0x307A 3566a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_123 0x307B 3576a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_124 0x307C 3586a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_125 0x307D 3596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_126 0x307E 3606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_127 0x307F 3616a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_128 0x3080 3626a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_129 0x3081 3636a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_130 0x3082 3646a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_131 0x3083 3656a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_132 0x3084 3666a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_133 0x3085 3676a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_134 0x3086 3686a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_135 0x3087 3696a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_136 0x3088 3706a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_137 0x3089 3716a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_138 0x308A 3726a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_139 0x308B 3736a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_140 0x308C 3746a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_141 0x308D 3756a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_142 0x308E 3766a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_143 0x308F 3776a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_144 0x3090 3786a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_145 0x3091 3796a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_146 0x3092 3806a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_147 0x3093 3816a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_148 0x3094 3826a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_149 0x3095 3836a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_150 0x3096 3846a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_151 0x3097 3856a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_152 0x3098 3866a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_153 0x3099 3876a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_154 0x309A 3886a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_155 0x309B 3896a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_156 0x309C 3906a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_157 0x309D 3916a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_158 0x309E 3926a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_159 0x309F 3936a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_160 0x30A0 3946a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_161 0x30A1 3956a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_162 0x30A2 3966a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_163 0x30A3 3976a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_164 0x30A4 3986a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_165 0x30A5 3996a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_166 0x30A6 4006a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_167 0x30A7 4016a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_168 0x30A8 4026a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_169 0x30A9 4036a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_170 0x30AA 4046a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_171 0x30AB 4056a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_172 0x30AC 4066a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_173 0x30AD 4076a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_174 0x30AE 4086a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_175 0x30AF 4096a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_176 0x30B0 4106a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_177 0x30B1 4116a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_178 0x30B2 4126a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_179 0x30B3 4136a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_180 0x30B4 4146a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_181 0x30B5 4156a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_182 0x30B6 4166a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_183 0x30B7 4176a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_184 0x30B8 4186a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_185 0x30B9 4196a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_186 0x30BA 4206a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_187 0x30BB 4216a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_188 0x30BC 4226a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_189 0x30BD 4236a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_190 0x30BE 4246a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_191 0x30BF 4256a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_192 0x30C0 4266a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_193 0x30C1 4276a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_194 0x30C2 4286a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_195 0x30C3 4296a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_196 0x30C4 4306a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_197 0x30C5 4316a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_198 0x30C6 4326a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_199 0x30C7 4336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_200 0x30C8 4346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_201 0x30C9 4356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_202 0x30CA 4366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_203 0x30CB 4376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_204 0x30CC 4386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_205 0x30CD 4396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_206 0x30CE 4406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_207 0x30CF 4416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_208 0x30D0 4426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_209 0x30D1 4436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_210 0x30D2 4446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_211 0x30D3 4456a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_212 0x30D4 4466a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_213 0x30D5 4476a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_214 0x30D6 4486a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_215 0x30D7 4496a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_216 0x30D8 4506a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_217 0x30D9 4516a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_218 0x30DA 4526a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_219 0x30DB 4536a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_220 0x30DC 4546a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_221 0x30DD 4556a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_222 0x30DE 4566a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_223 0x30DF 4576a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_224 0x30E0 4586a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_225 0x30E1 4596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_226 0x30E2 4606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_227 0x30E3 4616a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_228 0x30E4 4626a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_229 0x30E5 4636a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_230 0x30E6 4646a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_231 0x30E7 4656a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_232 0x30E8 4666a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_233 0x30E9 4676a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_234 0x30EA 4686a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_235 0x30EB 4696a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_236 0x30EC 4706a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_237 0x30ED 4716a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_238 0x30EE 4726a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_239 0x30EF 4736a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_240 0x30F0 4746a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_241 0x30F1 4756a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_242 0x30F2 4766a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_243 0x30F3 4776a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_244 0x30F4 4786a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_245 0x30F5 4796a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_246 0x30F6 4806a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_247 0x30F7 4816a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_248 0x30F8 4826a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_249 0x30F9 4836a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_250 0x30FA 4846a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_251 0x30FB 4856a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_252 0x30FC 4866a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_253 0x30FD 4876a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_254 0x30FE 4886a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_255 0x30FF 4896a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_256 0x3100 4906a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_257 0x3101 4916a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_258 0x3102 4926a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_259 0x3103 4936a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_260 0x3104 4946a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_261 0x3105 4956a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_262 0x3106 4966a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_263 0x3107 4976a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_264 0x3108 4986a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_265 0x3109 4996a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_266 0x310A 5006a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_267 0x310B 5016a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_268 0x310C 5026a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_269 0x310D 5036a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_270 0x310E 5046a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_271 0x310F 5056a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_272 0x3110 5066a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_273 0x3111 5076a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_274 0x3112 5086a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_275 0x3113 5096a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_276 0x3114 5106a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_277 0x3115 5116a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_278 0x3116 5126a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_279 0x3117 5136a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_280 0x3118 5146a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_281 0x3119 5156a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_282 0x311A 5166a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_283 0x311B 5176a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_284 0x311C 5186a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_285 0x311D 5196a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_286 0x311E 5206a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_287 0x311F 5216a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_288 0x3120 5226a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_289 0x3121 5236a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_290 0x3122 5246a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_291 0x3123 5256a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_292 0x3124 5266a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_293 0x3125 5276a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_294 0x3126 5286a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_295 0x3127 5296a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_296 0x3128 5306a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_297 0x3129 5316a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_298 0x312A 5326a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_299 0x312B 5336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_300 0x312C 5346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_301 0x312D 5356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_302 0x312E 5366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_303 0x312F 5376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_304 0x3130 5386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_305 0x3131 5396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_306 0x3132 5406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_307 0x3133 5416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_308 0x3134 5426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_309 0x3135 5436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_310 0x3136 5446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_311 0x3137 5456a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_312 0x3138 5466a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_313 0x3139 5476a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_314 0x313A 5486a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_315 0x313B 5496a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_316 0x313C 5506a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_317 0x313D 5516a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_318 0x313E 5526a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_319 0x313F 5536a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_320 0x3140 5546a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_321 0x3141 5556a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_322 0x3142 5566a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_323 0x3143 5576a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_324 0x3144 5586a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_325 0x3145 5596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_326 0x3146 5606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_327 0x3147 5616a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_328 0x3148 5626a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_329 0x3149 5636a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_330 0x314A 5646a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_331 0x314B 5656a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_332 0x314C 5666a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_333 0x314D 5676a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_334 0x314E 5686a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_335 0x314F 5696a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_336 0x3150 5706a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_337 0x3151 5716a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_338 0x3152 5726a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_339 0x3153 5736a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_340 0x3154 5746a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_341 0x3155 5756a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_342 0x3156 5766a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_343 0x3157 5776a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_344 0x3158 5786a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_345 0x3159 5796a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_346 0x315A 5806a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_347 0x315B 5816a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_348 0x315C 5826a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_349 0x315D 5836a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_350 0x315E 5846a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_351 0x315F 5856a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_352 0x3160 5866a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_353 0x3161 5876a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_354 0x3162 5886a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_355 0x3163 5896a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_356 0x3164 5906a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_357 0x3165 5916a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_358 0x3166 5926a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_359 0x3167 5936a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_360 0x3168 5946a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_361 0x3169 5956a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_362 0x316A 5966a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_363 0x316B 5976a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_364 0x316C 5986a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_365 0x316D 5996a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_366 0x316E 6006a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_367 0x316F 6016a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_368 0x3170 6026a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_369 0x3171 6036a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_370 0x3172 6046a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_371 0x3173 6056a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_372 0x3174 6066a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_373 0x3175 6076a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_374 0x3176 6086a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_375 0x3177 6096a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_376 0x3178 6106a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_377 0x3179 6116a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_378 0x317A 6126a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_379 0x317B 6136a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_380 0x317C 6146a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_381 0x317D 6156a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_382 0x317E 6166a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_383 0x317F 6176a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_384 0x3180 6186a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_385 0x3181 6196a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_386 0x3182 6206a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_387 0x3183 6216a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_388 0x3184 6226a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_389 0x3185 6236a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_390 0x3186 6246a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_391 0x3187 6256a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_392 0x3188 6266a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_393 0x3189 6276a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_394 0x318A 6286a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_395 0x318B 6296a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_396 0x318C 6306a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_397 0x318D 6316a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_398 0x318E 6326a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_399 0x318F 6336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_400 0x3190 6346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_401 0x3191 6356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_402 0x3192 6366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_403 0x3193 6376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_404 0x3194 6386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_405 0x3195 6396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_406 0x3196 6406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_407 0x3197 6416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_408 0x3198 6426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_409 0x3199 6436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_410 0x319A 6446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_411 0x319B 6456a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_412 0x319C 6466a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_413 0x319D 6476a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_414 0x319E 6486a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_415 0x319F 6496a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_416 0x31A0 6506a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_417 0x31A1 6516a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_418 0x31A2 6526a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_419 0x31A3 6536a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_420 0x31A4 6546a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_421 0x31A5 6556a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_422 0x31A6 6566a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_423 0x31A7 6576a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_424 0x31A8 6586a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_425 0x31A9 6596a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_426 0x31AA 6606a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_427 0x31AB 6616a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_428 0x31AC 6626a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_429 0x31AD 6636a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_430 0x31AE 6646a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_431 0x31AF 6656a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_432 0x31B0 6666a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_433 0x31B1 6676a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_434 0x31B2 6686a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_435 0x31B3 6696a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_436 0x31B4 6706a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_437 0x31B5 6716a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_438 0x31B6 6726a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_439 0x31B7 6736a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_440 0x31B8 6746a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_441 0x31B9 6756a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_442 0x31BA 6766a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_443 0x31BB 6776a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_444 0x31BC 6786a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_445 0x31BD 6796a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_446 0x31BE 6806a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_447 0x31BF 6816a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_448 0x31C0 6826a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_449 0x31C1 6836a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_450 0x31C2 6846a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_451 0x31C3 6856a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_452 0x31C4 6866a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_453 0x31C5 6876a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_454 0x31C6 6886a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_455 0x31C7 6896a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_456 0x31C8 6906a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_457 0x31C9 6916a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_458 0x31CA 6926a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_459 0x31CB 6936a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_460 0x31CC 6946a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_461 0x31CD 6956a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_462 0x31CE 6966a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_463 0x31CF 6976a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_464 0x31D0 6986a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_465 0x31D1 6996a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_466 0x31D2 7006a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_467 0x31D3 7016a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_468 0x31D4 7026a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_469 0x31D5 7036a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_470 0x31D6 7046a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_471 0x31D7 7056a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_472 0x31D8 7066a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_473 0x31D9 7076a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_474 0x31DA 7086a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_475 0x31DB 7096a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_476 0x31DC 7106a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_477 0x31DD 7116a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_478 0x31DE 7126a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_479 0x31DF 7136a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_480 0x31E0 7146a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_481 0x31E1 7156a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_482 0x31E2 7166a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_483 0x31E3 7176a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_484 0x31E4 7186a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_485 0x31E5 7196a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_486 0x31E6 7206a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_487 0x31E7 7216a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_488 0x31E8 7226a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_489 0x31E9 7236a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_490 0x31EA 7246a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_491 0x31EB 7256a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_492 0x31EC 7266a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_493 0x31ED 7276a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_494 0x31EE 7286a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_495 0x31EF 7296a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_496 0x31F0 7306a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_497 0x31F1 7316a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_498 0x31F2 7326a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_499 0x31F3 7336a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_500 0x31F4 7346a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_501 0x31F5 7356a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_502 0x31F6 7366a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_503 0x31F7 7376a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_504 0x31F8 7386a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_505 0x31F9 7396a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_506 0x31FA 7406a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_507 0x31FB 7416a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_508 0x31FC 7426a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_509 0x31FD 7436a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_510 0x31FE 7446a504a75SDimitris Papastamos #define WM8995_WRITE_SEQUENCER_511 0x31FF 7456a504a75SDimitris Papastamos 7466a504a75SDimitris Papastamos #define WM8995_REGISTER_COUNT 725 7476a504a75SDimitris Papastamos #define WM8995_MAX_REGISTER 0x31FF 7486a504a75SDimitris Papastamos 7496a504a75SDimitris Papastamos #define WM8995_MAX_CACHED_REGISTER WM8995_MAX_REGISTER 7506a504a75SDimitris Papastamos 7516a504a75SDimitris Papastamos /* 7526a504a75SDimitris Papastamos * Field Definitions. 7536a504a75SDimitris Papastamos */ 7546a504a75SDimitris Papastamos 7556a504a75SDimitris Papastamos /* 7566a504a75SDimitris Papastamos * R0 (0x00) - Software Reset 7576a504a75SDimitris Papastamos */ 7586a504a75SDimitris Papastamos #define WM8995_SW_RESET_MASK 0xFFFF /* SW_RESET - [15:0] */ 7596a504a75SDimitris Papastamos #define WM8995_SW_RESET_SHIFT 0 /* SW_RESET - [15:0] */ 7606a504a75SDimitris Papastamos #define WM8995_SW_RESET_WIDTH 16 /* SW_RESET - [15:0] */ 7616a504a75SDimitris Papastamos 7626a504a75SDimitris Papastamos /* 7636a504a75SDimitris Papastamos * R1 (0x01) - Power Management (1) 7646a504a75SDimitris Papastamos */ 7656a504a75SDimitris Papastamos #define WM8995_MICB2_ENA 0x0200 /* MICB2_ENA */ 7666a504a75SDimitris Papastamos #define WM8995_MICB2_ENA_MASK 0x0200 /* MICB2_ENA */ 7676a504a75SDimitris Papastamos #define WM8995_MICB2_ENA_SHIFT 9 /* MICB2_ENA */ 7686a504a75SDimitris Papastamos #define WM8995_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 7696a504a75SDimitris Papastamos #define WM8995_MICB1_ENA 0x0100 /* MICB1_ENA */ 7706a504a75SDimitris Papastamos #define WM8995_MICB1_ENA_MASK 0x0100 /* MICB1_ENA */ 7716a504a75SDimitris Papastamos #define WM8995_MICB1_ENA_SHIFT 8 /* MICB1_ENA */ 7726a504a75SDimitris Papastamos #define WM8995_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 7736a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ENA 0x0080 /* HPOUT2L_ENA */ 7746a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ENA_MASK 0x0080 /* HPOUT2L_ENA */ 7756a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */ 7766a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ENA_WIDTH 1 /* HPOUT2L_ENA */ 7776a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ENA 0x0040 /* HPOUT2R_ENA */ 7786a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ENA_MASK 0x0040 /* HPOUT2R_ENA */ 7796a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ENA_SHIFT 6 /* HPOUT2R_ENA */ 7806a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ENA_WIDTH 1 /* HPOUT2R_ENA */ 7816a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ENA 0x0020 /* HPOUT1L_ENA */ 7826a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ENA_MASK 0x0020 /* HPOUT1L_ENA */ 7836a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ENA_SHIFT 5 /* HPOUT1L_ENA */ 7846a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ENA_WIDTH 1 /* HPOUT1L_ENA */ 7856a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ENA 0x0010 /* HPOUT1R_ENA */ 7866a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ENA_MASK 0x0010 /* HPOUT1R_ENA */ 7876a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ENA_SHIFT 4 /* HPOUT1R_ENA */ 7886a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ENA_WIDTH 1 /* HPOUT1R_ENA */ 7896a504a75SDimitris Papastamos #define WM8995_BG_ENA 0x0001 /* BG_ENA */ 7906a504a75SDimitris Papastamos #define WM8995_BG_ENA_MASK 0x0001 /* BG_ENA */ 7916a504a75SDimitris Papastamos #define WM8995_BG_ENA_SHIFT 0 /* BG_ENA */ 7926a504a75SDimitris Papastamos #define WM8995_BG_ENA_WIDTH 1 /* BG_ENA */ 7936a504a75SDimitris Papastamos 7946a504a75SDimitris Papastamos /* 7956a504a75SDimitris Papastamos * R2 (0x02) - Power Management (2) 7966a504a75SDimitris Papastamos */ 7976a504a75SDimitris Papastamos #define WM8995_OPCLK_ENA 0x0800 /* OPCLK_ENA */ 7986a504a75SDimitris Papastamos #define WM8995_OPCLK_ENA_MASK 0x0800 /* OPCLK_ENA */ 7996a504a75SDimitris Papastamos #define WM8995_OPCLK_ENA_SHIFT 11 /* OPCLK_ENA */ 8006a504a75SDimitris Papastamos #define WM8995_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ 8016a504a75SDimitris Papastamos #define WM8995_IN1L_ENA 0x0020 /* IN1L_ENA */ 8026a504a75SDimitris Papastamos #define WM8995_IN1L_ENA_MASK 0x0020 /* IN1L_ENA */ 8036a504a75SDimitris Papastamos #define WM8995_IN1L_ENA_SHIFT 5 /* IN1L_ENA */ 8046a504a75SDimitris Papastamos #define WM8995_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 8056a504a75SDimitris Papastamos #define WM8995_IN1R_ENA 0x0010 /* IN1R_ENA */ 8066a504a75SDimitris Papastamos #define WM8995_IN1R_ENA_MASK 0x0010 /* IN1R_ENA */ 8076a504a75SDimitris Papastamos #define WM8995_IN1R_ENA_SHIFT 4 /* IN1R_ENA */ 8086a504a75SDimitris Papastamos #define WM8995_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 8096a504a75SDimitris Papastamos #define WM8995_LDO2_ENA 0x0002 /* LDO2_ENA */ 8106a504a75SDimitris Papastamos #define WM8995_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ 8116a504a75SDimitris Papastamos #define WM8995_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ 8126a504a75SDimitris Papastamos #define WM8995_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ 8136a504a75SDimitris Papastamos 8146a504a75SDimitris Papastamos /* 8156a504a75SDimitris Papastamos * R3 (0x03) - Power Management (3) 8166a504a75SDimitris Papastamos */ 8176a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_ENA 0x2000 /* AIF2ADCL_ENA */ 8186a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_ENA_MASK 0x2000 /* AIF2ADCL_ENA */ 8196a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_ENA_SHIFT 13 /* AIF2ADCL_ENA */ 8206a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_ENA_WIDTH 1 /* AIF2ADCL_ENA */ 8216a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_ENA 0x1000 /* AIF2ADCR_ENA */ 8226a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_ENA_MASK 0x1000 /* AIF2ADCR_ENA */ 8236a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_ENA_SHIFT 12 /* AIF2ADCR_ENA */ 8246a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_ENA_WIDTH 1 /* AIF2ADCR_ENA */ 8256a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_ENA 0x0800 /* AIF1ADC2L_ENA */ 8266a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_ENA_MASK 0x0800 /* AIF1ADC2L_ENA */ 8276a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_ENA_SHIFT 11 /* AIF1ADC2L_ENA */ 8286a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_ENA_WIDTH 1 /* AIF1ADC2L_ENA */ 8296a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_ENA 0x0400 /* AIF1ADC2R_ENA */ 8306a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_ENA_MASK 0x0400 /* AIF1ADC2R_ENA */ 8316a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_ENA_SHIFT 10 /* AIF1ADC2R_ENA */ 8326a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_ENA_WIDTH 1 /* AIF1ADC2R_ENA */ 8336a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_ENA 0x0200 /* AIF1ADC1L_ENA */ 8346a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_ENA_MASK 0x0200 /* AIF1ADC1L_ENA */ 8356a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_ENA_SHIFT 9 /* AIF1ADC1L_ENA */ 8366a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_ENA_WIDTH 1 /* AIF1ADC1L_ENA */ 8376a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_ENA 0x0100 /* AIF1ADC1R_ENA */ 8386a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_ENA_MASK 0x0100 /* AIF1ADC1R_ENA */ 8396a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_ENA_SHIFT 8 /* AIF1ADC1R_ENA */ 8406a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_ENA_WIDTH 1 /* AIF1ADC1R_ENA */ 8416a504a75SDimitris Papastamos #define WM8995_DMIC3L_ENA 0x0080 /* DMIC3L_ENA */ 8426a504a75SDimitris Papastamos #define WM8995_DMIC3L_ENA_MASK 0x0080 /* DMIC3L_ENA */ 8436a504a75SDimitris Papastamos #define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */ 8446a504a75SDimitris Papastamos #define WM8995_DMIC3L_ENA_WIDTH 1 /* DMIC3L_ENA */ 8456a504a75SDimitris Papastamos #define WM8995_DMIC3R_ENA 0x0040 /* DMIC3R_ENA */ 8466a504a75SDimitris Papastamos #define WM8995_DMIC3R_ENA_MASK 0x0040 /* DMIC3R_ENA */ 8476a504a75SDimitris Papastamos #define WM8995_DMIC3R_ENA_SHIFT 6 /* DMIC3R_ENA */ 8486a504a75SDimitris Papastamos #define WM8995_DMIC3R_ENA_WIDTH 1 /* DMIC3R_ENA */ 8496a504a75SDimitris Papastamos #define WM8995_DMIC2L_ENA 0x0020 /* DMIC2L_ENA */ 8506a504a75SDimitris Papastamos #define WM8995_DMIC2L_ENA_MASK 0x0020 /* DMIC2L_ENA */ 8516a504a75SDimitris Papastamos #define WM8995_DMIC2L_ENA_SHIFT 5 /* DMIC2L_ENA */ 8526a504a75SDimitris Papastamos #define WM8995_DMIC2L_ENA_WIDTH 1 /* DMIC2L_ENA */ 8536a504a75SDimitris Papastamos #define WM8995_DMIC2R_ENA 0x0010 /* DMIC2R_ENA */ 8546a504a75SDimitris Papastamos #define WM8995_DMIC2R_ENA_MASK 0x0010 /* DMIC2R_ENA */ 8556a504a75SDimitris Papastamos #define WM8995_DMIC2R_ENA_SHIFT 4 /* DMIC2R_ENA */ 8566a504a75SDimitris Papastamos #define WM8995_DMIC2R_ENA_WIDTH 1 /* DMIC2R_ENA */ 8576a504a75SDimitris Papastamos #define WM8995_DMIC1L_ENA 0x0008 /* DMIC1L_ENA */ 8586a504a75SDimitris Papastamos #define WM8995_DMIC1L_ENA_MASK 0x0008 /* DMIC1L_ENA */ 8596a504a75SDimitris Papastamos #define WM8995_DMIC1L_ENA_SHIFT 3 /* DMIC1L_ENA */ 8606a504a75SDimitris Papastamos #define WM8995_DMIC1L_ENA_WIDTH 1 /* DMIC1L_ENA */ 8616a504a75SDimitris Papastamos #define WM8995_DMIC1R_ENA 0x0004 /* DMIC1R_ENA */ 8626a504a75SDimitris Papastamos #define WM8995_DMIC1R_ENA_MASK 0x0004 /* DMIC1R_ENA */ 8636a504a75SDimitris Papastamos #define WM8995_DMIC1R_ENA_SHIFT 2 /* DMIC1R_ENA */ 8646a504a75SDimitris Papastamos #define WM8995_DMIC1R_ENA_WIDTH 1 /* DMIC1R_ENA */ 8656a504a75SDimitris Papastamos #define WM8995_ADCL_ENA 0x0002 /* ADCL_ENA */ 8666a504a75SDimitris Papastamos #define WM8995_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 8676a504a75SDimitris Papastamos #define WM8995_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 8686a504a75SDimitris Papastamos #define WM8995_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 8696a504a75SDimitris Papastamos #define WM8995_ADCR_ENA 0x0001 /* ADCR_ENA */ 8706a504a75SDimitris Papastamos #define WM8995_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 8716a504a75SDimitris Papastamos #define WM8995_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 8726a504a75SDimitris Papastamos #define WM8995_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 8736a504a75SDimitris Papastamos 8746a504a75SDimitris Papastamos /* 8756a504a75SDimitris Papastamos * R4 (0x04) - Power Management (4) 8766a504a75SDimitris Papastamos */ 8776a504a75SDimitris Papastamos #define WM8995_AIF2DACL_ENA 0x2000 /* AIF2DACL_ENA */ 8786a504a75SDimitris Papastamos #define WM8995_AIF2DACL_ENA_MASK 0x2000 /* AIF2DACL_ENA */ 8796a504a75SDimitris Papastamos #define WM8995_AIF2DACL_ENA_SHIFT 13 /* AIF2DACL_ENA */ 8806a504a75SDimitris Papastamos #define WM8995_AIF2DACL_ENA_WIDTH 1 /* AIF2DACL_ENA */ 8816a504a75SDimitris Papastamos #define WM8995_AIF2DACR_ENA 0x1000 /* AIF2DACR_ENA */ 8826a504a75SDimitris Papastamos #define WM8995_AIF2DACR_ENA_MASK 0x1000 /* AIF2DACR_ENA */ 8836a504a75SDimitris Papastamos #define WM8995_AIF2DACR_ENA_SHIFT 12 /* AIF2DACR_ENA */ 8846a504a75SDimitris Papastamos #define WM8995_AIF2DACR_ENA_WIDTH 1 /* AIF2DACR_ENA */ 8856a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_ENA 0x0800 /* AIF1DAC2L_ENA */ 8866a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_ENA_MASK 0x0800 /* AIF1DAC2L_ENA */ 8876a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_ENA_SHIFT 11 /* AIF1DAC2L_ENA */ 8886a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_ENA_WIDTH 1 /* AIF1DAC2L_ENA */ 8896a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_ENA 0x0400 /* AIF1DAC2R_ENA */ 8906a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_ENA_MASK 0x0400 /* AIF1DAC2R_ENA */ 8916a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_ENA_SHIFT 10 /* AIF1DAC2R_ENA */ 8926a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_ENA_WIDTH 1 /* AIF1DAC2R_ENA */ 8936a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_ENA 0x0200 /* AIF1DAC1L_ENA */ 8946a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_ENA_MASK 0x0200 /* AIF1DAC1L_ENA */ 8956a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_ENA_SHIFT 9 /* AIF1DAC1L_ENA */ 8966a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_ENA_WIDTH 1 /* AIF1DAC1L_ENA */ 8976a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_ENA 0x0100 /* AIF1DAC1R_ENA */ 8986a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_ENA_MASK 0x0100 /* AIF1DAC1R_ENA */ 8996a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_ENA_SHIFT 8 /* AIF1DAC1R_ENA */ 9006a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_ENA_WIDTH 1 /* AIF1DAC1R_ENA */ 9016a504a75SDimitris Papastamos #define WM8995_DAC2L_ENA 0x0008 /* DAC2L_ENA */ 9026a504a75SDimitris Papastamos #define WM8995_DAC2L_ENA_MASK 0x0008 /* DAC2L_ENA */ 9036a504a75SDimitris Papastamos #define WM8995_DAC2L_ENA_SHIFT 3 /* DAC2L_ENA */ 9046a504a75SDimitris Papastamos #define WM8995_DAC2L_ENA_WIDTH 1 /* DAC2L_ENA */ 9056a504a75SDimitris Papastamos #define WM8995_DAC2R_ENA 0x0004 /* DAC2R_ENA */ 9066a504a75SDimitris Papastamos #define WM8995_DAC2R_ENA_MASK 0x0004 /* DAC2R_ENA */ 9076a504a75SDimitris Papastamos #define WM8995_DAC2R_ENA_SHIFT 2 /* DAC2R_ENA */ 9086a504a75SDimitris Papastamos #define WM8995_DAC2R_ENA_WIDTH 1 /* DAC2R_ENA */ 9096a504a75SDimitris Papastamos #define WM8995_DAC1L_ENA 0x0002 /* DAC1L_ENA */ 9106a504a75SDimitris Papastamos #define WM8995_DAC1L_ENA_MASK 0x0002 /* DAC1L_ENA */ 9116a504a75SDimitris Papastamos #define WM8995_DAC1L_ENA_SHIFT 1 /* DAC1L_ENA */ 9126a504a75SDimitris Papastamos #define WM8995_DAC1L_ENA_WIDTH 1 /* DAC1L_ENA */ 9136a504a75SDimitris Papastamos #define WM8995_DAC1R_ENA 0x0001 /* DAC1R_ENA */ 9146a504a75SDimitris Papastamos #define WM8995_DAC1R_ENA_MASK 0x0001 /* DAC1R_ENA */ 9156a504a75SDimitris Papastamos #define WM8995_DAC1R_ENA_SHIFT 0 /* DAC1R_ENA */ 9166a504a75SDimitris Papastamos #define WM8995_DAC1R_ENA_WIDTH 1 /* DAC1R_ENA */ 9176a504a75SDimitris Papastamos 9186a504a75SDimitris Papastamos /* 9196a504a75SDimitris Papastamos * R5 (0x05) - Power Management (5) 9206a504a75SDimitris Papastamos */ 9216a504a75SDimitris Papastamos #define WM8995_DMIC_SRC2_MASK 0x0300 /* DMIC_SRC2 - [9:8] */ 9226a504a75SDimitris Papastamos #define WM8995_DMIC_SRC2_SHIFT 8 /* DMIC_SRC2 - [9:8] */ 9236a504a75SDimitris Papastamos #define WM8995_DMIC_SRC2_WIDTH 2 /* DMIC_SRC2 - [9:8] */ 9246a504a75SDimitris Papastamos #define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */ 9256a504a75SDimitris Papastamos #define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */ 9266a504a75SDimitris Papastamos #define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */ 9276a504a75SDimitris Papastamos #define WM8995_AIF3_TRI 0x0020 /* AIF3_TRI */ 9286a504a75SDimitris Papastamos #define WM8995_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */ 9296a504a75SDimitris Papastamos #define WM8995_AIF3_TRI_SHIFT 5 /* AIF3_TRI */ 9306a504a75SDimitris Papastamos #define WM8995_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 9316a504a75SDimitris Papastamos #define WM8995_AIF3_ADCDAT_SRC_MASK 0x0018 /* AIF3_ADCDAT_SRC - [4:3] */ 9326a504a75SDimitris Papastamos #define WM8995_AIF3_ADCDAT_SRC_SHIFT 3 /* AIF3_ADCDAT_SRC - [4:3] */ 9336a504a75SDimitris Papastamos #define WM8995_AIF3_ADCDAT_SRC_WIDTH 2 /* AIF3_ADCDAT_SRC - [4:3] */ 9346a504a75SDimitris Papastamos #define WM8995_AIF2_ADCDAT_SRC 0x0004 /* AIF2_ADCDAT_SRC */ 9356a504a75SDimitris Papastamos #define WM8995_AIF2_ADCDAT_SRC_MASK 0x0004 /* AIF2_ADCDAT_SRC */ 9366a504a75SDimitris Papastamos #define WM8995_AIF2_ADCDAT_SRC_SHIFT 2 /* AIF2_ADCDAT_SRC */ 9376a504a75SDimitris Papastamos #define WM8995_AIF2_ADCDAT_SRC_WIDTH 1 /* AIF2_ADCDAT_SRC */ 9386a504a75SDimitris Papastamos #define WM8995_AIF2_DACDAT_SRC 0x0002 /* AIF2_DACDAT_SRC */ 9396a504a75SDimitris Papastamos #define WM8995_AIF2_DACDAT_SRC_MASK 0x0002 /* AIF2_DACDAT_SRC */ 9406a504a75SDimitris Papastamos #define WM8995_AIF2_DACDAT_SRC_SHIFT 1 /* AIF2_DACDAT_SRC */ 9416a504a75SDimitris Papastamos #define WM8995_AIF2_DACDAT_SRC_WIDTH 1 /* AIF2_DACDAT_SRC */ 9426a504a75SDimitris Papastamos #define WM8995_AIF1_DACDAT_SRC 0x0001 /* AIF1_DACDAT_SRC */ 9436a504a75SDimitris Papastamos #define WM8995_AIF1_DACDAT_SRC_MASK 0x0001 /* AIF1_DACDAT_SRC */ 9446a504a75SDimitris Papastamos #define WM8995_AIF1_DACDAT_SRC_SHIFT 0 /* AIF1_DACDAT_SRC */ 9456a504a75SDimitris Papastamos #define WM8995_AIF1_DACDAT_SRC_WIDTH 1 /* AIF1_DACDAT_SRC */ 9466a504a75SDimitris Papastamos 9476a504a75SDimitris Papastamos /* 9486a504a75SDimitris Papastamos * R16 (0x10) - Left Line Input 1 Volume 9496a504a75SDimitris Papastamos */ 9506a504a75SDimitris Papastamos #define WM8995_IN1_VU 0x0080 /* IN1_VU */ 9516a504a75SDimitris Papastamos #define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 9526a504a75SDimitris Papastamos #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 9536a504a75SDimitris Papastamos #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 9546a504a75SDimitris Papastamos #define WM8995_IN1L_ZC 0x0020 /* IN1L_ZC */ 9556a504a75SDimitris Papastamos #define WM8995_IN1L_ZC_MASK 0x0020 /* IN1L_ZC */ 9566a504a75SDimitris Papastamos #define WM8995_IN1L_ZC_SHIFT 5 /* IN1L_ZC */ 9576a504a75SDimitris Papastamos #define WM8995_IN1L_ZC_WIDTH 1 /* IN1L_ZC */ 9586a504a75SDimitris Papastamos #define WM8995_IN1L_VOL_MASK 0x001F /* IN1L_VOL - [4:0] */ 9596a504a75SDimitris Papastamos #define WM8995_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [4:0] */ 9606a504a75SDimitris Papastamos #define WM8995_IN1L_VOL_WIDTH 5 /* IN1L_VOL - [4:0] */ 9616a504a75SDimitris Papastamos 9626a504a75SDimitris Papastamos /* 9636a504a75SDimitris Papastamos * R17 (0x11) - Right Line Input 1 Volume 9646a504a75SDimitris Papastamos */ 9656a504a75SDimitris Papastamos #define WM8995_IN1_VU 0x0080 /* IN1_VU */ 9666a504a75SDimitris Papastamos #define WM8995_IN1_VU_MASK 0x0080 /* IN1_VU */ 9676a504a75SDimitris Papastamos #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */ 9686a504a75SDimitris Papastamos #define WM8995_IN1_VU_WIDTH 1 /* IN1_VU */ 9696a504a75SDimitris Papastamos #define WM8995_IN1R_ZC 0x0020 /* IN1R_ZC */ 9706a504a75SDimitris Papastamos #define WM8995_IN1R_ZC_MASK 0x0020 /* IN1R_ZC */ 9716a504a75SDimitris Papastamos #define WM8995_IN1R_ZC_SHIFT 5 /* IN1R_ZC */ 9726a504a75SDimitris Papastamos #define WM8995_IN1R_ZC_WIDTH 1 /* IN1R_ZC */ 9736a504a75SDimitris Papastamos #define WM8995_IN1R_VOL_MASK 0x001F /* IN1R_VOL - [4:0] */ 9746a504a75SDimitris Papastamos #define WM8995_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [4:0] */ 9756a504a75SDimitris Papastamos #define WM8995_IN1R_VOL_WIDTH 5 /* IN1R_VOL - [4:0] */ 9766a504a75SDimitris Papastamos 9776a504a75SDimitris Papastamos /* 9786a504a75SDimitris Papastamos * R18 (0x12) - Left Line Input Control 9796a504a75SDimitris Papastamos */ 9806a504a75SDimitris Papastamos #define WM8995_IN1L_BOOST_MASK 0x0030 /* IN1L_BOOST - [5:4] */ 9816a504a75SDimitris Papastamos #define WM8995_IN1L_BOOST_SHIFT 4 /* IN1L_BOOST - [5:4] */ 9826a504a75SDimitris Papastamos #define WM8995_IN1L_BOOST_WIDTH 2 /* IN1L_BOOST - [5:4] */ 9836a504a75SDimitris Papastamos #define WM8995_IN1L_MODE_MASK 0x000C /* IN1L_MODE - [3:2] */ 9846a504a75SDimitris Papastamos #define WM8995_IN1L_MODE_SHIFT 2 /* IN1L_MODE - [3:2] */ 9856a504a75SDimitris Papastamos #define WM8995_IN1L_MODE_WIDTH 2 /* IN1L_MODE - [3:2] */ 9866a504a75SDimitris Papastamos #define WM8995_IN1R_MODE_MASK 0x0003 /* IN1R_MODE - [1:0] */ 9876a504a75SDimitris Papastamos #define WM8995_IN1R_MODE_SHIFT 0 /* IN1R_MODE - [1:0] */ 9886a504a75SDimitris Papastamos #define WM8995_IN1R_MODE_WIDTH 2 /* IN1R_MODE - [1:0] */ 9896a504a75SDimitris Papastamos 9906a504a75SDimitris Papastamos /* 9916a504a75SDimitris Papastamos * R24 (0x18) - DAC1 Left Volume 9926a504a75SDimitris Papastamos */ 9936a504a75SDimitris Papastamos #define WM8995_DAC1L_MUTE 0x0200 /* DAC1L_MUTE */ 9946a504a75SDimitris Papastamos #define WM8995_DAC1L_MUTE_MASK 0x0200 /* DAC1L_MUTE */ 9956a504a75SDimitris Papastamos #define WM8995_DAC1L_MUTE_SHIFT 9 /* DAC1L_MUTE */ 9966a504a75SDimitris Papastamos #define WM8995_DAC1L_MUTE_WIDTH 1 /* DAC1L_MUTE */ 9976a504a75SDimitris Papastamos #define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 9986a504a75SDimitris Papastamos #define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 9996a504a75SDimitris Papastamos #define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 10006a504a75SDimitris Papastamos #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 10016a504a75SDimitris Papastamos #define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */ 10026a504a75SDimitris Papastamos #define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */ 10036a504a75SDimitris Papastamos #define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */ 10046a504a75SDimitris Papastamos 10056a504a75SDimitris Papastamos /* 10066a504a75SDimitris Papastamos * R25 (0x19) - DAC1 Right Volume 10076a504a75SDimitris Papastamos */ 10086a504a75SDimitris Papastamos #define WM8995_DAC1R_MUTE 0x0200 /* DAC1R_MUTE */ 10096a504a75SDimitris Papastamos #define WM8995_DAC1R_MUTE_MASK 0x0200 /* DAC1R_MUTE */ 10106a504a75SDimitris Papastamos #define WM8995_DAC1R_MUTE_SHIFT 9 /* DAC1R_MUTE */ 10116a504a75SDimitris Papastamos #define WM8995_DAC1R_MUTE_WIDTH 1 /* DAC1R_MUTE */ 10126a504a75SDimitris Papastamos #define WM8995_DAC1_VU 0x0100 /* DAC1_VU */ 10136a504a75SDimitris Papastamos #define WM8995_DAC1_VU_MASK 0x0100 /* DAC1_VU */ 10146a504a75SDimitris Papastamos #define WM8995_DAC1_VU_SHIFT 8 /* DAC1_VU */ 10156a504a75SDimitris Papastamos #define WM8995_DAC1_VU_WIDTH 1 /* DAC1_VU */ 10166a504a75SDimitris Papastamos #define WM8995_DAC1R_VOL_MASK 0x00FF /* DAC1R_VOL - [7:0] */ 10176a504a75SDimitris Papastamos #define WM8995_DAC1R_VOL_SHIFT 0 /* DAC1R_VOL - [7:0] */ 10186a504a75SDimitris Papastamos #define WM8995_DAC1R_VOL_WIDTH 8 /* DAC1R_VOL - [7:0] */ 10196a504a75SDimitris Papastamos 10206a504a75SDimitris Papastamos /* 10216a504a75SDimitris Papastamos * R26 (0x1A) - DAC2 Left Volume 10226a504a75SDimitris Papastamos */ 10236a504a75SDimitris Papastamos #define WM8995_DAC2L_MUTE 0x0200 /* DAC2L_MUTE */ 10246a504a75SDimitris Papastamos #define WM8995_DAC2L_MUTE_MASK 0x0200 /* DAC2L_MUTE */ 10256a504a75SDimitris Papastamos #define WM8995_DAC2L_MUTE_SHIFT 9 /* DAC2L_MUTE */ 10266a504a75SDimitris Papastamos #define WM8995_DAC2L_MUTE_WIDTH 1 /* DAC2L_MUTE */ 10276a504a75SDimitris Papastamos #define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 10286a504a75SDimitris Papastamos #define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 10296a504a75SDimitris Papastamos #define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 10306a504a75SDimitris Papastamos #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 10316a504a75SDimitris Papastamos #define WM8995_DAC2L_VOL_MASK 0x00FF /* DAC2L_VOL - [7:0] */ 10326a504a75SDimitris Papastamos #define WM8995_DAC2L_VOL_SHIFT 0 /* DAC2L_VOL - [7:0] */ 10336a504a75SDimitris Papastamos #define WM8995_DAC2L_VOL_WIDTH 8 /* DAC2L_VOL - [7:0] */ 10346a504a75SDimitris Papastamos 10356a504a75SDimitris Papastamos /* 10366a504a75SDimitris Papastamos * R27 (0x1B) - DAC2 Right Volume 10376a504a75SDimitris Papastamos */ 10386a504a75SDimitris Papastamos #define WM8995_DAC2R_MUTE 0x0200 /* DAC2R_MUTE */ 10396a504a75SDimitris Papastamos #define WM8995_DAC2R_MUTE_MASK 0x0200 /* DAC2R_MUTE */ 10406a504a75SDimitris Papastamos #define WM8995_DAC2R_MUTE_SHIFT 9 /* DAC2R_MUTE */ 10416a504a75SDimitris Papastamos #define WM8995_DAC2R_MUTE_WIDTH 1 /* DAC2R_MUTE */ 10426a504a75SDimitris Papastamos #define WM8995_DAC2_VU 0x0100 /* DAC2_VU */ 10436a504a75SDimitris Papastamos #define WM8995_DAC2_VU_MASK 0x0100 /* DAC2_VU */ 10446a504a75SDimitris Papastamos #define WM8995_DAC2_VU_SHIFT 8 /* DAC2_VU */ 10456a504a75SDimitris Papastamos #define WM8995_DAC2_VU_WIDTH 1 /* DAC2_VU */ 10466a504a75SDimitris Papastamos #define WM8995_DAC2R_VOL_MASK 0x00FF /* DAC2R_VOL - [7:0] */ 10476a504a75SDimitris Papastamos #define WM8995_DAC2R_VOL_SHIFT 0 /* DAC2R_VOL - [7:0] */ 10486a504a75SDimitris Papastamos #define WM8995_DAC2R_VOL_WIDTH 8 /* DAC2R_VOL - [7:0] */ 10496a504a75SDimitris Papastamos 10506a504a75SDimitris Papastamos /* 10516a504a75SDimitris Papastamos * R28 (0x1C) - Output Volume ZC (1) 10526a504a75SDimitris Papastamos */ 10536a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ZC 0x0008 /* HPOUT2L_ZC */ 10546a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ZC_MASK 0x0008 /* HPOUT2L_ZC */ 10556a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ZC_SHIFT 3 /* HPOUT2L_ZC */ 10566a504a75SDimitris Papastamos #define WM8995_HPOUT2L_ZC_WIDTH 1 /* HPOUT2L_ZC */ 10576a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ZC 0x0004 /* HPOUT2R_ZC */ 10586a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ZC_MASK 0x0004 /* HPOUT2R_ZC */ 10596a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ZC_SHIFT 2 /* HPOUT2R_ZC */ 10606a504a75SDimitris Papastamos #define WM8995_HPOUT2R_ZC_WIDTH 1 /* HPOUT2R_ZC */ 10616a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ZC 0x0002 /* HPOUT1L_ZC */ 10626a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ZC_MASK 0x0002 /* HPOUT1L_ZC */ 10636a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ZC_SHIFT 1 /* HPOUT1L_ZC */ 10646a504a75SDimitris Papastamos #define WM8995_HPOUT1L_ZC_WIDTH 1 /* HPOUT1L_ZC */ 10656a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ZC 0x0001 /* HPOUT1R_ZC */ 10666a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ZC_MASK 0x0001 /* HPOUT1R_ZC */ 10676a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ZC_SHIFT 0 /* HPOUT1R_ZC */ 10686a504a75SDimitris Papastamos #define WM8995_HPOUT1R_ZC_WIDTH 1 /* HPOUT1R_ZC */ 10696a504a75SDimitris Papastamos 10706a504a75SDimitris Papastamos /* 10716a504a75SDimitris Papastamos * R32 (0x20) - MICBIAS (1) 10726a504a75SDimitris Papastamos */ 10736a504a75SDimitris Papastamos #define WM8995_MICB1_MODE 0x0008 /* MICB1_MODE */ 10746a504a75SDimitris Papastamos #define WM8995_MICB1_MODE_MASK 0x0008 /* MICB1_MODE */ 10756a504a75SDimitris Papastamos #define WM8995_MICB1_MODE_SHIFT 3 /* MICB1_MODE */ 10766a504a75SDimitris Papastamos #define WM8995_MICB1_MODE_WIDTH 1 /* MICB1_MODE */ 10776a504a75SDimitris Papastamos #define WM8995_MICB1_LVL_MASK 0x0006 /* MICB1_LVL - [2:1] */ 10786a504a75SDimitris Papastamos #define WM8995_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [2:1] */ 10796a504a75SDimitris Papastamos #define WM8995_MICB1_LVL_WIDTH 2 /* MICB1_LVL - [2:1] */ 10806a504a75SDimitris Papastamos #define WM8995_MICB1_DISCH 0x0001 /* MICB1_DISCH */ 10816a504a75SDimitris Papastamos #define WM8995_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */ 10826a504a75SDimitris Papastamos #define WM8995_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */ 10836a504a75SDimitris Papastamos #define WM8995_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 10846a504a75SDimitris Papastamos 10856a504a75SDimitris Papastamos /* 10866a504a75SDimitris Papastamos * R33 (0x21) - MICBIAS (2) 10876a504a75SDimitris Papastamos */ 10886a504a75SDimitris Papastamos #define WM8995_MICB2_MODE 0x0008 /* MICB2_MODE */ 10896a504a75SDimitris Papastamos #define WM8995_MICB2_MODE_MASK 0x0008 /* MICB2_MODE */ 10906a504a75SDimitris Papastamos #define WM8995_MICB2_MODE_SHIFT 3 /* MICB2_MODE */ 10916a504a75SDimitris Papastamos #define WM8995_MICB2_MODE_WIDTH 1 /* MICB2_MODE */ 10926a504a75SDimitris Papastamos #define WM8995_MICB2_LVL_MASK 0x0006 /* MICB2_LVL - [2:1] */ 10936a504a75SDimitris Papastamos #define WM8995_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [2:1] */ 10946a504a75SDimitris Papastamos #define WM8995_MICB2_LVL_WIDTH 2 /* MICB2_LVL - [2:1] */ 10956a504a75SDimitris Papastamos #define WM8995_MICB2_DISCH 0x0001 /* MICB2_DISCH */ 10966a504a75SDimitris Papastamos #define WM8995_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */ 10976a504a75SDimitris Papastamos #define WM8995_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */ 10986a504a75SDimitris Papastamos #define WM8995_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 10996a504a75SDimitris Papastamos 11006a504a75SDimitris Papastamos /* 11016a504a75SDimitris Papastamos * R40 (0x28) - LDO 1 11026a504a75SDimitris Papastamos */ 11036a504a75SDimitris Papastamos #define WM8995_LDO1_MODE 0x0020 /* LDO1_MODE */ 11046a504a75SDimitris Papastamos #define WM8995_LDO1_MODE_MASK 0x0020 /* LDO1_MODE */ 11056a504a75SDimitris Papastamos #define WM8995_LDO1_MODE_SHIFT 5 /* LDO1_MODE */ 11066a504a75SDimitris Papastamos #define WM8995_LDO1_MODE_WIDTH 1 /* LDO1_MODE */ 11076a504a75SDimitris Papastamos #define WM8995_LDO1_VSEL_MASK 0x0006 /* LDO1_VSEL - [2:1] */ 11086a504a75SDimitris Papastamos #define WM8995_LDO1_VSEL_SHIFT 1 /* LDO1_VSEL - [2:1] */ 11096a504a75SDimitris Papastamos #define WM8995_LDO1_VSEL_WIDTH 2 /* LDO1_VSEL - [2:1] */ 11106a504a75SDimitris Papastamos #define WM8995_LDO1_DISCH 0x0001 /* LDO1_DISCH */ 11116a504a75SDimitris Papastamos #define WM8995_LDO1_DISCH_MASK 0x0001 /* LDO1_DISCH */ 11126a504a75SDimitris Papastamos #define WM8995_LDO1_DISCH_SHIFT 0 /* LDO1_DISCH */ 11136a504a75SDimitris Papastamos #define WM8995_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */ 11146a504a75SDimitris Papastamos 11156a504a75SDimitris Papastamos /* 11166a504a75SDimitris Papastamos * R41 (0x29) - LDO 2 11176a504a75SDimitris Papastamos */ 11186a504a75SDimitris Papastamos #define WM8995_LDO2_MODE 0x0020 /* LDO2_MODE */ 11196a504a75SDimitris Papastamos #define WM8995_LDO2_MODE_MASK 0x0020 /* LDO2_MODE */ 11206a504a75SDimitris Papastamos #define WM8995_LDO2_MODE_SHIFT 5 /* LDO2_MODE */ 11216a504a75SDimitris Papastamos #define WM8995_LDO2_MODE_WIDTH 1 /* LDO2_MODE */ 11226a504a75SDimitris Papastamos #define WM8995_LDO2_VSEL_MASK 0x001E /* LDO2_VSEL - [4:1] */ 11236a504a75SDimitris Papastamos #define WM8995_LDO2_VSEL_SHIFT 1 /* LDO2_VSEL - [4:1] */ 11246a504a75SDimitris Papastamos #define WM8995_LDO2_VSEL_WIDTH 4 /* LDO2_VSEL - [4:1] */ 11256a504a75SDimitris Papastamos #define WM8995_LDO2_DISCH 0x0001 /* LDO2_DISCH */ 11266a504a75SDimitris Papastamos #define WM8995_LDO2_DISCH_MASK 0x0001 /* LDO2_DISCH */ 11276a504a75SDimitris Papastamos #define WM8995_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */ 11286a504a75SDimitris Papastamos #define WM8995_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */ 11296a504a75SDimitris Papastamos 11306a504a75SDimitris Papastamos /* 11316a504a75SDimitris Papastamos * R48 (0x30) - Accessory Detect Mode1 11326a504a75SDimitris Papastamos */ 11336a504a75SDimitris Papastamos #define WM8995_JD_MODE_MASK 0x0003 /* JD_MODE - [1:0] */ 11346a504a75SDimitris Papastamos #define WM8995_JD_MODE_SHIFT 0 /* JD_MODE - [1:0] */ 11356a504a75SDimitris Papastamos #define WM8995_JD_MODE_WIDTH 2 /* JD_MODE - [1:0] */ 11366a504a75SDimitris Papastamos 11376a504a75SDimitris Papastamos /* 11386a504a75SDimitris Papastamos * R49 (0x31) - Accessory Detect Mode2 11396a504a75SDimitris Papastamos */ 11406a504a75SDimitris Papastamos #define WM8995_VID_ENA 0x0001 /* VID_ENA */ 11416a504a75SDimitris Papastamos #define WM8995_VID_ENA_MASK 0x0001 /* VID_ENA */ 11426a504a75SDimitris Papastamos #define WM8995_VID_ENA_SHIFT 0 /* VID_ENA */ 11436a504a75SDimitris Papastamos #define WM8995_VID_ENA_WIDTH 1 /* VID_ENA */ 11446a504a75SDimitris Papastamos 11456a504a75SDimitris Papastamos /* 11466a504a75SDimitris Papastamos * R52 (0x34) - Headphone Detect1 11476a504a75SDimitris Papastamos */ 11486a504a75SDimitris Papastamos #define WM8995_HP_RAMPRATE 0x0002 /* HP_RAMPRATE */ 11496a504a75SDimitris Papastamos #define WM8995_HP_RAMPRATE_MASK 0x0002 /* HP_RAMPRATE */ 11506a504a75SDimitris Papastamos #define WM8995_HP_RAMPRATE_SHIFT 1 /* HP_RAMPRATE */ 11516a504a75SDimitris Papastamos #define WM8995_HP_RAMPRATE_WIDTH 1 /* HP_RAMPRATE */ 11526a504a75SDimitris Papastamos #define WM8995_HP_POLL 0x0001 /* HP_POLL */ 11536a504a75SDimitris Papastamos #define WM8995_HP_POLL_MASK 0x0001 /* HP_POLL */ 11546a504a75SDimitris Papastamos #define WM8995_HP_POLL_SHIFT 0 /* HP_POLL */ 11556a504a75SDimitris Papastamos #define WM8995_HP_POLL_WIDTH 1 /* HP_POLL */ 11566a504a75SDimitris Papastamos 11576a504a75SDimitris Papastamos /* 11586a504a75SDimitris Papastamos * R53 (0x35) - Headphone Detect2 11596a504a75SDimitris Papastamos */ 11606a504a75SDimitris Papastamos #define WM8995_HP_DONE 0x0080 /* HP_DONE */ 11616a504a75SDimitris Papastamos #define WM8995_HP_DONE_MASK 0x0080 /* HP_DONE */ 11626a504a75SDimitris Papastamos #define WM8995_HP_DONE_SHIFT 7 /* HP_DONE */ 11636a504a75SDimitris Papastamos #define WM8995_HP_DONE_WIDTH 1 /* HP_DONE */ 11646a504a75SDimitris Papastamos #define WM8995_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 11656a504a75SDimitris Papastamos #define WM8995_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 11666a504a75SDimitris Papastamos #define WM8995_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 11676a504a75SDimitris Papastamos 11686a504a75SDimitris Papastamos /* 11696a504a75SDimitris Papastamos * R56 (0x38) - Mic Detect (1) 11706a504a75SDimitris Papastamos */ 11716a504a75SDimitris Papastamos #define WM8995_MICD_RATE_MASK 0x7800 /* MICD_RATE - [14:11] */ 11726a504a75SDimitris Papastamos #define WM8995_MICD_RATE_SHIFT 11 /* MICD_RATE - [14:11] */ 11736a504a75SDimitris Papastamos #define WM8995_MICD_RATE_WIDTH 4 /* MICD_RATE - [14:11] */ 11746a504a75SDimitris Papastamos #define WM8995_MICD_LVL_SEL_MASK 0x01F8 /* MICD_LVL_SEL - [8:3] */ 11756a504a75SDimitris Papastamos #define WM8995_MICD_LVL_SEL_SHIFT 3 /* MICD_LVL_SEL - [8:3] */ 11766a504a75SDimitris Papastamos #define WM8995_MICD_LVL_SEL_WIDTH 6 /* MICD_LVL_SEL - [8:3] */ 11776a504a75SDimitris Papastamos #define WM8995_MICD_DBTIME 0x0002 /* MICD_DBTIME */ 11786a504a75SDimitris Papastamos #define WM8995_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */ 11796a504a75SDimitris Papastamos #define WM8995_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */ 11806a504a75SDimitris Papastamos #define WM8995_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */ 11816a504a75SDimitris Papastamos #define WM8995_MICD_ENA 0x0001 /* MICD_ENA */ 11826a504a75SDimitris Papastamos #define WM8995_MICD_ENA_MASK 0x0001 /* MICD_ENA */ 11836a504a75SDimitris Papastamos #define WM8995_MICD_ENA_SHIFT 0 /* MICD_ENA */ 11846a504a75SDimitris Papastamos #define WM8995_MICD_ENA_WIDTH 1 /* MICD_ENA */ 11856a504a75SDimitris Papastamos 11866a504a75SDimitris Papastamos /* 11876a504a75SDimitris Papastamos * R57 (0x39) - Mic Detect (2) 11886a504a75SDimitris Papastamos */ 11896a504a75SDimitris Papastamos #define WM8995_MICD_LVL_MASK 0x01FC /* MICD_LVL - [8:2] */ 11906a504a75SDimitris Papastamos #define WM8995_MICD_LVL_SHIFT 2 /* MICD_LVL - [8:2] */ 11916a504a75SDimitris Papastamos #define WM8995_MICD_LVL_WIDTH 7 /* MICD_LVL - [8:2] */ 11926a504a75SDimitris Papastamos #define WM8995_MICD_VALID 0x0002 /* MICD_VALID */ 11936a504a75SDimitris Papastamos #define WM8995_MICD_VALID_MASK 0x0002 /* MICD_VALID */ 11946a504a75SDimitris Papastamos #define WM8995_MICD_VALID_SHIFT 1 /* MICD_VALID */ 11956a504a75SDimitris Papastamos #define WM8995_MICD_VALID_WIDTH 1 /* MICD_VALID */ 11966a504a75SDimitris Papastamos #define WM8995_MICD_STS 0x0001 /* MICD_STS */ 11976a504a75SDimitris Papastamos #define WM8995_MICD_STS_MASK 0x0001 /* MICD_STS */ 11986a504a75SDimitris Papastamos #define WM8995_MICD_STS_SHIFT 0 /* MICD_STS */ 11996a504a75SDimitris Papastamos #define WM8995_MICD_STS_WIDTH 1 /* MICD_STS */ 12006a504a75SDimitris Papastamos 12016a504a75SDimitris Papastamos /* 12026a504a75SDimitris Papastamos * R64 (0x40) - Charge Pump (1) 12036a504a75SDimitris Papastamos */ 12046a504a75SDimitris Papastamos #define WM8995_CP_ENA 0x8000 /* CP_ENA */ 12056a504a75SDimitris Papastamos #define WM8995_CP_ENA_MASK 0x8000 /* CP_ENA */ 12066a504a75SDimitris Papastamos #define WM8995_CP_ENA_SHIFT 15 /* CP_ENA */ 12076a504a75SDimitris Papastamos #define WM8995_CP_ENA_WIDTH 1 /* CP_ENA */ 12086a504a75SDimitris Papastamos 12096a504a75SDimitris Papastamos /* 12106a504a75SDimitris Papastamos * R69 (0x45) - Class W (1) 12116a504a75SDimitris Papastamos */ 12126a504a75SDimitris Papastamos #define WM8995_CP_DYN_SRC_SEL_MASK 0x0300 /* CP_DYN_SRC_SEL - [9:8] */ 12136a504a75SDimitris Papastamos #define WM8995_CP_DYN_SRC_SEL_SHIFT 8 /* CP_DYN_SRC_SEL - [9:8] */ 12146a504a75SDimitris Papastamos #define WM8995_CP_DYN_SRC_SEL_WIDTH 2 /* CP_DYN_SRC_SEL - [9:8] */ 12156a504a75SDimitris Papastamos #define WM8995_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ 12166a504a75SDimitris Papastamos #define WM8995_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ 12176a504a75SDimitris Papastamos #define WM8995_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ 12186a504a75SDimitris Papastamos #define WM8995_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ 12196a504a75SDimitris Papastamos 12206a504a75SDimitris Papastamos /* 12216a504a75SDimitris Papastamos * R80 (0x50) - DC Servo (1) 12226a504a75SDimitris Papastamos */ 12236a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ 12246a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ 12256a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ 12266a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ 12276a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ 12286a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ 12296a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ 12306a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ 12316a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ 12326a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ 12336a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ 12346a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ 12356a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ 12366a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ 12376a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ 12386a504a75SDimitris Papastamos #define WM8995_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ 12396a504a75SDimitris Papastamos 12406a504a75SDimitris Papastamos /* 12416a504a75SDimitris Papastamos * R81 (0x51) - DC Servo (2) 12426a504a75SDimitris Papastamos */ 12436a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ 12446a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ 12456a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ 12466a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ 12476a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ 12486a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ 12496a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ 12506a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ 12516a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ 12526a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ 12536a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ 12546a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ 12556a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ 12566a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ 12576a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ 12586a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ 12596a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ 12606a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ 12616a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ 12626a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ 12636a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ 12646a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ 12656a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ 12666a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ 12676a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ 12686a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ 12696a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ 12706a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ 12716a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ 12726a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ 12736a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ 12746a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ 12756a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ 12766a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ 12776a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ 12786a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ 12796a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ 12806a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ 12816a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ 12826a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ 12836a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ 12846a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ 12856a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ 12866a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ 12876a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ 12886a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ 12896a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ 12906a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ 12916a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ 12926a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ 12936a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ 12946a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ 12956a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ 12966a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ 12976a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ 12986a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ 12996a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ 13006a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ 13016a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ 13026a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ 13036a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ 13046a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ 13056a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ 13066a504a75SDimitris Papastamos #define WM8995_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ 13076a504a75SDimitris Papastamos 13086a504a75SDimitris Papastamos /* 13096a504a75SDimitris Papastamos * R82 (0x52) - DC Servo (3) 13106a504a75SDimitris Papastamos */ 13116a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ 13126a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ 13136a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ 13146a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ 13156a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ 13166a504a75SDimitris Papastamos #define WM8995_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ 13176a504a75SDimitris Papastamos 13186a504a75SDimitris Papastamos /* 13196a504a75SDimitris Papastamos * R84 (0x54) - DC Servo (5) 13206a504a75SDimitris Papastamos */ 13216a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_23_MASK 0x7F00 /* DCS_SERIES_NO_23 - [14:8] */ 13226a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_23_SHIFT 8 /* DCS_SERIES_NO_23 - [14:8] */ 13236a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [14:8] */ 13246a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ 13256a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ 13266a504a75SDimitris Papastamos #define WM8995_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ 13276a504a75SDimitris Papastamos 13286a504a75SDimitris Papastamos /* 13296a504a75SDimitris Papastamos * R85 (0x55) - DC Servo (6) 13306a504a75SDimitris Papastamos */ 13316a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_3_MASK 0xFF00 /* DCS_DAC_WR_VAL_3 - [15:8] */ 13326a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_3_SHIFT 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 13336a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [15:8] */ 13346a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ 13356a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ 13366a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ 13376a504a75SDimitris Papastamos 13386a504a75SDimitris Papastamos /* 13396a504a75SDimitris Papastamos * R86 (0x56) - DC Servo (7) 13406a504a75SDimitris Papastamos */ 13416a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_1_MASK 0xFF00 /* DCS_DAC_WR_VAL_1 - [15:8] */ 13426a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_1_SHIFT 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 13436a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [15:8] */ 13446a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ 13456a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ 13466a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ 13476a504a75SDimitris Papastamos 13486a504a75SDimitris Papastamos /* 13496a504a75SDimitris Papastamos * R87 (0x57) - DC Servo Readback 0 13506a504a75SDimitris Papastamos */ 13516a504a75SDimitris Papastamos #define WM8995_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ 13526a504a75SDimitris Papastamos #define WM8995_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ 13536a504a75SDimitris Papastamos #define WM8995_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ 13546a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ 13556a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 13566a504a75SDimitris Papastamos #define WM8995_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ 13576a504a75SDimitris Papastamos #define WM8995_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ 13586a504a75SDimitris Papastamos #define WM8995_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ 13596a504a75SDimitris Papastamos #define WM8995_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ 13606a504a75SDimitris Papastamos 13616a504a75SDimitris Papastamos /* 13626a504a75SDimitris Papastamos * R96 (0x60) - Analogue HP (1) 13636a504a75SDimitris Papastamos */ 13646a504a75SDimitris Papastamos #define WM8995_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */ 13656a504a75SDimitris Papastamos #define WM8995_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */ 13666a504a75SDimitris Papastamos #define WM8995_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */ 13676a504a75SDimitris Papastamos #define WM8995_HPOUT1L_RMV_SHORT_WIDTH 1 /* HPOUT1L_RMV_SHORT */ 13686a504a75SDimitris Papastamos #define WM8995_HPOUT1L_OUTP 0x0040 /* HPOUT1L_OUTP */ 13696a504a75SDimitris Papastamos #define WM8995_HPOUT1L_OUTP_MASK 0x0040 /* HPOUT1L_OUTP */ 13706a504a75SDimitris Papastamos #define WM8995_HPOUT1L_OUTP_SHIFT 6 /* HPOUT1L_OUTP */ 13716a504a75SDimitris Papastamos #define WM8995_HPOUT1L_OUTP_WIDTH 1 /* HPOUT1L_OUTP */ 13726a504a75SDimitris Papastamos #define WM8995_HPOUT1L_DLY 0x0020 /* HPOUT1L_DLY */ 13736a504a75SDimitris Papastamos #define WM8995_HPOUT1L_DLY_MASK 0x0020 /* HPOUT1L_DLY */ 13746a504a75SDimitris Papastamos #define WM8995_HPOUT1L_DLY_SHIFT 5 /* HPOUT1L_DLY */ 13756a504a75SDimitris Papastamos #define WM8995_HPOUT1L_DLY_WIDTH 1 /* HPOUT1L_DLY */ 13766a504a75SDimitris Papastamos #define WM8995_HPOUT1R_RMV_SHORT 0x0008 /* HPOUT1R_RMV_SHORT */ 13776a504a75SDimitris Papastamos #define WM8995_HPOUT1R_RMV_SHORT_MASK 0x0008 /* HPOUT1R_RMV_SHORT */ 13786a504a75SDimitris Papastamos #define WM8995_HPOUT1R_RMV_SHORT_SHIFT 3 /* HPOUT1R_RMV_SHORT */ 13796a504a75SDimitris Papastamos #define WM8995_HPOUT1R_RMV_SHORT_WIDTH 1 /* HPOUT1R_RMV_SHORT */ 13806a504a75SDimitris Papastamos #define WM8995_HPOUT1R_OUTP 0x0004 /* HPOUT1R_OUTP */ 13816a504a75SDimitris Papastamos #define WM8995_HPOUT1R_OUTP_MASK 0x0004 /* HPOUT1R_OUTP */ 13826a504a75SDimitris Papastamos #define WM8995_HPOUT1R_OUTP_SHIFT 2 /* HPOUT1R_OUTP */ 13836a504a75SDimitris Papastamos #define WM8995_HPOUT1R_OUTP_WIDTH 1 /* HPOUT1R_OUTP */ 13846a504a75SDimitris Papastamos #define WM8995_HPOUT1R_DLY 0x0002 /* HPOUT1R_DLY */ 13856a504a75SDimitris Papastamos #define WM8995_HPOUT1R_DLY_MASK 0x0002 /* HPOUT1R_DLY */ 13866a504a75SDimitris Papastamos #define WM8995_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */ 13876a504a75SDimitris Papastamos #define WM8995_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */ 13886a504a75SDimitris Papastamos 13896a504a75SDimitris Papastamos /* 13906a504a75SDimitris Papastamos * R97 (0x61) - Analogue HP (2) 13916a504a75SDimitris Papastamos */ 13926a504a75SDimitris Papastamos #define WM8995_HPOUT2L_RMV_SHORT 0x0080 /* HPOUT2L_RMV_SHORT */ 13936a504a75SDimitris Papastamos #define WM8995_HPOUT2L_RMV_SHORT_MASK 0x0080 /* HPOUT2L_RMV_SHORT */ 13946a504a75SDimitris Papastamos #define WM8995_HPOUT2L_RMV_SHORT_SHIFT 7 /* HPOUT2L_RMV_SHORT */ 13956a504a75SDimitris Papastamos #define WM8995_HPOUT2L_RMV_SHORT_WIDTH 1 /* HPOUT2L_RMV_SHORT */ 13966a504a75SDimitris Papastamos #define WM8995_HPOUT2L_OUTP 0x0040 /* HPOUT2L_OUTP */ 13976a504a75SDimitris Papastamos #define WM8995_HPOUT2L_OUTP_MASK 0x0040 /* HPOUT2L_OUTP */ 13986a504a75SDimitris Papastamos #define WM8995_HPOUT2L_OUTP_SHIFT 6 /* HPOUT2L_OUTP */ 13996a504a75SDimitris Papastamos #define WM8995_HPOUT2L_OUTP_WIDTH 1 /* HPOUT2L_OUTP */ 14006a504a75SDimitris Papastamos #define WM8995_HPOUT2L_DLY 0x0020 /* HPOUT2L_DLY */ 14016a504a75SDimitris Papastamos #define WM8995_HPOUT2L_DLY_MASK 0x0020 /* HPOUT2L_DLY */ 14026a504a75SDimitris Papastamos #define WM8995_HPOUT2L_DLY_SHIFT 5 /* HPOUT2L_DLY */ 14036a504a75SDimitris Papastamos #define WM8995_HPOUT2L_DLY_WIDTH 1 /* HPOUT2L_DLY */ 14046a504a75SDimitris Papastamos #define WM8995_HPOUT2R_RMV_SHORT 0x0008 /* HPOUT2R_RMV_SHORT */ 14056a504a75SDimitris Papastamos #define WM8995_HPOUT2R_RMV_SHORT_MASK 0x0008 /* HPOUT2R_RMV_SHORT */ 14066a504a75SDimitris Papastamos #define WM8995_HPOUT2R_RMV_SHORT_SHIFT 3 /* HPOUT2R_RMV_SHORT */ 14076a504a75SDimitris Papastamos #define WM8995_HPOUT2R_RMV_SHORT_WIDTH 1 /* HPOUT2R_RMV_SHORT */ 14086a504a75SDimitris Papastamos #define WM8995_HPOUT2R_OUTP 0x0004 /* HPOUT2R_OUTP */ 14096a504a75SDimitris Papastamos #define WM8995_HPOUT2R_OUTP_MASK 0x0004 /* HPOUT2R_OUTP */ 14106a504a75SDimitris Papastamos #define WM8995_HPOUT2R_OUTP_SHIFT 2 /* HPOUT2R_OUTP */ 14116a504a75SDimitris Papastamos #define WM8995_HPOUT2R_OUTP_WIDTH 1 /* HPOUT2R_OUTP */ 14126a504a75SDimitris Papastamos #define WM8995_HPOUT2R_DLY 0x0002 /* HPOUT2R_DLY */ 14136a504a75SDimitris Papastamos #define WM8995_HPOUT2R_DLY_MASK 0x0002 /* HPOUT2R_DLY */ 14146a504a75SDimitris Papastamos #define WM8995_HPOUT2R_DLY_SHIFT 1 /* HPOUT2R_DLY */ 14156a504a75SDimitris Papastamos #define WM8995_HPOUT2R_DLY_WIDTH 1 /* HPOUT2R_DLY */ 14166a504a75SDimitris Papastamos 14176a504a75SDimitris Papastamos /* 14186a504a75SDimitris Papastamos * R256 (0x100) - Chip Revision 14196a504a75SDimitris Papastamos */ 14206a504a75SDimitris Papastamos #define WM8995_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 14216a504a75SDimitris Papastamos #define WM8995_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 14226a504a75SDimitris Papastamos #define WM8995_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 14236a504a75SDimitris Papastamos 14246a504a75SDimitris Papastamos /* 14256a504a75SDimitris Papastamos * R257 (0x101) - Control Interface (1) 14266a504a75SDimitris Papastamos */ 14276a504a75SDimitris Papastamos #define WM8995_REG_SYNC 0x8000 /* REG_SYNC */ 14286a504a75SDimitris Papastamos #define WM8995_REG_SYNC_MASK 0x8000 /* REG_SYNC */ 14296a504a75SDimitris Papastamos #define WM8995_REG_SYNC_SHIFT 15 /* REG_SYNC */ 14306a504a75SDimitris Papastamos #define WM8995_REG_SYNC_WIDTH 1 /* REG_SYNC */ 14316a504a75SDimitris Papastamos #define WM8995_SPI_CONTRD 0x0040 /* SPI_CONTRD */ 14326a504a75SDimitris Papastamos #define WM8995_SPI_CONTRD_MASK 0x0040 /* SPI_CONTRD */ 14336a504a75SDimitris Papastamos #define WM8995_SPI_CONTRD_SHIFT 6 /* SPI_CONTRD */ 14346a504a75SDimitris Papastamos #define WM8995_SPI_CONTRD_WIDTH 1 /* SPI_CONTRD */ 14356a504a75SDimitris Papastamos #define WM8995_SPI_4WIRE 0x0020 /* SPI_4WIRE */ 14366a504a75SDimitris Papastamos #define WM8995_SPI_4WIRE_MASK 0x0020 /* SPI_4WIRE */ 14376a504a75SDimitris Papastamos #define WM8995_SPI_4WIRE_SHIFT 5 /* SPI_4WIRE */ 14386a504a75SDimitris Papastamos #define WM8995_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */ 14396a504a75SDimitris Papastamos #define WM8995_SPI_CFG 0x0010 /* SPI_CFG */ 14406a504a75SDimitris Papastamos #define WM8995_SPI_CFG_MASK 0x0010 /* SPI_CFG */ 14416a504a75SDimitris Papastamos #define WM8995_SPI_CFG_SHIFT 4 /* SPI_CFG */ 14426a504a75SDimitris Papastamos #define WM8995_SPI_CFG_WIDTH 1 /* SPI_CFG */ 14436a504a75SDimitris Papastamos #define WM8995_AUTO_INC 0x0004 /* AUTO_INC */ 14446a504a75SDimitris Papastamos #define WM8995_AUTO_INC_MASK 0x0004 /* AUTO_INC */ 14456a504a75SDimitris Papastamos #define WM8995_AUTO_INC_SHIFT 2 /* AUTO_INC */ 14466a504a75SDimitris Papastamos #define WM8995_AUTO_INC_WIDTH 1 /* AUTO_INC */ 14476a504a75SDimitris Papastamos 14486a504a75SDimitris Papastamos /* 14496a504a75SDimitris Papastamos * R258 (0x102) - Control Interface (2) 14506a504a75SDimitris Papastamos */ 14516a504a75SDimitris Papastamos #define WM8995_CTRL_IF_SRC 0x0001 /* CTRL_IF_SRC */ 14526a504a75SDimitris Papastamos #define WM8995_CTRL_IF_SRC_MASK 0x0001 /* CTRL_IF_SRC */ 14536a504a75SDimitris Papastamos #define WM8995_CTRL_IF_SRC_SHIFT 0 /* CTRL_IF_SRC */ 14546a504a75SDimitris Papastamos #define WM8995_CTRL_IF_SRC_WIDTH 1 /* CTRL_IF_SRC */ 14556a504a75SDimitris Papastamos 14566a504a75SDimitris Papastamos /* 14576a504a75SDimitris Papastamos * R272 (0x110) - Write Sequencer Ctrl (1) 14586a504a75SDimitris Papastamos */ 14596a504a75SDimitris Papastamos #define WM8995_WSEQ_ENA 0x8000 /* WSEQ_ENA */ 14606a504a75SDimitris Papastamos #define WM8995_WSEQ_ENA_MASK 0x8000 /* WSEQ_ENA */ 14616a504a75SDimitris Papastamos #define WM8995_WSEQ_ENA_SHIFT 15 /* WSEQ_ENA */ 14626a504a75SDimitris Papastamos #define WM8995_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 14636a504a75SDimitris Papastamos #define WM8995_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 14646a504a75SDimitris Papastamos #define WM8995_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 14656a504a75SDimitris Papastamos #define WM8995_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 14666a504a75SDimitris Papastamos #define WM8995_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 14676a504a75SDimitris Papastamos #define WM8995_WSEQ_START 0x0100 /* WSEQ_START */ 14686a504a75SDimitris Papastamos #define WM8995_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 14696a504a75SDimitris Papastamos #define WM8995_WSEQ_START_SHIFT 8 /* WSEQ_START */ 14706a504a75SDimitris Papastamos #define WM8995_WSEQ_START_WIDTH 1 /* WSEQ_START */ 14716a504a75SDimitris Papastamos #define WM8995_WSEQ_START_INDEX_MASK 0x007F /* WSEQ_START_INDEX - [6:0] */ 14726a504a75SDimitris Papastamos #define WM8995_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [6:0] */ 14736a504a75SDimitris Papastamos #define WM8995_WSEQ_START_INDEX_WIDTH 7 /* WSEQ_START_INDEX - [6:0] */ 14746a504a75SDimitris Papastamos 14756a504a75SDimitris Papastamos /* 14766a504a75SDimitris Papastamos * R273 (0x111) - Write Sequencer Ctrl (2) 14776a504a75SDimitris Papastamos */ 14786a504a75SDimitris Papastamos #define WM8995_WSEQ_BUSY 0x0100 /* WSEQ_BUSY */ 14796a504a75SDimitris Papastamos #define WM8995_WSEQ_BUSY_MASK 0x0100 /* WSEQ_BUSY */ 14806a504a75SDimitris Papastamos #define WM8995_WSEQ_BUSY_SHIFT 8 /* WSEQ_BUSY */ 14816a504a75SDimitris Papastamos #define WM8995_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 14826a504a75SDimitris Papastamos #define WM8995_WSEQ_CURRENT_INDEX_MASK 0x007F /* WSEQ_CURRENT_INDEX - [6:0] */ 14836a504a75SDimitris Papastamos #define WM8995_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [6:0] */ 14846a504a75SDimitris Papastamos #define WM8995_WSEQ_CURRENT_INDEX_WIDTH 7 /* WSEQ_CURRENT_INDEX - [6:0] */ 14856a504a75SDimitris Papastamos 14866a504a75SDimitris Papastamos /* 14876a504a75SDimitris Papastamos * R512 (0x200) - AIF1 Clocking (1) 14886a504a75SDimitris Papastamos */ 14896a504a75SDimitris Papastamos #define WM8995_AIF1CLK_SRC_MASK 0x0018 /* AIF1CLK_SRC - [4:3] */ 14906a504a75SDimitris Papastamos #define WM8995_AIF1CLK_SRC_SHIFT 3 /* AIF1CLK_SRC - [4:3] */ 14916a504a75SDimitris Papastamos #define WM8995_AIF1CLK_SRC_WIDTH 2 /* AIF1CLK_SRC - [4:3] */ 14926a504a75SDimitris Papastamos #define WM8995_AIF1CLK_INV 0x0004 /* AIF1CLK_INV */ 14936a504a75SDimitris Papastamos #define WM8995_AIF1CLK_INV_MASK 0x0004 /* AIF1CLK_INV */ 14946a504a75SDimitris Papastamos #define WM8995_AIF1CLK_INV_SHIFT 2 /* AIF1CLK_INV */ 14956a504a75SDimitris Papastamos #define WM8995_AIF1CLK_INV_WIDTH 1 /* AIF1CLK_INV */ 14966a504a75SDimitris Papastamos #define WM8995_AIF1CLK_DIV 0x0002 /* AIF1CLK_DIV */ 14976a504a75SDimitris Papastamos #define WM8995_AIF1CLK_DIV_MASK 0x0002 /* AIF1CLK_DIV */ 14986a504a75SDimitris Papastamos #define WM8995_AIF1CLK_DIV_SHIFT 1 /* AIF1CLK_DIV */ 14996a504a75SDimitris Papastamos #define WM8995_AIF1CLK_DIV_WIDTH 1 /* AIF1CLK_DIV */ 15006a504a75SDimitris Papastamos #define WM8995_AIF1CLK_ENA 0x0001 /* AIF1CLK_ENA */ 15016a504a75SDimitris Papastamos #define WM8995_AIF1CLK_ENA_MASK 0x0001 /* AIF1CLK_ENA */ 15026a504a75SDimitris Papastamos #define WM8995_AIF1CLK_ENA_SHIFT 0 /* AIF1CLK_ENA */ 15036a504a75SDimitris Papastamos #define WM8995_AIF1CLK_ENA_WIDTH 1 /* AIF1CLK_ENA */ 15046a504a75SDimitris Papastamos 15056a504a75SDimitris Papastamos /* 15066a504a75SDimitris Papastamos * R513 (0x201) - AIF1 Clocking (2) 15076a504a75SDimitris Papastamos */ 15086a504a75SDimitris Papastamos #define WM8995_AIF1DAC_DIV_MASK 0x0038 /* AIF1DAC_DIV - [5:3] */ 15096a504a75SDimitris Papastamos #define WM8995_AIF1DAC_DIV_SHIFT 3 /* AIF1DAC_DIV - [5:3] */ 15106a504a75SDimitris Papastamos #define WM8995_AIF1DAC_DIV_WIDTH 3 /* AIF1DAC_DIV - [5:3] */ 15116a504a75SDimitris Papastamos #define WM8995_AIF1ADC_DIV_MASK 0x0007 /* AIF1ADC_DIV - [2:0] */ 15126a504a75SDimitris Papastamos #define WM8995_AIF1ADC_DIV_SHIFT 0 /* AIF1ADC_DIV - [2:0] */ 15136a504a75SDimitris Papastamos #define WM8995_AIF1ADC_DIV_WIDTH 3 /* AIF1ADC_DIV - [2:0] */ 15146a504a75SDimitris Papastamos 15156a504a75SDimitris Papastamos /* 15166a504a75SDimitris Papastamos * R516 (0x204) - AIF2 Clocking (1) 15176a504a75SDimitris Papastamos */ 15186a504a75SDimitris Papastamos #define WM8995_AIF2CLK_SRC_MASK 0x0018 /* AIF2CLK_SRC - [4:3] */ 15196a504a75SDimitris Papastamos #define WM8995_AIF2CLK_SRC_SHIFT 3 /* AIF2CLK_SRC - [4:3] */ 15206a504a75SDimitris Papastamos #define WM8995_AIF2CLK_SRC_WIDTH 2 /* AIF2CLK_SRC - [4:3] */ 15216a504a75SDimitris Papastamos #define WM8995_AIF2CLK_INV 0x0004 /* AIF2CLK_INV */ 15226a504a75SDimitris Papastamos #define WM8995_AIF2CLK_INV_MASK 0x0004 /* AIF2CLK_INV */ 15236a504a75SDimitris Papastamos #define WM8995_AIF2CLK_INV_SHIFT 2 /* AIF2CLK_INV */ 15246a504a75SDimitris Papastamos #define WM8995_AIF2CLK_INV_WIDTH 1 /* AIF2CLK_INV */ 15256a504a75SDimitris Papastamos #define WM8995_AIF2CLK_DIV 0x0002 /* AIF2CLK_DIV */ 15266a504a75SDimitris Papastamos #define WM8995_AIF2CLK_DIV_MASK 0x0002 /* AIF2CLK_DIV */ 15276a504a75SDimitris Papastamos #define WM8995_AIF2CLK_DIV_SHIFT 1 /* AIF2CLK_DIV */ 15286a504a75SDimitris Papastamos #define WM8995_AIF2CLK_DIV_WIDTH 1 /* AIF2CLK_DIV */ 15296a504a75SDimitris Papastamos #define WM8995_AIF2CLK_ENA 0x0001 /* AIF2CLK_ENA */ 15306a504a75SDimitris Papastamos #define WM8995_AIF2CLK_ENA_MASK 0x0001 /* AIF2CLK_ENA */ 15316a504a75SDimitris Papastamos #define WM8995_AIF2CLK_ENA_SHIFT 0 /* AIF2CLK_ENA */ 15326a504a75SDimitris Papastamos #define WM8995_AIF2CLK_ENA_WIDTH 1 /* AIF2CLK_ENA */ 15336a504a75SDimitris Papastamos 15346a504a75SDimitris Papastamos /* 15356a504a75SDimitris Papastamos * R517 (0x205) - AIF2 Clocking (2) 15366a504a75SDimitris Papastamos */ 15376a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DIV_MASK 0x0038 /* AIF2DAC_DIV - [5:3] */ 15386a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DIV_SHIFT 3 /* AIF2DAC_DIV - [5:3] */ 15396a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DIV_WIDTH 3 /* AIF2DAC_DIV - [5:3] */ 15406a504a75SDimitris Papastamos #define WM8995_AIF2ADC_DIV_MASK 0x0007 /* AIF2ADC_DIV - [2:0] */ 15416a504a75SDimitris Papastamos #define WM8995_AIF2ADC_DIV_SHIFT 0 /* AIF2ADC_DIV - [2:0] */ 15426a504a75SDimitris Papastamos #define WM8995_AIF2ADC_DIV_WIDTH 3 /* AIF2ADC_DIV - [2:0] */ 15436a504a75SDimitris Papastamos 15446a504a75SDimitris Papastamos /* 15456a504a75SDimitris Papastamos * R520 (0x208) - Clocking (1) 15466a504a75SDimitris Papastamos */ 15476a504a75SDimitris Papastamos #define WM8995_LFCLK_ENA 0x0020 /* LFCLK_ENA */ 15486a504a75SDimitris Papastamos #define WM8995_LFCLK_ENA_MASK 0x0020 /* LFCLK_ENA */ 15496a504a75SDimitris Papastamos #define WM8995_LFCLK_ENA_SHIFT 5 /* LFCLK_ENA */ 15506a504a75SDimitris Papastamos #define WM8995_LFCLK_ENA_WIDTH 1 /* LFCLK_ENA */ 15516a504a75SDimitris Papastamos #define WM8995_TOCLK_ENA 0x0010 /* TOCLK_ENA */ 15526a504a75SDimitris Papastamos #define WM8995_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */ 15536a504a75SDimitris Papastamos #define WM8995_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */ 15546a504a75SDimitris Papastamos #define WM8995_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ 15556a504a75SDimitris Papastamos #define WM8995_AIF1DSPCLK_ENA 0x0008 /* AIF1DSPCLK_ENA */ 15566a504a75SDimitris Papastamos #define WM8995_AIF1DSPCLK_ENA_MASK 0x0008 /* AIF1DSPCLK_ENA */ 15576a504a75SDimitris Papastamos #define WM8995_AIF1DSPCLK_ENA_SHIFT 3 /* AIF1DSPCLK_ENA */ 15586a504a75SDimitris Papastamos #define WM8995_AIF1DSPCLK_ENA_WIDTH 1 /* AIF1DSPCLK_ENA */ 15596a504a75SDimitris Papastamos #define WM8995_AIF2DSPCLK_ENA 0x0004 /* AIF2DSPCLK_ENA */ 15606a504a75SDimitris Papastamos #define WM8995_AIF2DSPCLK_ENA_MASK 0x0004 /* AIF2DSPCLK_ENA */ 15616a504a75SDimitris Papastamos #define WM8995_AIF2DSPCLK_ENA_SHIFT 2 /* AIF2DSPCLK_ENA */ 15626a504a75SDimitris Papastamos #define WM8995_AIF2DSPCLK_ENA_WIDTH 1 /* AIF2DSPCLK_ENA */ 15636a504a75SDimitris Papastamos #define WM8995_SYSDSPCLK_ENA 0x0002 /* SYSDSPCLK_ENA */ 15646a504a75SDimitris Papastamos #define WM8995_SYSDSPCLK_ENA_MASK 0x0002 /* SYSDSPCLK_ENA */ 15656a504a75SDimitris Papastamos #define WM8995_SYSDSPCLK_ENA_SHIFT 1 /* SYSDSPCLK_ENA */ 15666a504a75SDimitris Papastamos #define WM8995_SYSDSPCLK_ENA_WIDTH 1 /* SYSDSPCLK_ENA */ 15676a504a75SDimitris Papastamos #define WM8995_SYSCLK_SRC 0x0001 /* SYSCLK_SRC */ 15686a504a75SDimitris Papastamos #define WM8995_SYSCLK_SRC_MASK 0x0001 /* SYSCLK_SRC */ 15696a504a75SDimitris Papastamos #define WM8995_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC */ 15706a504a75SDimitris Papastamos #define WM8995_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ 15716a504a75SDimitris Papastamos 15726a504a75SDimitris Papastamos /* 15736a504a75SDimitris Papastamos * R521 (0x209) - Clocking (2) 15746a504a75SDimitris Papastamos */ 15756a504a75SDimitris Papastamos #define WM8995_TOCLK_DIV_MASK 0x0700 /* TOCLK_DIV - [10:8] */ 15766a504a75SDimitris Papastamos #define WM8995_TOCLK_DIV_SHIFT 8 /* TOCLK_DIV - [10:8] */ 15776a504a75SDimitris Papastamos #define WM8995_TOCLK_DIV_WIDTH 3 /* TOCLK_DIV - [10:8] */ 15786a504a75SDimitris Papastamos #define WM8995_DBCLK_DIV_MASK 0x00F0 /* DBCLK_DIV - [7:4] */ 15796a504a75SDimitris Papastamos #define WM8995_DBCLK_DIV_SHIFT 4 /* DBCLK_DIV - [7:4] */ 15806a504a75SDimitris Papastamos #define WM8995_DBCLK_DIV_WIDTH 4 /* DBCLK_DIV - [7:4] */ 15816a504a75SDimitris Papastamos #define WM8995_OPCLK_DIV_MASK 0x0007 /* OPCLK_DIV - [2:0] */ 15826a504a75SDimitris Papastamos #define WM8995_OPCLK_DIV_SHIFT 0 /* OPCLK_DIV - [2:0] */ 15836a504a75SDimitris Papastamos #define WM8995_OPCLK_DIV_WIDTH 3 /* OPCLK_DIV - [2:0] */ 15846a504a75SDimitris Papastamos 15856a504a75SDimitris Papastamos /* 15866a504a75SDimitris Papastamos * R528 (0x210) - AIF1 Rate 15876a504a75SDimitris Papastamos */ 15886a504a75SDimitris Papastamos #define WM8995_AIF1_SR_MASK 0x00F0 /* AIF1_SR - [7:4] */ 15896a504a75SDimitris Papastamos #define WM8995_AIF1_SR_SHIFT 4 /* AIF1_SR - [7:4] */ 15906a504a75SDimitris Papastamos #define WM8995_AIF1_SR_WIDTH 4 /* AIF1_SR - [7:4] */ 15916a504a75SDimitris Papastamos #define WM8995_AIF1CLK_RATE_MASK 0x000F /* AIF1CLK_RATE - [3:0] */ 15926a504a75SDimitris Papastamos #define WM8995_AIF1CLK_RATE_SHIFT 0 /* AIF1CLK_RATE - [3:0] */ 15936a504a75SDimitris Papastamos #define WM8995_AIF1CLK_RATE_WIDTH 4 /* AIF1CLK_RATE - [3:0] */ 15946a504a75SDimitris Papastamos 15956a504a75SDimitris Papastamos /* 15966a504a75SDimitris Papastamos * R529 (0x211) - AIF2 Rate 15976a504a75SDimitris Papastamos */ 15986a504a75SDimitris Papastamos #define WM8995_AIF2_SR_MASK 0x00F0 /* AIF2_SR - [7:4] */ 15996a504a75SDimitris Papastamos #define WM8995_AIF2_SR_SHIFT 4 /* AIF2_SR - [7:4] */ 16006a504a75SDimitris Papastamos #define WM8995_AIF2_SR_WIDTH 4 /* AIF2_SR - [7:4] */ 16016a504a75SDimitris Papastamos #define WM8995_AIF2CLK_RATE_MASK 0x000F /* AIF2CLK_RATE - [3:0] */ 16026a504a75SDimitris Papastamos #define WM8995_AIF2CLK_RATE_SHIFT 0 /* AIF2CLK_RATE - [3:0] */ 16036a504a75SDimitris Papastamos #define WM8995_AIF2CLK_RATE_WIDTH 4 /* AIF2CLK_RATE - [3:0] */ 16046a504a75SDimitris Papastamos 16056a504a75SDimitris Papastamos /* 16066a504a75SDimitris Papastamos * R530 (0x212) - Rate Status 16076a504a75SDimitris Papastamos */ 16086a504a75SDimitris Papastamos #define WM8995_SR_ERROR_MASK 0x000F /* SR_ERROR - [3:0] */ 16096a504a75SDimitris Papastamos #define WM8995_SR_ERROR_SHIFT 0 /* SR_ERROR - [3:0] */ 16106a504a75SDimitris Papastamos #define WM8995_SR_ERROR_WIDTH 4 /* SR_ERROR - [3:0] */ 16116a504a75SDimitris Papastamos 16126a504a75SDimitris Papastamos /* 16136a504a75SDimitris Papastamos * R544 (0x220) - FLL1 Control (1) 16146a504a75SDimitris Papastamos */ 16156a504a75SDimitris Papastamos #define WM8995_FLL1_OSC_ENA 0x0002 /* FLL1_OSC_ENA */ 16166a504a75SDimitris Papastamos #define WM8995_FLL1_OSC_ENA_MASK 0x0002 /* FLL1_OSC_ENA */ 16176a504a75SDimitris Papastamos #define WM8995_FLL1_OSC_ENA_SHIFT 1 /* FLL1_OSC_ENA */ 16186a504a75SDimitris Papastamos #define WM8995_FLL1_OSC_ENA_WIDTH 1 /* FLL1_OSC_ENA */ 16196a504a75SDimitris Papastamos #define WM8995_FLL1_ENA 0x0001 /* FLL1_ENA */ 16206a504a75SDimitris Papastamos #define WM8995_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 16216a504a75SDimitris Papastamos #define WM8995_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 16226a504a75SDimitris Papastamos #define WM8995_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 16236a504a75SDimitris Papastamos 16246a504a75SDimitris Papastamos /* 16256a504a75SDimitris Papastamos * R545 (0x221) - FLL1 Control (2) 16266a504a75SDimitris Papastamos */ 16276a504a75SDimitris Papastamos #define WM8995_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 16286a504a75SDimitris Papastamos #define WM8995_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 16296a504a75SDimitris Papastamos #define WM8995_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 16306a504a75SDimitris Papastamos #define WM8995_FLL1_CTRL_RATE_MASK 0x0070 /* FLL1_CTRL_RATE - [6:4] */ 16316a504a75SDimitris Papastamos #define WM8995_FLL1_CTRL_RATE_SHIFT 4 /* FLL1_CTRL_RATE - [6:4] */ 16326a504a75SDimitris Papastamos #define WM8995_FLL1_CTRL_RATE_WIDTH 3 /* FLL1_CTRL_RATE - [6:4] */ 16336a504a75SDimitris Papastamos #define WM8995_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 16346a504a75SDimitris Papastamos #define WM8995_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 16356a504a75SDimitris Papastamos #define WM8995_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 16366a504a75SDimitris Papastamos 16376a504a75SDimitris Papastamos /* 16386a504a75SDimitris Papastamos * R546 (0x222) - FLL1 Control (3) 16396a504a75SDimitris Papastamos */ 16406a504a75SDimitris Papastamos #define WM8995_FLL1_K_MASK 0xFFFF /* FLL1_K - [15:0] */ 16416a504a75SDimitris Papastamos #define WM8995_FLL1_K_SHIFT 0 /* FLL1_K - [15:0] */ 16426a504a75SDimitris Papastamos #define WM8995_FLL1_K_WIDTH 16 /* FLL1_K - [15:0] */ 16436a504a75SDimitris Papastamos 16446a504a75SDimitris Papastamos /* 16456a504a75SDimitris Papastamos * R547 (0x223) - FLL1 Control (4) 16466a504a75SDimitris Papastamos */ 16476a504a75SDimitris Papastamos #define WM8995_FLL1_N_MASK 0x7FE0 /* FLL1_N - [14:5] */ 16486a504a75SDimitris Papastamos #define WM8995_FLL1_N_SHIFT 5 /* FLL1_N - [14:5] */ 16496a504a75SDimitris Papastamos #define WM8995_FLL1_N_WIDTH 10 /* FLL1_N - [14:5] */ 16506a504a75SDimitris Papastamos #define WM8995_FLL1_LOOP_GAIN_MASK 0x000F /* FLL1_LOOP_GAIN - [3:0] */ 16516a504a75SDimitris Papastamos #define WM8995_FLL1_LOOP_GAIN_SHIFT 0 /* FLL1_LOOP_GAIN - [3:0] */ 16526a504a75SDimitris Papastamos #define WM8995_FLL1_LOOP_GAIN_WIDTH 4 /* FLL1_LOOP_GAIN - [3:0] */ 16536a504a75SDimitris Papastamos 16546a504a75SDimitris Papastamos /* 16556a504a75SDimitris Papastamos * R548 (0x224) - FLL1 Control (5) 16566a504a75SDimitris Papastamos */ 16576a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_VAL_MASK 0x1F80 /* FLL1_FRC_NCO_VAL - [12:7] */ 16586a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_VAL_SHIFT 7 /* FLL1_FRC_NCO_VAL - [12:7] */ 16596a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_VAL_WIDTH 6 /* FLL1_FRC_NCO_VAL - [12:7] */ 16606a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO 0x0040 /* FLL1_FRC_NCO */ 16616a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_MASK 0x0040 /* FLL1_FRC_NCO */ 16626a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_SHIFT 6 /* FLL1_FRC_NCO */ 16636a504a75SDimitris Papastamos #define WM8995_FLL1_FRC_NCO_WIDTH 1 /* FLL1_FRC_NCO */ 16646a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_DIV_MASK 0x0018 /* FLL1_REFCLK_DIV - [4:3] */ 16656a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_DIV_SHIFT 3 /* FLL1_REFCLK_DIV - [4:3] */ 16666a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [4:3] */ 16676a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_SRC_MASK 0x0003 /* FLL1_REFCLK_SRC - [1:0] */ 16686a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [1:0] */ 16696a504a75SDimitris Papastamos #define WM8995_FLL1_REFCLK_SRC_WIDTH 2 /* FLL1_REFCLK_SRC - [1:0] */ 16706a504a75SDimitris Papastamos 16716a504a75SDimitris Papastamos /* 16726a504a75SDimitris Papastamos * R576 (0x240) - FLL2 Control (1) 16736a504a75SDimitris Papastamos */ 16746a504a75SDimitris Papastamos #define WM8995_FLL2_OSC_ENA 0x0002 /* FLL2_OSC_ENA */ 16756a504a75SDimitris Papastamos #define WM8995_FLL2_OSC_ENA_MASK 0x0002 /* FLL2_OSC_ENA */ 16766a504a75SDimitris Papastamos #define WM8995_FLL2_OSC_ENA_SHIFT 1 /* FLL2_OSC_ENA */ 16776a504a75SDimitris Papastamos #define WM8995_FLL2_OSC_ENA_WIDTH 1 /* FLL2_OSC_ENA */ 16786a504a75SDimitris Papastamos #define WM8995_FLL2_ENA 0x0001 /* FLL2_ENA */ 16796a504a75SDimitris Papastamos #define WM8995_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 16806a504a75SDimitris Papastamos #define WM8995_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 16816a504a75SDimitris Papastamos #define WM8995_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 16826a504a75SDimitris Papastamos 16836a504a75SDimitris Papastamos /* 16846a504a75SDimitris Papastamos * R577 (0x241) - FLL2 Control (2) 16856a504a75SDimitris Papastamos */ 16866a504a75SDimitris Papastamos #define WM8995_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 16876a504a75SDimitris Papastamos #define WM8995_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 16886a504a75SDimitris Papastamos #define WM8995_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 16896a504a75SDimitris Papastamos #define WM8995_FLL2_CTRL_RATE_MASK 0x0070 /* FLL2_CTRL_RATE - [6:4] */ 16906a504a75SDimitris Papastamos #define WM8995_FLL2_CTRL_RATE_SHIFT 4 /* FLL2_CTRL_RATE - [6:4] */ 16916a504a75SDimitris Papastamos #define WM8995_FLL2_CTRL_RATE_WIDTH 3 /* FLL2_CTRL_RATE - [6:4] */ 16926a504a75SDimitris Papastamos #define WM8995_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 16936a504a75SDimitris Papastamos #define WM8995_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 16946a504a75SDimitris Papastamos #define WM8995_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 16956a504a75SDimitris Papastamos 16966a504a75SDimitris Papastamos /* 16976a504a75SDimitris Papastamos * R578 (0x242) - FLL2 Control (3) 16986a504a75SDimitris Papastamos */ 16996a504a75SDimitris Papastamos #define WM8995_FLL2_K_MASK 0xFFFF /* FLL2_K - [15:0] */ 17006a504a75SDimitris Papastamos #define WM8995_FLL2_K_SHIFT 0 /* FLL2_K - [15:0] */ 17016a504a75SDimitris Papastamos #define WM8995_FLL2_K_WIDTH 16 /* FLL2_K - [15:0] */ 17026a504a75SDimitris Papastamos 17036a504a75SDimitris Papastamos /* 17046a504a75SDimitris Papastamos * R579 (0x243) - FLL2 Control (4) 17056a504a75SDimitris Papastamos */ 17066a504a75SDimitris Papastamos #define WM8995_FLL2_N_MASK 0x7FE0 /* FLL2_N - [14:5] */ 17076a504a75SDimitris Papastamos #define WM8995_FLL2_N_SHIFT 5 /* FLL2_N - [14:5] */ 17086a504a75SDimitris Papastamos #define WM8995_FLL2_N_WIDTH 10 /* FLL2_N - [14:5] */ 17096a504a75SDimitris Papastamos #define WM8995_FLL2_LOOP_GAIN_MASK 0x000F /* FLL2_LOOP_GAIN - [3:0] */ 17106a504a75SDimitris Papastamos #define WM8995_FLL2_LOOP_GAIN_SHIFT 0 /* FLL2_LOOP_GAIN - [3:0] */ 17116a504a75SDimitris Papastamos #define WM8995_FLL2_LOOP_GAIN_WIDTH 4 /* FLL2_LOOP_GAIN - [3:0] */ 17126a504a75SDimitris Papastamos 17136a504a75SDimitris Papastamos /* 17146a504a75SDimitris Papastamos * R580 (0x244) - FLL2 Control (5) 17156a504a75SDimitris Papastamos */ 17166a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_VAL_MASK 0x1F80 /* FLL2_FRC_NCO_VAL - [12:7] */ 17176a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_VAL_SHIFT 7 /* FLL2_FRC_NCO_VAL - [12:7] */ 17186a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_VAL_WIDTH 6 /* FLL2_FRC_NCO_VAL - [12:7] */ 17196a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO 0x0040 /* FLL2_FRC_NCO */ 17206a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_MASK 0x0040 /* FLL2_FRC_NCO */ 17216a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_SHIFT 6 /* FLL2_FRC_NCO */ 17226a504a75SDimitris Papastamos #define WM8995_FLL2_FRC_NCO_WIDTH 1 /* FLL2_FRC_NCO */ 17236a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_DIV_MASK 0x0018 /* FLL2_REFCLK_DIV - [4:3] */ 17246a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_DIV_SHIFT 3 /* FLL2_REFCLK_DIV - [4:3] */ 17256a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [4:3] */ 17266a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_SRC_MASK 0x0003 /* FLL2_REFCLK_SRC - [1:0] */ 17276a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [1:0] */ 17286a504a75SDimitris Papastamos #define WM8995_FLL2_REFCLK_SRC_WIDTH 2 /* FLL2_REFCLK_SRC - [1:0] */ 17296a504a75SDimitris Papastamos 17306a504a75SDimitris Papastamos /* 17316a504a75SDimitris Papastamos * R768 (0x300) - AIF1 Control (1) 17326a504a75SDimitris Papastamos */ 17336a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_SRC 0x8000 /* AIF1ADCL_SRC */ 17346a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_SRC_MASK 0x8000 /* AIF1ADCL_SRC */ 17356a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_SRC_SHIFT 15 /* AIF1ADCL_SRC */ 17366a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_SRC_WIDTH 1 /* AIF1ADCL_SRC */ 17376a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_SRC 0x4000 /* AIF1ADCR_SRC */ 17386a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_SRC_MASK 0x4000 /* AIF1ADCR_SRC */ 17396a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_SRC_SHIFT 14 /* AIF1ADCR_SRC */ 17406a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_SRC_WIDTH 1 /* AIF1ADCR_SRC */ 17416a504a75SDimitris Papastamos #define WM8995_AIF1ADC_TDM 0x2000 /* AIF1ADC_TDM */ 17426a504a75SDimitris Papastamos #define WM8995_AIF1ADC_TDM_MASK 0x2000 /* AIF1ADC_TDM */ 17436a504a75SDimitris Papastamos #define WM8995_AIF1ADC_TDM_SHIFT 13 /* AIF1ADC_TDM */ 17446a504a75SDimitris Papastamos #define WM8995_AIF1ADC_TDM_WIDTH 1 /* AIF1ADC_TDM */ 17456a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_INV 0x0100 /* AIF1_BCLK_INV */ 17466a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_INV_MASK 0x0100 /* AIF1_BCLK_INV */ 17476a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_INV_SHIFT 8 /* AIF1_BCLK_INV */ 17486a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 17496a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_INV 0x0080 /* AIF1_LRCLK_INV */ 17506a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_INV_MASK 0x0080 /* AIF1_LRCLK_INV */ 17516a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_INV_SHIFT 7 /* AIF1_LRCLK_INV */ 17526a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_INV_WIDTH 1 /* AIF1_LRCLK_INV */ 17536a504a75SDimitris Papastamos #define WM8995_AIF1_WL_MASK 0x0060 /* AIF1_WL - [6:5] */ 17546a504a75SDimitris Papastamos #define WM8995_AIF1_WL_SHIFT 5 /* AIF1_WL - [6:5] */ 17556a504a75SDimitris Papastamos #define WM8995_AIF1_WL_WIDTH 2 /* AIF1_WL - [6:5] */ 17566a504a75SDimitris Papastamos #define WM8995_AIF1_FMT_MASK 0x0018 /* AIF1_FMT - [4:3] */ 17576a504a75SDimitris Papastamos #define WM8995_AIF1_FMT_SHIFT 3 /* AIF1_FMT - [4:3] */ 17586a504a75SDimitris Papastamos #define WM8995_AIF1_FMT_WIDTH 2 /* AIF1_FMT - [4:3] */ 17596a504a75SDimitris Papastamos 17606a504a75SDimitris Papastamos /* 17616a504a75SDimitris Papastamos * R769 (0x301) - AIF1 Control (2) 17626a504a75SDimitris Papastamos */ 17636a504a75SDimitris Papastamos #define WM8995_AIF1DACL_SRC 0x8000 /* AIF1DACL_SRC */ 17646a504a75SDimitris Papastamos #define WM8995_AIF1DACL_SRC_MASK 0x8000 /* AIF1DACL_SRC */ 17656a504a75SDimitris Papastamos #define WM8995_AIF1DACL_SRC_SHIFT 15 /* AIF1DACL_SRC */ 17666a504a75SDimitris Papastamos #define WM8995_AIF1DACL_SRC_WIDTH 1 /* AIF1DACL_SRC */ 17676a504a75SDimitris Papastamos #define WM8995_AIF1DACR_SRC 0x4000 /* AIF1DACR_SRC */ 17686a504a75SDimitris Papastamos #define WM8995_AIF1DACR_SRC_MASK 0x4000 /* AIF1DACR_SRC */ 17696a504a75SDimitris Papastamos #define WM8995_AIF1DACR_SRC_SHIFT 14 /* AIF1DACR_SRC */ 17706a504a75SDimitris Papastamos #define WM8995_AIF1DACR_SRC_WIDTH 1 /* AIF1DACR_SRC */ 17716a504a75SDimitris Papastamos #define WM8995_AIF1DAC_BOOST_MASK 0x0C00 /* AIF1DAC_BOOST - [11:10] */ 17726a504a75SDimitris Papastamos #define WM8995_AIF1DAC_BOOST_SHIFT 10 /* AIF1DAC_BOOST - [11:10] */ 17736a504a75SDimitris Papastamos #define WM8995_AIF1DAC_BOOST_WIDTH 2 /* AIF1DAC_BOOST - [11:10] */ 17746a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMP 0x0010 /* AIF1DAC_COMP */ 17756a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMP_MASK 0x0010 /* AIF1DAC_COMP */ 17766a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMP_SHIFT 4 /* AIF1DAC_COMP */ 17776a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMP_WIDTH 1 /* AIF1DAC_COMP */ 17786a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMPMODE 0x0008 /* AIF1DAC_COMPMODE */ 17796a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMPMODE_MASK 0x0008 /* AIF1DAC_COMPMODE */ 17806a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMPMODE_SHIFT 3 /* AIF1DAC_COMPMODE */ 17816a504a75SDimitris Papastamos #define WM8995_AIF1DAC_COMPMODE_WIDTH 1 /* AIF1DAC_COMPMODE */ 17826a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMP 0x0004 /* AIF1ADC_COMP */ 17836a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMP_MASK 0x0004 /* AIF1ADC_COMP */ 17846a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMP_SHIFT 2 /* AIF1ADC_COMP */ 17856a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMP_WIDTH 1 /* AIF1ADC_COMP */ 17866a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMPMODE 0x0002 /* AIF1ADC_COMPMODE */ 17876a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMPMODE_MASK 0x0002 /* AIF1ADC_COMPMODE */ 17886a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMPMODE_SHIFT 1 /* AIF1ADC_COMPMODE */ 17896a504a75SDimitris Papastamos #define WM8995_AIF1ADC_COMPMODE_WIDTH 1 /* AIF1ADC_COMPMODE */ 17906a504a75SDimitris Papastamos #define WM8995_AIF1_LOOPBACK 0x0001 /* AIF1_LOOPBACK */ 17916a504a75SDimitris Papastamos #define WM8995_AIF1_LOOPBACK_MASK 0x0001 /* AIF1_LOOPBACK */ 17926a504a75SDimitris Papastamos #define WM8995_AIF1_LOOPBACK_SHIFT 0 /* AIF1_LOOPBACK */ 17936a504a75SDimitris Papastamos #define WM8995_AIF1_LOOPBACK_WIDTH 1 /* AIF1_LOOPBACK */ 17946a504a75SDimitris Papastamos 17956a504a75SDimitris Papastamos /* 17966a504a75SDimitris Papastamos * R770 (0x302) - AIF1 Master/Slave 17976a504a75SDimitris Papastamos */ 17986a504a75SDimitris Papastamos #define WM8995_AIF1_TRI 0x8000 /* AIF1_TRI */ 17996a504a75SDimitris Papastamos #define WM8995_AIF1_TRI_MASK 0x8000 /* AIF1_TRI */ 18006a504a75SDimitris Papastamos #define WM8995_AIF1_TRI_SHIFT 15 /* AIF1_TRI */ 18016a504a75SDimitris Papastamos #define WM8995_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 18026a504a75SDimitris Papastamos #define WM8995_AIF1_MSTR 0x4000 /* AIF1_MSTR */ 18036a504a75SDimitris Papastamos #define WM8995_AIF1_MSTR_MASK 0x4000 /* AIF1_MSTR */ 18046a504a75SDimitris Papastamos #define WM8995_AIF1_MSTR_SHIFT 14 /* AIF1_MSTR */ 18056a504a75SDimitris Papastamos #define WM8995_AIF1_MSTR_WIDTH 1 /* AIF1_MSTR */ 18066a504a75SDimitris Papastamos #define WM8995_AIF1_CLK_FRC 0x2000 /* AIF1_CLK_FRC */ 18076a504a75SDimitris Papastamos #define WM8995_AIF1_CLK_FRC_MASK 0x2000 /* AIF1_CLK_FRC */ 18086a504a75SDimitris Papastamos #define WM8995_AIF1_CLK_FRC_SHIFT 13 /* AIF1_CLK_FRC */ 18096a504a75SDimitris Papastamos #define WM8995_AIF1_CLK_FRC_WIDTH 1 /* AIF1_CLK_FRC */ 18106a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_FRC 0x1000 /* AIF1_LRCLK_FRC */ 18116a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_FRC_MASK 0x1000 /* AIF1_LRCLK_FRC */ 18126a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_FRC_SHIFT 12 /* AIF1_LRCLK_FRC */ 18136a504a75SDimitris Papastamos #define WM8995_AIF1_LRCLK_FRC_WIDTH 1 /* AIF1_LRCLK_FRC */ 18146a504a75SDimitris Papastamos 18156a504a75SDimitris Papastamos /* 18166a504a75SDimitris Papastamos * R771 (0x303) - AIF1 BCLK 18176a504a75SDimitris Papastamos */ 18186a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_DIV_MASK 0x00F0 /* AIF1_BCLK_DIV - [7:4] */ 18196a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_DIV_SHIFT 4 /* AIF1_BCLK_DIV - [7:4] */ 18206a504a75SDimitris Papastamos #define WM8995_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [7:4] */ 18216a504a75SDimitris Papastamos 18226a504a75SDimitris Papastamos /* 18236a504a75SDimitris Papastamos * R772 (0x304) - AIF1ADC LRCLK 18246a504a75SDimitris Papastamos */ 18256a504a75SDimitris Papastamos #define WM8995_AIF1ADC_LRCLK_DIR 0x0800 /* AIF1ADC_LRCLK_DIR */ 18266a504a75SDimitris Papastamos #define WM8995_AIF1ADC_LRCLK_DIR_MASK 0x0800 /* AIF1ADC_LRCLK_DIR */ 18276a504a75SDimitris Papastamos #define WM8995_AIF1ADC_LRCLK_DIR_SHIFT 11 /* AIF1ADC_LRCLK_DIR */ 18286a504a75SDimitris Papastamos #define WM8995_AIF1ADC_LRCLK_DIR_WIDTH 1 /* AIF1ADC_LRCLK_DIR */ 18296a504a75SDimitris Papastamos #define WM8995_AIF1ADC_RATE_MASK 0x07FF /* AIF1ADC_RATE - [10:0] */ 18306a504a75SDimitris Papastamos #define WM8995_AIF1ADC_RATE_SHIFT 0 /* AIF1ADC_RATE - [10:0] */ 18316a504a75SDimitris Papastamos #define WM8995_AIF1ADC_RATE_WIDTH 11 /* AIF1ADC_RATE - [10:0] */ 18326a504a75SDimitris Papastamos 18336a504a75SDimitris Papastamos /* 18346a504a75SDimitris Papastamos * R773 (0x305) - AIF1DAC LRCLK 18356a504a75SDimitris Papastamos */ 18366a504a75SDimitris Papastamos #define WM8995_AIF1DAC_LRCLK_DIR 0x0800 /* AIF1DAC_LRCLK_DIR */ 18376a504a75SDimitris Papastamos #define WM8995_AIF1DAC_LRCLK_DIR_MASK 0x0800 /* AIF1DAC_LRCLK_DIR */ 18386a504a75SDimitris Papastamos #define WM8995_AIF1DAC_LRCLK_DIR_SHIFT 11 /* AIF1DAC_LRCLK_DIR */ 18396a504a75SDimitris Papastamos #define WM8995_AIF1DAC_LRCLK_DIR_WIDTH 1 /* AIF1DAC_LRCLK_DIR */ 18406a504a75SDimitris Papastamos #define WM8995_AIF1DAC_RATE_MASK 0x07FF /* AIF1DAC_RATE - [10:0] */ 18416a504a75SDimitris Papastamos #define WM8995_AIF1DAC_RATE_SHIFT 0 /* AIF1DAC_RATE - [10:0] */ 18426a504a75SDimitris Papastamos #define WM8995_AIF1DAC_RATE_WIDTH 11 /* AIF1DAC_RATE - [10:0] */ 18436a504a75SDimitris Papastamos 18446a504a75SDimitris Papastamos /* 18456a504a75SDimitris Papastamos * R774 (0x306) - AIF1DAC Data 18466a504a75SDimitris Papastamos */ 18476a504a75SDimitris Papastamos #define WM8995_AIF1DACL_DAT_INV 0x0002 /* AIF1DACL_DAT_INV */ 18486a504a75SDimitris Papastamos #define WM8995_AIF1DACL_DAT_INV_MASK 0x0002 /* AIF1DACL_DAT_INV */ 18496a504a75SDimitris Papastamos #define WM8995_AIF1DACL_DAT_INV_SHIFT 1 /* AIF1DACL_DAT_INV */ 18506a504a75SDimitris Papastamos #define WM8995_AIF1DACL_DAT_INV_WIDTH 1 /* AIF1DACL_DAT_INV */ 18516a504a75SDimitris Papastamos #define WM8995_AIF1DACR_DAT_INV 0x0001 /* AIF1DACR_DAT_INV */ 18526a504a75SDimitris Papastamos #define WM8995_AIF1DACR_DAT_INV_MASK 0x0001 /* AIF1DACR_DAT_INV */ 18536a504a75SDimitris Papastamos #define WM8995_AIF1DACR_DAT_INV_SHIFT 0 /* AIF1DACR_DAT_INV */ 18546a504a75SDimitris Papastamos #define WM8995_AIF1DACR_DAT_INV_WIDTH 1 /* AIF1DACR_DAT_INV */ 18556a504a75SDimitris Papastamos 18566a504a75SDimitris Papastamos /* 18576a504a75SDimitris Papastamos * R775 (0x307) - AIF1ADC Data 18586a504a75SDimitris Papastamos */ 18596a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_DAT_INV 0x0002 /* AIF1ADCL_DAT_INV */ 18606a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_DAT_INV_MASK 0x0002 /* AIF1ADCL_DAT_INV */ 18616a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_DAT_INV_SHIFT 1 /* AIF1ADCL_DAT_INV */ 18626a504a75SDimitris Papastamos #define WM8995_AIF1ADCL_DAT_INV_WIDTH 1 /* AIF1ADCL_DAT_INV */ 18636a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_DAT_INV 0x0001 /* AIF1ADCR_DAT_INV */ 18646a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_DAT_INV_MASK 0x0001 /* AIF1ADCR_DAT_INV */ 18656a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_DAT_INV_SHIFT 0 /* AIF1ADCR_DAT_INV */ 18666a504a75SDimitris Papastamos #define WM8995_AIF1ADCR_DAT_INV_WIDTH 1 /* AIF1ADCR_DAT_INV */ 18676a504a75SDimitris Papastamos 18686a504a75SDimitris Papastamos /* 18696a504a75SDimitris Papastamos * R784 (0x310) - AIF2 Control (1) 18706a504a75SDimitris Papastamos */ 18716a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_SRC 0x8000 /* AIF2ADCL_SRC */ 18726a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_SRC_MASK 0x8000 /* AIF2ADCL_SRC */ 18736a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_SRC_SHIFT 15 /* AIF2ADCL_SRC */ 18746a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_SRC_WIDTH 1 /* AIF2ADCL_SRC */ 18756a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_SRC 0x4000 /* AIF2ADCR_SRC */ 18766a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_SRC_MASK 0x4000 /* AIF2ADCR_SRC */ 18776a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_SRC_SHIFT 14 /* AIF2ADCR_SRC */ 18786a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_SRC_WIDTH 1 /* AIF2ADCR_SRC */ 18796a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM 0x2000 /* AIF2ADC_TDM */ 18806a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_MASK 0x2000 /* AIF2ADC_TDM */ 18816a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_SHIFT 13 /* AIF2ADC_TDM */ 18826a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_WIDTH 1 /* AIF2ADC_TDM */ 18836a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_CHAN 0x1000 /* AIF2ADC_TDM_CHAN */ 18846a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_CHAN_MASK 0x1000 /* AIF2ADC_TDM_CHAN */ 18856a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_CHAN_SHIFT 12 /* AIF2ADC_TDM_CHAN */ 18866a504a75SDimitris Papastamos #define WM8995_AIF2ADC_TDM_CHAN_WIDTH 1 /* AIF2ADC_TDM_CHAN */ 18876a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_INV 0x0100 /* AIF2_BCLK_INV */ 18886a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_INV_MASK 0x0100 /* AIF2_BCLK_INV */ 18896a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_INV_SHIFT 8 /* AIF2_BCLK_INV */ 18906a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 18916a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_INV 0x0080 /* AIF2_LRCLK_INV */ 18926a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_INV_MASK 0x0080 /* AIF2_LRCLK_INV */ 18936a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_INV_SHIFT 7 /* AIF2_LRCLK_INV */ 18946a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_INV_WIDTH 1 /* AIF2_LRCLK_INV */ 18956a504a75SDimitris Papastamos #define WM8995_AIF2_WL_MASK 0x0060 /* AIF2_WL - [6:5] */ 18966a504a75SDimitris Papastamos #define WM8995_AIF2_WL_SHIFT 5 /* AIF2_WL - [6:5] */ 18976a504a75SDimitris Papastamos #define WM8995_AIF2_WL_WIDTH 2 /* AIF2_WL - [6:5] */ 18986a504a75SDimitris Papastamos #define WM8995_AIF2_FMT_MASK 0x0018 /* AIF2_FMT - [4:3] */ 18996a504a75SDimitris Papastamos #define WM8995_AIF2_FMT_SHIFT 3 /* AIF2_FMT - [4:3] */ 19006a504a75SDimitris Papastamos #define WM8995_AIF2_FMT_WIDTH 2 /* AIF2_FMT - [4:3] */ 19016a504a75SDimitris Papastamos 19026a504a75SDimitris Papastamos /* 19036a504a75SDimitris Papastamos * R785 (0x311) - AIF2 Control (2) 19046a504a75SDimitris Papastamos */ 19056a504a75SDimitris Papastamos #define WM8995_AIF2DACL_SRC 0x8000 /* AIF2DACL_SRC */ 19066a504a75SDimitris Papastamos #define WM8995_AIF2DACL_SRC_MASK 0x8000 /* AIF2DACL_SRC */ 19076a504a75SDimitris Papastamos #define WM8995_AIF2DACL_SRC_SHIFT 15 /* AIF2DACL_SRC */ 19086a504a75SDimitris Papastamos #define WM8995_AIF2DACL_SRC_WIDTH 1 /* AIF2DACL_SRC */ 19096a504a75SDimitris Papastamos #define WM8995_AIF2DACR_SRC 0x4000 /* AIF2DACR_SRC */ 19106a504a75SDimitris Papastamos #define WM8995_AIF2DACR_SRC_MASK 0x4000 /* AIF2DACR_SRC */ 19116a504a75SDimitris Papastamos #define WM8995_AIF2DACR_SRC_SHIFT 14 /* AIF2DACR_SRC */ 19126a504a75SDimitris Papastamos #define WM8995_AIF2DACR_SRC_WIDTH 1 /* AIF2DACR_SRC */ 19136a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM 0x2000 /* AIF2DAC_TDM */ 19146a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_MASK 0x2000 /* AIF2DAC_TDM */ 19156a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_SHIFT 13 /* AIF2DAC_TDM */ 19166a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_WIDTH 1 /* AIF2DAC_TDM */ 19176a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_CHAN 0x1000 /* AIF2DAC_TDM_CHAN */ 19186a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_CHAN_MASK 0x1000 /* AIF2DAC_TDM_CHAN */ 19196a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_CHAN_SHIFT 12 /* AIF2DAC_TDM_CHAN */ 19206a504a75SDimitris Papastamos #define WM8995_AIF2DAC_TDM_CHAN_WIDTH 1 /* AIF2DAC_TDM_CHAN */ 19216a504a75SDimitris Papastamos #define WM8995_AIF2DAC_BOOST_MASK 0x0C00 /* AIF2DAC_BOOST - [11:10] */ 19226a504a75SDimitris Papastamos #define WM8995_AIF2DAC_BOOST_SHIFT 10 /* AIF2DAC_BOOST - [11:10] */ 19236a504a75SDimitris Papastamos #define WM8995_AIF2DAC_BOOST_WIDTH 2 /* AIF2DAC_BOOST - [11:10] */ 19246a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMP 0x0010 /* AIF2DAC_COMP */ 19256a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMP_MASK 0x0010 /* AIF2DAC_COMP */ 19266a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMP_SHIFT 4 /* AIF2DAC_COMP */ 19276a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMP_WIDTH 1 /* AIF2DAC_COMP */ 19286a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMPMODE 0x0008 /* AIF2DAC_COMPMODE */ 19296a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMPMODE_MASK 0x0008 /* AIF2DAC_COMPMODE */ 19306a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMPMODE_SHIFT 3 /* AIF2DAC_COMPMODE */ 19316a504a75SDimitris Papastamos #define WM8995_AIF2DAC_COMPMODE_WIDTH 1 /* AIF2DAC_COMPMODE */ 19326a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMP 0x0004 /* AIF2ADC_COMP */ 19336a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMP_MASK 0x0004 /* AIF2ADC_COMP */ 19346a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMP_SHIFT 2 /* AIF2ADC_COMP */ 19356a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMP_WIDTH 1 /* AIF2ADC_COMP */ 19366a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMPMODE 0x0002 /* AIF2ADC_COMPMODE */ 19376a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMPMODE_MASK 0x0002 /* AIF2ADC_COMPMODE */ 19386a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMPMODE_SHIFT 1 /* AIF2ADC_COMPMODE */ 19396a504a75SDimitris Papastamos #define WM8995_AIF2ADC_COMPMODE_WIDTH 1 /* AIF2ADC_COMPMODE */ 19406a504a75SDimitris Papastamos #define WM8995_AIF2_LOOPBACK 0x0001 /* AIF2_LOOPBACK */ 19416a504a75SDimitris Papastamos #define WM8995_AIF2_LOOPBACK_MASK 0x0001 /* AIF2_LOOPBACK */ 19426a504a75SDimitris Papastamos #define WM8995_AIF2_LOOPBACK_SHIFT 0 /* AIF2_LOOPBACK */ 19436a504a75SDimitris Papastamos #define WM8995_AIF2_LOOPBACK_WIDTH 1 /* AIF2_LOOPBACK */ 19446a504a75SDimitris Papastamos 19456a504a75SDimitris Papastamos /* 19466a504a75SDimitris Papastamos * R786 (0x312) - AIF2 Master/Slave 19476a504a75SDimitris Papastamos */ 19486a504a75SDimitris Papastamos #define WM8995_AIF2_TRI 0x8000 /* AIF2_TRI */ 19496a504a75SDimitris Papastamos #define WM8995_AIF2_TRI_MASK 0x8000 /* AIF2_TRI */ 19506a504a75SDimitris Papastamos #define WM8995_AIF2_TRI_SHIFT 15 /* AIF2_TRI */ 19516a504a75SDimitris Papastamos #define WM8995_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 19526a504a75SDimitris Papastamos #define WM8995_AIF2_MSTR 0x4000 /* AIF2_MSTR */ 19536a504a75SDimitris Papastamos #define WM8995_AIF2_MSTR_MASK 0x4000 /* AIF2_MSTR */ 19546a504a75SDimitris Papastamos #define WM8995_AIF2_MSTR_SHIFT 14 /* AIF2_MSTR */ 19556a504a75SDimitris Papastamos #define WM8995_AIF2_MSTR_WIDTH 1 /* AIF2_MSTR */ 19566a504a75SDimitris Papastamos #define WM8995_AIF2_CLK_FRC 0x2000 /* AIF2_CLK_FRC */ 19576a504a75SDimitris Papastamos #define WM8995_AIF2_CLK_FRC_MASK 0x2000 /* AIF2_CLK_FRC */ 19586a504a75SDimitris Papastamos #define WM8995_AIF2_CLK_FRC_SHIFT 13 /* AIF2_CLK_FRC */ 19596a504a75SDimitris Papastamos #define WM8995_AIF2_CLK_FRC_WIDTH 1 /* AIF2_CLK_FRC */ 19606a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_FRC 0x1000 /* AIF2_LRCLK_FRC */ 19616a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_FRC_MASK 0x1000 /* AIF2_LRCLK_FRC */ 19626a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_FRC_SHIFT 12 /* AIF2_LRCLK_FRC */ 19636a504a75SDimitris Papastamos #define WM8995_AIF2_LRCLK_FRC_WIDTH 1 /* AIF2_LRCLK_FRC */ 19646a504a75SDimitris Papastamos 19656a504a75SDimitris Papastamos /* 19666a504a75SDimitris Papastamos * R787 (0x313) - AIF2 BCLK 19676a504a75SDimitris Papastamos */ 19686a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_DIV_MASK 0x00F0 /* AIF2_BCLK_DIV - [7:4] */ 19696a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_DIV_SHIFT 4 /* AIF2_BCLK_DIV - [7:4] */ 19706a504a75SDimitris Papastamos #define WM8995_AIF2_BCLK_DIV_WIDTH 4 /* AIF2_BCLK_DIV - [7:4] */ 19716a504a75SDimitris Papastamos 19726a504a75SDimitris Papastamos /* 19736a504a75SDimitris Papastamos * R788 (0x314) - AIF2ADC LRCLK 19746a504a75SDimitris Papastamos */ 19756a504a75SDimitris Papastamos #define WM8995_AIF2ADC_LRCLK_DIR 0x0800 /* AIF2ADC_LRCLK_DIR */ 19766a504a75SDimitris Papastamos #define WM8995_AIF2ADC_LRCLK_DIR_MASK 0x0800 /* AIF2ADC_LRCLK_DIR */ 19776a504a75SDimitris Papastamos #define WM8995_AIF2ADC_LRCLK_DIR_SHIFT 11 /* AIF2ADC_LRCLK_DIR */ 19786a504a75SDimitris Papastamos #define WM8995_AIF2ADC_LRCLK_DIR_WIDTH 1 /* AIF2ADC_LRCLK_DIR */ 19796a504a75SDimitris Papastamos #define WM8995_AIF2ADC_RATE_MASK 0x07FF /* AIF2ADC_RATE - [10:0] */ 19806a504a75SDimitris Papastamos #define WM8995_AIF2ADC_RATE_SHIFT 0 /* AIF2ADC_RATE - [10:0] */ 19816a504a75SDimitris Papastamos #define WM8995_AIF2ADC_RATE_WIDTH 11 /* AIF2ADC_RATE - [10:0] */ 19826a504a75SDimitris Papastamos 19836a504a75SDimitris Papastamos /* 19846a504a75SDimitris Papastamos * R789 (0x315) - AIF2DAC LRCLK 19856a504a75SDimitris Papastamos */ 19866a504a75SDimitris Papastamos #define WM8995_AIF2DAC_LRCLK_DIR 0x0800 /* AIF2DAC_LRCLK_DIR */ 19876a504a75SDimitris Papastamos #define WM8995_AIF2DAC_LRCLK_DIR_MASK 0x0800 /* AIF2DAC_LRCLK_DIR */ 19886a504a75SDimitris Papastamos #define WM8995_AIF2DAC_LRCLK_DIR_SHIFT 11 /* AIF2DAC_LRCLK_DIR */ 19896a504a75SDimitris Papastamos #define WM8995_AIF2DAC_LRCLK_DIR_WIDTH 1 /* AIF2DAC_LRCLK_DIR */ 19906a504a75SDimitris Papastamos #define WM8995_AIF2DAC_RATE_MASK 0x07FF /* AIF2DAC_RATE - [10:0] */ 19916a504a75SDimitris Papastamos #define WM8995_AIF2DAC_RATE_SHIFT 0 /* AIF2DAC_RATE - [10:0] */ 19926a504a75SDimitris Papastamos #define WM8995_AIF2DAC_RATE_WIDTH 11 /* AIF2DAC_RATE - [10:0] */ 19936a504a75SDimitris Papastamos 19946a504a75SDimitris Papastamos /* 19956a504a75SDimitris Papastamos * R790 (0x316) - AIF2DAC Data 19966a504a75SDimitris Papastamos */ 19976a504a75SDimitris Papastamos #define WM8995_AIF2DACL_DAT_INV 0x0002 /* AIF2DACL_DAT_INV */ 19986a504a75SDimitris Papastamos #define WM8995_AIF2DACL_DAT_INV_MASK 0x0002 /* AIF2DACL_DAT_INV */ 19996a504a75SDimitris Papastamos #define WM8995_AIF2DACL_DAT_INV_SHIFT 1 /* AIF2DACL_DAT_INV */ 20006a504a75SDimitris Papastamos #define WM8995_AIF2DACL_DAT_INV_WIDTH 1 /* AIF2DACL_DAT_INV */ 20016a504a75SDimitris Papastamos #define WM8995_AIF2DACR_DAT_INV 0x0001 /* AIF2DACR_DAT_INV */ 20026a504a75SDimitris Papastamos #define WM8995_AIF2DACR_DAT_INV_MASK 0x0001 /* AIF2DACR_DAT_INV */ 20036a504a75SDimitris Papastamos #define WM8995_AIF2DACR_DAT_INV_SHIFT 0 /* AIF2DACR_DAT_INV */ 20046a504a75SDimitris Papastamos #define WM8995_AIF2DACR_DAT_INV_WIDTH 1 /* AIF2DACR_DAT_INV */ 20056a504a75SDimitris Papastamos 20066a504a75SDimitris Papastamos /* 20076a504a75SDimitris Papastamos * R791 (0x317) - AIF2ADC Data 20086a504a75SDimitris Papastamos */ 20096a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DAT_INV 0x0002 /* AIF2ADCL_DAT_INV */ 20106a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DAT_INV_MASK 0x0002 /* AIF2ADCL_DAT_INV */ 20116a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DAT_INV_SHIFT 1 /* AIF2ADCL_DAT_INV */ 20126a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DAT_INV_WIDTH 1 /* AIF2ADCL_DAT_INV */ 20136a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DAT_INV 0x0001 /* AIF2ADCR_DAT_INV */ 20146a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DAT_INV_MASK 0x0001 /* AIF2ADCR_DAT_INV */ 20156a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */ 20166a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */ 20176a504a75SDimitris Papastamos 20186a504a75SDimitris Papastamos /* 20196a504a75SDimitris Papastamos * R1024 (0x400) - AIF1 ADC1 Left Volume 20206a504a75SDimitris Papastamos */ 20216a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 20226a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 20236a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 20246a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 20256a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_VOL_MASK 0x00FF /* AIF1ADC1L_VOL - [7:0] */ 20266a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_VOL_SHIFT 0 /* AIF1ADC1L_VOL - [7:0] */ 20276a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_VOL_WIDTH 8 /* AIF1ADC1L_VOL - [7:0] */ 20286a504a75SDimitris Papastamos 20296a504a75SDimitris Papastamos /* 20306a504a75SDimitris Papastamos * R1025 (0x401) - AIF1 ADC1 Right Volume 20316a504a75SDimitris Papastamos */ 20326a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU 0x0100 /* AIF1ADC1_VU */ 20336a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_MASK 0x0100 /* AIF1ADC1_VU */ 20346a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_SHIFT 8 /* AIF1ADC1_VU */ 20356a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_VU_WIDTH 1 /* AIF1ADC1_VU */ 20366a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_VOL_MASK 0x00FF /* AIF1ADC1R_VOL - [7:0] */ 20376a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_VOL_SHIFT 0 /* AIF1ADC1R_VOL - [7:0] */ 20386a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_VOL_WIDTH 8 /* AIF1ADC1R_VOL - [7:0] */ 20396a504a75SDimitris Papastamos 20406a504a75SDimitris Papastamos /* 20416a504a75SDimitris Papastamos * R1026 (0x402) - AIF1 DAC1 Left Volume 20426a504a75SDimitris Papastamos */ 20436a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 20446a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 20456a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 20466a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 20476a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_VOL_MASK 0x00FF /* AIF1DAC1L_VOL - [7:0] */ 20486a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_VOL_SHIFT 0 /* AIF1DAC1L_VOL - [7:0] */ 20496a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_VOL_WIDTH 8 /* AIF1DAC1L_VOL - [7:0] */ 20506a504a75SDimitris Papastamos 20516a504a75SDimitris Papastamos /* 20526a504a75SDimitris Papastamos * R1027 (0x403) - AIF1 DAC1 Right Volume 20536a504a75SDimitris Papastamos */ 20546a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU 0x0100 /* AIF1DAC1_VU */ 20556a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_MASK 0x0100 /* AIF1DAC1_VU */ 20566a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_SHIFT 8 /* AIF1DAC1_VU */ 20576a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_VU_WIDTH 1 /* AIF1DAC1_VU */ 20586a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_VOL_MASK 0x00FF /* AIF1DAC1R_VOL - [7:0] */ 20596a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_VOL_SHIFT 0 /* AIF1DAC1R_VOL - [7:0] */ 20606a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_VOL_WIDTH 8 /* AIF1DAC1R_VOL - [7:0] */ 20616a504a75SDimitris Papastamos 20626a504a75SDimitris Papastamos /* 20636a504a75SDimitris Papastamos * R1028 (0x404) - AIF1 ADC2 Left Volume 20646a504a75SDimitris Papastamos */ 20656a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 20666a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 20676a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 20686a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 20696a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_VOL_MASK 0x00FF /* AIF1ADC2L_VOL - [7:0] */ 20706a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_VOL_SHIFT 0 /* AIF1ADC2L_VOL - [7:0] */ 20716a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_VOL_WIDTH 8 /* AIF1ADC2L_VOL - [7:0] */ 20726a504a75SDimitris Papastamos 20736a504a75SDimitris Papastamos /* 20746a504a75SDimitris Papastamos * R1029 (0x405) - AIF1 ADC2 Right Volume 20756a504a75SDimitris Papastamos */ 20766a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU 0x0100 /* AIF1ADC2_VU */ 20776a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_MASK 0x0100 /* AIF1ADC2_VU */ 20786a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_SHIFT 8 /* AIF1ADC2_VU */ 20796a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_VU_WIDTH 1 /* AIF1ADC2_VU */ 20806a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_VOL_MASK 0x00FF /* AIF1ADC2R_VOL - [7:0] */ 20816a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_VOL_SHIFT 0 /* AIF1ADC2R_VOL - [7:0] */ 20826a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_VOL_WIDTH 8 /* AIF1ADC2R_VOL - [7:0] */ 20836a504a75SDimitris Papastamos 20846a504a75SDimitris Papastamos /* 20856a504a75SDimitris Papastamos * R1030 (0x406) - AIF1 DAC2 Left Volume 20866a504a75SDimitris Papastamos */ 20876a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 20886a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 20896a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 20906a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 20916a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_VOL_MASK 0x00FF /* AIF1DAC2L_VOL - [7:0] */ 20926a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_VOL_SHIFT 0 /* AIF1DAC2L_VOL - [7:0] */ 20936a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_VOL_WIDTH 8 /* AIF1DAC2L_VOL - [7:0] */ 20946a504a75SDimitris Papastamos 20956a504a75SDimitris Papastamos /* 20966a504a75SDimitris Papastamos * R1031 (0x407) - AIF1 DAC2 Right Volume 20976a504a75SDimitris Papastamos */ 20986a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU 0x0100 /* AIF1DAC2_VU */ 20996a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_MASK 0x0100 /* AIF1DAC2_VU */ 21006a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_SHIFT 8 /* AIF1DAC2_VU */ 21016a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_VU_WIDTH 1 /* AIF1DAC2_VU */ 21026a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_VOL_MASK 0x00FF /* AIF1DAC2R_VOL - [7:0] */ 21036a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_VOL_SHIFT 0 /* AIF1DAC2R_VOL - [7:0] */ 21046a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_VOL_WIDTH 8 /* AIF1DAC2R_VOL - [7:0] */ 21056a504a75SDimitris Papastamos 21066a504a75SDimitris Papastamos /* 21076a504a75SDimitris Papastamos * R1040 (0x410) - AIF1 ADC1 Filters 21086a504a75SDimitris Papastamos */ 21096a504a75SDimitris Papastamos #define WM8995_AIF1ADC_4FS 0x8000 /* AIF1ADC_4FS */ 21106a504a75SDimitris Papastamos #define WM8995_AIF1ADC_4FS_MASK 0x8000 /* AIF1ADC_4FS */ 21116a504a75SDimitris Papastamos #define WM8995_AIF1ADC_4FS_SHIFT 15 /* AIF1ADC_4FS */ 21126a504a75SDimitris Papastamos #define WM8995_AIF1ADC_4FS_WIDTH 1 /* AIF1ADC_4FS */ 21136a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_HPF 0x1000 /* AIF1ADC1L_HPF */ 21146a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_HPF_MASK 0x1000 /* AIF1ADC1L_HPF */ 21156a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_HPF_SHIFT 12 /* AIF1ADC1L_HPF */ 21166a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_HPF_WIDTH 1 /* AIF1ADC1L_HPF */ 21176a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_HPF 0x0800 /* AIF1ADC1R_HPF */ 21186a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_HPF_MASK 0x0800 /* AIF1ADC1R_HPF */ 21196a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_HPF_SHIFT 11 /* AIF1ADC1R_HPF */ 21206a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_HPF_WIDTH 1 /* AIF1ADC1R_HPF */ 21216a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_MODE 0x0008 /* AIF1ADC1_HPF_MODE */ 21226a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_MODE_MASK 0x0008 /* AIF1ADC1_HPF_MODE */ 21236a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_MODE_SHIFT 3 /* AIF1ADC1_HPF_MODE */ 21246a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_MODE_WIDTH 1 /* AIF1ADC1_HPF_MODE */ 21256a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_CUT_MASK 0x0007 /* AIF1ADC1_HPF_CUT - [2:0] */ 21266a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_CUT_SHIFT 0 /* AIF1ADC1_HPF_CUT - [2:0] */ 21276a504a75SDimitris Papastamos #define WM8995_AIF1ADC1_HPF_CUT_WIDTH 3 /* AIF1ADC1_HPF_CUT - [2:0] */ 21286a504a75SDimitris Papastamos 21296a504a75SDimitris Papastamos /* 21306a504a75SDimitris Papastamos * R1041 (0x411) - AIF1 ADC2 Filters 21316a504a75SDimitris Papastamos */ 21326a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_HPF 0x1000 /* AIF1ADC2L_HPF */ 21336a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_HPF_MASK 0x1000 /* AIF1ADC2L_HPF */ 21346a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_HPF_SHIFT 12 /* AIF1ADC2L_HPF */ 21356a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_HPF_WIDTH 1 /* AIF1ADC2L_HPF */ 21366a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_HPF 0x0800 /* AIF1ADC2R_HPF */ 21376a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_HPF_MASK 0x0800 /* AIF1ADC2R_HPF */ 21386a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_HPF_SHIFT 11 /* AIF1ADC2R_HPF */ 21396a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_HPF_WIDTH 1 /* AIF1ADC2R_HPF */ 21406a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_MODE 0x0008 /* AIF1ADC2_HPF_MODE */ 21416a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_MODE_MASK 0x0008 /* AIF1ADC2_HPF_MODE */ 21426a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_MODE_SHIFT 3 /* AIF1ADC2_HPF_MODE */ 21436a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_MODE_WIDTH 1 /* AIF1ADC2_HPF_MODE */ 21446a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_CUT_MASK 0x0007 /* AIF1ADC2_HPF_CUT - [2:0] */ 21456a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_CUT_SHIFT 0 /* AIF1ADC2_HPF_CUT - [2:0] */ 21466a504a75SDimitris Papastamos #define WM8995_AIF1ADC2_HPF_CUT_WIDTH 3 /* AIF1ADC2_HPF_CUT - [2:0] */ 21476a504a75SDimitris Papastamos 21486a504a75SDimitris Papastamos /* 21496a504a75SDimitris Papastamos * R1056 (0x420) - AIF1 DAC1 Filters (1) 21506a504a75SDimitris Papastamos */ 21516a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTE 0x0200 /* AIF1DAC1_MUTE */ 21526a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTE_MASK 0x0200 /* AIF1DAC1_MUTE */ 21536a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTE_SHIFT 9 /* AIF1DAC1_MUTE */ 21546a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTE_WIDTH 1 /* AIF1DAC1_MUTE */ 21556a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MONO 0x0080 /* AIF1DAC1_MONO */ 21566a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MONO_MASK 0x0080 /* AIF1DAC1_MONO */ 21576a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MONO_SHIFT 7 /* AIF1DAC1_MONO */ 21586a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MONO_WIDTH 1 /* AIF1DAC1_MONO */ 21596a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTERATE 0x0020 /* AIF1DAC1_MUTERATE */ 21606a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTERATE_MASK 0x0020 /* AIF1DAC1_MUTERATE */ 21616a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTERATE_SHIFT 5 /* AIF1DAC1_MUTERATE */ 21626a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_MUTERATE_WIDTH 1 /* AIF1DAC1_MUTERATE */ 21636a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_UNMUTE_RAMP 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 21646a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC1_UNMUTE_RAMP */ 21656a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC1_UNMUTE_RAMP */ 21666a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC1_UNMUTE_RAMP */ 21676a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DEEMP_MASK 0x0006 /* AIF1DAC1_DEEMP - [2:1] */ 21686a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DEEMP_SHIFT 1 /* AIF1DAC1_DEEMP - [2:1] */ 21696a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DEEMP_WIDTH 2 /* AIF1DAC1_DEEMP - [2:1] */ 21706a504a75SDimitris Papastamos 21716a504a75SDimitris Papastamos /* 21726a504a75SDimitris Papastamos * R1057 (0x421) - AIF1 DAC1 Filters (2) 21736a504a75SDimitris Papastamos */ 21746a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_GAIN_MASK 0x3E00 /* AIF1DAC1_3D_GAIN - [13:9] */ 21756a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_GAIN_SHIFT 9 /* AIF1DAC1_3D_GAIN - [13:9] */ 21766a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_GAIN_WIDTH 5 /* AIF1DAC1_3D_GAIN - [13:9] */ 21776a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_ENA 0x0100 /* AIF1DAC1_3D_ENA */ 21786a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_ENA_MASK 0x0100 /* AIF1DAC1_3D_ENA */ 21796a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_ENA_SHIFT 8 /* AIF1DAC1_3D_ENA */ 21806a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_3D_ENA_WIDTH 1 /* AIF1DAC1_3D_ENA */ 21816a504a75SDimitris Papastamos 21826a504a75SDimitris Papastamos /* 21836a504a75SDimitris Papastamos * R1058 (0x422) - AIF1 DAC2 Filters (1) 21846a504a75SDimitris Papastamos */ 21856a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTE 0x0200 /* AIF1DAC2_MUTE */ 21866a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTE_MASK 0x0200 /* AIF1DAC2_MUTE */ 21876a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTE_SHIFT 9 /* AIF1DAC2_MUTE */ 21886a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTE_WIDTH 1 /* AIF1DAC2_MUTE */ 21896a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MONO 0x0080 /* AIF1DAC2_MONO */ 21906a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MONO_MASK 0x0080 /* AIF1DAC2_MONO */ 21916a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MONO_SHIFT 7 /* AIF1DAC2_MONO */ 21926a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MONO_WIDTH 1 /* AIF1DAC2_MONO */ 21936a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTERATE 0x0020 /* AIF1DAC2_MUTERATE */ 21946a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTERATE_MASK 0x0020 /* AIF1DAC2_MUTERATE */ 21956a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTERATE_SHIFT 5 /* AIF1DAC2_MUTERATE */ 21966a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_MUTERATE_WIDTH 1 /* AIF1DAC2_MUTERATE */ 21976a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_UNMUTE_RAMP 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 21986a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_UNMUTE_RAMP_MASK 0x0010 /* AIF1DAC2_UNMUTE_RAMP */ 21996a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_UNMUTE_RAMP_SHIFT 4 /* AIF1DAC2_UNMUTE_RAMP */ 22006a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_UNMUTE_RAMP_WIDTH 1 /* AIF1DAC2_UNMUTE_RAMP */ 22016a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DEEMP_MASK 0x0006 /* AIF1DAC2_DEEMP - [2:1] */ 22026a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DEEMP_SHIFT 1 /* AIF1DAC2_DEEMP - [2:1] */ 22036a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DEEMP_WIDTH 2 /* AIF1DAC2_DEEMP - [2:1] */ 22046a504a75SDimitris Papastamos 22056a504a75SDimitris Papastamos /* 22066a504a75SDimitris Papastamos * R1059 (0x423) - AIF1 DAC2 Filters (2) 22076a504a75SDimitris Papastamos */ 22086a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_GAIN_MASK 0x3E00 /* AIF1DAC2_3D_GAIN - [13:9] */ 22096a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_GAIN_SHIFT 9 /* AIF1DAC2_3D_GAIN - [13:9] */ 22106a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_GAIN_WIDTH 5 /* AIF1DAC2_3D_GAIN - [13:9] */ 22116a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_ENA 0x0100 /* AIF1DAC2_3D_ENA */ 22126a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_ENA_MASK 0x0100 /* AIF1DAC2_3D_ENA */ 22136a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */ 22146a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */ 22156a504a75SDimitris Papastamos 22166a504a75SDimitris Papastamos /* 22176a504a75SDimitris Papastamos * R1088 (0x440) - AIF1 DRC1 (1) 22186a504a75SDimitris Papastamos */ 22196a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 22206a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_RMS_SHIFT 11 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 22216a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_RMS_WIDTH 5 /* AIF1DRC1_SIG_DET_RMS - [15:11] */ 22226a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_PK_MASK 0x0600 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 22236a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_PK_SHIFT 9 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 22246a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_PK_WIDTH 2 /* AIF1DRC1_SIG_DET_PK - [10:9] */ 22256a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_ENA 0x0100 /* AIF1DRC1_NG_ENA */ 22266a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_ENA_MASK 0x0100 /* AIF1DRC1_NG_ENA */ 22276a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_ENA_SHIFT 8 /* AIF1DRC1_NG_ENA */ 22286a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_ENA_WIDTH 1 /* AIF1DRC1_NG_ENA */ 22296a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_MODE 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 22306a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC1_SIG_DET_MODE */ 22316a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_MODE_SHIFT 7 /* AIF1DRC1_SIG_DET_MODE */ 22326a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_MODE_WIDTH 1 /* AIF1DRC1_SIG_DET_MODE */ 22336a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET 0x0040 /* AIF1DRC1_SIG_DET */ 22346a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_MASK 0x0040 /* AIF1DRC1_SIG_DET */ 22356a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_SHIFT 6 /* AIF1DRC1_SIG_DET */ 22366a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_WIDTH 1 /* AIF1DRC1_SIG_DET */ 22376a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_ENA 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 22386a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC1_KNEE2_OP_ENA */ 22396a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC1_KNEE2_OP_ENA */ 22406a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC1_KNEE2_OP_ENA */ 22416a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR 0x0010 /* AIF1DRC1_QR */ 22426a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_MASK 0x0010 /* AIF1DRC1_QR */ 22436a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_SHIFT 4 /* AIF1DRC1_QR */ 22446a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_WIDTH 1 /* AIF1DRC1_QR */ 22456a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ANTICLIP 0x0008 /* AIF1DRC1_ANTICLIP */ 22466a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ANTICLIP_MASK 0x0008 /* AIF1DRC1_ANTICLIP */ 22476a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ANTICLIP_SHIFT 3 /* AIF1DRC1_ANTICLIP */ 22486a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ANTICLIP_WIDTH 1 /* AIF1DRC1_ANTICLIP */ 22496a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DRC_ENA 0x0004 /* AIF1DAC1_DRC_ENA */ 22506a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DRC_ENA_MASK 0x0004 /* AIF1DAC1_DRC_ENA */ 22516a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DRC_ENA_SHIFT 2 /* AIF1DAC1_DRC_ENA */ 22526a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_DRC_ENA_WIDTH 1 /* AIF1DAC1_DRC_ENA */ 22536a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_DRC_ENA 0x0002 /* AIF1ADC1L_DRC_ENA */ 22546a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_DRC_ENA_MASK 0x0002 /* AIF1ADC1L_DRC_ENA */ 22556a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_DRC_ENA_SHIFT 1 /* AIF1ADC1L_DRC_ENA */ 22566a504a75SDimitris Papastamos #define WM8995_AIF1ADC1L_DRC_ENA_WIDTH 1 /* AIF1ADC1L_DRC_ENA */ 22576a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_DRC_ENA 0x0001 /* AIF1ADC1R_DRC_ENA */ 22586a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_DRC_ENA_MASK 0x0001 /* AIF1ADC1R_DRC_ENA */ 22596a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_DRC_ENA_SHIFT 0 /* AIF1ADC1R_DRC_ENA */ 22606a504a75SDimitris Papastamos #define WM8995_AIF1ADC1R_DRC_ENA_WIDTH 1 /* AIF1ADC1R_DRC_ENA */ 22616a504a75SDimitris Papastamos 22626a504a75SDimitris Papastamos /* 22636a504a75SDimitris Papastamos * R1089 (0x441) - AIF1 DRC1 (2) 22646a504a75SDimitris Papastamos */ 22656a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ATK_MASK 0x1E00 /* AIF1DRC1_ATK - [12:9] */ 22666a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ATK_SHIFT 9 /* AIF1DRC1_ATK - [12:9] */ 22676a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_ATK_WIDTH 4 /* AIF1DRC1_ATK - [12:9] */ 22686a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_DCY_MASK 0x01E0 /* AIF1DRC1_DCY - [8:5] */ 22696a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_DCY_SHIFT 5 /* AIF1DRC1_DCY - [8:5] */ 22706a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_DCY_WIDTH 4 /* AIF1DRC1_DCY - [8:5] */ 22716a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MINGAIN_MASK 0x001C /* AIF1DRC1_MINGAIN - [4:2] */ 22726a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MINGAIN_SHIFT 2 /* AIF1DRC1_MINGAIN - [4:2] */ 22736a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MINGAIN_WIDTH 3 /* AIF1DRC1_MINGAIN - [4:2] */ 22746a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MAXGAIN_MASK 0x0003 /* AIF1DRC1_MAXGAIN - [1:0] */ 22756a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MAXGAIN_SHIFT 0 /* AIF1DRC1_MAXGAIN - [1:0] */ 22766a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_MAXGAIN_WIDTH 2 /* AIF1DRC1_MAXGAIN - [1:0] */ 22776a504a75SDimitris Papastamos 22786a504a75SDimitris Papastamos /* 22796a504a75SDimitris Papastamos * R1090 (0x442) - AIF1 DRC1 (3) 22806a504a75SDimitris Papastamos */ 22816a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_MINGAIN_MASK 0xF000 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 22826a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_MINGAIN_SHIFT 12 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 22836a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_MINGAIN_WIDTH 4 /* AIF1DRC1_NG_MINGAIN - [15:12] */ 22846a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_EXP_MASK 0x0C00 /* AIF1DRC1_NG_EXP - [11:10] */ 22856a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_EXP_SHIFT 10 /* AIF1DRC1_NG_EXP - [11:10] */ 22866a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_NG_EXP_WIDTH 2 /* AIF1DRC1_NG_EXP - [11:10] */ 22876a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_THR_MASK 0x0300 /* AIF1DRC1_QR_THR - [9:8] */ 22886a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_THR_SHIFT 8 /* AIF1DRC1_QR_THR - [9:8] */ 22896a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_THR_WIDTH 2 /* AIF1DRC1_QR_THR - [9:8] */ 22906a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_DCY_MASK 0x00C0 /* AIF1DRC1_QR_DCY - [7:6] */ 22916a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_DCY_SHIFT 6 /* AIF1DRC1_QR_DCY - [7:6] */ 22926a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_QR_DCY_WIDTH 2 /* AIF1DRC1_QR_DCY - [7:6] */ 22936a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_HI_COMP_MASK 0x0038 /* AIF1DRC1_HI_COMP - [5:3] */ 22946a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_HI_COMP_SHIFT 3 /* AIF1DRC1_HI_COMP - [5:3] */ 22956a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_HI_COMP_WIDTH 3 /* AIF1DRC1_HI_COMP - [5:3] */ 22966a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_LO_COMP_MASK 0x0007 /* AIF1DRC1_LO_COMP - [2:0] */ 22976a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_LO_COMP_SHIFT 0 /* AIF1DRC1_LO_COMP - [2:0] */ 22986a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_LO_COMP_WIDTH 3 /* AIF1DRC1_LO_COMP - [2:0] */ 22996a504a75SDimitris Papastamos 23006a504a75SDimitris Papastamos /* 23016a504a75SDimitris Papastamos * R1091 (0x443) - AIF1 DRC1 (4) 23026a504a75SDimitris Papastamos */ 23036a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_IP_MASK 0x07E0 /* AIF1DRC1_KNEE_IP - [10:5] */ 23046a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_IP_SHIFT 5 /* AIF1DRC1_KNEE_IP - [10:5] */ 23056a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_IP_WIDTH 6 /* AIF1DRC1_KNEE_IP - [10:5] */ 23066a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_OP_MASK 0x001F /* AIF1DRC1_KNEE_OP - [4:0] */ 23076a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_OP_SHIFT 0 /* AIF1DRC1_KNEE_OP - [4:0] */ 23086a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE_OP_WIDTH 5 /* AIF1DRC1_KNEE_OP - [4:0] */ 23096a504a75SDimitris Papastamos 23106a504a75SDimitris Papastamos /* 23116a504a75SDimitris Papastamos * R1092 (0x444) - AIF1 DRC1 (5) 23126a504a75SDimitris Papastamos */ 23136a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_IP_MASK 0x03E0 /* AIF1DRC1_KNEE2_IP - [9:5] */ 23146a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_IP_SHIFT 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 23156a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_IP_WIDTH 5 /* AIF1DRC1_KNEE2_IP - [9:5] */ 23166a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_MASK 0x001F /* AIF1DRC1_KNEE2_OP - [4:0] */ 23176a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_SHIFT 0 /* AIF1DRC1_KNEE2_OP - [4:0] */ 23186a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_KNEE2_OP_WIDTH 5 /* AIF1DRC1_KNEE2_OP - [4:0] */ 23196a504a75SDimitris Papastamos 23206a504a75SDimitris Papastamos /* 23216a504a75SDimitris Papastamos * R1104 (0x450) - AIF1 DRC2 (1) 23226a504a75SDimitris Papastamos */ 23236a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_RMS_MASK 0xF800 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 23246a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_RMS_SHIFT 11 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 23256a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_RMS_WIDTH 5 /* AIF1DRC2_SIG_DET_RMS - [15:11] */ 23266a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_PK_MASK 0x0600 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 23276a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_PK_SHIFT 9 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 23286a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_PK_WIDTH 2 /* AIF1DRC2_SIG_DET_PK - [10:9] */ 23296a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_ENA 0x0100 /* AIF1DRC2_NG_ENA */ 23306a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_ENA_MASK 0x0100 /* AIF1DRC2_NG_ENA */ 23316a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_ENA_SHIFT 8 /* AIF1DRC2_NG_ENA */ 23326a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_ENA_WIDTH 1 /* AIF1DRC2_NG_ENA */ 23336a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_MODE 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 23346a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_MODE_MASK 0x0080 /* AIF1DRC2_SIG_DET_MODE */ 23356a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_MODE_SHIFT 7 /* AIF1DRC2_SIG_DET_MODE */ 23366a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_MODE_WIDTH 1 /* AIF1DRC2_SIG_DET_MODE */ 23376a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET 0x0040 /* AIF1DRC2_SIG_DET */ 23386a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_MASK 0x0040 /* AIF1DRC2_SIG_DET */ 23396a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_SHIFT 6 /* AIF1DRC2_SIG_DET */ 23406a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_WIDTH 1 /* AIF1DRC2_SIG_DET */ 23416a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_ENA 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 23426a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_ENA_MASK 0x0020 /* AIF1DRC2_KNEE2_OP_ENA */ 23436a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_ENA_SHIFT 5 /* AIF1DRC2_KNEE2_OP_ENA */ 23446a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_ENA_WIDTH 1 /* AIF1DRC2_KNEE2_OP_ENA */ 23456a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR 0x0010 /* AIF1DRC2_QR */ 23466a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_MASK 0x0010 /* AIF1DRC2_QR */ 23476a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_SHIFT 4 /* AIF1DRC2_QR */ 23486a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_WIDTH 1 /* AIF1DRC2_QR */ 23496a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ANTICLIP 0x0008 /* AIF1DRC2_ANTICLIP */ 23506a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ANTICLIP_MASK 0x0008 /* AIF1DRC2_ANTICLIP */ 23516a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ANTICLIP_SHIFT 3 /* AIF1DRC2_ANTICLIP */ 23526a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ANTICLIP_WIDTH 1 /* AIF1DRC2_ANTICLIP */ 23536a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DRC_ENA 0x0004 /* AIF1DAC2_DRC_ENA */ 23546a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DRC_ENA_MASK 0x0004 /* AIF1DAC2_DRC_ENA */ 23556a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DRC_ENA_SHIFT 2 /* AIF1DAC2_DRC_ENA */ 23566a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_DRC_ENA_WIDTH 1 /* AIF1DAC2_DRC_ENA */ 23576a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_DRC_ENA 0x0002 /* AIF1ADC2L_DRC_ENA */ 23586a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_DRC_ENA_MASK 0x0002 /* AIF1ADC2L_DRC_ENA */ 23596a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_DRC_ENA_SHIFT 1 /* AIF1ADC2L_DRC_ENA */ 23606a504a75SDimitris Papastamos #define WM8995_AIF1ADC2L_DRC_ENA_WIDTH 1 /* AIF1ADC2L_DRC_ENA */ 23616a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_DRC_ENA 0x0001 /* AIF1ADC2R_DRC_ENA */ 23626a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_DRC_ENA_MASK 0x0001 /* AIF1ADC2R_DRC_ENA */ 23636a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_DRC_ENA_SHIFT 0 /* AIF1ADC2R_DRC_ENA */ 23646a504a75SDimitris Papastamos #define WM8995_AIF1ADC2R_DRC_ENA_WIDTH 1 /* AIF1ADC2R_DRC_ENA */ 23656a504a75SDimitris Papastamos 23666a504a75SDimitris Papastamos /* 23676a504a75SDimitris Papastamos * R1105 (0x451) - AIF1 DRC2 (2) 23686a504a75SDimitris Papastamos */ 23696a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ATK_MASK 0x1E00 /* AIF1DRC2_ATK - [12:9] */ 23706a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ATK_SHIFT 9 /* AIF1DRC2_ATK - [12:9] */ 23716a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_ATK_WIDTH 4 /* AIF1DRC2_ATK - [12:9] */ 23726a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_DCY_MASK 0x01E0 /* AIF1DRC2_DCY - [8:5] */ 23736a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_DCY_SHIFT 5 /* AIF1DRC2_DCY - [8:5] */ 23746a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_DCY_WIDTH 4 /* AIF1DRC2_DCY - [8:5] */ 23756a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MINGAIN_MASK 0x001C /* AIF1DRC2_MINGAIN - [4:2] */ 23766a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MINGAIN_SHIFT 2 /* AIF1DRC2_MINGAIN - [4:2] */ 23776a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MINGAIN_WIDTH 3 /* AIF1DRC2_MINGAIN - [4:2] */ 23786a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MAXGAIN_MASK 0x0003 /* AIF1DRC2_MAXGAIN - [1:0] */ 23796a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MAXGAIN_SHIFT 0 /* AIF1DRC2_MAXGAIN - [1:0] */ 23806a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_MAXGAIN_WIDTH 2 /* AIF1DRC2_MAXGAIN - [1:0] */ 23816a504a75SDimitris Papastamos 23826a504a75SDimitris Papastamos /* 23836a504a75SDimitris Papastamos * R1106 (0x452) - AIF1 DRC2 (3) 23846a504a75SDimitris Papastamos */ 23856a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_MINGAIN_MASK 0xF000 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 23866a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_MINGAIN_SHIFT 12 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 23876a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_MINGAIN_WIDTH 4 /* AIF1DRC2_NG_MINGAIN - [15:12] */ 23886a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_EXP_MASK 0x0C00 /* AIF1DRC2_NG_EXP - [11:10] */ 23896a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_EXP_SHIFT 10 /* AIF1DRC2_NG_EXP - [11:10] */ 23906a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_NG_EXP_WIDTH 2 /* AIF1DRC2_NG_EXP - [11:10] */ 23916a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_THR_MASK 0x0300 /* AIF1DRC2_QR_THR - [9:8] */ 23926a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_THR_SHIFT 8 /* AIF1DRC2_QR_THR - [9:8] */ 23936a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_THR_WIDTH 2 /* AIF1DRC2_QR_THR - [9:8] */ 23946a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_DCY_MASK 0x00C0 /* AIF1DRC2_QR_DCY - [7:6] */ 23956a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_DCY_SHIFT 6 /* AIF1DRC2_QR_DCY - [7:6] */ 23966a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_QR_DCY_WIDTH 2 /* AIF1DRC2_QR_DCY - [7:6] */ 23976a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_HI_COMP_MASK 0x0038 /* AIF1DRC2_HI_COMP - [5:3] */ 23986a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_HI_COMP_SHIFT 3 /* AIF1DRC2_HI_COMP - [5:3] */ 23996a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_HI_COMP_WIDTH 3 /* AIF1DRC2_HI_COMP - [5:3] */ 24006a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_LO_COMP_MASK 0x0007 /* AIF1DRC2_LO_COMP - [2:0] */ 24016a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_LO_COMP_SHIFT 0 /* AIF1DRC2_LO_COMP - [2:0] */ 24026a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_LO_COMP_WIDTH 3 /* AIF1DRC2_LO_COMP - [2:0] */ 24036a504a75SDimitris Papastamos 24046a504a75SDimitris Papastamos /* 24056a504a75SDimitris Papastamos * R1107 (0x453) - AIF1 DRC2 (4) 24066a504a75SDimitris Papastamos */ 24076a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_IP_MASK 0x07E0 /* AIF1DRC2_KNEE_IP - [10:5] */ 24086a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_IP_SHIFT 5 /* AIF1DRC2_KNEE_IP - [10:5] */ 24096a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_IP_WIDTH 6 /* AIF1DRC2_KNEE_IP - [10:5] */ 24106a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_OP_MASK 0x001F /* AIF1DRC2_KNEE_OP - [4:0] */ 24116a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_OP_SHIFT 0 /* AIF1DRC2_KNEE_OP - [4:0] */ 24126a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE_OP_WIDTH 5 /* AIF1DRC2_KNEE_OP - [4:0] */ 24136a504a75SDimitris Papastamos 24146a504a75SDimitris Papastamos /* 24156a504a75SDimitris Papastamos * R1108 (0x454) - AIF1 DRC2 (5) 24166a504a75SDimitris Papastamos */ 24176a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_IP_MASK 0x03E0 /* AIF1DRC2_KNEE2_IP - [9:5] */ 24186a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_IP_SHIFT 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 24196a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_IP_WIDTH 5 /* AIF1DRC2_KNEE2_IP - [9:5] */ 24206a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_MASK 0x001F /* AIF1DRC2_KNEE2_OP - [4:0] */ 24216a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_SHIFT 0 /* AIF1DRC2_KNEE2_OP - [4:0] */ 24226a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_KNEE2_OP_WIDTH 5 /* AIF1DRC2_KNEE2_OP - [4:0] */ 24236a504a75SDimitris Papastamos 24246a504a75SDimitris Papastamos /* 24256a504a75SDimitris Papastamos * R1152 (0x480) - AIF1 DAC1 EQ Gains (1) 24266a504a75SDimitris Papastamos */ 24276a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 24286a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 24296a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B1_GAIN - [15:11] */ 24306a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 24316a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 24326a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B2_GAIN - [10:6] */ 24336a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 24346a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 24356a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B3_GAIN - [5:1] */ 24366a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_ENA 0x0001 /* AIF1DAC1_EQ_ENA */ 24376a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_ENA_MASK 0x0001 /* AIF1DAC1_EQ_ENA */ 24386a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_ENA_SHIFT 0 /* AIF1DAC1_EQ_ENA */ 24396a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_ENA_WIDTH 1 /* AIF1DAC1_EQ_ENA */ 24406a504a75SDimitris Papastamos 24416a504a75SDimitris Papastamos /* 24426a504a75SDimitris Papastamos * R1153 (0x481) - AIF1 DAC1 EQ Gains (2) 24436a504a75SDimitris Papastamos */ 24446a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 24456a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 24466a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B4_GAIN - [15:11] */ 24476a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 24486a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 24496a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC1_EQ_B5_GAIN - [10:6] */ 24506a504a75SDimitris Papastamos 24516a504a75SDimitris Papastamos /* 24526a504a75SDimitris Papastamos * R1154 (0x482) - AIF1 DAC1 EQ Band 1 A 24536a504a75SDimitris Papastamos */ 24546a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_A_MASK 0xFFFF /* AIF1DAC1_EQ_B1_A - [15:0] */ 24556a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_A_SHIFT 0 /* AIF1DAC1_EQ_B1_A - [15:0] */ 24566a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_A_WIDTH 16 /* AIF1DAC1_EQ_B1_A - [15:0] */ 24576a504a75SDimitris Papastamos 24586a504a75SDimitris Papastamos /* 24596a504a75SDimitris Papastamos * R1155 (0x483) - AIF1 DAC1 EQ Band 1 B 24606a504a75SDimitris Papastamos */ 24616a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_B_MASK 0xFFFF /* AIF1DAC1_EQ_B1_B - [15:0] */ 24626a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_B_SHIFT 0 /* AIF1DAC1_EQ_B1_B - [15:0] */ 24636a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_B_WIDTH 16 /* AIF1DAC1_EQ_B1_B - [15:0] */ 24646a504a75SDimitris Papastamos 24656a504a75SDimitris Papastamos /* 24666a504a75SDimitris Papastamos * R1156 (0x484) - AIF1 DAC1 EQ Band 1 PG 24676a504a75SDimitris Papastamos */ 24686a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B1_PG - [15:0] */ 24696a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_PG_SHIFT 0 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 24706a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B1_PG_WIDTH 16 /* AIF1DAC1_EQ_B1_PG - [15:0] */ 24716a504a75SDimitris Papastamos 24726a504a75SDimitris Papastamos /* 24736a504a75SDimitris Papastamos * R1157 (0x485) - AIF1 DAC1 EQ Band 2 A 24746a504a75SDimitris Papastamos */ 24756a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_A_MASK 0xFFFF /* AIF1DAC1_EQ_B2_A - [15:0] */ 24766a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_A_SHIFT 0 /* AIF1DAC1_EQ_B2_A - [15:0] */ 24776a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_A_WIDTH 16 /* AIF1DAC1_EQ_B2_A - [15:0] */ 24786a504a75SDimitris Papastamos 24796a504a75SDimitris Papastamos /* 24806a504a75SDimitris Papastamos * R1158 (0x486) - AIF1 DAC1 EQ Band 2 B 24816a504a75SDimitris Papastamos */ 24826a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_B_MASK 0xFFFF /* AIF1DAC1_EQ_B2_B - [15:0] */ 24836a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_B_SHIFT 0 /* AIF1DAC1_EQ_B2_B - [15:0] */ 24846a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_B_WIDTH 16 /* AIF1DAC1_EQ_B2_B - [15:0] */ 24856a504a75SDimitris Papastamos 24866a504a75SDimitris Papastamos /* 24876a504a75SDimitris Papastamos * R1159 (0x487) - AIF1 DAC1 EQ Band 2 C 24886a504a75SDimitris Papastamos */ 24896a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_C_MASK 0xFFFF /* AIF1DAC1_EQ_B2_C - [15:0] */ 24906a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_C_SHIFT 0 /* AIF1DAC1_EQ_B2_C - [15:0] */ 24916a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_C_WIDTH 16 /* AIF1DAC1_EQ_B2_C - [15:0] */ 24926a504a75SDimitris Papastamos 24936a504a75SDimitris Papastamos /* 24946a504a75SDimitris Papastamos * R1160 (0x488) - AIF1 DAC1 EQ Band 2 PG 24956a504a75SDimitris Papastamos */ 24966a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B2_PG - [15:0] */ 24976a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_PG_SHIFT 0 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 24986a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B2_PG_WIDTH 16 /* AIF1DAC1_EQ_B2_PG - [15:0] */ 24996a504a75SDimitris Papastamos 25006a504a75SDimitris Papastamos /* 25016a504a75SDimitris Papastamos * R1161 (0x489) - AIF1 DAC1 EQ Band 3 A 25026a504a75SDimitris Papastamos */ 25036a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_A_MASK 0xFFFF /* AIF1DAC1_EQ_B3_A - [15:0] */ 25046a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_A_SHIFT 0 /* AIF1DAC1_EQ_B3_A - [15:0] */ 25056a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_A_WIDTH 16 /* AIF1DAC1_EQ_B3_A - [15:0] */ 25066a504a75SDimitris Papastamos 25076a504a75SDimitris Papastamos /* 25086a504a75SDimitris Papastamos * R1162 (0x48A) - AIF1 DAC1 EQ Band 3 B 25096a504a75SDimitris Papastamos */ 25106a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_B_MASK 0xFFFF /* AIF1DAC1_EQ_B3_B - [15:0] */ 25116a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_B_SHIFT 0 /* AIF1DAC1_EQ_B3_B - [15:0] */ 25126a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_B_WIDTH 16 /* AIF1DAC1_EQ_B3_B - [15:0] */ 25136a504a75SDimitris Papastamos 25146a504a75SDimitris Papastamos /* 25156a504a75SDimitris Papastamos * R1163 (0x48B) - AIF1 DAC1 EQ Band 3 C 25166a504a75SDimitris Papastamos */ 25176a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_C_MASK 0xFFFF /* AIF1DAC1_EQ_B3_C - [15:0] */ 25186a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_C_SHIFT 0 /* AIF1DAC1_EQ_B3_C - [15:0] */ 25196a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_C_WIDTH 16 /* AIF1DAC1_EQ_B3_C - [15:0] */ 25206a504a75SDimitris Papastamos 25216a504a75SDimitris Papastamos /* 25226a504a75SDimitris Papastamos * R1164 (0x48C) - AIF1 DAC1 EQ Band 3 PG 25236a504a75SDimitris Papastamos */ 25246a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B3_PG - [15:0] */ 25256a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_PG_SHIFT 0 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 25266a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B3_PG_WIDTH 16 /* AIF1DAC1_EQ_B3_PG - [15:0] */ 25276a504a75SDimitris Papastamos 25286a504a75SDimitris Papastamos /* 25296a504a75SDimitris Papastamos * R1165 (0x48D) - AIF1 DAC1 EQ Band 4 A 25306a504a75SDimitris Papastamos */ 25316a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_A_MASK 0xFFFF /* AIF1DAC1_EQ_B4_A - [15:0] */ 25326a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_A_SHIFT 0 /* AIF1DAC1_EQ_B4_A - [15:0] */ 25336a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_A_WIDTH 16 /* AIF1DAC1_EQ_B4_A - [15:0] */ 25346a504a75SDimitris Papastamos 25356a504a75SDimitris Papastamos /* 25366a504a75SDimitris Papastamos * R1166 (0x48E) - AIF1 DAC1 EQ Band 4 B 25376a504a75SDimitris Papastamos */ 25386a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_B_MASK 0xFFFF /* AIF1DAC1_EQ_B4_B - [15:0] */ 25396a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_B_SHIFT 0 /* AIF1DAC1_EQ_B4_B - [15:0] */ 25406a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_B_WIDTH 16 /* AIF1DAC1_EQ_B4_B - [15:0] */ 25416a504a75SDimitris Papastamos 25426a504a75SDimitris Papastamos /* 25436a504a75SDimitris Papastamos * R1167 (0x48F) - AIF1 DAC1 EQ Band 4 C 25446a504a75SDimitris Papastamos */ 25456a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_C_MASK 0xFFFF /* AIF1DAC1_EQ_B4_C - [15:0] */ 25466a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_C_SHIFT 0 /* AIF1DAC1_EQ_B4_C - [15:0] */ 25476a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_C_WIDTH 16 /* AIF1DAC1_EQ_B4_C - [15:0] */ 25486a504a75SDimitris Papastamos 25496a504a75SDimitris Papastamos /* 25506a504a75SDimitris Papastamos * R1168 (0x490) - AIF1 DAC1 EQ Band 4 PG 25516a504a75SDimitris Papastamos */ 25526a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B4_PG - [15:0] */ 25536a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_PG_SHIFT 0 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 25546a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B4_PG_WIDTH 16 /* AIF1DAC1_EQ_B4_PG - [15:0] */ 25556a504a75SDimitris Papastamos 25566a504a75SDimitris Papastamos /* 25576a504a75SDimitris Papastamos * R1169 (0x491) - AIF1 DAC1 EQ Band 5 A 25586a504a75SDimitris Papastamos */ 25596a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_A_MASK 0xFFFF /* AIF1DAC1_EQ_B5_A - [15:0] */ 25606a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_A_SHIFT 0 /* AIF1DAC1_EQ_B5_A - [15:0] */ 25616a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_A_WIDTH 16 /* AIF1DAC1_EQ_B5_A - [15:0] */ 25626a504a75SDimitris Papastamos 25636a504a75SDimitris Papastamos /* 25646a504a75SDimitris Papastamos * R1170 (0x492) - AIF1 DAC1 EQ Band 5 B 25656a504a75SDimitris Papastamos */ 25666a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_B_MASK 0xFFFF /* AIF1DAC1_EQ_B5_B - [15:0] */ 25676a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_B_SHIFT 0 /* AIF1DAC1_EQ_B5_B - [15:0] */ 25686a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_B_WIDTH 16 /* AIF1DAC1_EQ_B5_B - [15:0] */ 25696a504a75SDimitris Papastamos 25706a504a75SDimitris Papastamos /* 25716a504a75SDimitris Papastamos * R1171 (0x493) - AIF1 DAC1 EQ Band 5 PG 25726a504a75SDimitris Papastamos */ 25736a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC1_EQ_B5_PG - [15:0] */ 25746a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_PG_SHIFT 0 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 25756a504a75SDimitris Papastamos #define WM8995_AIF1DAC1_EQ_B5_PG_WIDTH 16 /* AIF1DAC1_EQ_B5_PG - [15:0] */ 25766a504a75SDimitris Papastamos 25776a504a75SDimitris Papastamos /* 25786a504a75SDimitris Papastamos * R1184 (0x4A0) - AIF1 DAC2 EQ Gains (1) 25796a504a75SDimitris Papastamos */ 25806a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 25816a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 25826a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B1_GAIN - [15:11] */ 25836a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 25846a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 25856a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B2_GAIN - [10:6] */ 25866a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_GAIN_MASK 0x003E /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 25876a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_GAIN_SHIFT 1 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 25886a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B3_GAIN - [5:1] */ 25896a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_ENA 0x0001 /* AIF1DAC2_EQ_ENA */ 25906a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_ENA_MASK 0x0001 /* AIF1DAC2_EQ_ENA */ 25916a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_ENA_SHIFT 0 /* AIF1DAC2_EQ_ENA */ 25926a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_ENA_WIDTH 1 /* AIF1DAC2_EQ_ENA */ 25936a504a75SDimitris Papastamos 25946a504a75SDimitris Papastamos /* 25956a504a75SDimitris Papastamos * R1185 (0x4A1) - AIF1 DAC2 EQ Gains (2) 25966a504a75SDimitris Papastamos */ 25976a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_GAIN_MASK 0xF800 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 25986a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_GAIN_SHIFT 11 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 25996a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B4_GAIN - [15:11] */ 26006a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_GAIN_MASK 0x07C0 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 26016a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_GAIN_SHIFT 6 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 26026a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_GAIN_WIDTH 5 /* AIF1DAC2_EQ_B5_GAIN - [10:6] */ 26036a504a75SDimitris Papastamos 26046a504a75SDimitris Papastamos /* 26056a504a75SDimitris Papastamos * R1186 (0x4A2) - AIF1 DAC2 EQ Band 1 A 26066a504a75SDimitris Papastamos */ 26076a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_A_MASK 0xFFFF /* AIF1DAC2_EQ_B1_A - [15:0] */ 26086a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_A_SHIFT 0 /* AIF1DAC2_EQ_B1_A - [15:0] */ 26096a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_A_WIDTH 16 /* AIF1DAC2_EQ_B1_A - [15:0] */ 26106a504a75SDimitris Papastamos 26116a504a75SDimitris Papastamos /* 26126a504a75SDimitris Papastamos * R1187 (0x4A3) - AIF1 DAC2 EQ Band 1 B 26136a504a75SDimitris Papastamos */ 26146a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_B_MASK 0xFFFF /* AIF1DAC2_EQ_B1_B - [15:0] */ 26156a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_B_SHIFT 0 /* AIF1DAC2_EQ_B1_B - [15:0] */ 26166a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_B_WIDTH 16 /* AIF1DAC2_EQ_B1_B - [15:0] */ 26176a504a75SDimitris Papastamos 26186a504a75SDimitris Papastamos /* 26196a504a75SDimitris Papastamos * R1188 (0x4A4) - AIF1 DAC2 EQ Band 1 PG 26206a504a75SDimitris Papastamos */ 26216a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B1_PG - [15:0] */ 26226a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_PG_SHIFT 0 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 26236a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B1_PG_WIDTH 16 /* AIF1DAC2_EQ_B1_PG - [15:0] */ 26246a504a75SDimitris Papastamos 26256a504a75SDimitris Papastamos /* 26266a504a75SDimitris Papastamos * R1189 (0x4A5) - AIF1 DAC2 EQ Band 2 A 26276a504a75SDimitris Papastamos */ 26286a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_A_MASK 0xFFFF /* AIF1DAC2_EQ_B2_A - [15:0] */ 26296a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_A_SHIFT 0 /* AIF1DAC2_EQ_B2_A - [15:0] */ 26306a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_A_WIDTH 16 /* AIF1DAC2_EQ_B2_A - [15:0] */ 26316a504a75SDimitris Papastamos 26326a504a75SDimitris Papastamos /* 26336a504a75SDimitris Papastamos * R1190 (0x4A6) - AIF1 DAC2 EQ Band 2 B 26346a504a75SDimitris Papastamos */ 26356a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_B_MASK 0xFFFF /* AIF1DAC2_EQ_B2_B - [15:0] */ 26366a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_B_SHIFT 0 /* AIF1DAC2_EQ_B2_B - [15:0] */ 26376a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_B_WIDTH 16 /* AIF1DAC2_EQ_B2_B - [15:0] */ 26386a504a75SDimitris Papastamos 26396a504a75SDimitris Papastamos /* 26406a504a75SDimitris Papastamos * R1191 (0x4A7) - AIF1 DAC2 EQ Band 2 C 26416a504a75SDimitris Papastamos */ 26426a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_C_MASK 0xFFFF /* AIF1DAC2_EQ_B2_C - [15:0] */ 26436a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_C_SHIFT 0 /* AIF1DAC2_EQ_B2_C - [15:0] */ 26446a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_C_WIDTH 16 /* AIF1DAC2_EQ_B2_C - [15:0] */ 26456a504a75SDimitris Papastamos 26466a504a75SDimitris Papastamos /* 26476a504a75SDimitris Papastamos * R1192 (0x4A8) - AIF1 DAC2 EQ Band 2 PG 26486a504a75SDimitris Papastamos */ 26496a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B2_PG - [15:0] */ 26506a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_PG_SHIFT 0 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 26516a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B2_PG_WIDTH 16 /* AIF1DAC2_EQ_B2_PG - [15:0] */ 26526a504a75SDimitris Papastamos 26536a504a75SDimitris Papastamos /* 26546a504a75SDimitris Papastamos * R1193 (0x4A9) - AIF1 DAC2 EQ Band 3 A 26556a504a75SDimitris Papastamos */ 26566a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_A_MASK 0xFFFF /* AIF1DAC2_EQ_B3_A - [15:0] */ 26576a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_A_SHIFT 0 /* AIF1DAC2_EQ_B3_A - [15:0] */ 26586a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_A_WIDTH 16 /* AIF1DAC2_EQ_B3_A - [15:0] */ 26596a504a75SDimitris Papastamos 26606a504a75SDimitris Papastamos /* 26616a504a75SDimitris Papastamos * R1194 (0x4AA) - AIF1 DAC2 EQ Band 3 B 26626a504a75SDimitris Papastamos */ 26636a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_B_MASK 0xFFFF /* AIF1DAC2_EQ_B3_B - [15:0] */ 26646a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_B_SHIFT 0 /* AIF1DAC2_EQ_B3_B - [15:0] */ 26656a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_B_WIDTH 16 /* AIF1DAC2_EQ_B3_B - [15:0] */ 26666a504a75SDimitris Papastamos 26676a504a75SDimitris Papastamos /* 26686a504a75SDimitris Papastamos * R1195 (0x4AB) - AIF1 DAC2 EQ Band 3 C 26696a504a75SDimitris Papastamos */ 26706a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_C_MASK 0xFFFF /* AIF1DAC2_EQ_B3_C - [15:0] */ 26716a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_C_SHIFT 0 /* AIF1DAC2_EQ_B3_C - [15:0] */ 26726a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_C_WIDTH 16 /* AIF1DAC2_EQ_B3_C - [15:0] */ 26736a504a75SDimitris Papastamos 26746a504a75SDimitris Papastamos /* 26756a504a75SDimitris Papastamos * R1196 (0x4AC) - AIF1 DAC2 EQ Band 3 PG 26766a504a75SDimitris Papastamos */ 26776a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B3_PG - [15:0] */ 26786a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_PG_SHIFT 0 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 26796a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B3_PG_WIDTH 16 /* AIF1DAC2_EQ_B3_PG - [15:0] */ 26806a504a75SDimitris Papastamos 26816a504a75SDimitris Papastamos /* 26826a504a75SDimitris Papastamos * R1197 (0x4AD) - AIF1 DAC2 EQ Band 4 A 26836a504a75SDimitris Papastamos */ 26846a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_A_MASK 0xFFFF /* AIF1DAC2_EQ_B4_A - [15:0] */ 26856a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_A_SHIFT 0 /* AIF1DAC2_EQ_B4_A - [15:0] */ 26866a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_A_WIDTH 16 /* AIF1DAC2_EQ_B4_A - [15:0] */ 26876a504a75SDimitris Papastamos 26886a504a75SDimitris Papastamos /* 26896a504a75SDimitris Papastamos * R1198 (0x4AE) - AIF1 DAC2 EQ Band 4 B 26906a504a75SDimitris Papastamos */ 26916a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_B_MASK 0xFFFF /* AIF1DAC2_EQ_B4_B - [15:0] */ 26926a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_B_SHIFT 0 /* AIF1DAC2_EQ_B4_B - [15:0] */ 26936a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_B_WIDTH 16 /* AIF1DAC2_EQ_B4_B - [15:0] */ 26946a504a75SDimitris Papastamos 26956a504a75SDimitris Papastamos /* 26966a504a75SDimitris Papastamos * R1199 (0x4AF) - AIF1 DAC2 EQ Band 4 C 26976a504a75SDimitris Papastamos */ 26986a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_C_MASK 0xFFFF /* AIF1DAC2_EQ_B4_C - [15:0] */ 26996a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_C_SHIFT 0 /* AIF1DAC2_EQ_B4_C - [15:0] */ 27006a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_C_WIDTH 16 /* AIF1DAC2_EQ_B4_C - [15:0] */ 27016a504a75SDimitris Papastamos 27026a504a75SDimitris Papastamos /* 27036a504a75SDimitris Papastamos * R1200 (0x4B0) - AIF1 DAC2 EQ Band 4 PG 27046a504a75SDimitris Papastamos */ 27056a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B4_PG - [15:0] */ 27066a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_PG_SHIFT 0 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 27076a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B4_PG_WIDTH 16 /* AIF1DAC2_EQ_B4_PG - [15:0] */ 27086a504a75SDimitris Papastamos 27096a504a75SDimitris Papastamos /* 27106a504a75SDimitris Papastamos * R1201 (0x4B1) - AIF1 DAC2 EQ Band 5 A 27116a504a75SDimitris Papastamos */ 27126a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_A_MASK 0xFFFF /* AIF1DAC2_EQ_B5_A - [15:0] */ 27136a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_A_SHIFT 0 /* AIF1DAC2_EQ_B5_A - [15:0] */ 27146a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_A_WIDTH 16 /* AIF1DAC2_EQ_B5_A - [15:0] */ 27156a504a75SDimitris Papastamos 27166a504a75SDimitris Papastamos /* 27176a504a75SDimitris Papastamos * R1202 (0x4B2) - AIF1 DAC2 EQ Band 5 B 27186a504a75SDimitris Papastamos */ 27196a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_B_MASK 0xFFFF /* AIF1DAC2_EQ_B5_B - [15:0] */ 27206a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_B_SHIFT 0 /* AIF1DAC2_EQ_B5_B - [15:0] */ 27216a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_B_WIDTH 16 /* AIF1DAC2_EQ_B5_B - [15:0] */ 27226a504a75SDimitris Papastamos 27236a504a75SDimitris Papastamos /* 27246a504a75SDimitris Papastamos * R1203 (0x4B3) - AIF1 DAC2 EQ Band 5 PG 27256a504a75SDimitris Papastamos */ 27266a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_PG_MASK 0xFFFF /* AIF1DAC2_EQ_B5_PG - [15:0] */ 27276a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_PG_SHIFT 0 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 27286a504a75SDimitris Papastamos #define WM8995_AIF1DAC2_EQ_B5_PG_WIDTH 16 /* AIF1DAC2_EQ_B5_PG - [15:0] */ 27296a504a75SDimitris Papastamos 27306a504a75SDimitris Papastamos /* 27316a504a75SDimitris Papastamos * R1280 (0x500) - AIF2 ADC Left Volume 27326a504a75SDimitris Papastamos */ 27336a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 27346a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 27356a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 27366a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 27376a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_VOL_MASK 0x00FF /* AIF2ADCL_VOL - [7:0] */ 27386a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_VOL_SHIFT 0 /* AIF2ADCL_VOL - [7:0] */ 27396a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_VOL_WIDTH 8 /* AIF2ADCL_VOL - [7:0] */ 27406a504a75SDimitris Papastamos 27416a504a75SDimitris Papastamos /* 27426a504a75SDimitris Papastamos * R1281 (0x501) - AIF2 ADC Right Volume 27436a504a75SDimitris Papastamos */ 27446a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU 0x0100 /* AIF2ADC_VU */ 27456a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_MASK 0x0100 /* AIF2ADC_VU */ 27466a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_SHIFT 8 /* AIF2ADC_VU */ 27476a504a75SDimitris Papastamos #define WM8995_AIF2ADC_VU_WIDTH 1 /* AIF2ADC_VU */ 27486a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_VOL_MASK 0x00FF /* AIF2ADCR_VOL - [7:0] */ 27496a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_VOL_SHIFT 0 /* AIF2ADCR_VOL - [7:0] */ 27506a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_VOL_WIDTH 8 /* AIF2ADCR_VOL - [7:0] */ 27516a504a75SDimitris Papastamos 27526a504a75SDimitris Papastamos /* 27536a504a75SDimitris Papastamos * R1282 (0x502) - AIF2 DAC Left Volume 27546a504a75SDimitris Papastamos */ 27556a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 27566a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 27576a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 27586a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 27596a504a75SDimitris Papastamos #define WM8995_AIF2DACL_VOL_MASK 0x00FF /* AIF2DACL_VOL - [7:0] */ 27606a504a75SDimitris Papastamos #define WM8995_AIF2DACL_VOL_SHIFT 0 /* AIF2DACL_VOL - [7:0] */ 27616a504a75SDimitris Papastamos #define WM8995_AIF2DACL_VOL_WIDTH 8 /* AIF2DACL_VOL - [7:0] */ 27626a504a75SDimitris Papastamos 27636a504a75SDimitris Papastamos /* 27646a504a75SDimitris Papastamos * R1283 (0x503) - AIF2 DAC Right Volume 27656a504a75SDimitris Papastamos */ 27666a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU 0x0100 /* AIF2DAC_VU */ 27676a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_MASK 0x0100 /* AIF2DAC_VU */ 27686a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_SHIFT 8 /* AIF2DAC_VU */ 27696a504a75SDimitris Papastamos #define WM8995_AIF2DAC_VU_WIDTH 1 /* AIF2DAC_VU */ 27706a504a75SDimitris Papastamos #define WM8995_AIF2DACR_VOL_MASK 0x00FF /* AIF2DACR_VOL - [7:0] */ 27716a504a75SDimitris Papastamos #define WM8995_AIF2DACR_VOL_SHIFT 0 /* AIF2DACR_VOL - [7:0] */ 27726a504a75SDimitris Papastamos #define WM8995_AIF2DACR_VOL_WIDTH 8 /* AIF2DACR_VOL - [7:0] */ 27736a504a75SDimitris Papastamos 27746a504a75SDimitris Papastamos /* 27756a504a75SDimitris Papastamos * R1296 (0x510) - AIF2 ADC Filters 27766a504a75SDimitris Papastamos */ 27776a504a75SDimitris Papastamos #define WM8995_AIF2ADC_4FS 0x8000 /* AIF2ADC_4FS */ 27786a504a75SDimitris Papastamos #define WM8995_AIF2ADC_4FS_MASK 0x8000 /* AIF2ADC_4FS */ 27796a504a75SDimitris Papastamos #define WM8995_AIF2ADC_4FS_SHIFT 15 /* AIF2ADC_4FS */ 27806a504a75SDimitris Papastamos #define WM8995_AIF2ADC_4FS_WIDTH 1 /* AIF2ADC_4FS */ 27816a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_HPF 0x1000 /* AIF2ADCL_HPF */ 27826a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_HPF_MASK 0x1000 /* AIF2ADCL_HPF */ 27836a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_HPF_SHIFT 12 /* AIF2ADCL_HPF */ 27846a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_HPF_WIDTH 1 /* AIF2ADCL_HPF */ 27856a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_HPF 0x0800 /* AIF2ADCR_HPF */ 27866a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_HPF_MASK 0x0800 /* AIF2ADCR_HPF */ 27876a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_HPF_SHIFT 11 /* AIF2ADCR_HPF */ 27886a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_HPF_WIDTH 1 /* AIF2ADCR_HPF */ 27896a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_MODE 0x0008 /* AIF2ADC_HPF_MODE */ 27906a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_MODE_MASK 0x0008 /* AIF2ADC_HPF_MODE */ 27916a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_MODE_SHIFT 3 /* AIF2ADC_HPF_MODE */ 27926a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_MODE_WIDTH 1 /* AIF2ADC_HPF_MODE */ 27936a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_CUT_MASK 0x0007 /* AIF2ADC_HPF_CUT - [2:0] */ 27946a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_CUT_SHIFT 0 /* AIF2ADC_HPF_CUT - [2:0] */ 27956a504a75SDimitris Papastamos #define WM8995_AIF2ADC_HPF_CUT_WIDTH 3 /* AIF2ADC_HPF_CUT - [2:0] */ 27966a504a75SDimitris Papastamos 27976a504a75SDimitris Papastamos /* 27986a504a75SDimitris Papastamos * R1312 (0x520) - AIF2 DAC Filters (1) 27996a504a75SDimitris Papastamos */ 28006a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTE 0x0200 /* AIF2DAC_MUTE */ 28016a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTE_MASK 0x0200 /* AIF2DAC_MUTE */ 28026a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTE_SHIFT 9 /* AIF2DAC_MUTE */ 28036a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTE_WIDTH 1 /* AIF2DAC_MUTE */ 28046a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MONO 0x0080 /* AIF2DAC_MONO */ 28056a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MONO_MASK 0x0080 /* AIF2DAC_MONO */ 28066a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MONO_SHIFT 7 /* AIF2DAC_MONO */ 28076a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MONO_WIDTH 1 /* AIF2DAC_MONO */ 28086a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTERATE 0x0020 /* AIF2DAC_MUTERATE */ 28096a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTERATE_MASK 0x0020 /* AIF2DAC_MUTERATE */ 28106a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTERATE_SHIFT 5 /* AIF2DAC_MUTERATE */ 28116a504a75SDimitris Papastamos #define WM8995_AIF2DAC_MUTERATE_WIDTH 1 /* AIF2DAC_MUTERATE */ 28126a504a75SDimitris Papastamos #define WM8995_AIF2DAC_UNMUTE_RAMP 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 28136a504a75SDimitris Papastamos #define WM8995_AIF2DAC_UNMUTE_RAMP_MASK 0x0010 /* AIF2DAC_UNMUTE_RAMP */ 28146a504a75SDimitris Papastamos #define WM8995_AIF2DAC_UNMUTE_RAMP_SHIFT 4 /* AIF2DAC_UNMUTE_RAMP */ 28156a504a75SDimitris Papastamos #define WM8995_AIF2DAC_UNMUTE_RAMP_WIDTH 1 /* AIF2DAC_UNMUTE_RAMP */ 28166a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DEEMP_MASK 0x0006 /* AIF2DAC_DEEMP - [2:1] */ 28176a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DEEMP_SHIFT 1 /* AIF2DAC_DEEMP - [2:1] */ 28186a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DEEMP_WIDTH 2 /* AIF2DAC_DEEMP - [2:1] */ 28196a504a75SDimitris Papastamos 28206a504a75SDimitris Papastamos /* 28216a504a75SDimitris Papastamos * R1313 (0x521) - AIF2 DAC Filters (2) 28226a504a75SDimitris Papastamos */ 28236a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_GAIN_MASK 0x3E00 /* AIF2DAC_3D_GAIN - [13:9] */ 28246a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_GAIN_SHIFT 9 /* AIF2DAC_3D_GAIN - [13:9] */ 28256a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_GAIN_WIDTH 5 /* AIF2DAC_3D_GAIN - [13:9] */ 28266a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_ENA 0x0100 /* AIF2DAC_3D_ENA */ 28276a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_ENA_MASK 0x0100 /* AIF2DAC_3D_ENA */ 28286a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */ 28296a504a75SDimitris Papastamos #define WM8995_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */ 28306a504a75SDimitris Papastamos 28316a504a75SDimitris Papastamos /* 28326a504a75SDimitris Papastamos * R1344 (0x540) - AIF2 DRC (1) 28336a504a75SDimitris Papastamos */ 28346a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_RMS_MASK 0xF800 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 28356a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_RMS_SHIFT 11 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 28366a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_RMS_WIDTH 5 /* AIF2DRC_SIG_DET_RMS - [15:11] */ 28376a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_PK_MASK 0x0600 /* AIF2DRC_SIG_DET_PK - [10:9] */ 28386a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_PK_SHIFT 9 /* AIF2DRC_SIG_DET_PK - [10:9] */ 28396a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_PK_WIDTH 2 /* AIF2DRC_SIG_DET_PK - [10:9] */ 28406a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_ENA 0x0100 /* AIF2DRC_NG_ENA */ 28416a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_ENA_MASK 0x0100 /* AIF2DRC_NG_ENA */ 28426a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_ENA_SHIFT 8 /* AIF2DRC_NG_ENA */ 28436a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_ENA_WIDTH 1 /* AIF2DRC_NG_ENA */ 28446a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_MODE 0x0080 /* AIF2DRC_SIG_DET_MODE */ 28456a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_MODE_MASK 0x0080 /* AIF2DRC_SIG_DET_MODE */ 28466a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_MODE_SHIFT 7 /* AIF2DRC_SIG_DET_MODE */ 28476a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_MODE_WIDTH 1 /* AIF2DRC_SIG_DET_MODE */ 28486a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET 0x0040 /* AIF2DRC_SIG_DET */ 28496a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_MASK 0x0040 /* AIF2DRC_SIG_DET */ 28506a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_SHIFT 6 /* AIF2DRC_SIG_DET */ 28516a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_WIDTH 1 /* AIF2DRC_SIG_DET */ 28526a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_ENA 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 28536a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_ENA_MASK 0x0020 /* AIF2DRC_KNEE2_OP_ENA */ 28546a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_ENA_SHIFT 5 /* AIF2DRC_KNEE2_OP_ENA */ 28556a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_ENA_WIDTH 1 /* AIF2DRC_KNEE2_OP_ENA */ 28566a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR 0x0010 /* AIF2DRC_QR */ 28576a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_MASK 0x0010 /* AIF2DRC_QR */ 28586a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_SHIFT 4 /* AIF2DRC_QR */ 28596a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_WIDTH 1 /* AIF2DRC_QR */ 28606a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ANTICLIP 0x0008 /* AIF2DRC_ANTICLIP */ 28616a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ANTICLIP_MASK 0x0008 /* AIF2DRC_ANTICLIP */ 28626a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ANTICLIP_SHIFT 3 /* AIF2DRC_ANTICLIP */ 28636a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ANTICLIP_WIDTH 1 /* AIF2DRC_ANTICLIP */ 28646a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DRC_ENA 0x0004 /* AIF2DAC_DRC_ENA */ 28656a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DRC_ENA_MASK 0x0004 /* AIF2DAC_DRC_ENA */ 28666a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DRC_ENA_SHIFT 2 /* AIF2DAC_DRC_ENA */ 28676a504a75SDimitris Papastamos #define WM8995_AIF2DAC_DRC_ENA_WIDTH 1 /* AIF2DAC_DRC_ENA */ 28686a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DRC_ENA 0x0002 /* AIF2ADCL_DRC_ENA */ 28696a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DRC_ENA_MASK 0x0002 /* AIF2ADCL_DRC_ENA */ 28706a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DRC_ENA_SHIFT 1 /* AIF2ADCL_DRC_ENA */ 28716a504a75SDimitris Papastamos #define WM8995_AIF2ADCL_DRC_ENA_WIDTH 1 /* AIF2ADCL_DRC_ENA */ 28726a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DRC_ENA 0x0001 /* AIF2ADCR_DRC_ENA */ 28736a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DRC_ENA_MASK 0x0001 /* AIF2ADCR_DRC_ENA */ 28746a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DRC_ENA_SHIFT 0 /* AIF2ADCR_DRC_ENA */ 28756a504a75SDimitris Papastamos #define WM8995_AIF2ADCR_DRC_ENA_WIDTH 1 /* AIF2ADCR_DRC_ENA */ 28766a504a75SDimitris Papastamos 28776a504a75SDimitris Papastamos /* 28786a504a75SDimitris Papastamos * R1345 (0x541) - AIF2 DRC (2) 28796a504a75SDimitris Papastamos */ 28806a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ATK_MASK 0x1E00 /* AIF2DRC_ATK - [12:9] */ 28816a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ATK_SHIFT 9 /* AIF2DRC_ATK - [12:9] */ 28826a504a75SDimitris Papastamos #define WM8995_AIF2DRC_ATK_WIDTH 4 /* AIF2DRC_ATK - [12:9] */ 28836a504a75SDimitris Papastamos #define WM8995_AIF2DRC_DCY_MASK 0x01E0 /* AIF2DRC_DCY - [8:5] */ 28846a504a75SDimitris Papastamos #define WM8995_AIF2DRC_DCY_SHIFT 5 /* AIF2DRC_DCY - [8:5] */ 28856a504a75SDimitris Papastamos #define WM8995_AIF2DRC_DCY_WIDTH 4 /* AIF2DRC_DCY - [8:5] */ 28866a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MINGAIN_MASK 0x001C /* AIF2DRC_MINGAIN - [4:2] */ 28876a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MINGAIN_SHIFT 2 /* AIF2DRC_MINGAIN - [4:2] */ 28886a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MINGAIN_WIDTH 3 /* AIF2DRC_MINGAIN - [4:2] */ 28896a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MAXGAIN_MASK 0x0003 /* AIF2DRC_MAXGAIN - [1:0] */ 28906a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MAXGAIN_SHIFT 0 /* AIF2DRC_MAXGAIN - [1:0] */ 28916a504a75SDimitris Papastamos #define WM8995_AIF2DRC_MAXGAIN_WIDTH 2 /* AIF2DRC_MAXGAIN - [1:0] */ 28926a504a75SDimitris Papastamos 28936a504a75SDimitris Papastamos /* 28946a504a75SDimitris Papastamos * R1346 (0x542) - AIF2 DRC (3) 28956a504a75SDimitris Papastamos */ 28966a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_MINGAIN_MASK 0xF000 /* AIF2DRC_NG_MINGAIN - [15:12] */ 28976a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_MINGAIN_SHIFT 12 /* AIF2DRC_NG_MINGAIN - [15:12] */ 28986a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_MINGAIN_WIDTH 4 /* AIF2DRC_NG_MINGAIN - [15:12] */ 28996a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_EXP_MASK 0x0C00 /* AIF2DRC_NG_EXP - [11:10] */ 29006a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_EXP_SHIFT 10 /* AIF2DRC_NG_EXP - [11:10] */ 29016a504a75SDimitris Papastamos #define WM8995_AIF2DRC_NG_EXP_WIDTH 2 /* AIF2DRC_NG_EXP - [11:10] */ 29026a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_THR_MASK 0x0300 /* AIF2DRC_QR_THR - [9:8] */ 29036a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_THR_SHIFT 8 /* AIF2DRC_QR_THR - [9:8] */ 29046a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_THR_WIDTH 2 /* AIF2DRC_QR_THR - [9:8] */ 29056a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_DCY_MASK 0x00C0 /* AIF2DRC_QR_DCY - [7:6] */ 29066a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_DCY_SHIFT 6 /* AIF2DRC_QR_DCY - [7:6] */ 29076a504a75SDimitris Papastamos #define WM8995_AIF2DRC_QR_DCY_WIDTH 2 /* AIF2DRC_QR_DCY - [7:6] */ 29086a504a75SDimitris Papastamos #define WM8995_AIF2DRC_HI_COMP_MASK 0x0038 /* AIF2DRC_HI_COMP - [5:3] */ 29096a504a75SDimitris Papastamos #define WM8995_AIF2DRC_HI_COMP_SHIFT 3 /* AIF2DRC_HI_COMP - [5:3] */ 29106a504a75SDimitris Papastamos #define WM8995_AIF2DRC_HI_COMP_WIDTH 3 /* AIF2DRC_HI_COMP - [5:3] */ 29116a504a75SDimitris Papastamos #define WM8995_AIF2DRC_LO_COMP_MASK 0x0007 /* AIF2DRC_LO_COMP - [2:0] */ 29126a504a75SDimitris Papastamos #define WM8995_AIF2DRC_LO_COMP_SHIFT 0 /* AIF2DRC_LO_COMP - [2:0] */ 29136a504a75SDimitris Papastamos #define WM8995_AIF2DRC_LO_COMP_WIDTH 3 /* AIF2DRC_LO_COMP - [2:0] */ 29146a504a75SDimitris Papastamos 29156a504a75SDimitris Papastamos /* 29166a504a75SDimitris Papastamos * R1347 (0x543) - AIF2 DRC (4) 29176a504a75SDimitris Papastamos */ 29186a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_IP_MASK 0x07E0 /* AIF2DRC_KNEE_IP - [10:5] */ 29196a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_IP_SHIFT 5 /* AIF2DRC_KNEE_IP - [10:5] */ 29206a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_IP_WIDTH 6 /* AIF2DRC_KNEE_IP - [10:5] */ 29216a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_OP_MASK 0x001F /* AIF2DRC_KNEE_OP - [4:0] */ 29226a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_OP_SHIFT 0 /* AIF2DRC_KNEE_OP - [4:0] */ 29236a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE_OP_WIDTH 5 /* AIF2DRC_KNEE_OP - [4:0] */ 29246a504a75SDimitris Papastamos 29256a504a75SDimitris Papastamos /* 29266a504a75SDimitris Papastamos * R1348 (0x544) - AIF2 DRC (5) 29276a504a75SDimitris Papastamos */ 29286a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_IP_MASK 0x03E0 /* AIF2DRC_KNEE2_IP - [9:5] */ 29296a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_IP_SHIFT 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 29306a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_IP_WIDTH 5 /* AIF2DRC_KNEE2_IP - [9:5] */ 29316a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_MASK 0x001F /* AIF2DRC_KNEE2_OP - [4:0] */ 29326a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_SHIFT 0 /* AIF2DRC_KNEE2_OP - [4:0] */ 29336a504a75SDimitris Papastamos #define WM8995_AIF2DRC_KNEE2_OP_WIDTH 5 /* AIF2DRC_KNEE2_OP - [4:0] */ 29346a504a75SDimitris Papastamos 29356a504a75SDimitris Papastamos /* 29366a504a75SDimitris Papastamos * R1408 (0x580) - AIF2 EQ Gains (1) 29376a504a75SDimitris Papastamos */ 29386a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 29396a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_GAIN_SHIFT 11 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 29406a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_GAIN_WIDTH 5 /* AIF2DAC_EQ_B1_GAIN - [15:11] */ 29416a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 29426a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_GAIN_SHIFT 6 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 29436a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_GAIN_WIDTH 5 /* AIF2DAC_EQ_B2_GAIN - [10:6] */ 29446a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_GAIN_MASK 0x003E /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 29456a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_GAIN_SHIFT 1 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 29466a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_GAIN_WIDTH 5 /* AIF2DAC_EQ_B3_GAIN - [5:1] */ 29476a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_ENA 0x0001 /* AIF2DAC_EQ_ENA */ 29486a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_ENA_MASK 0x0001 /* AIF2DAC_EQ_ENA */ 29496a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_ENA_SHIFT 0 /* AIF2DAC_EQ_ENA */ 29506a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_ENA_WIDTH 1 /* AIF2DAC_EQ_ENA */ 29516a504a75SDimitris Papastamos 29526a504a75SDimitris Papastamos /* 29536a504a75SDimitris Papastamos * R1409 (0x581) - AIF2 EQ Gains (2) 29546a504a75SDimitris Papastamos */ 29556a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_GAIN_MASK 0xF800 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 29566a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_GAIN_SHIFT 11 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 29576a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_GAIN_WIDTH 5 /* AIF2DAC_EQ_B4_GAIN - [15:11] */ 29586a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_GAIN_MASK 0x07C0 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 29596a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_GAIN_SHIFT 6 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 29606a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_GAIN_WIDTH 5 /* AIF2DAC_EQ_B5_GAIN - [10:6] */ 29616a504a75SDimitris Papastamos 29626a504a75SDimitris Papastamos /* 29636a504a75SDimitris Papastamos * R1410 (0x582) - AIF2 EQ Band 1 A 29646a504a75SDimitris Papastamos */ 29656a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_A_MASK 0xFFFF /* AIF2DAC_EQ_B1_A - [15:0] */ 29666a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_A_SHIFT 0 /* AIF2DAC_EQ_B1_A - [15:0] */ 29676a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_A_WIDTH 16 /* AIF2DAC_EQ_B1_A - [15:0] */ 29686a504a75SDimitris Papastamos 29696a504a75SDimitris Papastamos /* 29706a504a75SDimitris Papastamos * R1411 (0x583) - AIF2 EQ Band 1 B 29716a504a75SDimitris Papastamos */ 29726a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_B_MASK 0xFFFF /* AIF2DAC_EQ_B1_B - [15:0] */ 29736a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_B_SHIFT 0 /* AIF2DAC_EQ_B1_B - [15:0] */ 29746a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_B_WIDTH 16 /* AIF2DAC_EQ_B1_B - [15:0] */ 29756a504a75SDimitris Papastamos 29766a504a75SDimitris Papastamos /* 29776a504a75SDimitris Papastamos * R1412 (0x584) - AIF2 EQ Band 1 PG 29786a504a75SDimitris Papastamos */ 29796a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_PG_MASK 0xFFFF /* AIF2DAC_EQ_B1_PG - [15:0] */ 29806a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_PG_SHIFT 0 /* AIF2DAC_EQ_B1_PG - [15:0] */ 29816a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B1_PG_WIDTH 16 /* AIF2DAC_EQ_B1_PG - [15:0] */ 29826a504a75SDimitris Papastamos 29836a504a75SDimitris Papastamos /* 29846a504a75SDimitris Papastamos * R1413 (0x585) - AIF2 EQ Band 2 A 29856a504a75SDimitris Papastamos */ 29866a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_A_MASK 0xFFFF /* AIF2DAC_EQ_B2_A - [15:0] */ 29876a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_A_SHIFT 0 /* AIF2DAC_EQ_B2_A - [15:0] */ 29886a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_A_WIDTH 16 /* AIF2DAC_EQ_B2_A - [15:0] */ 29896a504a75SDimitris Papastamos 29906a504a75SDimitris Papastamos /* 29916a504a75SDimitris Papastamos * R1414 (0x586) - AIF2 EQ Band 2 B 29926a504a75SDimitris Papastamos */ 29936a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_B_MASK 0xFFFF /* AIF2DAC_EQ_B2_B - [15:0] */ 29946a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_B_SHIFT 0 /* AIF2DAC_EQ_B2_B - [15:0] */ 29956a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_B_WIDTH 16 /* AIF2DAC_EQ_B2_B - [15:0] */ 29966a504a75SDimitris Papastamos 29976a504a75SDimitris Papastamos /* 29986a504a75SDimitris Papastamos * R1415 (0x587) - AIF2 EQ Band 2 C 29996a504a75SDimitris Papastamos */ 30006a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_C_MASK 0xFFFF /* AIF2DAC_EQ_B2_C - [15:0] */ 30016a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_C_SHIFT 0 /* AIF2DAC_EQ_B2_C - [15:0] */ 30026a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_C_WIDTH 16 /* AIF2DAC_EQ_B2_C - [15:0] */ 30036a504a75SDimitris Papastamos 30046a504a75SDimitris Papastamos /* 30056a504a75SDimitris Papastamos * R1416 (0x588) - AIF2 EQ Band 2 PG 30066a504a75SDimitris Papastamos */ 30076a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_PG_MASK 0xFFFF /* AIF2DAC_EQ_B2_PG - [15:0] */ 30086a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_PG_SHIFT 0 /* AIF2DAC_EQ_B2_PG - [15:0] */ 30096a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B2_PG_WIDTH 16 /* AIF2DAC_EQ_B2_PG - [15:0] */ 30106a504a75SDimitris Papastamos 30116a504a75SDimitris Papastamos /* 30126a504a75SDimitris Papastamos * R1417 (0x589) - AIF2 EQ Band 3 A 30136a504a75SDimitris Papastamos */ 30146a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_A_MASK 0xFFFF /* AIF2DAC_EQ_B3_A - [15:0] */ 30156a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_A_SHIFT 0 /* AIF2DAC_EQ_B3_A - [15:0] */ 30166a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_A_WIDTH 16 /* AIF2DAC_EQ_B3_A - [15:0] */ 30176a504a75SDimitris Papastamos 30186a504a75SDimitris Papastamos /* 30196a504a75SDimitris Papastamos * R1418 (0x58A) - AIF2 EQ Band 3 B 30206a504a75SDimitris Papastamos */ 30216a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_B_MASK 0xFFFF /* AIF2DAC_EQ_B3_B - [15:0] */ 30226a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_B_SHIFT 0 /* AIF2DAC_EQ_B3_B - [15:0] */ 30236a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_B_WIDTH 16 /* AIF2DAC_EQ_B3_B - [15:0] */ 30246a504a75SDimitris Papastamos 30256a504a75SDimitris Papastamos /* 30266a504a75SDimitris Papastamos * R1419 (0x58B) - AIF2 EQ Band 3 C 30276a504a75SDimitris Papastamos */ 30286a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_C_MASK 0xFFFF /* AIF2DAC_EQ_B3_C - [15:0] */ 30296a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_C_SHIFT 0 /* AIF2DAC_EQ_B3_C - [15:0] */ 30306a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_C_WIDTH 16 /* AIF2DAC_EQ_B3_C - [15:0] */ 30316a504a75SDimitris Papastamos 30326a504a75SDimitris Papastamos /* 30336a504a75SDimitris Papastamos * R1420 (0x58C) - AIF2 EQ Band 3 PG 30346a504a75SDimitris Papastamos */ 30356a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_PG_MASK 0xFFFF /* AIF2DAC_EQ_B3_PG - [15:0] */ 30366a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_PG_SHIFT 0 /* AIF2DAC_EQ_B3_PG - [15:0] */ 30376a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B3_PG_WIDTH 16 /* AIF2DAC_EQ_B3_PG - [15:0] */ 30386a504a75SDimitris Papastamos 30396a504a75SDimitris Papastamos /* 30406a504a75SDimitris Papastamos * R1421 (0x58D) - AIF2 EQ Band 4 A 30416a504a75SDimitris Papastamos */ 30426a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_A_MASK 0xFFFF /* AIF2DAC_EQ_B4_A - [15:0] */ 30436a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_A_SHIFT 0 /* AIF2DAC_EQ_B4_A - [15:0] */ 30446a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_A_WIDTH 16 /* AIF2DAC_EQ_B4_A - [15:0] */ 30456a504a75SDimitris Papastamos 30466a504a75SDimitris Papastamos /* 30476a504a75SDimitris Papastamos * R1422 (0x58E) - AIF2 EQ Band 4 B 30486a504a75SDimitris Papastamos */ 30496a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_B_MASK 0xFFFF /* AIF2DAC_EQ_B4_B - [15:0] */ 30506a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_B_SHIFT 0 /* AIF2DAC_EQ_B4_B - [15:0] */ 30516a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_B_WIDTH 16 /* AIF2DAC_EQ_B4_B - [15:0] */ 30526a504a75SDimitris Papastamos 30536a504a75SDimitris Papastamos /* 30546a504a75SDimitris Papastamos * R1423 (0x58F) - AIF2 EQ Band 4 C 30556a504a75SDimitris Papastamos */ 30566a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_C_MASK 0xFFFF /* AIF2DAC_EQ_B4_C - [15:0] */ 30576a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_C_SHIFT 0 /* AIF2DAC_EQ_B4_C - [15:0] */ 30586a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_C_WIDTH 16 /* AIF2DAC_EQ_B4_C - [15:0] */ 30596a504a75SDimitris Papastamos 30606a504a75SDimitris Papastamos /* 30616a504a75SDimitris Papastamos * R1424 (0x590) - AIF2 EQ Band 4 PG 30626a504a75SDimitris Papastamos */ 30636a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_PG_MASK 0xFFFF /* AIF2DAC_EQ_B4_PG - [15:0] */ 30646a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_PG_SHIFT 0 /* AIF2DAC_EQ_B4_PG - [15:0] */ 30656a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B4_PG_WIDTH 16 /* AIF2DAC_EQ_B4_PG - [15:0] */ 30666a504a75SDimitris Papastamos 30676a504a75SDimitris Papastamos /* 30686a504a75SDimitris Papastamos * R1425 (0x591) - AIF2 EQ Band 5 A 30696a504a75SDimitris Papastamos */ 30706a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_A_MASK 0xFFFF /* AIF2DAC_EQ_B5_A - [15:0] */ 30716a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_A_SHIFT 0 /* AIF2DAC_EQ_B5_A - [15:0] */ 30726a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_A_WIDTH 16 /* AIF2DAC_EQ_B5_A - [15:0] */ 30736a504a75SDimitris Papastamos 30746a504a75SDimitris Papastamos /* 30756a504a75SDimitris Papastamos * R1426 (0x592) - AIF2 EQ Band 5 B 30766a504a75SDimitris Papastamos */ 30776a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_B_MASK 0xFFFF /* AIF2DAC_EQ_B5_B - [15:0] */ 30786a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_B_SHIFT 0 /* AIF2DAC_EQ_B5_B - [15:0] */ 30796a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_B_WIDTH 16 /* AIF2DAC_EQ_B5_B - [15:0] */ 30806a504a75SDimitris Papastamos 30816a504a75SDimitris Papastamos /* 30826a504a75SDimitris Papastamos * R1427 (0x593) - AIF2 EQ Band 5 PG 30836a504a75SDimitris Papastamos */ 30846a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_PG_MASK 0xFFFF /* AIF2DAC_EQ_B5_PG - [15:0] */ 30856a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_PG_SHIFT 0 /* AIF2DAC_EQ_B5_PG - [15:0] */ 30866a504a75SDimitris Papastamos #define WM8995_AIF2DAC_EQ_B5_PG_WIDTH 16 /* AIF2DAC_EQ_B5_PG - [15:0] */ 30876a504a75SDimitris Papastamos 30886a504a75SDimitris Papastamos /* 30896a504a75SDimitris Papastamos * R1536 (0x600) - DAC1 Mixer Volumes 30906a504a75SDimitris Papastamos */ 30916a504a75SDimitris Papastamos #define WM8995_ADCR_DAC1_VOL_MASK 0x03E0 /* ADCR_DAC1_VOL - [9:5] */ 30926a504a75SDimitris Papastamos #define WM8995_ADCR_DAC1_VOL_SHIFT 5 /* ADCR_DAC1_VOL - [9:5] */ 30936a504a75SDimitris Papastamos #define WM8995_ADCR_DAC1_VOL_WIDTH 5 /* ADCR_DAC1_VOL - [9:5] */ 30946a504a75SDimitris Papastamos #define WM8995_ADCL_DAC1_VOL_MASK 0x001F /* ADCL_DAC1_VOL - [4:0] */ 30956a504a75SDimitris Papastamos #define WM8995_ADCL_DAC1_VOL_SHIFT 0 /* ADCL_DAC1_VOL - [4:0] */ 30966a504a75SDimitris Papastamos #define WM8995_ADCL_DAC1_VOL_WIDTH 5 /* ADCL_DAC1_VOL - [4:0] */ 30976a504a75SDimitris Papastamos 30986a504a75SDimitris Papastamos /* 30996a504a75SDimitris Papastamos * R1537 (0x601) - DAC1 Left Mixer Routing 31006a504a75SDimitris Papastamos */ 31016a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1L 0x0020 /* ADCR_TO_DAC1L */ 31026a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1L_MASK 0x0020 /* ADCR_TO_DAC1L */ 31036a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1L_SHIFT 5 /* ADCR_TO_DAC1L */ 31046a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1L_WIDTH 1 /* ADCR_TO_DAC1L */ 31056a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1L 0x0010 /* ADCL_TO_DAC1L */ 31066a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1L_MASK 0x0010 /* ADCL_TO_DAC1L */ 31076a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1L_SHIFT 4 /* ADCL_TO_DAC1L */ 31086a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1L_WIDTH 1 /* ADCL_TO_DAC1L */ 31096a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC1L 0x0004 /* AIF2DACL_TO_DAC1L */ 31106a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC1L_MASK 0x0004 /* AIF2DACL_TO_DAC1L */ 31116a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC1L_SHIFT 2 /* AIF2DACL_TO_DAC1L */ 31126a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC1L_WIDTH 1 /* AIF2DACL_TO_DAC1L */ 31136a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC1L 0x0002 /* AIF1DAC2L_TO_DAC1L */ 31146a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC1L_MASK 0x0002 /* AIF1DAC2L_TO_DAC1L */ 31156a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC1L_SHIFT 1 /* AIF1DAC2L_TO_DAC1L */ 31166a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC1L_WIDTH 1 /* AIF1DAC2L_TO_DAC1L */ 31176a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC1L 0x0001 /* AIF1DAC1L_TO_DAC1L */ 31186a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC1L_MASK 0x0001 /* AIF1DAC1L_TO_DAC1L */ 31196a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC1L_SHIFT 0 /* AIF1DAC1L_TO_DAC1L */ 31206a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC1L_WIDTH 1 /* AIF1DAC1L_TO_DAC1L */ 31216a504a75SDimitris Papastamos 31226a504a75SDimitris Papastamos /* 31236a504a75SDimitris Papastamos * R1538 (0x602) - DAC1 Right Mixer Routing 31246a504a75SDimitris Papastamos */ 31256a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1R 0x0020 /* ADCR_TO_DAC1R */ 31266a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1R_MASK 0x0020 /* ADCR_TO_DAC1R */ 31276a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1R_SHIFT 5 /* ADCR_TO_DAC1R */ 31286a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC1R_WIDTH 1 /* ADCR_TO_DAC1R */ 31296a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1R 0x0010 /* ADCL_TO_DAC1R */ 31306a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1R_MASK 0x0010 /* ADCL_TO_DAC1R */ 31316a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1R_SHIFT 4 /* ADCL_TO_DAC1R */ 31326a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC1R_WIDTH 1 /* ADCL_TO_DAC1R */ 31336a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC1R 0x0004 /* AIF2DACR_TO_DAC1R */ 31346a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC1R_MASK 0x0004 /* AIF2DACR_TO_DAC1R */ 31356a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC1R_SHIFT 2 /* AIF2DACR_TO_DAC1R */ 31366a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC1R_WIDTH 1 /* AIF2DACR_TO_DAC1R */ 31376a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC1R 0x0002 /* AIF1DAC2R_TO_DAC1R */ 31386a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC1R_MASK 0x0002 /* AIF1DAC2R_TO_DAC1R */ 31396a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC1R_SHIFT 1 /* AIF1DAC2R_TO_DAC1R */ 31406a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC1R_WIDTH 1 /* AIF1DAC2R_TO_DAC1R */ 31416a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC1R 0x0001 /* AIF1DAC1R_TO_DAC1R */ 31426a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC1R_MASK 0x0001 /* AIF1DAC1R_TO_DAC1R */ 31436a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC1R_SHIFT 0 /* AIF1DAC1R_TO_DAC1R */ 31446a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC1R_WIDTH 1 /* AIF1DAC1R_TO_DAC1R */ 31456a504a75SDimitris Papastamos 31466a504a75SDimitris Papastamos /* 31476a504a75SDimitris Papastamos * R1539 (0x603) - DAC2 Mixer Volumes 31486a504a75SDimitris Papastamos */ 31496a504a75SDimitris Papastamos #define WM8995_ADCR_DAC2_VOL_MASK 0x03E0 /* ADCR_DAC2_VOL - [9:5] */ 31506a504a75SDimitris Papastamos #define WM8995_ADCR_DAC2_VOL_SHIFT 5 /* ADCR_DAC2_VOL - [9:5] */ 31516a504a75SDimitris Papastamos #define WM8995_ADCR_DAC2_VOL_WIDTH 5 /* ADCR_DAC2_VOL - [9:5] */ 31526a504a75SDimitris Papastamos #define WM8995_ADCL_DAC2_VOL_MASK 0x001F /* ADCL_DAC2_VOL - [4:0] */ 31536a504a75SDimitris Papastamos #define WM8995_ADCL_DAC2_VOL_SHIFT 0 /* ADCL_DAC2_VOL - [4:0] */ 31546a504a75SDimitris Papastamos #define WM8995_ADCL_DAC2_VOL_WIDTH 5 /* ADCL_DAC2_VOL - [4:0] */ 31556a504a75SDimitris Papastamos 31566a504a75SDimitris Papastamos /* 31576a504a75SDimitris Papastamos * R1540 (0x604) - DAC2 Left Mixer Routing 31586a504a75SDimitris Papastamos */ 31596a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2L 0x0020 /* ADCR_TO_DAC2L */ 31606a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2L_MASK 0x0020 /* ADCR_TO_DAC2L */ 31616a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2L_SHIFT 5 /* ADCR_TO_DAC2L */ 31626a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2L_WIDTH 1 /* ADCR_TO_DAC2L */ 31636a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2L 0x0010 /* ADCL_TO_DAC2L */ 31646a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2L_MASK 0x0010 /* ADCL_TO_DAC2L */ 31656a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2L_SHIFT 4 /* ADCL_TO_DAC2L */ 31666a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2L_WIDTH 1 /* ADCL_TO_DAC2L */ 31676a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC2L 0x0004 /* AIF2DACL_TO_DAC2L */ 31686a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC2L_MASK 0x0004 /* AIF2DACL_TO_DAC2L */ 31696a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC2L_SHIFT 2 /* AIF2DACL_TO_DAC2L */ 31706a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_DAC2L_WIDTH 1 /* AIF2DACL_TO_DAC2L */ 31716a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC2L 0x0002 /* AIF1DAC2L_TO_DAC2L */ 31726a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC2L_MASK 0x0002 /* AIF1DAC2L_TO_DAC2L */ 31736a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC2L_SHIFT 1 /* AIF1DAC2L_TO_DAC2L */ 31746a504a75SDimitris Papastamos #define WM8995_AIF1DAC2L_TO_DAC2L_WIDTH 1 /* AIF1DAC2L_TO_DAC2L */ 31756a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC2L 0x0001 /* AIF1DAC1L_TO_DAC2L */ 31766a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC2L_MASK 0x0001 /* AIF1DAC1L_TO_DAC2L */ 31776a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC2L_SHIFT 0 /* AIF1DAC1L_TO_DAC2L */ 31786a504a75SDimitris Papastamos #define WM8995_AIF1DAC1L_TO_DAC2L_WIDTH 1 /* AIF1DAC1L_TO_DAC2L */ 31796a504a75SDimitris Papastamos 31806a504a75SDimitris Papastamos /* 31816a504a75SDimitris Papastamos * R1541 (0x605) - DAC2 Right Mixer Routing 31826a504a75SDimitris Papastamos */ 31836a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2R 0x0020 /* ADCR_TO_DAC2R */ 31846a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2R_MASK 0x0020 /* ADCR_TO_DAC2R */ 31856a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2R_SHIFT 5 /* ADCR_TO_DAC2R */ 31866a504a75SDimitris Papastamos #define WM8995_ADCR_TO_DAC2R_WIDTH 1 /* ADCR_TO_DAC2R */ 31876a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2R 0x0010 /* ADCL_TO_DAC2R */ 31886a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2R_MASK 0x0010 /* ADCL_TO_DAC2R */ 31896a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2R_SHIFT 4 /* ADCL_TO_DAC2R */ 31906a504a75SDimitris Papastamos #define WM8995_ADCL_TO_DAC2R_WIDTH 1 /* ADCL_TO_DAC2R */ 31916a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC2R 0x0004 /* AIF2DACR_TO_DAC2R */ 31926a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC2R_MASK 0x0004 /* AIF2DACR_TO_DAC2R */ 31936a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC2R_SHIFT 2 /* AIF2DACR_TO_DAC2R */ 31946a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_DAC2R_WIDTH 1 /* AIF2DACR_TO_DAC2R */ 31956a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC2R 0x0002 /* AIF1DAC2R_TO_DAC2R */ 31966a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC2R_MASK 0x0002 /* AIF1DAC2R_TO_DAC2R */ 31976a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC2R_SHIFT 1 /* AIF1DAC2R_TO_DAC2R */ 31986a504a75SDimitris Papastamos #define WM8995_AIF1DAC2R_TO_DAC2R_WIDTH 1 /* AIF1DAC2R_TO_DAC2R */ 31996a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC2R 0x0001 /* AIF1DAC1R_TO_DAC2R */ 32006a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC2R_MASK 0x0001 /* AIF1DAC1R_TO_DAC2R */ 32016a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC2R_SHIFT 0 /* AIF1DAC1R_TO_DAC2R */ 32026a504a75SDimitris Papastamos #define WM8995_AIF1DAC1R_TO_DAC2R_WIDTH 1 /* AIF1DAC1R_TO_DAC2R */ 32036a504a75SDimitris Papastamos 32046a504a75SDimitris Papastamos /* 32056a504a75SDimitris Papastamos * R1542 (0x606) - AIF1 ADC1 Left Mixer Routing 32066a504a75SDimitris Papastamos */ 32076a504a75SDimitris Papastamos #define WM8995_ADC1L_TO_AIF1ADC1L 0x0002 /* ADC1L_TO_AIF1ADC1L */ 32086a504a75SDimitris Papastamos #define WM8995_ADC1L_TO_AIF1ADC1L_MASK 0x0002 /* ADC1L_TO_AIF1ADC1L */ 32096a504a75SDimitris Papastamos #define WM8995_ADC1L_TO_AIF1ADC1L_SHIFT 1 /* ADC1L_TO_AIF1ADC1L */ 32106a504a75SDimitris Papastamos #define WM8995_ADC1L_TO_AIF1ADC1L_WIDTH 1 /* ADC1L_TO_AIF1ADC1L */ 32116a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC1L 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 32126a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC1L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC1L */ 32136a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC1L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC1L */ 32146a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC1L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC1L */ 32156a504a75SDimitris Papastamos 32166a504a75SDimitris Papastamos /* 32176a504a75SDimitris Papastamos * R1543 (0x607) - AIF1 ADC1 Right Mixer Routing 32186a504a75SDimitris Papastamos */ 32196a504a75SDimitris Papastamos #define WM8995_ADC1R_TO_AIF1ADC1R 0x0002 /* ADC1R_TO_AIF1ADC1R */ 32206a504a75SDimitris Papastamos #define WM8995_ADC1R_TO_AIF1ADC1R_MASK 0x0002 /* ADC1R_TO_AIF1ADC1R */ 32216a504a75SDimitris Papastamos #define WM8995_ADC1R_TO_AIF1ADC1R_SHIFT 1 /* ADC1R_TO_AIF1ADC1R */ 32226a504a75SDimitris Papastamos #define WM8995_ADC1R_TO_AIF1ADC1R_WIDTH 1 /* ADC1R_TO_AIF1ADC1R */ 32236a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC1R 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 32246a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC1R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC1R */ 32256a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC1R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC1R */ 32266a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC1R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC1R */ 32276a504a75SDimitris Papastamos 32286a504a75SDimitris Papastamos /* 32296a504a75SDimitris Papastamos * R1544 (0x608) - AIF1 ADC2 Left Mixer Routing 32306a504a75SDimitris Papastamos */ 32316a504a75SDimitris Papastamos #define WM8995_ADC2L_TO_AIF1ADC2L 0x0002 /* ADC2L_TO_AIF1ADC2L */ 32326a504a75SDimitris Papastamos #define WM8995_ADC2L_TO_AIF1ADC2L_MASK 0x0002 /* ADC2L_TO_AIF1ADC2L */ 32336a504a75SDimitris Papastamos #define WM8995_ADC2L_TO_AIF1ADC2L_SHIFT 1 /* ADC2L_TO_AIF1ADC2L */ 32346a504a75SDimitris Papastamos #define WM8995_ADC2L_TO_AIF1ADC2L_WIDTH 1 /* ADC2L_TO_AIF1ADC2L */ 32356a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC2L 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 32366a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC2L_MASK 0x0001 /* AIF2DACL_TO_AIF1ADC2L */ 32376a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC2L_SHIFT 0 /* AIF2DACL_TO_AIF1ADC2L */ 32386a504a75SDimitris Papastamos #define WM8995_AIF2DACL_TO_AIF1ADC2L_WIDTH 1 /* AIF2DACL_TO_AIF1ADC2L */ 32396a504a75SDimitris Papastamos 32406a504a75SDimitris Papastamos /* 32416a504a75SDimitris Papastamos * R1545 (0x609) - AIF1 ADC2 Right mixer Routing 32426a504a75SDimitris Papastamos */ 32436a504a75SDimitris Papastamos #define WM8995_ADC2R_TO_AIF1ADC2R 0x0002 /* ADC2R_TO_AIF1ADC2R */ 32446a504a75SDimitris Papastamos #define WM8995_ADC2R_TO_AIF1ADC2R_MASK 0x0002 /* ADC2R_TO_AIF1ADC2R */ 32456a504a75SDimitris Papastamos #define WM8995_ADC2R_TO_AIF1ADC2R_SHIFT 1 /* ADC2R_TO_AIF1ADC2R */ 32466a504a75SDimitris Papastamos #define WM8995_ADC2R_TO_AIF1ADC2R_WIDTH 1 /* ADC2R_TO_AIF1ADC2R */ 32476a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC2R 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 32486a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC2R_MASK 0x0001 /* AIF2DACR_TO_AIF1ADC2R */ 32496a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC2R_SHIFT 0 /* AIF2DACR_TO_AIF1ADC2R */ 32506a504a75SDimitris Papastamos #define WM8995_AIF2DACR_TO_AIF1ADC2R_WIDTH 1 /* AIF2DACR_TO_AIF1ADC2R */ 32516a504a75SDimitris Papastamos 32526a504a75SDimitris Papastamos /* 32536a504a75SDimitris Papastamos * R1552 (0x610) - DAC Softmute 32546a504a75SDimitris Papastamos */ 32556a504a75SDimitris Papastamos #define WM8995_DAC_SOFTMUTEMODE 0x0002 /* DAC_SOFTMUTEMODE */ 32566a504a75SDimitris Papastamos #define WM8995_DAC_SOFTMUTEMODE_MASK 0x0002 /* DAC_SOFTMUTEMODE */ 32576a504a75SDimitris Papastamos #define WM8995_DAC_SOFTMUTEMODE_SHIFT 1 /* DAC_SOFTMUTEMODE */ 32586a504a75SDimitris Papastamos #define WM8995_DAC_SOFTMUTEMODE_WIDTH 1 /* DAC_SOFTMUTEMODE */ 32596a504a75SDimitris Papastamos #define WM8995_DAC_MUTERATE 0x0001 /* DAC_MUTERATE */ 32606a504a75SDimitris Papastamos #define WM8995_DAC_MUTERATE_MASK 0x0001 /* DAC_MUTERATE */ 32616a504a75SDimitris Papastamos #define WM8995_DAC_MUTERATE_SHIFT 0 /* DAC_MUTERATE */ 32626a504a75SDimitris Papastamos #define WM8995_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 32636a504a75SDimitris Papastamos 32646a504a75SDimitris Papastamos /* 32656a504a75SDimitris Papastamos * R1568 (0x620) - Oversampling 32666a504a75SDimitris Papastamos */ 32676a504a75SDimitris Papastamos #define WM8995_ADC_OSR128 0x0002 /* ADC_OSR128 */ 32686a504a75SDimitris Papastamos #define WM8995_ADC_OSR128_MASK 0x0002 /* ADC_OSR128 */ 32696a504a75SDimitris Papastamos #define WM8995_ADC_OSR128_SHIFT 1 /* ADC_OSR128 */ 32706a504a75SDimitris Papastamos #define WM8995_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 32716a504a75SDimitris Papastamos #define WM8995_DAC_OSR128 0x0001 /* DAC_OSR128 */ 32726a504a75SDimitris Papastamos #define WM8995_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ 32736a504a75SDimitris Papastamos #define WM8995_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ 32746a504a75SDimitris Papastamos #define WM8995_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ 32756a504a75SDimitris Papastamos 32766a504a75SDimitris Papastamos /* 32776a504a75SDimitris Papastamos * R1569 (0x621) - Sidetone 32786a504a75SDimitris Papastamos */ 32796a504a75SDimitris Papastamos #define WM8995_ST_LPF 0x1000 /* ST_LPF */ 32806a504a75SDimitris Papastamos #define WM8995_ST_LPF_MASK 0x1000 /* ST_LPF */ 32816a504a75SDimitris Papastamos #define WM8995_ST_LPF_SHIFT 12 /* ST_LPF */ 32826a504a75SDimitris Papastamos #define WM8995_ST_LPF_WIDTH 1 /* ST_LPF */ 32836a504a75SDimitris Papastamos #define WM8995_ST_HPF_CUT_MASK 0x0380 /* ST_HPF_CUT - [9:7] */ 32846a504a75SDimitris Papastamos #define WM8995_ST_HPF_CUT_SHIFT 7 /* ST_HPF_CUT - [9:7] */ 32856a504a75SDimitris Papastamos #define WM8995_ST_HPF_CUT_WIDTH 3 /* ST_HPF_CUT - [9:7] */ 32866a504a75SDimitris Papastamos #define WM8995_ST_HPF 0x0040 /* ST_HPF */ 32876a504a75SDimitris Papastamos #define WM8995_ST_HPF_MASK 0x0040 /* ST_HPF */ 32886a504a75SDimitris Papastamos #define WM8995_ST_HPF_SHIFT 6 /* ST_HPF */ 32896a504a75SDimitris Papastamos #define WM8995_ST_HPF_WIDTH 1 /* ST_HPF */ 32906a504a75SDimitris Papastamos #define WM8995_STR_SEL 0x0002 /* STR_SEL */ 32916a504a75SDimitris Papastamos #define WM8995_STR_SEL_MASK 0x0002 /* STR_SEL */ 32926a504a75SDimitris Papastamos #define WM8995_STR_SEL_SHIFT 1 /* STR_SEL */ 32936a504a75SDimitris Papastamos #define WM8995_STR_SEL_WIDTH 1 /* STR_SEL */ 32946a504a75SDimitris Papastamos #define WM8995_STL_SEL 0x0001 /* STL_SEL */ 32956a504a75SDimitris Papastamos #define WM8995_STL_SEL_MASK 0x0001 /* STL_SEL */ 32966a504a75SDimitris Papastamos #define WM8995_STL_SEL_SHIFT 0 /* STL_SEL */ 32976a504a75SDimitris Papastamos #define WM8995_STL_SEL_WIDTH 1 /* STL_SEL */ 32986a504a75SDimitris Papastamos 32996a504a75SDimitris Papastamos /* 33006a504a75SDimitris Papastamos * R1792 (0x700) - GPIO 1 33016a504a75SDimitris Papastamos */ 33026a504a75SDimitris Papastamos #define WM8995_GP1_DIR 0x8000 /* GP1_DIR */ 33036a504a75SDimitris Papastamos #define WM8995_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 33046a504a75SDimitris Papastamos #define WM8995_GP1_DIR_SHIFT 15 /* GP1_DIR */ 33056a504a75SDimitris Papastamos #define WM8995_GP1_DIR_WIDTH 1 /* GP1_DIR */ 33066a504a75SDimitris Papastamos #define WM8995_GP1_PU 0x4000 /* GP1_PU */ 33076a504a75SDimitris Papastamos #define WM8995_GP1_PU_MASK 0x4000 /* GP1_PU */ 33086a504a75SDimitris Papastamos #define WM8995_GP1_PU_SHIFT 14 /* GP1_PU */ 33096a504a75SDimitris Papastamos #define WM8995_GP1_PU_WIDTH 1 /* GP1_PU */ 33106a504a75SDimitris Papastamos #define WM8995_GP1_PD 0x2000 /* GP1_PD */ 33116a504a75SDimitris Papastamos #define WM8995_GP1_PD_MASK 0x2000 /* GP1_PD */ 33126a504a75SDimitris Papastamos #define WM8995_GP1_PD_SHIFT 13 /* GP1_PD */ 33136a504a75SDimitris Papastamos #define WM8995_GP1_PD_WIDTH 1 /* GP1_PD */ 33146a504a75SDimitris Papastamos #define WM8995_GP1_POL 0x0400 /* GP1_POL */ 33156a504a75SDimitris Papastamos #define WM8995_GP1_POL_MASK 0x0400 /* GP1_POL */ 33166a504a75SDimitris Papastamos #define WM8995_GP1_POL_SHIFT 10 /* GP1_POL */ 33176a504a75SDimitris Papastamos #define WM8995_GP1_POL_WIDTH 1 /* GP1_POL */ 33186a504a75SDimitris Papastamos #define WM8995_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 33196a504a75SDimitris Papastamos #define WM8995_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 33206a504a75SDimitris Papastamos #define WM8995_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 33216a504a75SDimitris Papastamos #define WM8995_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 33226a504a75SDimitris Papastamos #define WM8995_GP1_DB 0x0100 /* GP1_DB */ 33236a504a75SDimitris Papastamos #define WM8995_GP1_DB_MASK 0x0100 /* GP1_DB */ 33246a504a75SDimitris Papastamos #define WM8995_GP1_DB_SHIFT 8 /* GP1_DB */ 33256a504a75SDimitris Papastamos #define WM8995_GP1_DB_WIDTH 1 /* GP1_DB */ 33266a504a75SDimitris Papastamos #define WM8995_GP1_LVL 0x0040 /* GP1_LVL */ 33276a504a75SDimitris Papastamos #define WM8995_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 33286a504a75SDimitris Papastamos #define WM8995_GP1_LVL_SHIFT 6 /* GP1_LVL */ 33296a504a75SDimitris Papastamos #define WM8995_GP1_LVL_WIDTH 1 /* GP1_LVL */ 33306a504a75SDimitris Papastamos #define WM8995_GP1_FN_MASK 0x001F /* GP1_FN - [4:0] */ 33316a504a75SDimitris Papastamos #define WM8995_GP1_FN_SHIFT 0 /* GP1_FN - [4:0] */ 33326a504a75SDimitris Papastamos #define WM8995_GP1_FN_WIDTH 5 /* GP1_FN - [4:0] */ 33336a504a75SDimitris Papastamos 33346a504a75SDimitris Papastamos /* 33356a504a75SDimitris Papastamos * R1793 (0x701) - GPIO 2 33366a504a75SDimitris Papastamos */ 33376a504a75SDimitris Papastamos #define WM8995_GP2_DIR 0x8000 /* GP2_DIR */ 33386a504a75SDimitris Papastamos #define WM8995_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 33396a504a75SDimitris Papastamos #define WM8995_GP2_DIR_SHIFT 15 /* GP2_DIR */ 33406a504a75SDimitris Papastamos #define WM8995_GP2_DIR_WIDTH 1 /* GP2_DIR */ 33416a504a75SDimitris Papastamos #define WM8995_GP2_PU 0x4000 /* GP2_PU */ 33426a504a75SDimitris Papastamos #define WM8995_GP2_PU_MASK 0x4000 /* GP2_PU */ 33436a504a75SDimitris Papastamos #define WM8995_GP2_PU_SHIFT 14 /* GP2_PU */ 33446a504a75SDimitris Papastamos #define WM8995_GP2_PU_WIDTH 1 /* GP2_PU */ 33456a504a75SDimitris Papastamos #define WM8995_GP2_PD 0x2000 /* GP2_PD */ 33466a504a75SDimitris Papastamos #define WM8995_GP2_PD_MASK 0x2000 /* GP2_PD */ 33476a504a75SDimitris Papastamos #define WM8995_GP2_PD_SHIFT 13 /* GP2_PD */ 33486a504a75SDimitris Papastamos #define WM8995_GP2_PD_WIDTH 1 /* GP2_PD */ 33496a504a75SDimitris Papastamos #define WM8995_GP2_POL 0x0400 /* GP2_POL */ 33506a504a75SDimitris Papastamos #define WM8995_GP2_POL_MASK 0x0400 /* GP2_POL */ 33516a504a75SDimitris Papastamos #define WM8995_GP2_POL_SHIFT 10 /* GP2_POL */ 33526a504a75SDimitris Papastamos #define WM8995_GP2_POL_WIDTH 1 /* GP2_POL */ 33536a504a75SDimitris Papastamos #define WM8995_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 33546a504a75SDimitris Papastamos #define WM8995_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 33556a504a75SDimitris Papastamos #define WM8995_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 33566a504a75SDimitris Papastamos #define WM8995_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 33576a504a75SDimitris Papastamos #define WM8995_GP2_DB 0x0100 /* GP2_DB */ 33586a504a75SDimitris Papastamos #define WM8995_GP2_DB_MASK 0x0100 /* GP2_DB */ 33596a504a75SDimitris Papastamos #define WM8995_GP2_DB_SHIFT 8 /* GP2_DB */ 33606a504a75SDimitris Papastamos #define WM8995_GP2_DB_WIDTH 1 /* GP2_DB */ 33616a504a75SDimitris Papastamos #define WM8995_GP2_LVL 0x0040 /* GP2_LVL */ 33626a504a75SDimitris Papastamos #define WM8995_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 33636a504a75SDimitris Papastamos #define WM8995_GP2_LVL_SHIFT 6 /* GP2_LVL */ 33646a504a75SDimitris Papastamos #define WM8995_GP2_LVL_WIDTH 1 /* GP2_LVL */ 33656a504a75SDimitris Papastamos #define WM8995_GP2_FN_MASK 0x001F /* GP2_FN - [4:0] */ 33666a504a75SDimitris Papastamos #define WM8995_GP2_FN_SHIFT 0 /* GP2_FN - [4:0] */ 33676a504a75SDimitris Papastamos #define WM8995_GP2_FN_WIDTH 5 /* GP2_FN - [4:0] */ 33686a504a75SDimitris Papastamos 33696a504a75SDimitris Papastamos /* 33706a504a75SDimitris Papastamos * R1794 (0x702) - GPIO 3 33716a504a75SDimitris Papastamos */ 33726a504a75SDimitris Papastamos #define WM8995_GP3_DIR 0x8000 /* GP3_DIR */ 33736a504a75SDimitris Papastamos #define WM8995_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 33746a504a75SDimitris Papastamos #define WM8995_GP3_DIR_SHIFT 15 /* GP3_DIR */ 33756a504a75SDimitris Papastamos #define WM8995_GP3_DIR_WIDTH 1 /* GP3_DIR */ 33766a504a75SDimitris Papastamos #define WM8995_GP3_PU 0x4000 /* GP3_PU */ 33776a504a75SDimitris Papastamos #define WM8995_GP3_PU_MASK 0x4000 /* GP3_PU */ 33786a504a75SDimitris Papastamos #define WM8995_GP3_PU_SHIFT 14 /* GP3_PU */ 33796a504a75SDimitris Papastamos #define WM8995_GP3_PU_WIDTH 1 /* GP3_PU */ 33806a504a75SDimitris Papastamos #define WM8995_GP3_PD 0x2000 /* GP3_PD */ 33816a504a75SDimitris Papastamos #define WM8995_GP3_PD_MASK 0x2000 /* GP3_PD */ 33826a504a75SDimitris Papastamos #define WM8995_GP3_PD_SHIFT 13 /* GP3_PD */ 33836a504a75SDimitris Papastamos #define WM8995_GP3_PD_WIDTH 1 /* GP3_PD */ 33846a504a75SDimitris Papastamos #define WM8995_GP3_POL 0x0400 /* GP3_POL */ 33856a504a75SDimitris Papastamos #define WM8995_GP3_POL_MASK 0x0400 /* GP3_POL */ 33866a504a75SDimitris Papastamos #define WM8995_GP3_POL_SHIFT 10 /* GP3_POL */ 33876a504a75SDimitris Papastamos #define WM8995_GP3_POL_WIDTH 1 /* GP3_POL */ 33886a504a75SDimitris Papastamos #define WM8995_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 33896a504a75SDimitris Papastamos #define WM8995_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 33906a504a75SDimitris Papastamos #define WM8995_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 33916a504a75SDimitris Papastamos #define WM8995_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 33926a504a75SDimitris Papastamos #define WM8995_GP3_DB 0x0100 /* GP3_DB */ 33936a504a75SDimitris Papastamos #define WM8995_GP3_DB_MASK 0x0100 /* GP3_DB */ 33946a504a75SDimitris Papastamos #define WM8995_GP3_DB_SHIFT 8 /* GP3_DB */ 33956a504a75SDimitris Papastamos #define WM8995_GP3_DB_WIDTH 1 /* GP3_DB */ 33966a504a75SDimitris Papastamos #define WM8995_GP3_LVL 0x0040 /* GP3_LVL */ 33976a504a75SDimitris Papastamos #define WM8995_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 33986a504a75SDimitris Papastamos #define WM8995_GP3_LVL_SHIFT 6 /* GP3_LVL */ 33996a504a75SDimitris Papastamos #define WM8995_GP3_LVL_WIDTH 1 /* GP3_LVL */ 34006a504a75SDimitris Papastamos #define WM8995_GP3_FN_MASK 0x001F /* GP3_FN - [4:0] */ 34016a504a75SDimitris Papastamos #define WM8995_GP3_FN_SHIFT 0 /* GP3_FN - [4:0] */ 34026a504a75SDimitris Papastamos #define WM8995_GP3_FN_WIDTH 5 /* GP3_FN - [4:0] */ 34036a504a75SDimitris Papastamos 34046a504a75SDimitris Papastamos /* 34056a504a75SDimitris Papastamos * R1795 (0x703) - GPIO 4 34066a504a75SDimitris Papastamos */ 34076a504a75SDimitris Papastamos #define WM8995_GP4_DIR 0x8000 /* GP4_DIR */ 34086a504a75SDimitris Papastamos #define WM8995_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 34096a504a75SDimitris Papastamos #define WM8995_GP4_DIR_SHIFT 15 /* GP4_DIR */ 34106a504a75SDimitris Papastamos #define WM8995_GP4_DIR_WIDTH 1 /* GP4_DIR */ 34116a504a75SDimitris Papastamos #define WM8995_GP4_PU 0x4000 /* GP4_PU */ 34126a504a75SDimitris Papastamos #define WM8995_GP4_PU_MASK 0x4000 /* GP4_PU */ 34136a504a75SDimitris Papastamos #define WM8995_GP4_PU_SHIFT 14 /* GP4_PU */ 34146a504a75SDimitris Papastamos #define WM8995_GP4_PU_WIDTH 1 /* GP4_PU */ 34156a504a75SDimitris Papastamos #define WM8995_GP4_PD 0x2000 /* GP4_PD */ 34166a504a75SDimitris Papastamos #define WM8995_GP4_PD_MASK 0x2000 /* GP4_PD */ 34176a504a75SDimitris Papastamos #define WM8995_GP4_PD_SHIFT 13 /* GP4_PD */ 34186a504a75SDimitris Papastamos #define WM8995_GP4_PD_WIDTH 1 /* GP4_PD */ 34196a504a75SDimitris Papastamos #define WM8995_GP4_POL 0x0400 /* GP4_POL */ 34206a504a75SDimitris Papastamos #define WM8995_GP4_POL_MASK 0x0400 /* GP4_POL */ 34216a504a75SDimitris Papastamos #define WM8995_GP4_POL_SHIFT 10 /* GP4_POL */ 34226a504a75SDimitris Papastamos #define WM8995_GP4_POL_WIDTH 1 /* GP4_POL */ 34236a504a75SDimitris Papastamos #define WM8995_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 34246a504a75SDimitris Papastamos #define WM8995_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 34256a504a75SDimitris Papastamos #define WM8995_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 34266a504a75SDimitris Papastamos #define WM8995_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 34276a504a75SDimitris Papastamos #define WM8995_GP4_DB 0x0100 /* GP4_DB */ 34286a504a75SDimitris Papastamos #define WM8995_GP4_DB_MASK 0x0100 /* GP4_DB */ 34296a504a75SDimitris Papastamos #define WM8995_GP4_DB_SHIFT 8 /* GP4_DB */ 34306a504a75SDimitris Papastamos #define WM8995_GP4_DB_WIDTH 1 /* GP4_DB */ 34316a504a75SDimitris Papastamos #define WM8995_GP4_LVL 0x0040 /* GP4_LVL */ 34326a504a75SDimitris Papastamos #define WM8995_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 34336a504a75SDimitris Papastamos #define WM8995_GP4_LVL_SHIFT 6 /* GP4_LVL */ 34346a504a75SDimitris Papastamos #define WM8995_GP4_LVL_WIDTH 1 /* GP4_LVL */ 34356a504a75SDimitris Papastamos #define WM8995_GP4_FN_MASK 0x001F /* GP4_FN - [4:0] */ 34366a504a75SDimitris Papastamos #define WM8995_GP4_FN_SHIFT 0 /* GP4_FN - [4:0] */ 34376a504a75SDimitris Papastamos #define WM8995_GP4_FN_WIDTH 5 /* GP4_FN - [4:0] */ 34386a504a75SDimitris Papastamos 34396a504a75SDimitris Papastamos /* 34406a504a75SDimitris Papastamos * R1796 (0x704) - GPIO 5 34416a504a75SDimitris Papastamos */ 34426a504a75SDimitris Papastamos #define WM8995_GP5_DIR 0x8000 /* GP5_DIR */ 34436a504a75SDimitris Papastamos #define WM8995_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 34446a504a75SDimitris Papastamos #define WM8995_GP5_DIR_SHIFT 15 /* GP5_DIR */ 34456a504a75SDimitris Papastamos #define WM8995_GP5_DIR_WIDTH 1 /* GP5_DIR */ 34466a504a75SDimitris Papastamos #define WM8995_GP5_PU 0x4000 /* GP5_PU */ 34476a504a75SDimitris Papastamos #define WM8995_GP5_PU_MASK 0x4000 /* GP5_PU */ 34486a504a75SDimitris Papastamos #define WM8995_GP5_PU_SHIFT 14 /* GP5_PU */ 34496a504a75SDimitris Papastamos #define WM8995_GP5_PU_WIDTH 1 /* GP5_PU */ 34506a504a75SDimitris Papastamos #define WM8995_GP5_PD 0x2000 /* GP5_PD */ 34516a504a75SDimitris Papastamos #define WM8995_GP5_PD_MASK 0x2000 /* GP5_PD */ 34526a504a75SDimitris Papastamos #define WM8995_GP5_PD_SHIFT 13 /* GP5_PD */ 34536a504a75SDimitris Papastamos #define WM8995_GP5_PD_WIDTH 1 /* GP5_PD */ 34546a504a75SDimitris Papastamos #define WM8995_GP5_POL 0x0400 /* GP5_POL */ 34556a504a75SDimitris Papastamos #define WM8995_GP5_POL_MASK 0x0400 /* GP5_POL */ 34566a504a75SDimitris Papastamos #define WM8995_GP5_POL_SHIFT 10 /* GP5_POL */ 34576a504a75SDimitris Papastamos #define WM8995_GP5_POL_WIDTH 1 /* GP5_POL */ 34586a504a75SDimitris Papastamos #define WM8995_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 34596a504a75SDimitris Papastamos #define WM8995_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 34606a504a75SDimitris Papastamos #define WM8995_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 34616a504a75SDimitris Papastamos #define WM8995_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 34626a504a75SDimitris Papastamos #define WM8995_GP5_DB 0x0100 /* GP5_DB */ 34636a504a75SDimitris Papastamos #define WM8995_GP5_DB_MASK 0x0100 /* GP5_DB */ 34646a504a75SDimitris Papastamos #define WM8995_GP5_DB_SHIFT 8 /* GP5_DB */ 34656a504a75SDimitris Papastamos #define WM8995_GP5_DB_WIDTH 1 /* GP5_DB */ 34666a504a75SDimitris Papastamos #define WM8995_GP5_LVL 0x0040 /* GP5_LVL */ 34676a504a75SDimitris Papastamos #define WM8995_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 34686a504a75SDimitris Papastamos #define WM8995_GP5_LVL_SHIFT 6 /* GP5_LVL */ 34696a504a75SDimitris Papastamos #define WM8995_GP5_LVL_WIDTH 1 /* GP5_LVL */ 34706a504a75SDimitris Papastamos #define WM8995_GP5_FN_MASK 0x001F /* GP5_FN - [4:0] */ 34716a504a75SDimitris Papastamos #define WM8995_GP5_FN_SHIFT 0 /* GP5_FN - [4:0] */ 34726a504a75SDimitris Papastamos #define WM8995_GP5_FN_WIDTH 5 /* GP5_FN - [4:0] */ 34736a504a75SDimitris Papastamos 34746a504a75SDimitris Papastamos /* 34756a504a75SDimitris Papastamos * R1797 (0x705) - GPIO 6 34766a504a75SDimitris Papastamos */ 34776a504a75SDimitris Papastamos #define WM8995_GP6_DIR 0x8000 /* GP6_DIR */ 34786a504a75SDimitris Papastamos #define WM8995_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 34796a504a75SDimitris Papastamos #define WM8995_GP6_DIR_SHIFT 15 /* GP6_DIR */ 34806a504a75SDimitris Papastamos #define WM8995_GP6_DIR_WIDTH 1 /* GP6_DIR */ 34816a504a75SDimitris Papastamos #define WM8995_GP6_PU 0x4000 /* GP6_PU */ 34826a504a75SDimitris Papastamos #define WM8995_GP6_PU_MASK 0x4000 /* GP6_PU */ 34836a504a75SDimitris Papastamos #define WM8995_GP6_PU_SHIFT 14 /* GP6_PU */ 34846a504a75SDimitris Papastamos #define WM8995_GP6_PU_WIDTH 1 /* GP6_PU */ 34856a504a75SDimitris Papastamos #define WM8995_GP6_PD 0x2000 /* GP6_PD */ 34866a504a75SDimitris Papastamos #define WM8995_GP6_PD_MASK 0x2000 /* GP6_PD */ 34876a504a75SDimitris Papastamos #define WM8995_GP6_PD_SHIFT 13 /* GP6_PD */ 34886a504a75SDimitris Papastamos #define WM8995_GP6_PD_WIDTH 1 /* GP6_PD */ 34896a504a75SDimitris Papastamos #define WM8995_GP6_POL 0x0400 /* GP6_POL */ 34906a504a75SDimitris Papastamos #define WM8995_GP6_POL_MASK 0x0400 /* GP6_POL */ 34916a504a75SDimitris Papastamos #define WM8995_GP6_POL_SHIFT 10 /* GP6_POL */ 34926a504a75SDimitris Papastamos #define WM8995_GP6_POL_WIDTH 1 /* GP6_POL */ 34936a504a75SDimitris Papastamos #define WM8995_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 34946a504a75SDimitris Papastamos #define WM8995_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 34956a504a75SDimitris Papastamos #define WM8995_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 34966a504a75SDimitris Papastamos #define WM8995_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 34976a504a75SDimitris Papastamos #define WM8995_GP6_DB 0x0100 /* GP6_DB */ 34986a504a75SDimitris Papastamos #define WM8995_GP6_DB_MASK 0x0100 /* GP6_DB */ 34996a504a75SDimitris Papastamos #define WM8995_GP6_DB_SHIFT 8 /* GP6_DB */ 35006a504a75SDimitris Papastamos #define WM8995_GP6_DB_WIDTH 1 /* GP6_DB */ 35016a504a75SDimitris Papastamos #define WM8995_GP6_LVL 0x0040 /* GP6_LVL */ 35026a504a75SDimitris Papastamos #define WM8995_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 35036a504a75SDimitris Papastamos #define WM8995_GP6_LVL_SHIFT 6 /* GP6_LVL */ 35046a504a75SDimitris Papastamos #define WM8995_GP6_LVL_WIDTH 1 /* GP6_LVL */ 35056a504a75SDimitris Papastamos #define WM8995_GP6_FN_MASK 0x001F /* GP6_FN - [4:0] */ 35066a504a75SDimitris Papastamos #define WM8995_GP6_FN_SHIFT 0 /* GP6_FN - [4:0] */ 35076a504a75SDimitris Papastamos #define WM8995_GP6_FN_WIDTH 5 /* GP6_FN - [4:0] */ 35086a504a75SDimitris Papastamos 35096a504a75SDimitris Papastamos /* 35106a504a75SDimitris Papastamos * R1798 (0x706) - GPIO 7 35116a504a75SDimitris Papastamos */ 35126a504a75SDimitris Papastamos #define WM8995_GP7_DIR 0x8000 /* GP7_DIR */ 35136a504a75SDimitris Papastamos #define WM8995_GP7_DIR_MASK 0x8000 /* GP7_DIR */ 35146a504a75SDimitris Papastamos #define WM8995_GP7_DIR_SHIFT 15 /* GP7_DIR */ 35156a504a75SDimitris Papastamos #define WM8995_GP7_DIR_WIDTH 1 /* GP7_DIR */ 35166a504a75SDimitris Papastamos #define WM8995_GP7_PU 0x4000 /* GP7_PU */ 35176a504a75SDimitris Papastamos #define WM8995_GP7_PU_MASK 0x4000 /* GP7_PU */ 35186a504a75SDimitris Papastamos #define WM8995_GP7_PU_SHIFT 14 /* GP7_PU */ 35196a504a75SDimitris Papastamos #define WM8995_GP7_PU_WIDTH 1 /* GP7_PU */ 35206a504a75SDimitris Papastamos #define WM8995_GP7_PD 0x2000 /* GP7_PD */ 35216a504a75SDimitris Papastamos #define WM8995_GP7_PD_MASK 0x2000 /* GP7_PD */ 35226a504a75SDimitris Papastamos #define WM8995_GP7_PD_SHIFT 13 /* GP7_PD */ 35236a504a75SDimitris Papastamos #define WM8995_GP7_PD_WIDTH 1 /* GP7_PD */ 35246a504a75SDimitris Papastamos #define WM8995_GP7_POL 0x0400 /* GP7_POL */ 35256a504a75SDimitris Papastamos #define WM8995_GP7_POL_MASK 0x0400 /* GP7_POL */ 35266a504a75SDimitris Papastamos #define WM8995_GP7_POL_SHIFT 10 /* GP7_POL */ 35276a504a75SDimitris Papastamos #define WM8995_GP7_POL_WIDTH 1 /* GP7_POL */ 35286a504a75SDimitris Papastamos #define WM8995_GP7_OP_CFG 0x0200 /* GP7_OP_CFG */ 35296a504a75SDimitris Papastamos #define WM8995_GP7_OP_CFG_MASK 0x0200 /* GP7_OP_CFG */ 35306a504a75SDimitris Papastamos #define WM8995_GP7_OP_CFG_SHIFT 9 /* GP7_OP_CFG */ 35316a504a75SDimitris Papastamos #define WM8995_GP7_OP_CFG_WIDTH 1 /* GP7_OP_CFG */ 35326a504a75SDimitris Papastamos #define WM8995_GP7_DB 0x0100 /* GP7_DB */ 35336a504a75SDimitris Papastamos #define WM8995_GP7_DB_MASK 0x0100 /* GP7_DB */ 35346a504a75SDimitris Papastamos #define WM8995_GP7_DB_SHIFT 8 /* GP7_DB */ 35356a504a75SDimitris Papastamos #define WM8995_GP7_DB_WIDTH 1 /* GP7_DB */ 35366a504a75SDimitris Papastamos #define WM8995_GP7_LVL 0x0040 /* GP7_LVL */ 35376a504a75SDimitris Papastamos #define WM8995_GP7_LVL_MASK 0x0040 /* GP7_LVL */ 35386a504a75SDimitris Papastamos #define WM8995_GP7_LVL_SHIFT 6 /* GP7_LVL */ 35396a504a75SDimitris Papastamos #define WM8995_GP7_LVL_WIDTH 1 /* GP7_LVL */ 35406a504a75SDimitris Papastamos #define WM8995_GP7_FN_MASK 0x001F /* GP7_FN - [4:0] */ 35416a504a75SDimitris Papastamos #define WM8995_GP7_FN_SHIFT 0 /* GP7_FN - [4:0] */ 35426a504a75SDimitris Papastamos #define WM8995_GP7_FN_WIDTH 5 /* GP7_FN - [4:0] */ 35436a504a75SDimitris Papastamos 35446a504a75SDimitris Papastamos /* 35456a504a75SDimitris Papastamos * R1799 (0x707) - GPIO 8 35466a504a75SDimitris Papastamos */ 35476a504a75SDimitris Papastamos #define WM8995_GP8_DIR 0x8000 /* GP8_DIR */ 35486a504a75SDimitris Papastamos #define WM8995_GP8_DIR_MASK 0x8000 /* GP8_DIR */ 35496a504a75SDimitris Papastamos #define WM8995_GP8_DIR_SHIFT 15 /* GP8_DIR */ 35506a504a75SDimitris Papastamos #define WM8995_GP8_DIR_WIDTH 1 /* GP8_DIR */ 35516a504a75SDimitris Papastamos #define WM8995_GP8_PU 0x4000 /* GP8_PU */ 35526a504a75SDimitris Papastamos #define WM8995_GP8_PU_MASK 0x4000 /* GP8_PU */ 35536a504a75SDimitris Papastamos #define WM8995_GP8_PU_SHIFT 14 /* GP8_PU */ 35546a504a75SDimitris Papastamos #define WM8995_GP8_PU_WIDTH 1 /* GP8_PU */ 35556a504a75SDimitris Papastamos #define WM8995_GP8_PD 0x2000 /* GP8_PD */ 35566a504a75SDimitris Papastamos #define WM8995_GP8_PD_MASK 0x2000 /* GP8_PD */ 35576a504a75SDimitris Papastamos #define WM8995_GP8_PD_SHIFT 13 /* GP8_PD */ 35586a504a75SDimitris Papastamos #define WM8995_GP8_PD_WIDTH 1 /* GP8_PD */ 35596a504a75SDimitris Papastamos #define WM8995_GP8_POL 0x0400 /* GP8_POL */ 35606a504a75SDimitris Papastamos #define WM8995_GP8_POL_MASK 0x0400 /* GP8_POL */ 35616a504a75SDimitris Papastamos #define WM8995_GP8_POL_SHIFT 10 /* GP8_POL */ 35626a504a75SDimitris Papastamos #define WM8995_GP8_POL_WIDTH 1 /* GP8_POL */ 35636a504a75SDimitris Papastamos #define WM8995_GP8_OP_CFG 0x0200 /* GP8_OP_CFG */ 35646a504a75SDimitris Papastamos #define WM8995_GP8_OP_CFG_MASK 0x0200 /* GP8_OP_CFG */ 35656a504a75SDimitris Papastamos #define WM8995_GP8_OP_CFG_SHIFT 9 /* GP8_OP_CFG */ 35666a504a75SDimitris Papastamos #define WM8995_GP8_OP_CFG_WIDTH 1 /* GP8_OP_CFG */ 35676a504a75SDimitris Papastamos #define WM8995_GP8_DB 0x0100 /* GP8_DB */ 35686a504a75SDimitris Papastamos #define WM8995_GP8_DB_MASK 0x0100 /* GP8_DB */ 35696a504a75SDimitris Papastamos #define WM8995_GP8_DB_SHIFT 8 /* GP8_DB */ 35706a504a75SDimitris Papastamos #define WM8995_GP8_DB_WIDTH 1 /* GP8_DB */ 35716a504a75SDimitris Papastamos #define WM8995_GP8_LVL 0x0040 /* GP8_LVL */ 35726a504a75SDimitris Papastamos #define WM8995_GP8_LVL_MASK 0x0040 /* GP8_LVL */ 35736a504a75SDimitris Papastamos #define WM8995_GP8_LVL_SHIFT 6 /* GP8_LVL */ 35746a504a75SDimitris Papastamos #define WM8995_GP8_LVL_WIDTH 1 /* GP8_LVL */ 35756a504a75SDimitris Papastamos #define WM8995_GP8_FN_MASK 0x001F /* GP8_FN - [4:0] */ 35766a504a75SDimitris Papastamos #define WM8995_GP8_FN_SHIFT 0 /* GP8_FN - [4:0] */ 35776a504a75SDimitris Papastamos #define WM8995_GP8_FN_WIDTH 5 /* GP8_FN - [4:0] */ 35786a504a75SDimitris Papastamos 35796a504a75SDimitris Papastamos /* 35806a504a75SDimitris Papastamos * R1800 (0x708) - GPIO 9 35816a504a75SDimitris Papastamos */ 35826a504a75SDimitris Papastamos #define WM8995_GP9_DIR 0x8000 /* GP9_DIR */ 35836a504a75SDimitris Papastamos #define WM8995_GP9_DIR_MASK 0x8000 /* GP9_DIR */ 35846a504a75SDimitris Papastamos #define WM8995_GP9_DIR_SHIFT 15 /* GP9_DIR */ 35856a504a75SDimitris Papastamos #define WM8995_GP9_DIR_WIDTH 1 /* GP9_DIR */ 35866a504a75SDimitris Papastamos #define WM8995_GP9_PU 0x4000 /* GP9_PU */ 35876a504a75SDimitris Papastamos #define WM8995_GP9_PU_MASK 0x4000 /* GP9_PU */ 35886a504a75SDimitris Papastamos #define WM8995_GP9_PU_SHIFT 14 /* GP9_PU */ 35896a504a75SDimitris Papastamos #define WM8995_GP9_PU_WIDTH 1 /* GP9_PU */ 35906a504a75SDimitris Papastamos #define WM8995_GP9_PD 0x2000 /* GP9_PD */ 35916a504a75SDimitris Papastamos #define WM8995_GP9_PD_MASK 0x2000 /* GP9_PD */ 35926a504a75SDimitris Papastamos #define WM8995_GP9_PD_SHIFT 13 /* GP9_PD */ 35936a504a75SDimitris Papastamos #define WM8995_GP9_PD_WIDTH 1 /* GP9_PD */ 35946a504a75SDimitris Papastamos #define WM8995_GP9_POL 0x0400 /* GP9_POL */ 35956a504a75SDimitris Papastamos #define WM8995_GP9_POL_MASK 0x0400 /* GP9_POL */ 35966a504a75SDimitris Papastamos #define WM8995_GP9_POL_SHIFT 10 /* GP9_POL */ 35976a504a75SDimitris Papastamos #define WM8995_GP9_POL_WIDTH 1 /* GP9_POL */ 35986a504a75SDimitris Papastamos #define WM8995_GP9_OP_CFG 0x0200 /* GP9_OP_CFG */ 35996a504a75SDimitris Papastamos #define WM8995_GP9_OP_CFG_MASK 0x0200 /* GP9_OP_CFG */ 36006a504a75SDimitris Papastamos #define WM8995_GP9_OP_CFG_SHIFT 9 /* GP9_OP_CFG */ 36016a504a75SDimitris Papastamos #define WM8995_GP9_OP_CFG_WIDTH 1 /* GP9_OP_CFG */ 36026a504a75SDimitris Papastamos #define WM8995_GP9_DB 0x0100 /* GP9_DB */ 36036a504a75SDimitris Papastamos #define WM8995_GP9_DB_MASK 0x0100 /* GP9_DB */ 36046a504a75SDimitris Papastamos #define WM8995_GP9_DB_SHIFT 8 /* GP9_DB */ 36056a504a75SDimitris Papastamos #define WM8995_GP9_DB_WIDTH 1 /* GP9_DB */ 36066a504a75SDimitris Papastamos #define WM8995_GP9_LVL 0x0040 /* GP9_LVL */ 36076a504a75SDimitris Papastamos #define WM8995_GP9_LVL_MASK 0x0040 /* GP9_LVL */ 36086a504a75SDimitris Papastamos #define WM8995_GP9_LVL_SHIFT 6 /* GP9_LVL */ 36096a504a75SDimitris Papastamos #define WM8995_GP9_LVL_WIDTH 1 /* GP9_LVL */ 36106a504a75SDimitris Papastamos #define WM8995_GP9_FN_MASK 0x001F /* GP9_FN - [4:0] */ 36116a504a75SDimitris Papastamos #define WM8995_GP9_FN_SHIFT 0 /* GP9_FN - [4:0] */ 36126a504a75SDimitris Papastamos #define WM8995_GP9_FN_WIDTH 5 /* GP9_FN - [4:0] */ 36136a504a75SDimitris Papastamos 36146a504a75SDimitris Papastamos /* 36156a504a75SDimitris Papastamos * R1801 (0x709) - GPIO 10 36166a504a75SDimitris Papastamos */ 36176a504a75SDimitris Papastamos #define WM8995_GP10_DIR 0x8000 /* GP10_DIR */ 36186a504a75SDimitris Papastamos #define WM8995_GP10_DIR_MASK 0x8000 /* GP10_DIR */ 36196a504a75SDimitris Papastamos #define WM8995_GP10_DIR_SHIFT 15 /* GP10_DIR */ 36206a504a75SDimitris Papastamos #define WM8995_GP10_DIR_WIDTH 1 /* GP10_DIR */ 36216a504a75SDimitris Papastamos #define WM8995_GP10_PU 0x4000 /* GP10_PU */ 36226a504a75SDimitris Papastamos #define WM8995_GP10_PU_MASK 0x4000 /* GP10_PU */ 36236a504a75SDimitris Papastamos #define WM8995_GP10_PU_SHIFT 14 /* GP10_PU */ 36246a504a75SDimitris Papastamos #define WM8995_GP10_PU_WIDTH 1 /* GP10_PU */ 36256a504a75SDimitris Papastamos #define WM8995_GP10_PD 0x2000 /* GP10_PD */ 36266a504a75SDimitris Papastamos #define WM8995_GP10_PD_MASK 0x2000 /* GP10_PD */ 36276a504a75SDimitris Papastamos #define WM8995_GP10_PD_SHIFT 13 /* GP10_PD */ 36286a504a75SDimitris Papastamos #define WM8995_GP10_PD_WIDTH 1 /* GP10_PD */ 36296a504a75SDimitris Papastamos #define WM8995_GP10_POL 0x0400 /* GP10_POL */ 36306a504a75SDimitris Papastamos #define WM8995_GP10_POL_MASK 0x0400 /* GP10_POL */ 36316a504a75SDimitris Papastamos #define WM8995_GP10_POL_SHIFT 10 /* GP10_POL */ 36326a504a75SDimitris Papastamos #define WM8995_GP10_POL_WIDTH 1 /* GP10_POL */ 36336a504a75SDimitris Papastamos #define WM8995_GP10_OP_CFG 0x0200 /* GP10_OP_CFG */ 36346a504a75SDimitris Papastamos #define WM8995_GP10_OP_CFG_MASK 0x0200 /* GP10_OP_CFG */ 36356a504a75SDimitris Papastamos #define WM8995_GP10_OP_CFG_SHIFT 9 /* GP10_OP_CFG */ 36366a504a75SDimitris Papastamos #define WM8995_GP10_OP_CFG_WIDTH 1 /* GP10_OP_CFG */ 36376a504a75SDimitris Papastamos #define WM8995_GP10_DB 0x0100 /* GP10_DB */ 36386a504a75SDimitris Papastamos #define WM8995_GP10_DB_MASK 0x0100 /* GP10_DB */ 36396a504a75SDimitris Papastamos #define WM8995_GP10_DB_SHIFT 8 /* GP10_DB */ 36406a504a75SDimitris Papastamos #define WM8995_GP10_DB_WIDTH 1 /* GP10_DB */ 36416a504a75SDimitris Papastamos #define WM8995_GP10_LVL 0x0040 /* GP10_LVL */ 36426a504a75SDimitris Papastamos #define WM8995_GP10_LVL_MASK 0x0040 /* GP10_LVL */ 36436a504a75SDimitris Papastamos #define WM8995_GP10_LVL_SHIFT 6 /* GP10_LVL */ 36446a504a75SDimitris Papastamos #define WM8995_GP10_LVL_WIDTH 1 /* GP10_LVL */ 36456a504a75SDimitris Papastamos #define WM8995_GP10_FN_MASK 0x001F /* GP10_FN - [4:0] */ 36466a504a75SDimitris Papastamos #define WM8995_GP10_FN_SHIFT 0 /* GP10_FN - [4:0] */ 36476a504a75SDimitris Papastamos #define WM8995_GP10_FN_WIDTH 5 /* GP10_FN - [4:0] */ 36486a504a75SDimitris Papastamos 36496a504a75SDimitris Papastamos /* 36506a504a75SDimitris Papastamos * R1802 (0x70A) - GPIO 11 36516a504a75SDimitris Papastamos */ 36526a504a75SDimitris Papastamos #define WM8995_GP11_DIR 0x8000 /* GP11_DIR */ 36536a504a75SDimitris Papastamos #define WM8995_GP11_DIR_MASK 0x8000 /* GP11_DIR */ 36546a504a75SDimitris Papastamos #define WM8995_GP11_DIR_SHIFT 15 /* GP11_DIR */ 36556a504a75SDimitris Papastamos #define WM8995_GP11_DIR_WIDTH 1 /* GP11_DIR */ 36566a504a75SDimitris Papastamos #define WM8995_GP11_PU 0x4000 /* GP11_PU */ 36576a504a75SDimitris Papastamos #define WM8995_GP11_PU_MASK 0x4000 /* GP11_PU */ 36586a504a75SDimitris Papastamos #define WM8995_GP11_PU_SHIFT 14 /* GP11_PU */ 36596a504a75SDimitris Papastamos #define WM8995_GP11_PU_WIDTH 1 /* GP11_PU */ 36606a504a75SDimitris Papastamos #define WM8995_GP11_PD 0x2000 /* GP11_PD */ 36616a504a75SDimitris Papastamos #define WM8995_GP11_PD_MASK 0x2000 /* GP11_PD */ 36626a504a75SDimitris Papastamos #define WM8995_GP11_PD_SHIFT 13 /* GP11_PD */ 36636a504a75SDimitris Papastamos #define WM8995_GP11_PD_WIDTH 1 /* GP11_PD */ 36646a504a75SDimitris Papastamos #define WM8995_GP11_POL 0x0400 /* GP11_POL */ 36656a504a75SDimitris Papastamos #define WM8995_GP11_POL_MASK 0x0400 /* GP11_POL */ 36666a504a75SDimitris Papastamos #define WM8995_GP11_POL_SHIFT 10 /* GP11_POL */ 36676a504a75SDimitris Papastamos #define WM8995_GP11_POL_WIDTH 1 /* GP11_POL */ 36686a504a75SDimitris Papastamos #define WM8995_GP11_OP_CFG 0x0200 /* GP11_OP_CFG */ 36696a504a75SDimitris Papastamos #define WM8995_GP11_OP_CFG_MASK 0x0200 /* GP11_OP_CFG */ 36706a504a75SDimitris Papastamos #define WM8995_GP11_OP_CFG_SHIFT 9 /* GP11_OP_CFG */ 36716a504a75SDimitris Papastamos #define WM8995_GP11_OP_CFG_WIDTH 1 /* GP11_OP_CFG */ 36726a504a75SDimitris Papastamos #define WM8995_GP11_DB 0x0100 /* GP11_DB */ 36736a504a75SDimitris Papastamos #define WM8995_GP11_DB_MASK 0x0100 /* GP11_DB */ 36746a504a75SDimitris Papastamos #define WM8995_GP11_DB_SHIFT 8 /* GP11_DB */ 36756a504a75SDimitris Papastamos #define WM8995_GP11_DB_WIDTH 1 /* GP11_DB */ 36766a504a75SDimitris Papastamos #define WM8995_GP11_LVL 0x0040 /* GP11_LVL */ 36776a504a75SDimitris Papastamos #define WM8995_GP11_LVL_MASK 0x0040 /* GP11_LVL */ 36786a504a75SDimitris Papastamos #define WM8995_GP11_LVL_SHIFT 6 /* GP11_LVL */ 36796a504a75SDimitris Papastamos #define WM8995_GP11_LVL_WIDTH 1 /* GP11_LVL */ 36806a504a75SDimitris Papastamos #define WM8995_GP11_FN_MASK 0x001F /* GP11_FN - [4:0] */ 36816a504a75SDimitris Papastamos #define WM8995_GP11_FN_SHIFT 0 /* GP11_FN - [4:0] */ 36826a504a75SDimitris Papastamos #define WM8995_GP11_FN_WIDTH 5 /* GP11_FN - [4:0] */ 36836a504a75SDimitris Papastamos 36846a504a75SDimitris Papastamos /* 36856a504a75SDimitris Papastamos * R1803 (0x70B) - GPIO 12 36866a504a75SDimitris Papastamos */ 36876a504a75SDimitris Papastamos #define WM8995_GP12_DIR 0x8000 /* GP12_DIR */ 36886a504a75SDimitris Papastamos #define WM8995_GP12_DIR_MASK 0x8000 /* GP12_DIR */ 36896a504a75SDimitris Papastamos #define WM8995_GP12_DIR_SHIFT 15 /* GP12_DIR */ 36906a504a75SDimitris Papastamos #define WM8995_GP12_DIR_WIDTH 1 /* GP12_DIR */ 36916a504a75SDimitris Papastamos #define WM8995_GP12_PU 0x4000 /* GP12_PU */ 36926a504a75SDimitris Papastamos #define WM8995_GP12_PU_MASK 0x4000 /* GP12_PU */ 36936a504a75SDimitris Papastamos #define WM8995_GP12_PU_SHIFT 14 /* GP12_PU */ 36946a504a75SDimitris Papastamos #define WM8995_GP12_PU_WIDTH 1 /* GP12_PU */ 36956a504a75SDimitris Papastamos #define WM8995_GP12_PD 0x2000 /* GP12_PD */ 36966a504a75SDimitris Papastamos #define WM8995_GP12_PD_MASK 0x2000 /* GP12_PD */ 36976a504a75SDimitris Papastamos #define WM8995_GP12_PD_SHIFT 13 /* GP12_PD */ 36986a504a75SDimitris Papastamos #define WM8995_GP12_PD_WIDTH 1 /* GP12_PD */ 36996a504a75SDimitris Papastamos #define WM8995_GP12_POL 0x0400 /* GP12_POL */ 37006a504a75SDimitris Papastamos #define WM8995_GP12_POL_MASK 0x0400 /* GP12_POL */ 37016a504a75SDimitris Papastamos #define WM8995_GP12_POL_SHIFT 10 /* GP12_POL */ 37026a504a75SDimitris Papastamos #define WM8995_GP12_POL_WIDTH 1 /* GP12_POL */ 37036a504a75SDimitris Papastamos #define WM8995_GP12_OP_CFG 0x0200 /* GP12_OP_CFG */ 37046a504a75SDimitris Papastamos #define WM8995_GP12_OP_CFG_MASK 0x0200 /* GP12_OP_CFG */ 37056a504a75SDimitris Papastamos #define WM8995_GP12_OP_CFG_SHIFT 9 /* GP12_OP_CFG */ 37066a504a75SDimitris Papastamos #define WM8995_GP12_OP_CFG_WIDTH 1 /* GP12_OP_CFG */ 37076a504a75SDimitris Papastamos #define WM8995_GP12_DB 0x0100 /* GP12_DB */ 37086a504a75SDimitris Papastamos #define WM8995_GP12_DB_MASK 0x0100 /* GP12_DB */ 37096a504a75SDimitris Papastamos #define WM8995_GP12_DB_SHIFT 8 /* GP12_DB */ 37106a504a75SDimitris Papastamos #define WM8995_GP12_DB_WIDTH 1 /* GP12_DB */ 37116a504a75SDimitris Papastamos #define WM8995_GP12_LVL 0x0040 /* GP12_LVL */ 37126a504a75SDimitris Papastamos #define WM8995_GP12_LVL_MASK 0x0040 /* GP12_LVL */ 37136a504a75SDimitris Papastamos #define WM8995_GP12_LVL_SHIFT 6 /* GP12_LVL */ 37146a504a75SDimitris Papastamos #define WM8995_GP12_LVL_WIDTH 1 /* GP12_LVL */ 37156a504a75SDimitris Papastamos #define WM8995_GP12_FN_MASK 0x001F /* GP12_FN - [4:0] */ 37166a504a75SDimitris Papastamos #define WM8995_GP12_FN_SHIFT 0 /* GP12_FN - [4:0] */ 37176a504a75SDimitris Papastamos #define WM8995_GP12_FN_WIDTH 5 /* GP12_FN - [4:0] */ 37186a504a75SDimitris Papastamos 37196a504a75SDimitris Papastamos /* 37206a504a75SDimitris Papastamos * R1804 (0x70C) - GPIO 13 37216a504a75SDimitris Papastamos */ 37226a504a75SDimitris Papastamos #define WM8995_GP13_DIR 0x8000 /* GP13_DIR */ 37236a504a75SDimitris Papastamos #define WM8995_GP13_DIR_MASK 0x8000 /* GP13_DIR */ 37246a504a75SDimitris Papastamos #define WM8995_GP13_DIR_SHIFT 15 /* GP13_DIR */ 37256a504a75SDimitris Papastamos #define WM8995_GP13_DIR_WIDTH 1 /* GP13_DIR */ 37266a504a75SDimitris Papastamos #define WM8995_GP13_PU 0x4000 /* GP13_PU */ 37276a504a75SDimitris Papastamos #define WM8995_GP13_PU_MASK 0x4000 /* GP13_PU */ 37286a504a75SDimitris Papastamos #define WM8995_GP13_PU_SHIFT 14 /* GP13_PU */ 37296a504a75SDimitris Papastamos #define WM8995_GP13_PU_WIDTH 1 /* GP13_PU */ 37306a504a75SDimitris Papastamos #define WM8995_GP13_PD 0x2000 /* GP13_PD */ 37316a504a75SDimitris Papastamos #define WM8995_GP13_PD_MASK 0x2000 /* GP13_PD */ 37326a504a75SDimitris Papastamos #define WM8995_GP13_PD_SHIFT 13 /* GP13_PD */ 37336a504a75SDimitris Papastamos #define WM8995_GP13_PD_WIDTH 1 /* GP13_PD */ 37346a504a75SDimitris Papastamos #define WM8995_GP13_POL 0x0400 /* GP13_POL */ 37356a504a75SDimitris Papastamos #define WM8995_GP13_POL_MASK 0x0400 /* GP13_POL */ 37366a504a75SDimitris Papastamos #define WM8995_GP13_POL_SHIFT 10 /* GP13_POL */ 37376a504a75SDimitris Papastamos #define WM8995_GP13_POL_WIDTH 1 /* GP13_POL */ 37386a504a75SDimitris Papastamos #define WM8995_GP13_OP_CFG 0x0200 /* GP13_OP_CFG */ 37396a504a75SDimitris Papastamos #define WM8995_GP13_OP_CFG_MASK 0x0200 /* GP13_OP_CFG */ 37406a504a75SDimitris Papastamos #define WM8995_GP13_OP_CFG_SHIFT 9 /* GP13_OP_CFG */ 37416a504a75SDimitris Papastamos #define WM8995_GP13_OP_CFG_WIDTH 1 /* GP13_OP_CFG */ 37426a504a75SDimitris Papastamos #define WM8995_GP13_DB 0x0100 /* GP13_DB */ 37436a504a75SDimitris Papastamos #define WM8995_GP13_DB_MASK 0x0100 /* GP13_DB */ 37446a504a75SDimitris Papastamos #define WM8995_GP13_DB_SHIFT 8 /* GP13_DB */ 37456a504a75SDimitris Papastamos #define WM8995_GP13_DB_WIDTH 1 /* GP13_DB */ 37466a504a75SDimitris Papastamos #define WM8995_GP13_LVL 0x0040 /* GP13_LVL */ 37476a504a75SDimitris Papastamos #define WM8995_GP13_LVL_MASK 0x0040 /* GP13_LVL */ 37486a504a75SDimitris Papastamos #define WM8995_GP13_LVL_SHIFT 6 /* GP13_LVL */ 37496a504a75SDimitris Papastamos #define WM8995_GP13_LVL_WIDTH 1 /* GP13_LVL */ 37506a504a75SDimitris Papastamos #define WM8995_GP13_FN_MASK 0x001F /* GP13_FN - [4:0] */ 37516a504a75SDimitris Papastamos #define WM8995_GP13_FN_SHIFT 0 /* GP13_FN - [4:0] */ 37526a504a75SDimitris Papastamos #define WM8995_GP13_FN_WIDTH 5 /* GP13_FN - [4:0] */ 37536a504a75SDimitris Papastamos 37546a504a75SDimitris Papastamos /* 37556a504a75SDimitris Papastamos * R1805 (0x70D) - GPIO 14 37566a504a75SDimitris Papastamos */ 37576a504a75SDimitris Papastamos #define WM8995_GP14_DIR 0x8000 /* GP14_DIR */ 37586a504a75SDimitris Papastamos #define WM8995_GP14_DIR_MASK 0x8000 /* GP14_DIR */ 37596a504a75SDimitris Papastamos #define WM8995_GP14_DIR_SHIFT 15 /* GP14_DIR */ 37606a504a75SDimitris Papastamos #define WM8995_GP14_DIR_WIDTH 1 /* GP14_DIR */ 37616a504a75SDimitris Papastamos #define WM8995_GP14_PU 0x4000 /* GP14_PU */ 37626a504a75SDimitris Papastamos #define WM8995_GP14_PU_MASK 0x4000 /* GP14_PU */ 37636a504a75SDimitris Papastamos #define WM8995_GP14_PU_SHIFT 14 /* GP14_PU */ 37646a504a75SDimitris Papastamos #define WM8995_GP14_PU_WIDTH 1 /* GP14_PU */ 37656a504a75SDimitris Papastamos #define WM8995_GP14_PD 0x2000 /* GP14_PD */ 37666a504a75SDimitris Papastamos #define WM8995_GP14_PD_MASK 0x2000 /* GP14_PD */ 37676a504a75SDimitris Papastamos #define WM8995_GP14_PD_SHIFT 13 /* GP14_PD */ 37686a504a75SDimitris Papastamos #define WM8995_GP14_PD_WIDTH 1 /* GP14_PD */ 37696a504a75SDimitris Papastamos #define WM8995_GP14_POL 0x0400 /* GP14_POL */ 37706a504a75SDimitris Papastamos #define WM8995_GP14_POL_MASK 0x0400 /* GP14_POL */ 37716a504a75SDimitris Papastamos #define WM8995_GP14_POL_SHIFT 10 /* GP14_POL */ 37726a504a75SDimitris Papastamos #define WM8995_GP14_POL_WIDTH 1 /* GP14_POL */ 37736a504a75SDimitris Papastamos #define WM8995_GP14_OP_CFG 0x0200 /* GP14_OP_CFG */ 37746a504a75SDimitris Papastamos #define WM8995_GP14_OP_CFG_MASK 0x0200 /* GP14_OP_CFG */ 37756a504a75SDimitris Papastamos #define WM8995_GP14_OP_CFG_SHIFT 9 /* GP14_OP_CFG */ 37766a504a75SDimitris Papastamos #define WM8995_GP14_OP_CFG_WIDTH 1 /* GP14_OP_CFG */ 37776a504a75SDimitris Papastamos #define WM8995_GP14_DB 0x0100 /* GP14_DB */ 37786a504a75SDimitris Papastamos #define WM8995_GP14_DB_MASK 0x0100 /* GP14_DB */ 37796a504a75SDimitris Papastamos #define WM8995_GP14_DB_SHIFT 8 /* GP14_DB */ 37806a504a75SDimitris Papastamos #define WM8995_GP14_DB_WIDTH 1 /* GP14_DB */ 37816a504a75SDimitris Papastamos #define WM8995_GP14_LVL 0x0040 /* GP14_LVL */ 37826a504a75SDimitris Papastamos #define WM8995_GP14_LVL_MASK 0x0040 /* GP14_LVL */ 37836a504a75SDimitris Papastamos #define WM8995_GP14_LVL_SHIFT 6 /* GP14_LVL */ 37846a504a75SDimitris Papastamos #define WM8995_GP14_LVL_WIDTH 1 /* GP14_LVL */ 37856a504a75SDimitris Papastamos #define WM8995_GP14_FN_MASK 0x001F /* GP14_FN - [4:0] */ 37866a504a75SDimitris Papastamos #define WM8995_GP14_FN_SHIFT 0 /* GP14_FN - [4:0] */ 37876a504a75SDimitris Papastamos #define WM8995_GP14_FN_WIDTH 5 /* GP14_FN - [4:0] */ 37886a504a75SDimitris Papastamos 37896a504a75SDimitris Papastamos /* 37906a504a75SDimitris Papastamos * R1824 (0x720) - Pull Control (1) 37916a504a75SDimitris Papastamos */ 37926a504a75SDimitris Papastamos #define WM8995_DMICDAT3_PD 0x4000 /* DMICDAT3_PD */ 37936a504a75SDimitris Papastamos #define WM8995_DMICDAT3_PD_MASK 0x4000 /* DMICDAT3_PD */ 37946a504a75SDimitris Papastamos #define WM8995_DMICDAT3_PD_SHIFT 14 /* DMICDAT3_PD */ 37956a504a75SDimitris Papastamos #define WM8995_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 37966a504a75SDimitris Papastamos #define WM8995_DMICDAT2_PD 0x1000 /* DMICDAT2_PD */ 37976a504a75SDimitris Papastamos #define WM8995_DMICDAT2_PD_MASK 0x1000 /* DMICDAT2_PD */ 37986a504a75SDimitris Papastamos #define WM8995_DMICDAT2_PD_SHIFT 12 /* DMICDAT2_PD */ 37996a504a75SDimitris Papastamos #define WM8995_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 38006a504a75SDimitris Papastamos #define WM8995_DMICDAT1_PD 0x0400 /* DMICDAT1_PD */ 38016a504a75SDimitris Papastamos #define WM8995_DMICDAT1_PD_MASK 0x0400 /* DMICDAT1_PD */ 38026a504a75SDimitris Papastamos #define WM8995_DMICDAT1_PD_SHIFT 10 /* DMICDAT1_PD */ 38036a504a75SDimitris Papastamos #define WM8995_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 38046a504a75SDimitris Papastamos #define WM8995_MCLK2_PU 0x0200 /* MCLK2_PU */ 38056a504a75SDimitris Papastamos #define WM8995_MCLK2_PU_MASK 0x0200 /* MCLK2_PU */ 38066a504a75SDimitris Papastamos #define WM8995_MCLK2_PU_SHIFT 9 /* MCLK2_PU */ 38076a504a75SDimitris Papastamos #define WM8995_MCLK2_PU_WIDTH 1 /* MCLK2_PU */ 38086a504a75SDimitris Papastamos #define WM8995_MCLK2_PD 0x0100 /* MCLK2_PD */ 38096a504a75SDimitris Papastamos #define WM8995_MCLK2_PD_MASK 0x0100 /* MCLK2_PD */ 38106a504a75SDimitris Papastamos #define WM8995_MCLK2_PD_SHIFT 8 /* MCLK2_PD */ 38116a504a75SDimitris Papastamos #define WM8995_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 38126a504a75SDimitris Papastamos #define WM8995_MCLK1_PU 0x0080 /* MCLK1_PU */ 38136a504a75SDimitris Papastamos #define WM8995_MCLK1_PU_MASK 0x0080 /* MCLK1_PU */ 38146a504a75SDimitris Papastamos #define WM8995_MCLK1_PU_SHIFT 7 /* MCLK1_PU */ 38156a504a75SDimitris Papastamos #define WM8995_MCLK1_PU_WIDTH 1 /* MCLK1_PU */ 38166a504a75SDimitris Papastamos #define WM8995_MCLK1_PD 0x0040 /* MCLK1_PD */ 38176a504a75SDimitris Papastamos #define WM8995_MCLK1_PD_MASK 0x0040 /* MCLK1_PD */ 38186a504a75SDimitris Papastamos #define WM8995_MCLK1_PD_SHIFT 6 /* MCLK1_PD */ 38196a504a75SDimitris Papastamos #define WM8995_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 38206a504a75SDimitris Papastamos #define WM8995_DACDAT1_PU 0x0020 /* DACDAT1_PU */ 38216a504a75SDimitris Papastamos #define WM8995_DACDAT1_PU_MASK 0x0020 /* DACDAT1_PU */ 38226a504a75SDimitris Papastamos #define WM8995_DACDAT1_PU_SHIFT 5 /* DACDAT1_PU */ 38236a504a75SDimitris Papastamos #define WM8995_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */ 38246a504a75SDimitris Papastamos #define WM8995_DACDAT1_PD 0x0010 /* DACDAT1_PD */ 38256a504a75SDimitris Papastamos #define WM8995_DACDAT1_PD_MASK 0x0010 /* DACDAT1_PD */ 38266a504a75SDimitris Papastamos #define WM8995_DACDAT1_PD_SHIFT 4 /* DACDAT1_PD */ 38276a504a75SDimitris Papastamos #define WM8995_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */ 38286a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PU 0x0008 /* DACLRCLK1_PU */ 38296a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PU_MASK 0x0008 /* DACLRCLK1_PU */ 38306a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PU_SHIFT 3 /* DACLRCLK1_PU */ 38316a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */ 38326a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PD 0x0004 /* DACLRCLK1_PD */ 38336a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PD_MASK 0x0004 /* DACLRCLK1_PD */ 38346a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PD_SHIFT 2 /* DACLRCLK1_PD */ 38356a504a75SDimitris Papastamos #define WM8995_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */ 38366a504a75SDimitris Papastamos #define WM8995_BCLK1_PU 0x0002 /* BCLK1_PU */ 38376a504a75SDimitris Papastamos #define WM8995_BCLK1_PU_MASK 0x0002 /* BCLK1_PU */ 38386a504a75SDimitris Papastamos #define WM8995_BCLK1_PU_SHIFT 1 /* BCLK1_PU */ 38396a504a75SDimitris Papastamos #define WM8995_BCLK1_PU_WIDTH 1 /* BCLK1_PU */ 38406a504a75SDimitris Papastamos #define WM8995_BCLK1_PD 0x0001 /* BCLK1_PD */ 38416a504a75SDimitris Papastamos #define WM8995_BCLK1_PD_MASK 0x0001 /* BCLK1_PD */ 38426a504a75SDimitris Papastamos #define WM8995_BCLK1_PD_SHIFT 0 /* BCLK1_PD */ 38436a504a75SDimitris Papastamos #define WM8995_BCLK1_PD_WIDTH 1 /* BCLK1_PD */ 38446a504a75SDimitris Papastamos 38456a504a75SDimitris Papastamos /* 38466a504a75SDimitris Papastamos * R1825 (0x721) - Pull Control (2) 38476a504a75SDimitris Papastamos */ 38486a504a75SDimitris Papastamos #define WM8995_LDO1ENA_PD 0x0010 /* LDO1ENA_PD */ 38496a504a75SDimitris Papastamos #define WM8995_LDO1ENA_PD_MASK 0x0010 /* LDO1ENA_PD */ 38506a504a75SDimitris Papastamos #define WM8995_LDO1ENA_PD_SHIFT 4 /* LDO1ENA_PD */ 38516a504a75SDimitris Papastamos #define WM8995_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 38526a504a75SDimitris Papastamos #define WM8995_MODE_PD 0x0004 /* MODE_PD */ 38536a504a75SDimitris Papastamos #define WM8995_MODE_PD_MASK 0x0004 /* MODE_PD */ 38546a504a75SDimitris Papastamos #define WM8995_MODE_PD_SHIFT 2 /* MODE_PD */ 38556a504a75SDimitris Papastamos #define WM8995_MODE_PD_WIDTH 1 /* MODE_PD */ 38566a504a75SDimitris Papastamos #define WM8995_CSNADDR_PD 0x0001 /* CSNADDR_PD */ 38576a504a75SDimitris Papastamos #define WM8995_CSNADDR_PD_MASK 0x0001 /* CSNADDR_PD */ 38586a504a75SDimitris Papastamos #define WM8995_CSNADDR_PD_SHIFT 0 /* CSNADDR_PD */ 38596a504a75SDimitris Papastamos #define WM8995_CSNADDR_PD_WIDTH 1 /* CSNADDR_PD */ 38606a504a75SDimitris Papastamos 38616a504a75SDimitris Papastamos /* 38626a504a75SDimitris Papastamos * R1840 (0x730) - Interrupt Status 1 38636a504a75SDimitris Papastamos */ 38646a504a75SDimitris Papastamos #define WM8995_GP14_EINT 0x2000 /* GP14_EINT */ 38656a504a75SDimitris Papastamos #define WM8995_GP14_EINT_MASK 0x2000 /* GP14_EINT */ 38666a504a75SDimitris Papastamos #define WM8995_GP14_EINT_SHIFT 13 /* GP14_EINT */ 38676a504a75SDimitris Papastamos #define WM8995_GP14_EINT_WIDTH 1 /* GP14_EINT */ 38686a504a75SDimitris Papastamos #define WM8995_GP13_EINT 0x1000 /* GP13_EINT */ 38696a504a75SDimitris Papastamos #define WM8995_GP13_EINT_MASK 0x1000 /* GP13_EINT */ 38706a504a75SDimitris Papastamos #define WM8995_GP13_EINT_SHIFT 12 /* GP13_EINT */ 38716a504a75SDimitris Papastamos #define WM8995_GP13_EINT_WIDTH 1 /* GP13_EINT */ 38726a504a75SDimitris Papastamos #define WM8995_GP12_EINT 0x0800 /* GP12_EINT */ 38736a504a75SDimitris Papastamos #define WM8995_GP12_EINT_MASK 0x0800 /* GP12_EINT */ 38746a504a75SDimitris Papastamos #define WM8995_GP12_EINT_SHIFT 11 /* GP12_EINT */ 38756a504a75SDimitris Papastamos #define WM8995_GP12_EINT_WIDTH 1 /* GP12_EINT */ 38766a504a75SDimitris Papastamos #define WM8995_GP11_EINT 0x0400 /* GP11_EINT */ 38776a504a75SDimitris Papastamos #define WM8995_GP11_EINT_MASK 0x0400 /* GP11_EINT */ 38786a504a75SDimitris Papastamos #define WM8995_GP11_EINT_SHIFT 10 /* GP11_EINT */ 38796a504a75SDimitris Papastamos #define WM8995_GP11_EINT_WIDTH 1 /* GP11_EINT */ 38806a504a75SDimitris Papastamos #define WM8995_GP10_EINT 0x0200 /* GP10_EINT */ 38816a504a75SDimitris Papastamos #define WM8995_GP10_EINT_MASK 0x0200 /* GP10_EINT */ 38826a504a75SDimitris Papastamos #define WM8995_GP10_EINT_SHIFT 9 /* GP10_EINT */ 38836a504a75SDimitris Papastamos #define WM8995_GP10_EINT_WIDTH 1 /* GP10_EINT */ 38846a504a75SDimitris Papastamos #define WM8995_GP9_EINT 0x0100 /* GP9_EINT */ 38856a504a75SDimitris Papastamos #define WM8995_GP9_EINT_MASK 0x0100 /* GP9_EINT */ 38866a504a75SDimitris Papastamos #define WM8995_GP9_EINT_SHIFT 8 /* GP9_EINT */ 38876a504a75SDimitris Papastamos #define WM8995_GP9_EINT_WIDTH 1 /* GP9_EINT */ 38886a504a75SDimitris Papastamos #define WM8995_GP8_EINT 0x0080 /* GP8_EINT */ 38896a504a75SDimitris Papastamos #define WM8995_GP8_EINT_MASK 0x0080 /* GP8_EINT */ 38906a504a75SDimitris Papastamos #define WM8995_GP8_EINT_SHIFT 7 /* GP8_EINT */ 38916a504a75SDimitris Papastamos #define WM8995_GP8_EINT_WIDTH 1 /* GP8_EINT */ 38926a504a75SDimitris Papastamos #define WM8995_GP7_EINT 0x0040 /* GP7_EINT */ 38936a504a75SDimitris Papastamos #define WM8995_GP7_EINT_MASK 0x0040 /* GP7_EINT */ 38946a504a75SDimitris Papastamos #define WM8995_GP7_EINT_SHIFT 6 /* GP7_EINT */ 38956a504a75SDimitris Papastamos #define WM8995_GP7_EINT_WIDTH 1 /* GP7_EINT */ 38966a504a75SDimitris Papastamos #define WM8995_GP6_EINT 0x0020 /* GP6_EINT */ 38976a504a75SDimitris Papastamos #define WM8995_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 38986a504a75SDimitris Papastamos #define WM8995_GP6_EINT_SHIFT 5 /* GP6_EINT */ 38996a504a75SDimitris Papastamos #define WM8995_GP6_EINT_WIDTH 1 /* GP6_EINT */ 39006a504a75SDimitris Papastamos #define WM8995_GP5_EINT 0x0010 /* GP5_EINT */ 39016a504a75SDimitris Papastamos #define WM8995_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 39026a504a75SDimitris Papastamos #define WM8995_GP5_EINT_SHIFT 4 /* GP5_EINT */ 39036a504a75SDimitris Papastamos #define WM8995_GP5_EINT_WIDTH 1 /* GP5_EINT */ 39046a504a75SDimitris Papastamos #define WM8995_GP4_EINT 0x0008 /* GP4_EINT */ 39056a504a75SDimitris Papastamos #define WM8995_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 39066a504a75SDimitris Papastamos #define WM8995_GP4_EINT_SHIFT 3 /* GP4_EINT */ 39076a504a75SDimitris Papastamos #define WM8995_GP4_EINT_WIDTH 1 /* GP4_EINT */ 39086a504a75SDimitris Papastamos #define WM8995_GP3_EINT 0x0004 /* GP3_EINT */ 39096a504a75SDimitris Papastamos #define WM8995_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 39106a504a75SDimitris Papastamos #define WM8995_GP3_EINT_SHIFT 2 /* GP3_EINT */ 39116a504a75SDimitris Papastamos #define WM8995_GP3_EINT_WIDTH 1 /* GP3_EINT */ 39126a504a75SDimitris Papastamos #define WM8995_GP2_EINT 0x0002 /* GP2_EINT */ 39136a504a75SDimitris Papastamos #define WM8995_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 39146a504a75SDimitris Papastamos #define WM8995_GP2_EINT_SHIFT 1 /* GP2_EINT */ 39156a504a75SDimitris Papastamos #define WM8995_GP2_EINT_WIDTH 1 /* GP2_EINT */ 39166a504a75SDimitris Papastamos #define WM8995_GP1_EINT 0x0001 /* GP1_EINT */ 39176a504a75SDimitris Papastamos #define WM8995_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 39186a504a75SDimitris Papastamos #define WM8995_GP1_EINT_SHIFT 0 /* GP1_EINT */ 39196a504a75SDimitris Papastamos #define WM8995_GP1_EINT_WIDTH 1 /* GP1_EINT */ 39206a504a75SDimitris Papastamos 39216a504a75SDimitris Papastamos /* 39226a504a75SDimitris Papastamos * R1841 (0x731) - Interrupt Status 2 39236a504a75SDimitris Papastamos */ 39246a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_EINT 0x1000 /* DCS_DONE_23_EINT */ 39256a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_EINT_MASK 0x1000 /* DCS_DONE_23_EINT */ 39266a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_EINT_SHIFT 12 /* DCS_DONE_23_EINT */ 39276a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_EINT_WIDTH 1 /* DCS_DONE_23_EINT */ 39286a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_EINT 0x0800 /* DCS_DONE_01_EINT */ 39296a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_EINT_MASK 0x0800 /* DCS_DONE_01_EINT */ 39306a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_EINT_SHIFT 11 /* DCS_DONE_01_EINT */ 39316a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_EINT_WIDTH 1 /* DCS_DONE_01_EINT */ 39326a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_EINT 0x0400 /* WSEQ_DONE_EINT */ 39336a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_EINT_MASK 0x0400 /* WSEQ_DONE_EINT */ 39346a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_EINT_SHIFT 10 /* WSEQ_DONE_EINT */ 39356a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_EINT_WIDTH 1 /* WSEQ_DONE_EINT */ 39366a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_EINT 0x0200 /* FIFOS_ERR_EINT */ 39376a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_EINT_MASK 0x0200 /* FIFOS_ERR_EINT */ 39386a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_EINT_SHIFT 9 /* FIFOS_ERR_EINT */ 39396a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_EINT_WIDTH 1 /* FIFOS_ERR_EINT */ 39406a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_EINT 0x0100 /* AIF2DRC_SIG_DET_EINT */ 39416a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* AIF2DRC_SIG_DET_EINT */ 39426a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* AIF2DRC_SIG_DET_EINT */ 39436a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* AIF2DRC_SIG_DET_EINT */ 39446a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_EINT 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 39456a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* AIF1DRC2_SIG_DET_EINT */ 39466a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* AIF1DRC2_SIG_DET_EINT */ 39476a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* AIF1DRC2_SIG_DET_EINT */ 39486a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_EINT 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 39496a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* AIF1DRC1_SIG_DET_EINT */ 39506a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* AIF1DRC1_SIG_DET_EINT */ 39516a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* AIF1DRC1_SIG_DET_EINT */ 39526a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_EINT 0x0020 /* SRC2_LOCK_EINT */ 39536a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_EINT_MASK 0x0020 /* SRC2_LOCK_EINT */ 39546a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_EINT_SHIFT 5 /* SRC2_LOCK_EINT */ 39556a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_EINT_WIDTH 1 /* SRC2_LOCK_EINT */ 39566a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_EINT 0x0010 /* SRC1_LOCK_EINT */ 39576a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_EINT_MASK 0x0010 /* SRC1_LOCK_EINT */ 39586a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_EINT_SHIFT 4 /* SRC1_LOCK_EINT */ 39596a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_EINT_WIDTH 1 /* SRC1_LOCK_EINT */ 39606a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 39616a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 39626a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 39636a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 39646a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 39656a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 39666a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 39676a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 39686a504a75SDimitris Papastamos #define WM8995_HP_DONE_EINT 0x0002 /* HP_DONE_EINT */ 39696a504a75SDimitris Papastamos #define WM8995_HP_DONE_EINT_MASK 0x0002 /* HP_DONE_EINT */ 39706a504a75SDimitris Papastamos #define WM8995_HP_DONE_EINT_SHIFT 1 /* HP_DONE_EINT */ 39716a504a75SDimitris Papastamos #define WM8995_HP_DONE_EINT_WIDTH 1 /* HP_DONE_EINT */ 39726a504a75SDimitris Papastamos #define WM8995_MICD_EINT 0x0001 /* MICD_EINT */ 39736a504a75SDimitris Papastamos #define WM8995_MICD_EINT_MASK 0x0001 /* MICD_EINT */ 39746a504a75SDimitris Papastamos #define WM8995_MICD_EINT_SHIFT 0 /* MICD_EINT */ 39756a504a75SDimitris Papastamos #define WM8995_MICD_EINT_WIDTH 1 /* MICD_EINT */ 39766a504a75SDimitris Papastamos 39776a504a75SDimitris Papastamos /* 39786a504a75SDimitris Papastamos * R1842 (0x732) - Interrupt Raw Status 2 39796a504a75SDimitris Papastamos */ 39806a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_STS 0x1000 /* DCS_DONE_23_STS */ 39816a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_STS_MASK 0x1000 /* DCS_DONE_23_STS */ 39826a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_STS_SHIFT 12 /* DCS_DONE_23_STS */ 39836a504a75SDimitris Papastamos #define WM8995_DCS_DONE_23_STS_WIDTH 1 /* DCS_DONE_23_STS */ 39846a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_STS 0x0800 /* DCS_DONE_01_STS */ 39856a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_STS_MASK 0x0800 /* DCS_DONE_01_STS */ 39866a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_STS_SHIFT 11 /* DCS_DONE_01_STS */ 39876a504a75SDimitris Papastamos #define WM8995_DCS_DONE_01_STS_WIDTH 1 /* DCS_DONE_01_STS */ 39886a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_STS 0x0400 /* WSEQ_DONE_STS */ 39896a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_STS_MASK 0x0400 /* WSEQ_DONE_STS */ 39906a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_STS_SHIFT 10 /* WSEQ_DONE_STS */ 39916a504a75SDimitris Papastamos #define WM8995_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */ 39926a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_STS 0x0200 /* FIFOS_ERR_STS */ 39936a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_STS_MASK 0x0200 /* FIFOS_ERR_STS */ 39946a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_STS_SHIFT 9 /* FIFOS_ERR_STS */ 39956a504a75SDimitris Papastamos #define WM8995_FIFOS_ERR_STS_WIDTH 1 /* FIFOS_ERR_STS */ 39966a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_STS 0x0100 /* AIF2DRC_SIG_DET_STS */ 39976a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_STS_MASK 0x0100 /* AIF2DRC_SIG_DET_STS */ 39986a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_STS_SHIFT 8 /* AIF2DRC_SIG_DET_STS */ 39996a504a75SDimitris Papastamos #define WM8995_AIF2DRC_SIG_DET_STS_WIDTH 1 /* AIF2DRC_SIG_DET_STS */ 40006a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_STS 0x0080 /* AIF1DRC2_SIG_DET_STS */ 40016a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_STS_MASK 0x0080 /* AIF1DRC2_SIG_DET_STS */ 40026a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_STS_SHIFT 7 /* AIF1DRC2_SIG_DET_STS */ 40036a504a75SDimitris Papastamos #define WM8995_AIF1DRC2_SIG_DET_STS_WIDTH 1 /* AIF1DRC2_SIG_DET_STS */ 40046a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_STS 0x0040 /* AIF1DRC1_SIG_DET_STS */ 40056a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_STS_MASK 0x0040 /* AIF1DRC1_SIG_DET_STS */ 40066a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_STS_SHIFT 6 /* AIF1DRC1_SIG_DET_STS */ 40076a504a75SDimitris Papastamos #define WM8995_AIF1DRC1_SIG_DET_STS_WIDTH 1 /* AIF1DRC1_SIG_DET_STS */ 40086a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_STS 0x0020 /* SRC2_LOCK_STS */ 40096a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_STS_MASK 0x0020 /* SRC2_LOCK_STS */ 40106a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_STS_SHIFT 5 /* SRC2_LOCK_STS */ 40116a504a75SDimitris Papastamos #define WM8995_SRC2_LOCK_STS_WIDTH 1 /* SRC2_LOCK_STS */ 40126a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_STS 0x0010 /* SRC1_LOCK_STS */ 40136a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_STS_MASK 0x0010 /* SRC1_LOCK_STS */ 40146a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_STS_SHIFT 4 /* SRC1_LOCK_STS */ 40156a504a75SDimitris Papastamos #define WM8995_SRC1_LOCK_STS_WIDTH 1 /* SRC1_LOCK_STS */ 40166a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 40176a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 40186a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 40196a504a75SDimitris Papastamos #define WM8995_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 40206a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 40216a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 40226a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 40236a504a75SDimitris Papastamos #define WM8995_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 40246a504a75SDimitris Papastamos 40256a504a75SDimitris Papastamos /* 40266a504a75SDimitris Papastamos * R1848 (0x738) - Interrupt Status 1 Mask 40276a504a75SDimitris Papastamos */ 40286a504a75SDimitris Papastamos #define WM8995_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */ 40296a504a75SDimitris Papastamos #define WM8995_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */ 40306a504a75SDimitris Papastamos #define WM8995_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */ 40316a504a75SDimitris Papastamos #define WM8995_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */ 40326a504a75SDimitris Papastamos #define WM8995_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */ 40336a504a75SDimitris Papastamos #define WM8995_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */ 40346a504a75SDimitris Papastamos #define WM8995_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */ 40356a504a75SDimitris Papastamos #define WM8995_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */ 40366a504a75SDimitris Papastamos #define WM8995_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */ 40376a504a75SDimitris Papastamos #define WM8995_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */ 40386a504a75SDimitris Papastamos #define WM8995_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */ 40396a504a75SDimitris Papastamos #define WM8995_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */ 40406a504a75SDimitris Papastamos #define WM8995_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */ 40416a504a75SDimitris Papastamos #define WM8995_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */ 40426a504a75SDimitris Papastamos #define WM8995_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */ 40436a504a75SDimitris Papastamos #define WM8995_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */ 40446a504a75SDimitris Papastamos #define WM8995_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */ 40456a504a75SDimitris Papastamos #define WM8995_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */ 40466a504a75SDimitris Papastamos #define WM8995_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */ 40476a504a75SDimitris Papastamos #define WM8995_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */ 40486a504a75SDimitris Papastamos #define WM8995_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */ 40496a504a75SDimitris Papastamos #define WM8995_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */ 40506a504a75SDimitris Papastamos #define WM8995_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */ 40516a504a75SDimitris Papastamos #define WM8995_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */ 40526a504a75SDimitris Papastamos #define WM8995_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */ 40536a504a75SDimitris Papastamos #define WM8995_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */ 40546a504a75SDimitris Papastamos #define WM8995_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */ 40556a504a75SDimitris Papastamos #define WM8995_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */ 40566a504a75SDimitris Papastamos #define WM8995_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */ 40576a504a75SDimitris Papastamos #define WM8995_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */ 40586a504a75SDimitris Papastamos #define WM8995_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */ 40596a504a75SDimitris Papastamos #define WM8995_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */ 40606a504a75SDimitris Papastamos #define WM8995_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 40616a504a75SDimitris Papastamos #define WM8995_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 40626a504a75SDimitris Papastamos #define WM8995_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 40636a504a75SDimitris Papastamos #define WM8995_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 40646a504a75SDimitris Papastamos #define WM8995_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 40656a504a75SDimitris Papastamos #define WM8995_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 40666a504a75SDimitris Papastamos #define WM8995_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 40676a504a75SDimitris Papastamos #define WM8995_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 40686a504a75SDimitris Papastamos #define WM8995_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 40696a504a75SDimitris Papastamos #define WM8995_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 40706a504a75SDimitris Papastamos #define WM8995_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 40716a504a75SDimitris Papastamos #define WM8995_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 40726a504a75SDimitris Papastamos #define WM8995_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 40736a504a75SDimitris Papastamos #define WM8995_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 40746a504a75SDimitris Papastamos #define WM8995_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 40756a504a75SDimitris Papastamos #define WM8995_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 40766a504a75SDimitris Papastamos #define WM8995_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 40776a504a75SDimitris Papastamos #define WM8995_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 40786a504a75SDimitris Papastamos #define WM8995_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 40796a504a75SDimitris Papastamos #define WM8995_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 40806a504a75SDimitris Papastamos #define WM8995_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 40816a504a75SDimitris Papastamos #define WM8995_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 40826a504a75SDimitris Papastamos #define WM8995_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 40836a504a75SDimitris Papastamos #define WM8995_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 40846a504a75SDimitris Papastamos 40856a504a75SDimitris Papastamos /* 40866a504a75SDimitris Papastamos * R1849 (0x739) - Interrupt Status 2 Mask 40876a504a75SDimitris Papastamos */ 40886a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_23_EINT 0x1000 /* IM_DCS_DONE_23_EINT */ 40896a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_23_EINT_MASK 0x1000 /* IM_DCS_DONE_23_EINT */ 40906a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_23_EINT_SHIFT 12 /* IM_DCS_DONE_23_EINT */ 40916a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_23_EINT_WIDTH 1 /* IM_DCS_DONE_23_EINT */ 40926a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_01_EINT 0x0800 /* IM_DCS_DONE_01_EINT */ 40936a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_01_EINT_MASK 0x0800 /* IM_DCS_DONE_01_EINT */ 40946a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_01_EINT_SHIFT 11 /* IM_DCS_DONE_01_EINT */ 40956a504a75SDimitris Papastamos #define WM8995_IM_DCS_DONE_01_EINT_WIDTH 1 /* IM_DCS_DONE_01_EINT */ 40966a504a75SDimitris Papastamos #define WM8995_IM_WSEQ_DONE_EINT 0x0400 /* IM_WSEQ_DONE_EINT */ 40976a504a75SDimitris Papastamos #define WM8995_IM_WSEQ_DONE_EINT_MASK 0x0400 /* IM_WSEQ_DONE_EINT */ 40986a504a75SDimitris Papastamos #define WM8995_IM_WSEQ_DONE_EINT_SHIFT 10 /* IM_WSEQ_DONE_EINT */ 40996a504a75SDimitris Papastamos #define WM8995_IM_WSEQ_DONE_EINT_WIDTH 1 /* IM_WSEQ_DONE_EINT */ 41006a504a75SDimitris Papastamos #define WM8995_IM_FIFOS_ERR_EINT 0x0200 /* IM_FIFOS_ERR_EINT */ 41016a504a75SDimitris Papastamos #define WM8995_IM_FIFOS_ERR_EINT_MASK 0x0200 /* IM_FIFOS_ERR_EINT */ 41026a504a75SDimitris Papastamos #define WM8995_IM_FIFOS_ERR_EINT_SHIFT 9 /* IM_FIFOS_ERR_EINT */ 41036a504a75SDimitris Papastamos #define WM8995_IM_FIFOS_ERR_EINT_WIDTH 1 /* IM_FIFOS_ERR_EINT */ 41046a504a75SDimitris Papastamos #define WM8995_IM_AIF2DRC_SIG_DET_EINT 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 41056a504a75SDimitris Papastamos #define WM8995_IM_AIF2DRC_SIG_DET_EINT_MASK 0x0100 /* IM_AIF2DRC_SIG_DET_EINT */ 41066a504a75SDimitris Papastamos #define WM8995_IM_AIF2DRC_SIG_DET_EINT_SHIFT 8 /* IM_AIF2DRC_SIG_DET_EINT */ 41076a504a75SDimitris Papastamos #define WM8995_IM_AIF2DRC_SIG_DET_EINT_WIDTH 1 /* IM_AIF2DRC_SIG_DET_EINT */ 41086a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC2_SIG_DET_EINT 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 41096a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_MASK 0x0080 /* IM_AIF1DRC2_SIG_DET_EINT */ 41106a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_SHIFT 7 /* IM_AIF1DRC2_SIG_DET_EINT */ 41116a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC2_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC2_SIG_DET_EINT */ 41126a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC1_SIG_DET_EINT 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 41136a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_MASK 0x0040 /* IM_AIF1DRC1_SIG_DET_EINT */ 41146a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_SHIFT 6 /* IM_AIF1DRC1_SIG_DET_EINT */ 41156a504a75SDimitris Papastamos #define WM8995_IM_AIF1DRC1_SIG_DET_EINT_WIDTH 1 /* IM_AIF1DRC1_SIG_DET_EINT */ 41166a504a75SDimitris Papastamos #define WM8995_IM_SRC2_LOCK_EINT 0x0020 /* IM_SRC2_LOCK_EINT */ 41176a504a75SDimitris Papastamos #define WM8995_IM_SRC2_LOCK_EINT_MASK 0x0020 /* IM_SRC2_LOCK_EINT */ 41186a504a75SDimitris Papastamos #define WM8995_IM_SRC2_LOCK_EINT_SHIFT 5 /* IM_SRC2_LOCK_EINT */ 41196a504a75SDimitris Papastamos #define WM8995_IM_SRC2_LOCK_EINT_WIDTH 1 /* IM_SRC2_LOCK_EINT */ 41206a504a75SDimitris Papastamos #define WM8995_IM_SRC1_LOCK_EINT 0x0010 /* IM_SRC1_LOCK_EINT */ 41216a504a75SDimitris Papastamos #define WM8995_IM_SRC1_LOCK_EINT_MASK 0x0010 /* IM_SRC1_LOCK_EINT */ 41226a504a75SDimitris Papastamos #define WM8995_IM_SRC1_LOCK_EINT_SHIFT 4 /* IM_SRC1_LOCK_EINT */ 41236a504a75SDimitris Papastamos #define WM8995_IM_SRC1_LOCK_EINT_WIDTH 1 /* IM_SRC1_LOCK_EINT */ 41246a504a75SDimitris Papastamos #define WM8995_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 41256a504a75SDimitris Papastamos #define WM8995_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 41266a504a75SDimitris Papastamos #define WM8995_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 41276a504a75SDimitris Papastamos #define WM8995_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 41286a504a75SDimitris Papastamos #define WM8995_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 41296a504a75SDimitris Papastamos #define WM8995_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 41306a504a75SDimitris Papastamos #define WM8995_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 41316a504a75SDimitris Papastamos #define WM8995_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 41326a504a75SDimitris Papastamos #define WM8995_IM_HP_DONE_EINT 0x0002 /* IM_HP_DONE_EINT */ 41336a504a75SDimitris Papastamos #define WM8995_IM_HP_DONE_EINT_MASK 0x0002 /* IM_HP_DONE_EINT */ 41346a504a75SDimitris Papastamos #define WM8995_IM_HP_DONE_EINT_SHIFT 1 /* IM_HP_DONE_EINT */ 41356a504a75SDimitris Papastamos #define WM8995_IM_HP_DONE_EINT_WIDTH 1 /* IM_HP_DONE_EINT */ 41366a504a75SDimitris Papastamos #define WM8995_IM_MICD_EINT 0x0001 /* IM_MICD_EINT */ 41376a504a75SDimitris Papastamos #define WM8995_IM_MICD_EINT_MASK 0x0001 /* IM_MICD_EINT */ 41386a504a75SDimitris Papastamos #define WM8995_IM_MICD_EINT_SHIFT 0 /* IM_MICD_EINT */ 41396a504a75SDimitris Papastamos #define WM8995_IM_MICD_EINT_WIDTH 1 /* IM_MICD_EINT */ 41406a504a75SDimitris Papastamos 41416a504a75SDimitris Papastamos /* 41426a504a75SDimitris Papastamos * R1856 (0x740) - Interrupt Control 41436a504a75SDimitris Papastamos */ 41446a504a75SDimitris Papastamos #define WM8995_IM_IRQ 0x0001 /* IM_IRQ */ 41456a504a75SDimitris Papastamos #define WM8995_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 41466a504a75SDimitris Papastamos #define WM8995_IM_IRQ_SHIFT 0 /* IM_IRQ */ 41476a504a75SDimitris Papastamos #define WM8995_IM_IRQ_WIDTH 1 /* IM_IRQ */ 41486a504a75SDimitris Papastamos 41496a504a75SDimitris Papastamos /* 41506a504a75SDimitris Papastamos * R2048 (0x800) - Left PDM Speaker 1 41516a504a75SDimitris Papastamos */ 41526a504a75SDimitris Papastamos #define WM8995_SPK1L_ENA 0x0010 /* SPK1L_ENA */ 41536a504a75SDimitris Papastamos #define WM8995_SPK1L_ENA_MASK 0x0010 /* SPK1L_ENA */ 41546a504a75SDimitris Papastamos #define WM8995_SPK1L_ENA_SHIFT 4 /* SPK1L_ENA */ 41556a504a75SDimitris Papastamos #define WM8995_SPK1L_ENA_WIDTH 1 /* SPK1L_ENA */ 41566a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE 0x0008 /* SPK1L_MUTE */ 41576a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_MASK 0x0008 /* SPK1L_MUTE */ 41586a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_SHIFT 3 /* SPK1L_MUTE */ 41596a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 41606a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_ZC 0x0004 /* SPK1L_MUTE_ZC */ 41616a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_ZC_MASK 0x0004 /* SPK1L_MUTE_ZC */ 41626a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_ZC_SHIFT 2 /* SPK1L_MUTE_ZC */ 41636a504a75SDimitris Papastamos #define WM8995_SPK1L_MUTE_ZC_WIDTH 1 /* SPK1L_MUTE_ZC */ 41646a504a75SDimitris Papastamos #define WM8995_SPK1L_SRC_MASK 0x0003 /* SPK1L_SRC - [1:0] */ 41656a504a75SDimitris Papastamos #define WM8995_SPK1L_SRC_SHIFT 0 /* SPK1L_SRC - [1:0] */ 41666a504a75SDimitris Papastamos #define WM8995_SPK1L_SRC_WIDTH 2 /* SPK1L_SRC - [1:0] */ 41676a504a75SDimitris Papastamos 41686a504a75SDimitris Papastamos /* 41696a504a75SDimitris Papastamos * R2049 (0x801) - Right PDM Speaker 1 41706a504a75SDimitris Papastamos */ 41716a504a75SDimitris Papastamos #define WM8995_SPK1R_ENA 0x0010 /* SPK1R_ENA */ 41726a504a75SDimitris Papastamos #define WM8995_SPK1R_ENA_MASK 0x0010 /* SPK1R_ENA */ 41736a504a75SDimitris Papastamos #define WM8995_SPK1R_ENA_SHIFT 4 /* SPK1R_ENA */ 41746a504a75SDimitris Papastamos #define WM8995_SPK1R_ENA_WIDTH 1 /* SPK1R_ENA */ 41756a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE 0x0008 /* SPK1R_MUTE */ 41766a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_MASK 0x0008 /* SPK1R_MUTE */ 41776a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_SHIFT 3 /* SPK1R_MUTE */ 41786a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 41796a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_ZC 0x0004 /* SPK1R_MUTE_ZC */ 41806a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_ZC_MASK 0x0004 /* SPK1R_MUTE_ZC */ 41816a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_ZC_SHIFT 2 /* SPK1R_MUTE_ZC */ 41826a504a75SDimitris Papastamos #define WM8995_SPK1R_MUTE_ZC_WIDTH 1 /* SPK1R_MUTE_ZC */ 41836a504a75SDimitris Papastamos #define WM8995_SPK1R_SRC_MASK 0x0003 /* SPK1R_SRC - [1:0] */ 41846a504a75SDimitris Papastamos #define WM8995_SPK1R_SRC_SHIFT 0 /* SPK1R_SRC - [1:0] */ 41856a504a75SDimitris Papastamos #define WM8995_SPK1R_SRC_WIDTH 2 /* SPK1R_SRC - [1:0] */ 41866a504a75SDimitris Papastamos 41876a504a75SDimitris Papastamos /* 41886a504a75SDimitris Papastamos * R2050 (0x802) - PDM Speaker 1 Mute Sequence 41896a504a75SDimitris Papastamos */ 41906a504a75SDimitris Papastamos #define WM8995_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 41916a504a75SDimitris Papastamos #define WM8995_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 41926a504a75SDimitris Papastamos #define WM8995_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 41936a504a75SDimitris Papastamos 41946a504a75SDimitris Papastamos /* 41956a504a75SDimitris Papastamos * R2056 (0x808) - Left PDM Speaker 2 41966a504a75SDimitris Papastamos */ 41976a504a75SDimitris Papastamos #define WM8995_SPK2L_ENA 0x0010 /* SPK2L_ENA */ 41986a504a75SDimitris Papastamos #define WM8995_SPK2L_ENA_MASK 0x0010 /* SPK2L_ENA */ 41996a504a75SDimitris Papastamos #define WM8995_SPK2L_ENA_SHIFT 4 /* SPK2L_ENA */ 42006a504a75SDimitris Papastamos #define WM8995_SPK2L_ENA_WIDTH 1 /* SPK2L_ENA */ 42016a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE 0x0008 /* SPK2L_MUTE */ 42026a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_MASK 0x0008 /* SPK2L_MUTE */ 42036a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_SHIFT 3 /* SPK2L_MUTE */ 42046a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 42056a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_ZC 0x0004 /* SPK2L_MUTE_ZC */ 42066a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_ZC_MASK 0x0004 /* SPK2L_MUTE_ZC */ 42076a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_ZC_SHIFT 2 /* SPK2L_MUTE_ZC */ 42086a504a75SDimitris Papastamos #define WM8995_SPK2L_MUTE_ZC_WIDTH 1 /* SPK2L_MUTE_ZC */ 42096a504a75SDimitris Papastamos #define WM8995_SPK2L_SRC_MASK 0x0003 /* SPK2L_SRC - [1:0] */ 42106a504a75SDimitris Papastamos #define WM8995_SPK2L_SRC_SHIFT 0 /* SPK2L_SRC - [1:0] */ 42116a504a75SDimitris Papastamos #define WM8995_SPK2L_SRC_WIDTH 2 /* SPK2L_SRC - [1:0] */ 42126a504a75SDimitris Papastamos 42136a504a75SDimitris Papastamos /* 42146a504a75SDimitris Papastamos * R2057 (0x809) - Right PDM Speaker 2 42156a504a75SDimitris Papastamos */ 42166a504a75SDimitris Papastamos #define WM8995_SPK2R_ENA 0x0010 /* SPK2R_ENA */ 42176a504a75SDimitris Papastamos #define WM8995_SPK2R_ENA_MASK 0x0010 /* SPK2R_ENA */ 42186a504a75SDimitris Papastamos #define WM8995_SPK2R_ENA_SHIFT 4 /* SPK2R_ENA */ 42196a504a75SDimitris Papastamos #define WM8995_SPK2R_ENA_WIDTH 1 /* SPK2R_ENA */ 42206a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE 0x0008 /* SPK2R_MUTE */ 42216a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_MASK 0x0008 /* SPK2R_MUTE */ 42226a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_SHIFT 3 /* SPK2R_MUTE */ 42236a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 42246a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_ZC 0x0004 /* SPK2R_MUTE_ZC */ 42256a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_ZC_MASK 0x0004 /* SPK2R_MUTE_ZC */ 42266a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_ZC_SHIFT 2 /* SPK2R_MUTE_ZC */ 42276a504a75SDimitris Papastamos #define WM8995_SPK2R_MUTE_ZC_WIDTH 1 /* SPK2R_MUTE_ZC */ 42286a504a75SDimitris Papastamos #define WM8995_SPK2R_SRC_MASK 0x0003 /* SPK2R_SRC - [1:0] */ 42296a504a75SDimitris Papastamos #define WM8995_SPK2R_SRC_SHIFT 0 /* SPK2R_SRC - [1:0] */ 42306a504a75SDimitris Papastamos #define WM8995_SPK2R_SRC_WIDTH 2 /* SPK2R_SRC - [1:0] */ 42316a504a75SDimitris Papastamos 42326a504a75SDimitris Papastamos /* 42336a504a75SDimitris Papastamos * R2058 (0x80A) - PDM Speaker 2 Mute Sequence 42346a504a75SDimitris Papastamos */ 42356a504a75SDimitris Papastamos #define WM8995_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 42366a504a75SDimitris Papastamos #define WM8995_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 42376a504a75SDimitris Papastamos #define WM8995_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 42386a504a75SDimitris Papastamos 42396a504a75SDimitris Papastamos /* 42406a504a75SDimitris Papastamos * R12288 (0x3000) - Write Sequencer 0 42416a504a75SDimitris Papastamos */ 42426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR0_MASK 0x3FFF /* WSEQ_ADDR0 - [13:0] */ 42436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR0_SHIFT 0 /* WSEQ_ADDR0 - [13:0] */ 42446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR0_WIDTH 14 /* WSEQ_ADDR0 - [13:0] */ 42456a504a75SDimitris Papastamos 42466a504a75SDimitris Papastamos /* 42476a504a75SDimitris Papastamos * R12289 (0x3001) - Write Sequencer 1 42486a504a75SDimitris Papastamos */ 42496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA0_MASK 0x00FF /* WSEQ_DATA0 - [7:0] */ 42506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA0_SHIFT 0 /* WSEQ_DATA0 - [7:0] */ 42516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA0_WIDTH 8 /* WSEQ_DATA0 - [7:0] */ 42526a504a75SDimitris Papastamos 42536a504a75SDimitris Papastamos /* 42546a504a75SDimitris Papastamos * R12290 (0x3002) - Write Sequencer 2 42556a504a75SDimitris Papastamos */ 42566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH0_MASK 0x0700 /* WSEQ_DATA_WIDTH0 - [10:8] */ 42576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH0_SHIFT 8 /* WSEQ_DATA_WIDTH0 - [10:8] */ 42586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH0_WIDTH 3 /* WSEQ_DATA_WIDTH0 - [10:8] */ 42596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START0_MASK 0x000F /* WSEQ_DATA_START0 - [3:0] */ 42606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START0_SHIFT 0 /* WSEQ_DATA_START0 - [3:0] */ 42616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START0_WIDTH 4 /* WSEQ_DATA_START0 - [3:0] */ 42626a504a75SDimitris Papastamos 42636a504a75SDimitris Papastamos /* 42646a504a75SDimitris Papastamos * R12291 (0x3003) - Write Sequencer 3 42656a504a75SDimitris Papastamos */ 42666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS0 0x0100 /* WSEQ_EOS0 */ 42676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS0_MASK 0x0100 /* WSEQ_EOS0 */ 42686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS0_SHIFT 8 /* WSEQ_EOS0 */ 42696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS0_WIDTH 1 /* WSEQ_EOS0 */ 42706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY0_MASK 0x000F /* WSEQ_DELAY0 - [3:0] */ 42716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY0_SHIFT 0 /* WSEQ_DELAY0 - [3:0] */ 42726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY0_WIDTH 4 /* WSEQ_DELAY0 - [3:0] */ 42736a504a75SDimitris Papastamos 42746a504a75SDimitris Papastamos /* 42756a504a75SDimitris Papastamos * R12292 (0x3004) - Write Sequencer 4 42766a504a75SDimitris Papastamos */ 42776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR1_MASK 0x3FFF /* WSEQ_ADDR1 - [13:0] */ 42786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR1_SHIFT 0 /* WSEQ_ADDR1 - [13:0] */ 42796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR1_WIDTH 14 /* WSEQ_ADDR1 - [13:0] */ 42806a504a75SDimitris Papastamos 42816a504a75SDimitris Papastamos /* 42826a504a75SDimitris Papastamos * R12293 (0x3005) - Write Sequencer 5 42836a504a75SDimitris Papastamos */ 42846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA1_MASK 0x00FF /* WSEQ_DATA1 - [7:0] */ 42856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA1_SHIFT 0 /* WSEQ_DATA1 - [7:0] */ 42866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA1_WIDTH 8 /* WSEQ_DATA1 - [7:0] */ 42876a504a75SDimitris Papastamos 42886a504a75SDimitris Papastamos /* 42896a504a75SDimitris Papastamos * R12294 (0x3006) - Write Sequencer 6 42906a504a75SDimitris Papastamos */ 42916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH1_MASK 0x0700 /* WSEQ_DATA_WIDTH1 - [10:8] */ 42926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH1_SHIFT 8 /* WSEQ_DATA_WIDTH1 - [10:8] */ 42936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH1_WIDTH 3 /* WSEQ_DATA_WIDTH1 - [10:8] */ 42946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START1_MASK 0x000F /* WSEQ_DATA_START1 - [3:0] */ 42956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START1_SHIFT 0 /* WSEQ_DATA_START1 - [3:0] */ 42966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START1_WIDTH 4 /* WSEQ_DATA_START1 - [3:0] */ 42976a504a75SDimitris Papastamos 42986a504a75SDimitris Papastamos /* 42996a504a75SDimitris Papastamos * R12295 (0x3007) - Write Sequencer 7 43006a504a75SDimitris Papastamos */ 43016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS1 0x0100 /* WSEQ_EOS1 */ 43026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS1_MASK 0x0100 /* WSEQ_EOS1 */ 43036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS1_SHIFT 8 /* WSEQ_EOS1 */ 43046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS1_WIDTH 1 /* WSEQ_EOS1 */ 43056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY1_MASK 0x000F /* WSEQ_DELAY1 - [3:0] */ 43066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY1_SHIFT 0 /* WSEQ_DELAY1 - [3:0] */ 43076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY1_WIDTH 4 /* WSEQ_DELAY1 - [3:0] */ 43086a504a75SDimitris Papastamos 43096a504a75SDimitris Papastamos /* 43106a504a75SDimitris Papastamos * R12296 (0x3008) - Write Sequencer 8 43116a504a75SDimitris Papastamos */ 43126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR2_MASK 0x3FFF /* WSEQ_ADDR2 - [13:0] */ 43136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR2_SHIFT 0 /* WSEQ_ADDR2 - [13:0] */ 43146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR2_WIDTH 14 /* WSEQ_ADDR2 - [13:0] */ 43156a504a75SDimitris Papastamos 43166a504a75SDimitris Papastamos /* 43176a504a75SDimitris Papastamos * R12297 (0x3009) - Write Sequencer 9 43186a504a75SDimitris Papastamos */ 43196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA2_MASK 0x00FF /* WSEQ_DATA2 - [7:0] */ 43206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA2_SHIFT 0 /* WSEQ_DATA2 - [7:0] */ 43216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA2_WIDTH 8 /* WSEQ_DATA2 - [7:0] */ 43226a504a75SDimitris Papastamos 43236a504a75SDimitris Papastamos /* 43246a504a75SDimitris Papastamos * R12298 (0x300A) - Write Sequencer 10 43256a504a75SDimitris Papastamos */ 43266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH2_MASK 0x0700 /* WSEQ_DATA_WIDTH2 - [10:8] */ 43276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH2_SHIFT 8 /* WSEQ_DATA_WIDTH2 - [10:8] */ 43286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH2_WIDTH 3 /* WSEQ_DATA_WIDTH2 - [10:8] */ 43296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START2_MASK 0x000F /* WSEQ_DATA_START2 - [3:0] */ 43306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START2_SHIFT 0 /* WSEQ_DATA_START2 - [3:0] */ 43316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START2_WIDTH 4 /* WSEQ_DATA_START2 - [3:0] */ 43326a504a75SDimitris Papastamos 43336a504a75SDimitris Papastamos /* 43346a504a75SDimitris Papastamos * R12299 (0x300B) - Write Sequencer 11 43356a504a75SDimitris Papastamos */ 43366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS2 0x0100 /* WSEQ_EOS2 */ 43376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS2_MASK 0x0100 /* WSEQ_EOS2 */ 43386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS2_SHIFT 8 /* WSEQ_EOS2 */ 43396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS2_WIDTH 1 /* WSEQ_EOS2 */ 43406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY2_MASK 0x000F /* WSEQ_DELAY2 - [3:0] */ 43416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY2_SHIFT 0 /* WSEQ_DELAY2 - [3:0] */ 43426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY2_WIDTH 4 /* WSEQ_DELAY2 - [3:0] */ 43436a504a75SDimitris Papastamos 43446a504a75SDimitris Papastamos /* 43456a504a75SDimitris Papastamos * R12300 (0x300C) - Write Sequencer 12 43466a504a75SDimitris Papastamos */ 43476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR3_MASK 0x3FFF /* WSEQ_ADDR3 - [13:0] */ 43486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR3_SHIFT 0 /* WSEQ_ADDR3 - [13:0] */ 43496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR3_WIDTH 14 /* WSEQ_ADDR3 - [13:0] */ 43506a504a75SDimitris Papastamos 43516a504a75SDimitris Papastamos /* 43526a504a75SDimitris Papastamos * R12301 (0x300D) - Write Sequencer 13 43536a504a75SDimitris Papastamos */ 43546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA3_MASK 0x00FF /* WSEQ_DATA3 - [7:0] */ 43556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA3_SHIFT 0 /* WSEQ_DATA3 - [7:0] */ 43566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA3_WIDTH 8 /* WSEQ_DATA3 - [7:0] */ 43576a504a75SDimitris Papastamos 43586a504a75SDimitris Papastamos /* 43596a504a75SDimitris Papastamos * R12302 (0x300E) - Write Sequencer 14 43606a504a75SDimitris Papastamos */ 43616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH3_MASK 0x0700 /* WSEQ_DATA_WIDTH3 - [10:8] */ 43626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH3_SHIFT 8 /* WSEQ_DATA_WIDTH3 - [10:8] */ 43636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH3_WIDTH 3 /* WSEQ_DATA_WIDTH3 - [10:8] */ 43646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START3_MASK 0x000F /* WSEQ_DATA_START3 - [3:0] */ 43656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START3_SHIFT 0 /* WSEQ_DATA_START3 - [3:0] */ 43666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START3_WIDTH 4 /* WSEQ_DATA_START3 - [3:0] */ 43676a504a75SDimitris Papastamos 43686a504a75SDimitris Papastamos /* 43696a504a75SDimitris Papastamos * R12303 (0x300F) - Write Sequencer 15 43706a504a75SDimitris Papastamos */ 43716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS3 0x0100 /* WSEQ_EOS3 */ 43726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS3_MASK 0x0100 /* WSEQ_EOS3 */ 43736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS3_SHIFT 8 /* WSEQ_EOS3 */ 43746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS3_WIDTH 1 /* WSEQ_EOS3 */ 43756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY3_MASK 0x000F /* WSEQ_DELAY3 - [3:0] */ 43766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY3_SHIFT 0 /* WSEQ_DELAY3 - [3:0] */ 43776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY3_WIDTH 4 /* WSEQ_DELAY3 - [3:0] */ 43786a504a75SDimitris Papastamos 43796a504a75SDimitris Papastamos /* 43806a504a75SDimitris Papastamos * R12304 (0x3010) - Write Sequencer 16 43816a504a75SDimitris Papastamos */ 43826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR4_MASK 0x3FFF /* WSEQ_ADDR4 - [13:0] */ 43836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR4_SHIFT 0 /* WSEQ_ADDR4 - [13:0] */ 43846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR4_WIDTH 14 /* WSEQ_ADDR4 - [13:0] */ 43856a504a75SDimitris Papastamos 43866a504a75SDimitris Papastamos /* 43876a504a75SDimitris Papastamos * R12305 (0x3011) - Write Sequencer 17 43886a504a75SDimitris Papastamos */ 43896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA4_MASK 0x00FF /* WSEQ_DATA4 - [7:0] */ 43906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA4_SHIFT 0 /* WSEQ_DATA4 - [7:0] */ 43916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA4_WIDTH 8 /* WSEQ_DATA4 - [7:0] */ 43926a504a75SDimitris Papastamos 43936a504a75SDimitris Papastamos /* 43946a504a75SDimitris Papastamos * R12306 (0x3012) - Write Sequencer 18 43956a504a75SDimitris Papastamos */ 43966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH4_MASK 0x0700 /* WSEQ_DATA_WIDTH4 - [10:8] */ 43976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH4_SHIFT 8 /* WSEQ_DATA_WIDTH4 - [10:8] */ 43986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH4_WIDTH 3 /* WSEQ_DATA_WIDTH4 - [10:8] */ 43996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START4_MASK 0x000F /* WSEQ_DATA_START4 - [3:0] */ 44006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START4_SHIFT 0 /* WSEQ_DATA_START4 - [3:0] */ 44016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START4_WIDTH 4 /* WSEQ_DATA_START4 - [3:0] */ 44026a504a75SDimitris Papastamos 44036a504a75SDimitris Papastamos /* 44046a504a75SDimitris Papastamos * R12307 (0x3013) - Write Sequencer 19 44056a504a75SDimitris Papastamos */ 44066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS4 0x0100 /* WSEQ_EOS4 */ 44076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS4_MASK 0x0100 /* WSEQ_EOS4 */ 44086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS4_SHIFT 8 /* WSEQ_EOS4 */ 44096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS4_WIDTH 1 /* WSEQ_EOS4 */ 44106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY4_MASK 0x000F /* WSEQ_DELAY4 - [3:0] */ 44116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY4_SHIFT 0 /* WSEQ_DELAY4 - [3:0] */ 44126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY4_WIDTH 4 /* WSEQ_DELAY4 - [3:0] */ 44136a504a75SDimitris Papastamos 44146a504a75SDimitris Papastamos /* 44156a504a75SDimitris Papastamos * R12308 (0x3014) - Write Sequencer 20 44166a504a75SDimitris Papastamos */ 44176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR5_MASK 0x3FFF /* WSEQ_ADDR5 - [13:0] */ 44186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR5_SHIFT 0 /* WSEQ_ADDR5 - [13:0] */ 44196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR5_WIDTH 14 /* WSEQ_ADDR5 - [13:0] */ 44206a504a75SDimitris Papastamos 44216a504a75SDimitris Papastamos /* 44226a504a75SDimitris Papastamos * R12309 (0x3015) - Write Sequencer 21 44236a504a75SDimitris Papastamos */ 44246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA5_MASK 0x00FF /* WSEQ_DATA5 - [7:0] */ 44256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA5_SHIFT 0 /* WSEQ_DATA5 - [7:0] */ 44266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA5_WIDTH 8 /* WSEQ_DATA5 - [7:0] */ 44276a504a75SDimitris Papastamos 44286a504a75SDimitris Papastamos /* 44296a504a75SDimitris Papastamos * R12310 (0x3016) - Write Sequencer 22 44306a504a75SDimitris Papastamos */ 44316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH5_MASK 0x0700 /* WSEQ_DATA_WIDTH5 - [10:8] */ 44326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH5_SHIFT 8 /* WSEQ_DATA_WIDTH5 - [10:8] */ 44336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH5_WIDTH 3 /* WSEQ_DATA_WIDTH5 - [10:8] */ 44346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START5_MASK 0x000F /* WSEQ_DATA_START5 - [3:0] */ 44356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START5_SHIFT 0 /* WSEQ_DATA_START5 - [3:0] */ 44366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START5_WIDTH 4 /* WSEQ_DATA_START5 - [3:0] */ 44376a504a75SDimitris Papastamos 44386a504a75SDimitris Papastamos /* 44396a504a75SDimitris Papastamos * R12311 (0x3017) - Write Sequencer 23 44406a504a75SDimitris Papastamos */ 44416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS5 0x0100 /* WSEQ_EOS5 */ 44426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS5_MASK 0x0100 /* WSEQ_EOS5 */ 44436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS5_SHIFT 8 /* WSEQ_EOS5 */ 44446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS5_WIDTH 1 /* WSEQ_EOS5 */ 44456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY5_MASK 0x000F /* WSEQ_DELAY5 - [3:0] */ 44466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY5_SHIFT 0 /* WSEQ_DELAY5 - [3:0] */ 44476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY5_WIDTH 4 /* WSEQ_DELAY5 - [3:0] */ 44486a504a75SDimitris Papastamos 44496a504a75SDimitris Papastamos /* 44506a504a75SDimitris Papastamos * R12312 (0x3018) - Write Sequencer 24 44516a504a75SDimitris Papastamos */ 44526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR6_MASK 0x3FFF /* WSEQ_ADDR6 - [13:0] */ 44536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR6_SHIFT 0 /* WSEQ_ADDR6 - [13:0] */ 44546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR6_WIDTH 14 /* WSEQ_ADDR6 - [13:0] */ 44556a504a75SDimitris Papastamos 44566a504a75SDimitris Papastamos /* 44576a504a75SDimitris Papastamos * R12313 (0x3019) - Write Sequencer 25 44586a504a75SDimitris Papastamos */ 44596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA6_MASK 0x00FF /* WSEQ_DATA6 - [7:0] */ 44606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA6_SHIFT 0 /* WSEQ_DATA6 - [7:0] */ 44616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA6_WIDTH 8 /* WSEQ_DATA6 - [7:0] */ 44626a504a75SDimitris Papastamos 44636a504a75SDimitris Papastamos /* 44646a504a75SDimitris Papastamos * R12314 (0x301A) - Write Sequencer 26 44656a504a75SDimitris Papastamos */ 44666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH6_MASK 0x0700 /* WSEQ_DATA_WIDTH6 - [10:8] */ 44676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH6_SHIFT 8 /* WSEQ_DATA_WIDTH6 - [10:8] */ 44686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH6_WIDTH 3 /* WSEQ_DATA_WIDTH6 - [10:8] */ 44696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START6_MASK 0x000F /* WSEQ_DATA_START6 - [3:0] */ 44706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START6_SHIFT 0 /* WSEQ_DATA_START6 - [3:0] */ 44716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START6_WIDTH 4 /* WSEQ_DATA_START6 - [3:0] */ 44726a504a75SDimitris Papastamos 44736a504a75SDimitris Papastamos /* 44746a504a75SDimitris Papastamos * R12315 (0x301B) - Write Sequencer 27 44756a504a75SDimitris Papastamos */ 44766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS6 0x0100 /* WSEQ_EOS6 */ 44776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS6_MASK 0x0100 /* WSEQ_EOS6 */ 44786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS6_SHIFT 8 /* WSEQ_EOS6 */ 44796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS6_WIDTH 1 /* WSEQ_EOS6 */ 44806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY6_MASK 0x000F /* WSEQ_DELAY6 - [3:0] */ 44816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY6_SHIFT 0 /* WSEQ_DELAY6 - [3:0] */ 44826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY6_WIDTH 4 /* WSEQ_DELAY6 - [3:0] */ 44836a504a75SDimitris Papastamos 44846a504a75SDimitris Papastamos /* 44856a504a75SDimitris Papastamos * R12316 (0x301C) - Write Sequencer 28 44866a504a75SDimitris Papastamos */ 44876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR7_MASK 0x3FFF /* WSEQ_ADDR7 - [13:0] */ 44886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR7_SHIFT 0 /* WSEQ_ADDR7 - [13:0] */ 44896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR7_WIDTH 14 /* WSEQ_ADDR7 - [13:0] */ 44906a504a75SDimitris Papastamos 44916a504a75SDimitris Papastamos /* 44926a504a75SDimitris Papastamos * R12317 (0x301D) - Write Sequencer 29 44936a504a75SDimitris Papastamos */ 44946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA7_MASK 0x00FF /* WSEQ_DATA7 - [7:0] */ 44956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA7_SHIFT 0 /* WSEQ_DATA7 - [7:0] */ 44966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA7_WIDTH 8 /* WSEQ_DATA7 - [7:0] */ 44976a504a75SDimitris Papastamos 44986a504a75SDimitris Papastamos /* 44996a504a75SDimitris Papastamos * R12318 (0x301E) - Write Sequencer 30 45006a504a75SDimitris Papastamos */ 45016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH7_MASK 0x0700 /* WSEQ_DATA_WIDTH7 - [10:8] */ 45026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH7_SHIFT 8 /* WSEQ_DATA_WIDTH7 - [10:8] */ 45036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH7_WIDTH 3 /* WSEQ_DATA_WIDTH7 - [10:8] */ 45046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START7_MASK 0x000F /* WSEQ_DATA_START7 - [3:0] */ 45056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START7_SHIFT 0 /* WSEQ_DATA_START7 - [3:0] */ 45066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START7_WIDTH 4 /* WSEQ_DATA_START7 - [3:0] */ 45076a504a75SDimitris Papastamos 45086a504a75SDimitris Papastamos /* 45096a504a75SDimitris Papastamos * R12319 (0x301F) - Write Sequencer 31 45106a504a75SDimitris Papastamos */ 45116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS7 0x0100 /* WSEQ_EOS7 */ 45126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS7_MASK 0x0100 /* WSEQ_EOS7 */ 45136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS7_SHIFT 8 /* WSEQ_EOS7 */ 45146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS7_WIDTH 1 /* WSEQ_EOS7 */ 45156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY7_MASK 0x000F /* WSEQ_DELAY7 - [3:0] */ 45166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY7_SHIFT 0 /* WSEQ_DELAY7 - [3:0] */ 45176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY7_WIDTH 4 /* WSEQ_DELAY7 - [3:0] */ 45186a504a75SDimitris Papastamos 45196a504a75SDimitris Papastamos /* 45206a504a75SDimitris Papastamos * R12320 (0x3020) - Write Sequencer 32 45216a504a75SDimitris Papastamos */ 45226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR8_MASK 0x3FFF /* WSEQ_ADDR8 - [13:0] */ 45236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR8_SHIFT 0 /* WSEQ_ADDR8 - [13:0] */ 45246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR8_WIDTH 14 /* WSEQ_ADDR8 - [13:0] */ 45256a504a75SDimitris Papastamos 45266a504a75SDimitris Papastamos /* 45276a504a75SDimitris Papastamos * R12321 (0x3021) - Write Sequencer 33 45286a504a75SDimitris Papastamos */ 45296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA8_MASK 0x00FF /* WSEQ_DATA8 - [7:0] */ 45306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA8_SHIFT 0 /* WSEQ_DATA8 - [7:0] */ 45316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA8_WIDTH 8 /* WSEQ_DATA8 - [7:0] */ 45326a504a75SDimitris Papastamos 45336a504a75SDimitris Papastamos /* 45346a504a75SDimitris Papastamos * R12322 (0x3022) - Write Sequencer 34 45356a504a75SDimitris Papastamos */ 45366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH8_MASK 0x0700 /* WSEQ_DATA_WIDTH8 - [10:8] */ 45376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH8_SHIFT 8 /* WSEQ_DATA_WIDTH8 - [10:8] */ 45386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH8_WIDTH 3 /* WSEQ_DATA_WIDTH8 - [10:8] */ 45396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START8_MASK 0x000F /* WSEQ_DATA_START8 - [3:0] */ 45406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START8_SHIFT 0 /* WSEQ_DATA_START8 - [3:0] */ 45416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START8_WIDTH 4 /* WSEQ_DATA_START8 - [3:0] */ 45426a504a75SDimitris Papastamos 45436a504a75SDimitris Papastamos /* 45446a504a75SDimitris Papastamos * R12323 (0x3023) - Write Sequencer 35 45456a504a75SDimitris Papastamos */ 45466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS8 0x0100 /* WSEQ_EOS8 */ 45476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS8_MASK 0x0100 /* WSEQ_EOS8 */ 45486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS8_SHIFT 8 /* WSEQ_EOS8 */ 45496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS8_WIDTH 1 /* WSEQ_EOS8 */ 45506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY8_MASK 0x000F /* WSEQ_DELAY8 - [3:0] */ 45516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY8_SHIFT 0 /* WSEQ_DELAY8 - [3:0] */ 45526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY8_WIDTH 4 /* WSEQ_DELAY8 - [3:0] */ 45536a504a75SDimitris Papastamos 45546a504a75SDimitris Papastamos /* 45556a504a75SDimitris Papastamos * R12324 (0x3024) - Write Sequencer 36 45566a504a75SDimitris Papastamos */ 45576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR9_MASK 0x3FFF /* WSEQ_ADDR9 - [13:0] */ 45586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR9_SHIFT 0 /* WSEQ_ADDR9 - [13:0] */ 45596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR9_WIDTH 14 /* WSEQ_ADDR9 - [13:0] */ 45606a504a75SDimitris Papastamos 45616a504a75SDimitris Papastamos /* 45626a504a75SDimitris Papastamos * R12325 (0x3025) - Write Sequencer 37 45636a504a75SDimitris Papastamos */ 45646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA9_MASK 0x00FF /* WSEQ_DATA9 - [7:0] */ 45656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA9_SHIFT 0 /* WSEQ_DATA9 - [7:0] */ 45666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA9_WIDTH 8 /* WSEQ_DATA9 - [7:0] */ 45676a504a75SDimitris Papastamos 45686a504a75SDimitris Papastamos /* 45696a504a75SDimitris Papastamos * R12326 (0x3026) - Write Sequencer 38 45706a504a75SDimitris Papastamos */ 45716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH9_MASK 0x0700 /* WSEQ_DATA_WIDTH9 - [10:8] */ 45726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH9_SHIFT 8 /* WSEQ_DATA_WIDTH9 - [10:8] */ 45736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH9_WIDTH 3 /* WSEQ_DATA_WIDTH9 - [10:8] */ 45746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START9_MASK 0x000F /* WSEQ_DATA_START9 - [3:0] */ 45756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START9_SHIFT 0 /* WSEQ_DATA_START9 - [3:0] */ 45766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START9_WIDTH 4 /* WSEQ_DATA_START9 - [3:0] */ 45776a504a75SDimitris Papastamos 45786a504a75SDimitris Papastamos /* 45796a504a75SDimitris Papastamos * R12327 (0x3027) - Write Sequencer 39 45806a504a75SDimitris Papastamos */ 45816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS9 0x0100 /* WSEQ_EOS9 */ 45826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS9_MASK 0x0100 /* WSEQ_EOS9 */ 45836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS9_SHIFT 8 /* WSEQ_EOS9 */ 45846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS9_WIDTH 1 /* WSEQ_EOS9 */ 45856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY9_MASK 0x000F /* WSEQ_DELAY9 - [3:0] */ 45866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY9_SHIFT 0 /* WSEQ_DELAY9 - [3:0] */ 45876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY9_WIDTH 4 /* WSEQ_DELAY9 - [3:0] */ 45886a504a75SDimitris Papastamos 45896a504a75SDimitris Papastamos /* 45906a504a75SDimitris Papastamos * R12328 (0x3028) - Write Sequencer 40 45916a504a75SDimitris Papastamos */ 45926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR10_MASK 0x3FFF /* WSEQ_ADDR10 - [13:0] */ 45936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR10_SHIFT 0 /* WSEQ_ADDR10 - [13:0] */ 45946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR10_WIDTH 14 /* WSEQ_ADDR10 - [13:0] */ 45956a504a75SDimitris Papastamos 45966a504a75SDimitris Papastamos /* 45976a504a75SDimitris Papastamos * R12329 (0x3029) - Write Sequencer 41 45986a504a75SDimitris Papastamos */ 45996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA10_MASK 0x00FF /* WSEQ_DATA10 - [7:0] */ 46006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA10_SHIFT 0 /* WSEQ_DATA10 - [7:0] */ 46016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA10_WIDTH 8 /* WSEQ_DATA10 - [7:0] */ 46026a504a75SDimitris Papastamos 46036a504a75SDimitris Papastamos /* 46046a504a75SDimitris Papastamos * R12330 (0x302A) - Write Sequencer 42 46056a504a75SDimitris Papastamos */ 46066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH10_MASK 0x0700 /* WSEQ_DATA_WIDTH10 - [10:8] */ 46076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH10_SHIFT 8 /* WSEQ_DATA_WIDTH10 - [10:8] */ 46086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH10_WIDTH 3 /* WSEQ_DATA_WIDTH10 - [10:8] */ 46096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START10_MASK 0x000F /* WSEQ_DATA_START10 - [3:0] */ 46106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START10_SHIFT 0 /* WSEQ_DATA_START10 - [3:0] */ 46116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START10_WIDTH 4 /* WSEQ_DATA_START10 - [3:0] */ 46126a504a75SDimitris Papastamos 46136a504a75SDimitris Papastamos /* 46146a504a75SDimitris Papastamos * R12331 (0x302B) - Write Sequencer 43 46156a504a75SDimitris Papastamos */ 46166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS10 0x0100 /* WSEQ_EOS10 */ 46176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS10_MASK 0x0100 /* WSEQ_EOS10 */ 46186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS10_SHIFT 8 /* WSEQ_EOS10 */ 46196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS10_WIDTH 1 /* WSEQ_EOS10 */ 46206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY10_MASK 0x000F /* WSEQ_DELAY10 - [3:0] */ 46216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY10_SHIFT 0 /* WSEQ_DELAY10 - [3:0] */ 46226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY10_WIDTH 4 /* WSEQ_DELAY10 - [3:0] */ 46236a504a75SDimitris Papastamos 46246a504a75SDimitris Papastamos /* 46256a504a75SDimitris Papastamos * R12332 (0x302C) - Write Sequencer 44 46266a504a75SDimitris Papastamos */ 46276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR11_MASK 0x3FFF /* WSEQ_ADDR11 - [13:0] */ 46286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR11_SHIFT 0 /* WSEQ_ADDR11 - [13:0] */ 46296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR11_WIDTH 14 /* WSEQ_ADDR11 - [13:0] */ 46306a504a75SDimitris Papastamos 46316a504a75SDimitris Papastamos /* 46326a504a75SDimitris Papastamos * R12333 (0x302D) - Write Sequencer 45 46336a504a75SDimitris Papastamos */ 46346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA11_MASK 0x00FF /* WSEQ_DATA11 - [7:0] */ 46356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA11_SHIFT 0 /* WSEQ_DATA11 - [7:0] */ 46366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA11_WIDTH 8 /* WSEQ_DATA11 - [7:0] */ 46376a504a75SDimitris Papastamos 46386a504a75SDimitris Papastamos /* 46396a504a75SDimitris Papastamos * R12334 (0x302E) - Write Sequencer 46 46406a504a75SDimitris Papastamos */ 46416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH11_MASK 0x0700 /* WSEQ_DATA_WIDTH11 - [10:8] */ 46426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH11_SHIFT 8 /* WSEQ_DATA_WIDTH11 - [10:8] */ 46436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH11_WIDTH 3 /* WSEQ_DATA_WIDTH11 - [10:8] */ 46446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START11_MASK 0x000F /* WSEQ_DATA_START11 - [3:0] */ 46456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START11_SHIFT 0 /* WSEQ_DATA_START11 - [3:0] */ 46466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START11_WIDTH 4 /* WSEQ_DATA_START11 - [3:0] */ 46476a504a75SDimitris Papastamos 46486a504a75SDimitris Papastamos /* 46496a504a75SDimitris Papastamos * R12335 (0x302F) - Write Sequencer 47 46506a504a75SDimitris Papastamos */ 46516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS11 0x0100 /* WSEQ_EOS11 */ 46526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS11_MASK 0x0100 /* WSEQ_EOS11 */ 46536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS11_SHIFT 8 /* WSEQ_EOS11 */ 46546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS11_WIDTH 1 /* WSEQ_EOS11 */ 46556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY11_MASK 0x000F /* WSEQ_DELAY11 - [3:0] */ 46566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY11_SHIFT 0 /* WSEQ_DELAY11 - [3:0] */ 46576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY11_WIDTH 4 /* WSEQ_DELAY11 - [3:0] */ 46586a504a75SDimitris Papastamos 46596a504a75SDimitris Papastamos /* 46606a504a75SDimitris Papastamos * R12336 (0x3030) - Write Sequencer 48 46616a504a75SDimitris Papastamos */ 46626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR12_MASK 0x3FFF /* WSEQ_ADDR12 - [13:0] */ 46636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR12_SHIFT 0 /* WSEQ_ADDR12 - [13:0] */ 46646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR12_WIDTH 14 /* WSEQ_ADDR12 - [13:0] */ 46656a504a75SDimitris Papastamos 46666a504a75SDimitris Papastamos /* 46676a504a75SDimitris Papastamos * R12337 (0x3031) - Write Sequencer 49 46686a504a75SDimitris Papastamos */ 46696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA12_MASK 0x00FF /* WSEQ_DATA12 - [7:0] */ 46706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA12_SHIFT 0 /* WSEQ_DATA12 - [7:0] */ 46716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA12_WIDTH 8 /* WSEQ_DATA12 - [7:0] */ 46726a504a75SDimitris Papastamos 46736a504a75SDimitris Papastamos /* 46746a504a75SDimitris Papastamos * R12338 (0x3032) - Write Sequencer 50 46756a504a75SDimitris Papastamos */ 46766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH12_MASK 0x0700 /* WSEQ_DATA_WIDTH12 - [10:8] */ 46776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH12_SHIFT 8 /* WSEQ_DATA_WIDTH12 - [10:8] */ 46786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH12_WIDTH 3 /* WSEQ_DATA_WIDTH12 - [10:8] */ 46796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START12_MASK 0x000F /* WSEQ_DATA_START12 - [3:0] */ 46806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START12_SHIFT 0 /* WSEQ_DATA_START12 - [3:0] */ 46816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START12_WIDTH 4 /* WSEQ_DATA_START12 - [3:0] */ 46826a504a75SDimitris Papastamos 46836a504a75SDimitris Papastamos /* 46846a504a75SDimitris Papastamos * R12339 (0x3033) - Write Sequencer 51 46856a504a75SDimitris Papastamos */ 46866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS12 0x0100 /* WSEQ_EOS12 */ 46876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS12_MASK 0x0100 /* WSEQ_EOS12 */ 46886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS12_SHIFT 8 /* WSEQ_EOS12 */ 46896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS12_WIDTH 1 /* WSEQ_EOS12 */ 46906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY12_MASK 0x000F /* WSEQ_DELAY12 - [3:0] */ 46916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY12_SHIFT 0 /* WSEQ_DELAY12 - [3:0] */ 46926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY12_WIDTH 4 /* WSEQ_DELAY12 - [3:0] */ 46936a504a75SDimitris Papastamos 46946a504a75SDimitris Papastamos /* 46956a504a75SDimitris Papastamos * R12340 (0x3034) - Write Sequencer 52 46966a504a75SDimitris Papastamos */ 46976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR13_MASK 0x3FFF /* WSEQ_ADDR13 - [13:0] */ 46986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR13_SHIFT 0 /* WSEQ_ADDR13 - [13:0] */ 46996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR13_WIDTH 14 /* WSEQ_ADDR13 - [13:0] */ 47006a504a75SDimitris Papastamos 47016a504a75SDimitris Papastamos /* 47026a504a75SDimitris Papastamos * R12341 (0x3035) - Write Sequencer 53 47036a504a75SDimitris Papastamos */ 47046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA13_MASK 0x00FF /* WSEQ_DATA13 - [7:0] */ 47056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA13_SHIFT 0 /* WSEQ_DATA13 - [7:0] */ 47066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA13_WIDTH 8 /* WSEQ_DATA13 - [7:0] */ 47076a504a75SDimitris Papastamos 47086a504a75SDimitris Papastamos /* 47096a504a75SDimitris Papastamos * R12342 (0x3036) - Write Sequencer 54 47106a504a75SDimitris Papastamos */ 47116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH13_MASK 0x0700 /* WSEQ_DATA_WIDTH13 - [10:8] */ 47126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH13_SHIFT 8 /* WSEQ_DATA_WIDTH13 - [10:8] */ 47136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH13_WIDTH 3 /* WSEQ_DATA_WIDTH13 - [10:8] */ 47146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START13_MASK 0x000F /* WSEQ_DATA_START13 - [3:0] */ 47156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START13_SHIFT 0 /* WSEQ_DATA_START13 - [3:0] */ 47166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START13_WIDTH 4 /* WSEQ_DATA_START13 - [3:0] */ 47176a504a75SDimitris Papastamos 47186a504a75SDimitris Papastamos /* 47196a504a75SDimitris Papastamos * R12343 (0x3037) - Write Sequencer 55 47206a504a75SDimitris Papastamos */ 47216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS13 0x0100 /* WSEQ_EOS13 */ 47226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS13_MASK 0x0100 /* WSEQ_EOS13 */ 47236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS13_SHIFT 8 /* WSEQ_EOS13 */ 47246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS13_WIDTH 1 /* WSEQ_EOS13 */ 47256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY13_MASK 0x000F /* WSEQ_DELAY13 - [3:0] */ 47266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY13_SHIFT 0 /* WSEQ_DELAY13 - [3:0] */ 47276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY13_WIDTH 4 /* WSEQ_DELAY13 - [3:0] */ 47286a504a75SDimitris Papastamos 47296a504a75SDimitris Papastamos /* 47306a504a75SDimitris Papastamos * R12344 (0x3038) - Write Sequencer 56 47316a504a75SDimitris Papastamos */ 47326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR14_MASK 0x3FFF /* WSEQ_ADDR14 - [13:0] */ 47336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR14_SHIFT 0 /* WSEQ_ADDR14 - [13:0] */ 47346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR14_WIDTH 14 /* WSEQ_ADDR14 - [13:0] */ 47356a504a75SDimitris Papastamos 47366a504a75SDimitris Papastamos /* 47376a504a75SDimitris Papastamos * R12345 (0x3039) - Write Sequencer 57 47386a504a75SDimitris Papastamos */ 47396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA14_MASK 0x00FF /* WSEQ_DATA14 - [7:0] */ 47406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA14_SHIFT 0 /* WSEQ_DATA14 - [7:0] */ 47416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA14_WIDTH 8 /* WSEQ_DATA14 - [7:0] */ 47426a504a75SDimitris Papastamos 47436a504a75SDimitris Papastamos /* 47446a504a75SDimitris Papastamos * R12346 (0x303A) - Write Sequencer 58 47456a504a75SDimitris Papastamos */ 47466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH14_MASK 0x0700 /* WSEQ_DATA_WIDTH14 - [10:8] */ 47476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH14_SHIFT 8 /* WSEQ_DATA_WIDTH14 - [10:8] */ 47486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH14_WIDTH 3 /* WSEQ_DATA_WIDTH14 - [10:8] */ 47496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START14_MASK 0x000F /* WSEQ_DATA_START14 - [3:0] */ 47506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START14_SHIFT 0 /* WSEQ_DATA_START14 - [3:0] */ 47516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START14_WIDTH 4 /* WSEQ_DATA_START14 - [3:0] */ 47526a504a75SDimitris Papastamos 47536a504a75SDimitris Papastamos /* 47546a504a75SDimitris Papastamos * R12347 (0x303B) - Write Sequencer 59 47556a504a75SDimitris Papastamos */ 47566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS14 0x0100 /* WSEQ_EOS14 */ 47576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS14_MASK 0x0100 /* WSEQ_EOS14 */ 47586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS14_SHIFT 8 /* WSEQ_EOS14 */ 47596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS14_WIDTH 1 /* WSEQ_EOS14 */ 47606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY14_MASK 0x000F /* WSEQ_DELAY14 - [3:0] */ 47616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY14_SHIFT 0 /* WSEQ_DELAY14 - [3:0] */ 47626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY14_WIDTH 4 /* WSEQ_DELAY14 - [3:0] */ 47636a504a75SDimitris Papastamos 47646a504a75SDimitris Papastamos /* 47656a504a75SDimitris Papastamos * R12348 (0x303C) - Write Sequencer 60 47666a504a75SDimitris Papastamos */ 47676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR15_MASK 0x3FFF /* WSEQ_ADDR15 - [13:0] */ 47686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR15_SHIFT 0 /* WSEQ_ADDR15 - [13:0] */ 47696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR15_WIDTH 14 /* WSEQ_ADDR15 - [13:0] */ 47706a504a75SDimitris Papastamos 47716a504a75SDimitris Papastamos /* 47726a504a75SDimitris Papastamos * R12349 (0x303D) - Write Sequencer 61 47736a504a75SDimitris Papastamos */ 47746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA15_MASK 0x00FF /* WSEQ_DATA15 - [7:0] */ 47756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA15_SHIFT 0 /* WSEQ_DATA15 - [7:0] */ 47766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA15_WIDTH 8 /* WSEQ_DATA15 - [7:0] */ 47776a504a75SDimitris Papastamos 47786a504a75SDimitris Papastamos /* 47796a504a75SDimitris Papastamos * R12350 (0x303E) - Write Sequencer 62 47806a504a75SDimitris Papastamos */ 47816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH15_MASK 0x0700 /* WSEQ_DATA_WIDTH15 - [10:8] */ 47826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH15_SHIFT 8 /* WSEQ_DATA_WIDTH15 - [10:8] */ 47836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH15_WIDTH 3 /* WSEQ_DATA_WIDTH15 - [10:8] */ 47846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START15_MASK 0x000F /* WSEQ_DATA_START15 - [3:0] */ 47856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START15_SHIFT 0 /* WSEQ_DATA_START15 - [3:0] */ 47866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START15_WIDTH 4 /* WSEQ_DATA_START15 - [3:0] */ 47876a504a75SDimitris Papastamos 47886a504a75SDimitris Papastamos /* 47896a504a75SDimitris Papastamos * R12351 (0x303F) - Write Sequencer 63 47906a504a75SDimitris Papastamos */ 47916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS15 0x0100 /* WSEQ_EOS15 */ 47926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS15_MASK 0x0100 /* WSEQ_EOS15 */ 47936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS15_SHIFT 8 /* WSEQ_EOS15 */ 47946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS15_WIDTH 1 /* WSEQ_EOS15 */ 47956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY15_MASK 0x000F /* WSEQ_DELAY15 - [3:0] */ 47966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY15_SHIFT 0 /* WSEQ_DELAY15 - [3:0] */ 47976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY15_WIDTH 4 /* WSEQ_DELAY15 - [3:0] */ 47986a504a75SDimitris Papastamos 47996a504a75SDimitris Papastamos /* 48006a504a75SDimitris Papastamos * R12352 (0x3040) - Write Sequencer 64 48016a504a75SDimitris Papastamos */ 48026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR16_MASK 0x3FFF /* WSEQ_ADDR16 - [13:0] */ 48036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR16_SHIFT 0 /* WSEQ_ADDR16 - [13:0] */ 48046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR16_WIDTH 14 /* WSEQ_ADDR16 - [13:0] */ 48056a504a75SDimitris Papastamos 48066a504a75SDimitris Papastamos /* 48076a504a75SDimitris Papastamos * R12353 (0x3041) - Write Sequencer 65 48086a504a75SDimitris Papastamos */ 48096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA16_MASK 0x00FF /* WSEQ_DATA16 - [7:0] */ 48106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA16_SHIFT 0 /* WSEQ_DATA16 - [7:0] */ 48116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA16_WIDTH 8 /* WSEQ_DATA16 - [7:0] */ 48126a504a75SDimitris Papastamos 48136a504a75SDimitris Papastamos /* 48146a504a75SDimitris Papastamos * R12354 (0x3042) - Write Sequencer 66 48156a504a75SDimitris Papastamos */ 48166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH16_MASK 0x0700 /* WSEQ_DATA_WIDTH16 - [10:8] */ 48176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH16_SHIFT 8 /* WSEQ_DATA_WIDTH16 - [10:8] */ 48186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH16_WIDTH 3 /* WSEQ_DATA_WIDTH16 - [10:8] */ 48196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START16_MASK 0x000F /* WSEQ_DATA_START16 - [3:0] */ 48206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START16_SHIFT 0 /* WSEQ_DATA_START16 - [3:0] */ 48216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START16_WIDTH 4 /* WSEQ_DATA_START16 - [3:0] */ 48226a504a75SDimitris Papastamos 48236a504a75SDimitris Papastamos /* 48246a504a75SDimitris Papastamos * R12355 (0x3043) - Write Sequencer 67 48256a504a75SDimitris Papastamos */ 48266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS16 0x0100 /* WSEQ_EOS16 */ 48276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS16_MASK 0x0100 /* WSEQ_EOS16 */ 48286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS16_SHIFT 8 /* WSEQ_EOS16 */ 48296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS16_WIDTH 1 /* WSEQ_EOS16 */ 48306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY16_MASK 0x000F /* WSEQ_DELAY16 - [3:0] */ 48316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY16_SHIFT 0 /* WSEQ_DELAY16 - [3:0] */ 48326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY16_WIDTH 4 /* WSEQ_DELAY16 - [3:0] */ 48336a504a75SDimitris Papastamos 48346a504a75SDimitris Papastamos /* 48356a504a75SDimitris Papastamos * R12356 (0x3044) - Write Sequencer 68 48366a504a75SDimitris Papastamos */ 48376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR17_MASK 0x3FFF /* WSEQ_ADDR17 - [13:0] */ 48386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR17_SHIFT 0 /* WSEQ_ADDR17 - [13:0] */ 48396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR17_WIDTH 14 /* WSEQ_ADDR17 - [13:0] */ 48406a504a75SDimitris Papastamos 48416a504a75SDimitris Papastamos /* 48426a504a75SDimitris Papastamos * R12357 (0x3045) - Write Sequencer 69 48436a504a75SDimitris Papastamos */ 48446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA17_MASK 0x00FF /* WSEQ_DATA17 - [7:0] */ 48456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA17_SHIFT 0 /* WSEQ_DATA17 - [7:0] */ 48466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA17_WIDTH 8 /* WSEQ_DATA17 - [7:0] */ 48476a504a75SDimitris Papastamos 48486a504a75SDimitris Papastamos /* 48496a504a75SDimitris Papastamos * R12358 (0x3046) - Write Sequencer 70 48506a504a75SDimitris Papastamos */ 48516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH17_MASK 0x0700 /* WSEQ_DATA_WIDTH17 - [10:8] */ 48526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH17_SHIFT 8 /* WSEQ_DATA_WIDTH17 - [10:8] */ 48536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH17_WIDTH 3 /* WSEQ_DATA_WIDTH17 - [10:8] */ 48546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START17_MASK 0x000F /* WSEQ_DATA_START17 - [3:0] */ 48556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START17_SHIFT 0 /* WSEQ_DATA_START17 - [3:0] */ 48566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START17_WIDTH 4 /* WSEQ_DATA_START17 - [3:0] */ 48576a504a75SDimitris Papastamos 48586a504a75SDimitris Papastamos /* 48596a504a75SDimitris Papastamos * R12359 (0x3047) - Write Sequencer 71 48606a504a75SDimitris Papastamos */ 48616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS17 0x0100 /* WSEQ_EOS17 */ 48626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS17_MASK 0x0100 /* WSEQ_EOS17 */ 48636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS17_SHIFT 8 /* WSEQ_EOS17 */ 48646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS17_WIDTH 1 /* WSEQ_EOS17 */ 48656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY17_MASK 0x000F /* WSEQ_DELAY17 - [3:0] */ 48666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY17_SHIFT 0 /* WSEQ_DELAY17 - [3:0] */ 48676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY17_WIDTH 4 /* WSEQ_DELAY17 - [3:0] */ 48686a504a75SDimitris Papastamos 48696a504a75SDimitris Papastamos /* 48706a504a75SDimitris Papastamos * R12360 (0x3048) - Write Sequencer 72 48716a504a75SDimitris Papastamos */ 48726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR18_MASK 0x3FFF /* WSEQ_ADDR18 - [13:0] */ 48736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR18_SHIFT 0 /* WSEQ_ADDR18 - [13:0] */ 48746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR18_WIDTH 14 /* WSEQ_ADDR18 - [13:0] */ 48756a504a75SDimitris Papastamos 48766a504a75SDimitris Papastamos /* 48776a504a75SDimitris Papastamos * R12361 (0x3049) - Write Sequencer 73 48786a504a75SDimitris Papastamos */ 48796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA18_MASK 0x00FF /* WSEQ_DATA18 - [7:0] */ 48806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA18_SHIFT 0 /* WSEQ_DATA18 - [7:0] */ 48816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA18_WIDTH 8 /* WSEQ_DATA18 - [7:0] */ 48826a504a75SDimitris Papastamos 48836a504a75SDimitris Papastamos /* 48846a504a75SDimitris Papastamos * R12362 (0x304A) - Write Sequencer 74 48856a504a75SDimitris Papastamos */ 48866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH18_MASK 0x0700 /* WSEQ_DATA_WIDTH18 - [10:8] */ 48876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH18_SHIFT 8 /* WSEQ_DATA_WIDTH18 - [10:8] */ 48886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH18_WIDTH 3 /* WSEQ_DATA_WIDTH18 - [10:8] */ 48896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START18_MASK 0x000F /* WSEQ_DATA_START18 - [3:0] */ 48906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START18_SHIFT 0 /* WSEQ_DATA_START18 - [3:0] */ 48916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START18_WIDTH 4 /* WSEQ_DATA_START18 - [3:0] */ 48926a504a75SDimitris Papastamos 48936a504a75SDimitris Papastamos /* 48946a504a75SDimitris Papastamos * R12363 (0x304B) - Write Sequencer 75 48956a504a75SDimitris Papastamos */ 48966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS18 0x0100 /* WSEQ_EOS18 */ 48976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS18_MASK 0x0100 /* WSEQ_EOS18 */ 48986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS18_SHIFT 8 /* WSEQ_EOS18 */ 48996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS18_WIDTH 1 /* WSEQ_EOS18 */ 49006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY18_MASK 0x000F /* WSEQ_DELAY18 - [3:0] */ 49016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY18_SHIFT 0 /* WSEQ_DELAY18 - [3:0] */ 49026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY18_WIDTH 4 /* WSEQ_DELAY18 - [3:0] */ 49036a504a75SDimitris Papastamos 49046a504a75SDimitris Papastamos /* 49056a504a75SDimitris Papastamos * R12364 (0x304C) - Write Sequencer 76 49066a504a75SDimitris Papastamos */ 49076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR19_MASK 0x3FFF /* WSEQ_ADDR19 - [13:0] */ 49086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR19_SHIFT 0 /* WSEQ_ADDR19 - [13:0] */ 49096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR19_WIDTH 14 /* WSEQ_ADDR19 - [13:0] */ 49106a504a75SDimitris Papastamos 49116a504a75SDimitris Papastamos /* 49126a504a75SDimitris Papastamos * R12365 (0x304D) - Write Sequencer 77 49136a504a75SDimitris Papastamos */ 49146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA19_MASK 0x00FF /* WSEQ_DATA19 - [7:0] */ 49156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA19_SHIFT 0 /* WSEQ_DATA19 - [7:0] */ 49166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA19_WIDTH 8 /* WSEQ_DATA19 - [7:0] */ 49176a504a75SDimitris Papastamos 49186a504a75SDimitris Papastamos /* 49196a504a75SDimitris Papastamos * R12366 (0x304E) - Write Sequencer 78 49206a504a75SDimitris Papastamos */ 49216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH19_MASK 0x0700 /* WSEQ_DATA_WIDTH19 - [10:8] */ 49226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH19_SHIFT 8 /* WSEQ_DATA_WIDTH19 - [10:8] */ 49236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH19_WIDTH 3 /* WSEQ_DATA_WIDTH19 - [10:8] */ 49246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START19_MASK 0x000F /* WSEQ_DATA_START19 - [3:0] */ 49256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START19_SHIFT 0 /* WSEQ_DATA_START19 - [3:0] */ 49266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START19_WIDTH 4 /* WSEQ_DATA_START19 - [3:0] */ 49276a504a75SDimitris Papastamos 49286a504a75SDimitris Papastamos /* 49296a504a75SDimitris Papastamos * R12367 (0x304F) - Write Sequencer 79 49306a504a75SDimitris Papastamos */ 49316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS19 0x0100 /* WSEQ_EOS19 */ 49326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS19_MASK 0x0100 /* WSEQ_EOS19 */ 49336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS19_SHIFT 8 /* WSEQ_EOS19 */ 49346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS19_WIDTH 1 /* WSEQ_EOS19 */ 49356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY19_MASK 0x000F /* WSEQ_DELAY19 - [3:0] */ 49366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY19_SHIFT 0 /* WSEQ_DELAY19 - [3:0] */ 49376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY19_WIDTH 4 /* WSEQ_DELAY19 - [3:0] */ 49386a504a75SDimitris Papastamos 49396a504a75SDimitris Papastamos /* 49406a504a75SDimitris Papastamos * R12368 (0x3050) - Write Sequencer 80 49416a504a75SDimitris Papastamos */ 49426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR20_MASK 0x3FFF /* WSEQ_ADDR20 - [13:0] */ 49436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR20_SHIFT 0 /* WSEQ_ADDR20 - [13:0] */ 49446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR20_WIDTH 14 /* WSEQ_ADDR20 - [13:0] */ 49456a504a75SDimitris Papastamos 49466a504a75SDimitris Papastamos /* 49476a504a75SDimitris Papastamos * R12369 (0x3051) - Write Sequencer 81 49486a504a75SDimitris Papastamos */ 49496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA20_MASK 0x00FF /* WSEQ_DATA20 - [7:0] */ 49506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA20_SHIFT 0 /* WSEQ_DATA20 - [7:0] */ 49516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA20_WIDTH 8 /* WSEQ_DATA20 - [7:0] */ 49526a504a75SDimitris Papastamos 49536a504a75SDimitris Papastamos /* 49546a504a75SDimitris Papastamos * R12370 (0x3052) - Write Sequencer 82 49556a504a75SDimitris Papastamos */ 49566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH20_MASK 0x0700 /* WSEQ_DATA_WIDTH20 - [10:8] */ 49576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH20_SHIFT 8 /* WSEQ_DATA_WIDTH20 - [10:8] */ 49586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH20_WIDTH 3 /* WSEQ_DATA_WIDTH20 - [10:8] */ 49596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START20_MASK 0x000F /* WSEQ_DATA_START20 - [3:0] */ 49606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START20_SHIFT 0 /* WSEQ_DATA_START20 - [3:0] */ 49616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START20_WIDTH 4 /* WSEQ_DATA_START20 - [3:0] */ 49626a504a75SDimitris Papastamos 49636a504a75SDimitris Papastamos /* 49646a504a75SDimitris Papastamos * R12371 (0x3053) - Write Sequencer 83 49656a504a75SDimitris Papastamos */ 49666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS20 0x0100 /* WSEQ_EOS20 */ 49676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS20_MASK 0x0100 /* WSEQ_EOS20 */ 49686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS20_SHIFT 8 /* WSEQ_EOS20 */ 49696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS20_WIDTH 1 /* WSEQ_EOS20 */ 49706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY20_MASK 0x000F /* WSEQ_DELAY20 - [3:0] */ 49716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY20_SHIFT 0 /* WSEQ_DELAY20 - [3:0] */ 49726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY20_WIDTH 4 /* WSEQ_DELAY20 - [3:0] */ 49736a504a75SDimitris Papastamos 49746a504a75SDimitris Papastamos /* 49756a504a75SDimitris Papastamos * R12372 (0x3054) - Write Sequencer 84 49766a504a75SDimitris Papastamos */ 49776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR21_MASK 0x3FFF /* WSEQ_ADDR21 - [13:0] */ 49786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR21_SHIFT 0 /* WSEQ_ADDR21 - [13:0] */ 49796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR21_WIDTH 14 /* WSEQ_ADDR21 - [13:0] */ 49806a504a75SDimitris Papastamos 49816a504a75SDimitris Papastamos /* 49826a504a75SDimitris Papastamos * R12373 (0x3055) - Write Sequencer 85 49836a504a75SDimitris Papastamos */ 49846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA21_MASK 0x00FF /* WSEQ_DATA21 - [7:0] */ 49856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA21_SHIFT 0 /* WSEQ_DATA21 - [7:0] */ 49866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA21_WIDTH 8 /* WSEQ_DATA21 - [7:0] */ 49876a504a75SDimitris Papastamos 49886a504a75SDimitris Papastamos /* 49896a504a75SDimitris Papastamos * R12374 (0x3056) - Write Sequencer 86 49906a504a75SDimitris Papastamos */ 49916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH21_MASK 0x0700 /* WSEQ_DATA_WIDTH21 - [10:8] */ 49926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH21_SHIFT 8 /* WSEQ_DATA_WIDTH21 - [10:8] */ 49936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH21_WIDTH 3 /* WSEQ_DATA_WIDTH21 - [10:8] */ 49946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START21_MASK 0x000F /* WSEQ_DATA_START21 - [3:0] */ 49956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START21_SHIFT 0 /* WSEQ_DATA_START21 - [3:0] */ 49966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START21_WIDTH 4 /* WSEQ_DATA_START21 - [3:0] */ 49976a504a75SDimitris Papastamos 49986a504a75SDimitris Papastamos /* 49996a504a75SDimitris Papastamos * R12375 (0x3057) - Write Sequencer 87 50006a504a75SDimitris Papastamos */ 50016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS21 0x0100 /* WSEQ_EOS21 */ 50026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS21_MASK 0x0100 /* WSEQ_EOS21 */ 50036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS21_SHIFT 8 /* WSEQ_EOS21 */ 50046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS21_WIDTH 1 /* WSEQ_EOS21 */ 50056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY21_MASK 0x000F /* WSEQ_DELAY21 - [3:0] */ 50066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY21_SHIFT 0 /* WSEQ_DELAY21 - [3:0] */ 50076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY21_WIDTH 4 /* WSEQ_DELAY21 - [3:0] */ 50086a504a75SDimitris Papastamos 50096a504a75SDimitris Papastamos /* 50106a504a75SDimitris Papastamos * R12376 (0x3058) - Write Sequencer 88 50116a504a75SDimitris Papastamos */ 50126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR22_MASK 0x3FFF /* WSEQ_ADDR22 - [13:0] */ 50136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR22_SHIFT 0 /* WSEQ_ADDR22 - [13:0] */ 50146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR22_WIDTH 14 /* WSEQ_ADDR22 - [13:0] */ 50156a504a75SDimitris Papastamos 50166a504a75SDimitris Papastamos /* 50176a504a75SDimitris Papastamos * R12377 (0x3059) - Write Sequencer 89 50186a504a75SDimitris Papastamos */ 50196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA22_MASK 0x00FF /* WSEQ_DATA22 - [7:0] */ 50206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA22_SHIFT 0 /* WSEQ_DATA22 - [7:0] */ 50216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA22_WIDTH 8 /* WSEQ_DATA22 - [7:0] */ 50226a504a75SDimitris Papastamos 50236a504a75SDimitris Papastamos /* 50246a504a75SDimitris Papastamos * R12378 (0x305A) - Write Sequencer 90 50256a504a75SDimitris Papastamos */ 50266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH22_MASK 0x0700 /* WSEQ_DATA_WIDTH22 - [10:8] */ 50276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH22_SHIFT 8 /* WSEQ_DATA_WIDTH22 - [10:8] */ 50286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH22_WIDTH 3 /* WSEQ_DATA_WIDTH22 - [10:8] */ 50296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START22_MASK 0x000F /* WSEQ_DATA_START22 - [3:0] */ 50306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START22_SHIFT 0 /* WSEQ_DATA_START22 - [3:0] */ 50316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START22_WIDTH 4 /* WSEQ_DATA_START22 - [3:0] */ 50326a504a75SDimitris Papastamos 50336a504a75SDimitris Papastamos /* 50346a504a75SDimitris Papastamos * R12379 (0x305B) - Write Sequencer 91 50356a504a75SDimitris Papastamos */ 50366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS22 0x0100 /* WSEQ_EOS22 */ 50376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS22_MASK 0x0100 /* WSEQ_EOS22 */ 50386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS22_SHIFT 8 /* WSEQ_EOS22 */ 50396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS22_WIDTH 1 /* WSEQ_EOS22 */ 50406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY22_MASK 0x000F /* WSEQ_DELAY22 - [3:0] */ 50416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY22_SHIFT 0 /* WSEQ_DELAY22 - [3:0] */ 50426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY22_WIDTH 4 /* WSEQ_DELAY22 - [3:0] */ 50436a504a75SDimitris Papastamos 50446a504a75SDimitris Papastamos /* 50456a504a75SDimitris Papastamos * R12380 (0x305C) - Write Sequencer 92 50466a504a75SDimitris Papastamos */ 50476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR23_MASK 0x3FFF /* WSEQ_ADDR23 - [13:0] */ 50486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR23_SHIFT 0 /* WSEQ_ADDR23 - [13:0] */ 50496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR23_WIDTH 14 /* WSEQ_ADDR23 - [13:0] */ 50506a504a75SDimitris Papastamos 50516a504a75SDimitris Papastamos /* 50526a504a75SDimitris Papastamos * R12381 (0x305D) - Write Sequencer 93 50536a504a75SDimitris Papastamos */ 50546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA23_MASK 0x00FF /* WSEQ_DATA23 - [7:0] */ 50556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA23_SHIFT 0 /* WSEQ_DATA23 - [7:0] */ 50566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA23_WIDTH 8 /* WSEQ_DATA23 - [7:0] */ 50576a504a75SDimitris Papastamos 50586a504a75SDimitris Papastamos /* 50596a504a75SDimitris Papastamos * R12382 (0x305E) - Write Sequencer 94 50606a504a75SDimitris Papastamos */ 50616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH23_MASK 0x0700 /* WSEQ_DATA_WIDTH23 - [10:8] */ 50626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH23_SHIFT 8 /* WSEQ_DATA_WIDTH23 - [10:8] */ 50636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH23_WIDTH 3 /* WSEQ_DATA_WIDTH23 - [10:8] */ 50646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START23_MASK 0x000F /* WSEQ_DATA_START23 - [3:0] */ 50656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START23_SHIFT 0 /* WSEQ_DATA_START23 - [3:0] */ 50666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START23_WIDTH 4 /* WSEQ_DATA_START23 - [3:0] */ 50676a504a75SDimitris Papastamos 50686a504a75SDimitris Papastamos /* 50696a504a75SDimitris Papastamos * R12383 (0x305F) - Write Sequencer 95 50706a504a75SDimitris Papastamos */ 50716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS23 0x0100 /* WSEQ_EOS23 */ 50726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS23_MASK 0x0100 /* WSEQ_EOS23 */ 50736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS23_SHIFT 8 /* WSEQ_EOS23 */ 50746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS23_WIDTH 1 /* WSEQ_EOS23 */ 50756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY23_MASK 0x000F /* WSEQ_DELAY23 - [3:0] */ 50766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY23_SHIFT 0 /* WSEQ_DELAY23 - [3:0] */ 50776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY23_WIDTH 4 /* WSEQ_DELAY23 - [3:0] */ 50786a504a75SDimitris Papastamos 50796a504a75SDimitris Papastamos /* 50806a504a75SDimitris Papastamos * R12384 (0x3060) - Write Sequencer 96 50816a504a75SDimitris Papastamos */ 50826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR24_MASK 0x3FFF /* WSEQ_ADDR24 - [13:0] */ 50836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR24_SHIFT 0 /* WSEQ_ADDR24 - [13:0] */ 50846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR24_WIDTH 14 /* WSEQ_ADDR24 - [13:0] */ 50856a504a75SDimitris Papastamos 50866a504a75SDimitris Papastamos /* 50876a504a75SDimitris Papastamos * R12385 (0x3061) - Write Sequencer 97 50886a504a75SDimitris Papastamos */ 50896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA24_MASK 0x00FF /* WSEQ_DATA24 - [7:0] */ 50906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA24_SHIFT 0 /* WSEQ_DATA24 - [7:0] */ 50916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA24_WIDTH 8 /* WSEQ_DATA24 - [7:0] */ 50926a504a75SDimitris Papastamos 50936a504a75SDimitris Papastamos /* 50946a504a75SDimitris Papastamos * R12386 (0x3062) - Write Sequencer 98 50956a504a75SDimitris Papastamos */ 50966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH24_MASK 0x0700 /* WSEQ_DATA_WIDTH24 - [10:8] */ 50976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH24_SHIFT 8 /* WSEQ_DATA_WIDTH24 - [10:8] */ 50986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH24_WIDTH 3 /* WSEQ_DATA_WIDTH24 - [10:8] */ 50996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START24_MASK 0x000F /* WSEQ_DATA_START24 - [3:0] */ 51006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START24_SHIFT 0 /* WSEQ_DATA_START24 - [3:0] */ 51016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START24_WIDTH 4 /* WSEQ_DATA_START24 - [3:0] */ 51026a504a75SDimitris Papastamos 51036a504a75SDimitris Papastamos /* 51046a504a75SDimitris Papastamos * R12387 (0x3063) - Write Sequencer 99 51056a504a75SDimitris Papastamos */ 51066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS24 0x0100 /* WSEQ_EOS24 */ 51076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS24_MASK 0x0100 /* WSEQ_EOS24 */ 51086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS24_SHIFT 8 /* WSEQ_EOS24 */ 51096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS24_WIDTH 1 /* WSEQ_EOS24 */ 51106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY24_MASK 0x000F /* WSEQ_DELAY24 - [3:0] */ 51116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY24_SHIFT 0 /* WSEQ_DELAY24 - [3:0] */ 51126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY24_WIDTH 4 /* WSEQ_DELAY24 - [3:0] */ 51136a504a75SDimitris Papastamos 51146a504a75SDimitris Papastamos /* 51156a504a75SDimitris Papastamos * R12388 (0x3064) - Write Sequencer 100 51166a504a75SDimitris Papastamos */ 51176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR25_MASK 0x3FFF /* WSEQ_ADDR25 - [13:0] */ 51186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR25_SHIFT 0 /* WSEQ_ADDR25 - [13:0] */ 51196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR25_WIDTH 14 /* WSEQ_ADDR25 - [13:0] */ 51206a504a75SDimitris Papastamos 51216a504a75SDimitris Papastamos /* 51226a504a75SDimitris Papastamos * R12389 (0x3065) - Write Sequencer 101 51236a504a75SDimitris Papastamos */ 51246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA25_MASK 0x00FF /* WSEQ_DATA25 - [7:0] */ 51256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA25_SHIFT 0 /* WSEQ_DATA25 - [7:0] */ 51266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA25_WIDTH 8 /* WSEQ_DATA25 - [7:0] */ 51276a504a75SDimitris Papastamos 51286a504a75SDimitris Papastamos /* 51296a504a75SDimitris Papastamos * R12390 (0x3066) - Write Sequencer 102 51306a504a75SDimitris Papastamos */ 51316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH25_MASK 0x0700 /* WSEQ_DATA_WIDTH25 - [10:8] */ 51326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH25_SHIFT 8 /* WSEQ_DATA_WIDTH25 - [10:8] */ 51336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH25_WIDTH 3 /* WSEQ_DATA_WIDTH25 - [10:8] */ 51346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START25_MASK 0x000F /* WSEQ_DATA_START25 - [3:0] */ 51356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START25_SHIFT 0 /* WSEQ_DATA_START25 - [3:0] */ 51366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START25_WIDTH 4 /* WSEQ_DATA_START25 - [3:0] */ 51376a504a75SDimitris Papastamos 51386a504a75SDimitris Papastamos /* 51396a504a75SDimitris Papastamos * R12391 (0x3067) - Write Sequencer 103 51406a504a75SDimitris Papastamos */ 51416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS25 0x0100 /* WSEQ_EOS25 */ 51426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS25_MASK 0x0100 /* WSEQ_EOS25 */ 51436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS25_SHIFT 8 /* WSEQ_EOS25 */ 51446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS25_WIDTH 1 /* WSEQ_EOS25 */ 51456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY25_MASK 0x000F /* WSEQ_DELAY25 - [3:0] */ 51466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY25_SHIFT 0 /* WSEQ_DELAY25 - [3:0] */ 51476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY25_WIDTH 4 /* WSEQ_DELAY25 - [3:0] */ 51486a504a75SDimitris Papastamos 51496a504a75SDimitris Papastamos /* 51506a504a75SDimitris Papastamos * R12392 (0x3068) - Write Sequencer 104 51516a504a75SDimitris Papastamos */ 51526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR26_MASK 0x3FFF /* WSEQ_ADDR26 - [13:0] */ 51536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR26_SHIFT 0 /* WSEQ_ADDR26 - [13:0] */ 51546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR26_WIDTH 14 /* WSEQ_ADDR26 - [13:0] */ 51556a504a75SDimitris Papastamos 51566a504a75SDimitris Papastamos /* 51576a504a75SDimitris Papastamos * R12393 (0x3069) - Write Sequencer 105 51586a504a75SDimitris Papastamos */ 51596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA26_MASK 0x00FF /* WSEQ_DATA26 - [7:0] */ 51606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA26_SHIFT 0 /* WSEQ_DATA26 - [7:0] */ 51616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA26_WIDTH 8 /* WSEQ_DATA26 - [7:0] */ 51626a504a75SDimitris Papastamos 51636a504a75SDimitris Papastamos /* 51646a504a75SDimitris Papastamos * R12394 (0x306A) - Write Sequencer 106 51656a504a75SDimitris Papastamos */ 51666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH26_MASK 0x0700 /* WSEQ_DATA_WIDTH26 - [10:8] */ 51676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH26_SHIFT 8 /* WSEQ_DATA_WIDTH26 - [10:8] */ 51686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH26_WIDTH 3 /* WSEQ_DATA_WIDTH26 - [10:8] */ 51696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START26_MASK 0x000F /* WSEQ_DATA_START26 - [3:0] */ 51706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START26_SHIFT 0 /* WSEQ_DATA_START26 - [3:0] */ 51716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START26_WIDTH 4 /* WSEQ_DATA_START26 - [3:0] */ 51726a504a75SDimitris Papastamos 51736a504a75SDimitris Papastamos /* 51746a504a75SDimitris Papastamos * R12395 (0x306B) - Write Sequencer 107 51756a504a75SDimitris Papastamos */ 51766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS26 0x0100 /* WSEQ_EOS26 */ 51776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS26_MASK 0x0100 /* WSEQ_EOS26 */ 51786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS26_SHIFT 8 /* WSEQ_EOS26 */ 51796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS26_WIDTH 1 /* WSEQ_EOS26 */ 51806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY26_MASK 0x000F /* WSEQ_DELAY26 - [3:0] */ 51816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY26_SHIFT 0 /* WSEQ_DELAY26 - [3:0] */ 51826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY26_WIDTH 4 /* WSEQ_DELAY26 - [3:0] */ 51836a504a75SDimitris Papastamos 51846a504a75SDimitris Papastamos /* 51856a504a75SDimitris Papastamos * R12396 (0x306C) - Write Sequencer 108 51866a504a75SDimitris Papastamos */ 51876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR27_MASK 0x3FFF /* WSEQ_ADDR27 - [13:0] */ 51886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR27_SHIFT 0 /* WSEQ_ADDR27 - [13:0] */ 51896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR27_WIDTH 14 /* WSEQ_ADDR27 - [13:0] */ 51906a504a75SDimitris Papastamos 51916a504a75SDimitris Papastamos /* 51926a504a75SDimitris Papastamos * R12397 (0x306D) - Write Sequencer 109 51936a504a75SDimitris Papastamos */ 51946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA27_MASK 0x00FF /* WSEQ_DATA27 - [7:0] */ 51956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA27_SHIFT 0 /* WSEQ_DATA27 - [7:0] */ 51966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA27_WIDTH 8 /* WSEQ_DATA27 - [7:0] */ 51976a504a75SDimitris Papastamos 51986a504a75SDimitris Papastamos /* 51996a504a75SDimitris Papastamos * R12398 (0x306E) - Write Sequencer 110 52006a504a75SDimitris Papastamos */ 52016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH27_MASK 0x0700 /* WSEQ_DATA_WIDTH27 - [10:8] */ 52026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH27_SHIFT 8 /* WSEQ_DATA_WIDTH27 - [10:8] */ 52036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH27_WIDTH 3 /* WSEQ_DATA_WIDTH27 - [10:8] */ 52046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START27_MASK 0x000F /* WSEQ_DATA_START27 - [3:0] */ 52056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START27_SHIFT 0 /* WSEQ_DATA_START27 - [3:0] */ 52066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START27_WIDTH 4 /* WSEQ_DATA_START27 - [3:0] */ 52076a504a75SDimitris Papastamos 52086a504a75SDimitris Papastamos /* 52096a504a75SDimitris Papastamos * R12399 (0x306F) - Write Sequencer 111 52106a504a75SDimitris Papastamos */ 52116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS27 0x0100 /* WSEQ_EOS27 */ 52126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS27_MASK 0x0100 /* WSEQ_EOS27 */ 52136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS27_SHIFT 8 /* WSEQ_EOS27 */ 52146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS27_WIDTH 1 /* WSEQ_EOS27 */ 52156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY27_MASK 0x000F /* WSEQ_DELAY27 - [3:0] */ 52166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY27_SHIFT 0 /* WSEQ_DELAY27 - [3:0] */ 52176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY27_WIDTH 4 /* WSEQ_DELAY27 - [3:0] */ 52186a504a75SDimitris Papastamos 52196a504a75SDimitris Papastamos /* 52206a504a75SDimitris Papastamos * R12400 (0x3070) - Write Sequencer 112 52216a504a75SDimitris Papastamos */ 52226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR28_MASK 0x3FFF /* WSEQ_ADDR28 - [13:0] */ 52236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR28_SHIFT 0 /* WSEQ_ADDR28 - [13:0] */ 52246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR28_WIDTH 14 /* WSEQ_ADDR28 - [13:0] */ 52256a504a75SDimitris Papastamos 52266a504a75SDimitris Papastamos /* 52276a504a75SDimitris Papastamos * R12401 (0x3071) - Write Sequencer 113 52286a504a75SDimitris Papastamos */ 52296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA28_MASK 0x00FF /* WSEQ_DATA28 - [7:0] */ 52306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA28_SHIFT 0 /* WSEQ_DATA28 - [7:0] */ 52316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA28_WIDTH 8 /* WSEQ_DATA28 - [7:0] */ 52326a504a75SDimitris Papastamos 52336a504a75SDimitris Papastamos /* 52346a504a75SDimitris Papastamos * R12402 (0x3072) - Write Sequencer 114 52356a504a75SDimitris Papastamos */ 52366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH28_MASK 0x0700 /* WSEQ_DATA_WIDTH28 - [10:8] */ 52376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH28_SHIFT 8 /* WSEQ_DATA_WIDTH28 - [10:8] */ 52386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH28_WIDTH 3 /* WSEQ_DATA_WIDTH28 - [10:8] */ 52396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START28_MASK 0x000F /* WSEQ_DATA_START28 - [3:0] */ 52406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START28_SHIFT 0 /* WSEQ_DATA_START28 - [3:0] */ 52416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START28_WIDTH 4 /* WSEQ_DATA_START28 - [3:0] */ 52426a504a75SDimitris Papastamos 52436a504a75SDimitris Papastamos /* 52446a504a75SDimitris Papastamos * R12403 (0x3073) - Write Sequencer 115 52456a504a75SDimitris Papastamos */ 52466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS28 0x0100 /* WSEQ_EOS28 */ 52476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS28_MASK 0x0100 /* WSEQ_EOS28 */ 52486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS28_SHIFT 8 /* WSEQ_EOS28 */ 52496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS28_WIDTH 1 /* WSEQ_EOS28 */ 52506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY28_MASK 0x000F /* WSEQ_DELAY28 - [3:0] */ 52516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY28_SHIFT 0 /* WSEQ_DELAY28 - [3:0] */ 52526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY28_WIDTH 4 /* WSEQ_DELAY28 - [3:0] */ 52536a504a75SDimitris Papastamos 52546a504a75SDimitris Papastamos /* 52556a504a75SDimitris Papastamos * R12404 (0x3074) - Write Sequencer 116 52566a504a75SDimitris Papastamos */ 52576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR29_MASK 0x3FFF /* WSEQ_ADDR29 - [13:0] */ 52586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR29_SHIFT 0 /* WSEQ_ADDR29 - [13:0] */ 52596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR29_WIDTH 14 /* WSEQ_ADDR29 - [13:0] */ 52606a504a75SDimitris Papastamos 52616a504a75SDimitris Papastamos /* 52626a504a75SDimitris Papastamos * R12405 (0x3075) - Write Sequencer 117 52636a504a75SDimitris Papastamos */ 52646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA29_MASK 0x00FF /* WSEQ_DATA29 - [7:0] */ 52656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA29_SHIFT 0 /* WSEQ_DATA29 - [7:0] */ 52666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA29_WIDTH 8 /* WSEQ_DATA29 - [7:0] */ 52676a504a75SDimitris Papastamos 52686a504a75SDimitris Papastamos /* 52696a504a75SDimitris Papastamos * R12406 (0x3076) - Write Sequencer 118 52706a504a75SDimitris Papastamos */ 52716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH29_MASK 0x0700 /* WSEQ_DATA_WIDTH29 - [10:8] */ 52726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH29_SHIFT 8 /* WSEQ_DATA_WIDTH29 - [10:8] */ 52736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH29_WIDTH 3 /* WSEQ_DATA_WIDTH29 - [10:8] */ 52746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START29_MASK 0x000F /* WSEQ_DATA_START29 - [3:0] */ 52756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START29_SHIFT 0 /* WSEQ_DATA_START29 - [3:0] */ 52766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START29_WIDTH 4 /* WSEQ_DATA_START29 - [3:0] */ 52776a504a75SDimitris Papastamos 52786a504a75SDimitris Papastamos /* 52796a504a75SDimitris Papastamos * R12407 (0x3077) - Write Sequencer 119 52806a504a75SDimitris Papastamos */ 52816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS29 0x0100 /* WSEQ_EOS29 */ 52826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS29_MASK 0x0100 /* WSEQ_EOS29 */ 52836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS29_SHIFT 8 /* WSEQ_EOS29 */ 52846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS29_WIDTH 1 /* WSEQ_EOS29 */ 52856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY29_MASK 0x000F /* WSEQ_DELAY29 - [3:0] */ 52866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY29_SHIFT 0 /* WSEQ_DELAY29 - [3:0] */ 52876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY29_WIDTH 4 /* WSEQ_DELAY29 - [3:0] */ 52886a504a75SDimitris Papastamos 52896a504a75SDimitris Papastamos /* 52906a504a75SDimitris Papastamos * R12408 (0x3078) - Write Sequencer 120 52916a504a75SDimitris Papastamos */ 52926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR30_MASK 0x3FFF /* WSEQ_ADDR30 - [13:0] */ 52936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR30_SHIFT 0 /* WSEQ_ADDR30 - [13:0] */ 52946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR30_WIDTH 14 /* WSEQ_ADDR30 - [13:0] */ 52956a504a75SDimitris Papastamos 52966a504a75SDimitris Papastamos /* 52976a504a75SDimitris Papastamos * R12409 (0x3079) - Write Sequencer 121 52986a504a75SDimitris Papastamos */ 52996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA30_MASK 0x00FF /* WSEQ_DATA30 - [7:0] */ 53006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA30_SHIFT 0 /* WSEQ_DATA30 - [7:0] */ 53016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA30_WIDTH 8 /* WSEQ_DATA30 - [7:0] */ 53026a504a75SDimitris Papastamos 53036a504a75SDimitris Papastamos /* 53046a504a75SDimitris Papastamos * R12410 (0x307A) - Write Sequencer 122 53056a504a75SDimitris Papastamos */ 53066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH30_MASK 0x0700 /* WSEQ_DATA_WIDTH30 - [10:8] */ 53076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH30_SHIFT 8 /* WSEQ_DATA_WIDTH30 - [10:8] */ 53086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH30_WIDTH 3 /* WSEQ_DATA_WIDTH30 - [10:8] */ 53096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START30_MASK 0x000F /* WSEQ_DATA_START30 - [3:0] */ 53106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START30_SHIFT 0 /* WSEQ_DATA_START30 - [3:0] */ 53116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START30_WIDTH 4 /* WSEQ_DATA_START30 - [3:0] */ 53126a504a75SDimitris Papastamos 53136a504a75SDimitris Papastamos /* 53146a504a75SDimitris Papastamos * R12411 (0x307B) - Write Sequencer 123 53156a504a75SDimitris Papastamos */ 53166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS30 0x0100 /* WSEQ_EOS30 */ 53176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS30_MASK 0x0100 /* WSEQ_EOS30 */ 53186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS30_SHIFT 8 /* WSEQ_EOS30 */ 53196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS30_WIDTH 1 /* WSEQ_EOS30 */ 53206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY30_MASK 0x000F /* WSEQ_DELAY30 - [3:0] */ 53216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY30_SHIFT 0 /* WSEQ_DELAY30 - [3:0] */ 53226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY30_WIDTH 4 /* WSEQ_DELAY30 - [3:0] */ 53236a504a75SDimitris Papastamos 53246a504a75SDimitris Papastamos /* 53256a504a75SDimitris Papastamos * R12412 (0x307C) - Write Sequencer 124 53266a504a75SDimitris Papastamos */ 53276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR31_MASK 0x3FFF /* WSEQ_ADDR31 - [13:0] */ 53286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR31_SHIFT 0 /* WSEQ_ADDR31 - [13:0] */ 53296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR31_WIDTH 14 /* WSEQ_ADDR31 - [13:0] */ 53306a504a75SDimitris Papastamos 53316a504a75SDimitris Papastamos /* 53326a504a75SDimitris Papastamos * R12413 (0x307D) - Write Sequencer 125 53336a504a75SDimitris Papastamos */ 53346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA31_MASK 0x00FF /* WSEQ_DATA31 - [7:0] */ 53356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA31_SHIFT 0 /* WSEQ_DATA31 - [7:0] */ 53366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA31_WIDTH 8 /* WSEQ_DATA31 - [7:0] */ 53376a504a75SDimitris Papastamos 53386a504a75SDimitris Papastamos /* 53396a504a75SDimitris Papastamos * R12414 (0x307E) - Write Sequencer 126 53406a504a75SDimitris Papastamos */ 53416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH31_MASK 0x0700 /* WSEQ_DATA_WIDTH31 - [10:8] */ 53426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH31_SHIFT 8 /* WSEQ_DATA_WIDTH31 - [10:8] */ 53436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH31_WIDTH 3 /* WSEQ_DATA_WIDTH31 - [10:8] */ 53446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START31_MASK 0x000F /* WSEQ_DATA_START31 - [3:0] */ 53456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START31_SHIFT 0 /* WSEQ_DATA_START31 - [3:0] */ 53466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START31_WIDTH 4 /* WSEQ_DATA_START31 - [3:0] */ 53476a504a75SDimitris Papastamos 53486a504a75SDimitris Papastamos /* 53496a504a75SDimitris Papastamos * R12415 (0x307F) - Write Sequencer 127 53506a504a75SDimitris Papastamos */ 53516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS31 0x0100 /* WSEQ_EOS31 */ 53526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS31_MASK 0x0100 /* WSEQ_EOS31 */ 53536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS31_SHIFT 8 /* WSEQ_EOS31 */ 53546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS31_WIDTH 1 /* WSEQ_EOS31 */ 53556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY31_MASK 0x000F /* WSEQ_DELAY31 - [3:0] */ 53566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY31_SHIFT 0 /* WSEQ_DELAY31 - [3:0] */ 53576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY31_WIDTH 4 /* WSEQ_DELAY31 - [3:0] */ 53586a504a75SDimitris Papastamos 53596a504a75SDimitris Papastamos /* 53606a504a75SDimitris Papastamos * R12416 (0x3080) - Write Sequencer 128 53616a504a75SDimitris Papastamos */ 53626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR32_MASK 0x3FFF /* WSEQ_ADDR32 - [13:0] */ 53636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR32_SHIFT 0 /* WSEQ_ADDR32 - [13:0] */ 53646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR32_WIDTH 14 /* WSEQ_ADDR32 - [13:0] */ 53656a504a75SDimitris Papastamos 53666a504a75SDimitris Papastamos /* 53676a504a75SDimitris Papastamos * R12417 (0x3081) - Write Sequencer 129 53686a504a75SDimitris Papastamos */ 53696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA32_MASK 0x00FF /* WSEQ_DATA32 - [7:0] */ 53706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA32_SHIFT 0 /* WSEQ_DATA32 - [7:0] */ 53716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA32_WIDTH 8 /* WSEQ_DATA32 - [7:0] */ 53726a504a75SDimitris Papastamos 53736a504a75SDimitris Papastamos /* 53746a504a75SDimitris Papastamos * R12418 (0x3082) - Write Sequencer 130 53756a504a75SDimitris Papastamos */ 53766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH32_MASK 0x0700 /* WSEQ_DATA_WIDTH32 - [10:8] */ 53776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH32_SHIFT 8 /* WSEQ_DATA_WIDTH32 - [10:8] */ 53786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH32_WIDTH 3 /* WSEQ_DATA_WIDTH32 - [10:8] */ 53796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START32_MASK 0x000F /* WSEQ_DATA_START32 - [3:0] */ 53806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START32_SHIFT 0 /* WSEQ_DATA_START32 - [3:0] */ 53816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START32_WIDTH 4 /* WSEQ_DATA_START32 - [3:0] */ 53826a504a75SDimitris Papastamos 53836a504a75SDimitris Papastamos /* 53846a504a75SDimitris Papastamos * R12419 (0x3083) - Write Sequencer 131 53856a504a75SDimitris Papastamos */ 53866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS32 0x0100 /* WSEQ_EOS32 */ 53876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS32_MASK 0x0100 /* WSEQ_EOS32 */ 53886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS32_SHIFT 8 /* WSEQ_EOS32 */ 53896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS32_WIDTH 1 /* WSEQ_EOS32 */ 53906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY32_MASK 0x000F /* WSEQ_DELAY32 - [3:0] */ 53916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY32_SHIFT 0 /* WSEQ_DELAY32 - [3:0] */ 53926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY32_WIDTH 4 /* WSEQ_DELAY32 - [3:0] */ 53936a504a75SDimitris Papastamos 53946a504a75SDimitris Papastamos /* 53956a504a75SDimitris Papastamos * R12420 (0x3084) - Write Sequencer 132 53966a504a75SDimitris Papastamos */ 53976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR33_MASK 0x3FFF /* WSEQ_ADDR33 - [13:0] */ 53986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR33_SHIFT 0 /* WSEQ_ADDR33 - [13:0] */ 53996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR33_WIDTH 14 /* WSEQ_ADDR33 - [13:0] */ 54006a504a75SDimitris Papastamos 54016a504a75SDimitris Papastamos /* 54026a504a75SDimitris Papastamos * R12421 (0x3085) - Write Sequencer 133 54036a504a75SDimitris Papastamos */ 54046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA33_MASK 0x00FF /* WSEQ_DATA33 - [7:0] */ 54056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA33_SHIFT 0 /* WSEQ_DATA33 - [7:0] */ 54066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA33_WIDTH 8 /* WSEQ_DATA33 - [7:0] */ 54076a504a75SDimitris Papastamos 54086a504a75SDimitris Papastamos /* 54096a504a75SDimitris Papastamos * R12422 (0x3086) - Write Sequencer 134 54106a504a75SDimitris Papastamos */ 54116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH33_MASK 0x0700 /* WSEQ_DATA_WIDTH33 - [10:8] */ 54126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH33_SHIFT 8 /* WSEQ_DATA_WIDTH33 - [10:8] */ 54136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH33_WIDTH 3 /* WSEQ_DATA_WIDTH33 - [10:8] */ 54146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START33_MASK 0x000F /* WSEQ_DATA_START33 - [3:0] */ 54156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START33_SHIFT 0 /* WSEQ_DATA_START33 - [3:0] */ 54166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START33_WIDTH 4 /* WSEQ_DATA_START33 - [3:0] */ 54176a504a75SDimitris Papastamos 54186a504a75SDimitris Papastamos /* 54196a504a75SDimitris Papastamos * R12423 (0x3087) - Write Sequencer 135 54206a504a75SDimitris Papastamos */ 54216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS33 0x0100 /* WSEQ_EOS33 */ 54226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS33_MASK 0x0100 /* WSEQ_EOS33 */ 54236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS33_SHIFT 8 /* WSEQ_EOS33 */ 54246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS33_WIDTH 1 /* WSEQ_EOS33 */ 54256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY33_MASK 0x000F /* WSEQ_DELAY33 - [3:0] */ 54266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY33_SHIFT 0 /* WSEQ_DELAY33 - [3:0] */ 54276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY33_WIDTH 4 /* WSEQ_DELAY33 - [3:0] */ 54286a504a75SDimitris Papastamos 54296a504a75SDimitris Papastamos /* 54306a504a75SDimitris Papastamos * R12424 (0x3088) - Write Sequencer 136 54316a504a75SDimitris Papastamos */ 54326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR34_MASK 0x3FFF /* WSEQ_ADDR34 - [13:0] */ 54336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR34_SHIFT 0 /* WSEQ_ADDR34 - [13:0] */ 54346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR34_WIDTH 14 /* WSEQ_ADDR34 - [13:0] */ 54356a504a75SDimitris Papastamos 54366a504a75SDimitris Papastamos /* 54376a504a75SDimitris Papastamos * R12425 (0x3089) - Write Sequencer 137 54386a504a75SDimitris Papastamos */ 54396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA34_MASK 0x00FF /* WSEQ_DATA34 - [7:0] */ 54406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA34_SHIFT 0 /* WSEQ_DATA34 - [7:0] */ 54416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA34_WIDTH 8 /* WSEQ_DATA34 - [7:0] */ 54426a504a75SDimitris Papastamos 54436a504a75SDimitris Papastamos /* 54446a504a75SDimitris Papastamos * R12426 (0x308A) - Write Sequencer 138 54456a504a75SDimitris Papastamos */ 54466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH34_MASK 0x0700 /* WSEQ_DATA_WIDTH34 - [10:8] */ 54476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH34_SHIFT 8 /* WSEQ_DATA_WIDTH34 - [10:8] */ 54486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH34_WIDTH 3 /* WSEQ_DATA_WIDTH34 - [10:8] */ 54496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START34_MASK 0x000F /* WSEQ_DATA_START34 - [3:0] */ 54506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START34_SHIFT 0 /* WSEQ_DATA_START34 - [3:0] */ 54516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START34_WIDTH 4 /* WSEQ_DATA_START34 - [3:0] */ 54526a504a75SDimitris Papastamos 54536a504a75SDimitris Papastamos /* 54546a504a75SDimitris Papastamos * R12427 (0x308B) - Write Sequencer 139 54556a504a75SDimitris Papastamos */ 54566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS34 0x0100 /* WSEQ_EOS34 */ 54576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS34_MASK 0x0100 /* WSEQ_EOS34 */ 54586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS34_SHIFT 8 /* WSEQ_EOS34 */ 54596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS34_WIDTH 1 /* WSEQ_EOS34 */ 54606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY34_MASK 0x000F /* WSEQ_DELAY34 - [3:0] */ 54616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY34_SHIFT 0 /* WSEQ_DELAY34 - [3:0] */ 54626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY34_WIDTH 4 /* WSEQ_DELAY34 - [3:0] */ 54636a504a75SDimitris Papastamos 54646a504a75SDimitris Papastamos /* 54656a504a75SDimitris Papastamos * R12428 (0x308C) - Write Sequencer 140 54666a504a75SDimitris Papastamos */ 54676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR35_MASK 0x3FFF /* WSEQ_ADDR35 - [13:0] */ 54686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR35_SHIFT 0 /* WSEQ_ADDR35 - [13:0] */ 54696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR35_WIDTH 14 /* WSEQ_ADDR35 - [13:0] */ 54706a504a75SDimitris Papastamos 54716a504a75SDimitris Papastamos /* 54726a504a75SDimitris Papastamos * R12429 (0x308D) - Write Sequencer 141 54736a504a75SDimitris Papastamos */ 54746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA35_MASK 0x00FF /* WSEQ_DATA35 - [7:0] */ 54756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA35_SHIFT 0 /* WSEQ_DATA35 - [7:0] */ 54766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA35_WIDTH 8 /* WSEQ_DATA35 - [7:0] */ 54776a504a75SDimitris Papastamos 54786a504a75SDimitris Papastamos /* 54796a504a75SDimitris Papastamos * R12430 (0x308E) - Write Sequencer 142 54806a504a75SDimitris Papastamos */ 54816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH35_MASK 0x0700 /* WSEQ_DATA_WIDTH35 - [10:8] */ 54826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH35_SHIFT 8 /* WSEQ_DATA_WIDTH35 - [10:8] */ 54836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH35_WIDTH 3 /* WSEQ_DATA_WIDTH35 - [10:8] */ 54846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START35_MASK 0x000F /* WSEQ_DATA_START35 - [3:0] */ 54856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START35_SHIFT 0 /* WSEQ_DATA_START35 - [3:0] */ 54866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START35_WIDTH 4 /* WSEQ_DATA_START35 - [3:0] */ 54876a504a75SDimitris Papastamos 54886a504a75SDimitris Papastamos /* 54896a504a75SDimitris Papastamos * R12431 (0x308F) - Write Sequencer 143 54906a504a75SDimitris Papastamos */ 54916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS35 0x0100 /* WSEQ_EOS35 */ 54926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS35_MASK 0x0100 /* WSEQ_EOS35 */ 54936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS35_SHIFT 8 /* WSEQ_EOS35 */ 54946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS35_WIDTH 1 /* WSEQ_EOS35 */ 54956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY35_MASK 0x000F /* WSEQ_DELAY35 - [3:0] */ 54966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY35_SHIFT 0 /* WSEQ_DELAY35 - [3:0] */ 54976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY35_WIDTH 4 /* WSEQ_DELAY35 - [3:0] */ 54986a504a75SDimitris Papastamos 54996a504a75SDimitris Papastamos /* 55006a504a75SDimitris Papastamos * R12432 (0x3090) - Write Sequencer 144 55016a504a75SDimitris Papastamos */ 55026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR36_MASK 0x3FFF /* WSEQ_ADDR36 - [13:0] */ 55036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR36_SHIFT 0 /* WSEQ_ADDR36 - [13:0] */ 55046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR36_WIDTH 14 /* WSEQ_ADDR36 - [13:0] */ 55056a504a75SDimitris Papastamos 55066a504a75SDimitris Papastamos /* 55076a504a75SDimitris Papastamos * R12433 (0x3091) - Write Sequencer 145 55086a504a75SDimitris Papastamos */ 55096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA36_MASK 0x00FF /* WSEQ_DATA36 - [7:0] */ 55106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA36_SHIFT 0 /* WSEQ_DATA36 - [7:0] */ 55116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA36_WIDTH 8 /* WSEQ_DATA36 - [7:0] */ 55126a504a75SDimitris Papastamos 55136a504a75SDimitris Papastamos /* 55146a504a75SDimitris Papastamos * R12434 (0x3092) - Write Sequencer 146 55156a504a75SDimitris Papastamos */ 55166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH36_MASK 0x0700 /* WSEQ_DATA_WIDTH36 - [10:8] */ 55176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH36_SHIFT 8 /* WSEQ_DATA_WIDTH36 - [10:8] */ 55186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH36_WIDTH 3 /* WSEQ_DATA_WIDTH36 - [10:8] */ 55196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START36_MASK 0x000F /* WSEQ_DATA_START36 - [3:0] */ 55206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START36_SHIFT 0 /* WSEQ_DATA_START36 - [3:0] */ 55216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START36_WIDTH 4 /* WSEQ_DATA_START36 - [3:0] */ 55226a504a75SDimitris Papastamos 55236a504a75SDimitris Papastamos /* 55246a504a75SDimitris Papastamos * R12435 (0x3093) - Write Sequencer 147 55256a504a75SDimitris Papastamos */ 55266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS36 0x0100 /* WSEQ_EOS36 */ 55276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS36_MASK 0x0100 /* WSEQ_EOS36 */ 55286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS36_SHIFT 8 /* WSEQ_EOS36 */ 55296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS36_WIDTH 1 /* WSEQ_EOS36 */ 55306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY36_MASK 0x000F /* WSEQ_DELAY36 - [3:0] */ 55316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY36_SHIFT 0 /* WSEQ_DELAY36 - [3:0] */ 55326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY36_WIDTH 4 /* WSEQ_DELAY36 - [3:0] */ 55336a504a75SDimitris Papastamos 55346a504a75SDimitris Papastamos /* 55356a504a75SDimitris Papastamos * R12436 (0x3094) - Write Sequencer 148 55366a504a75SDimitris Papastamos */ 55376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR37_MASK 0x3FFF /* WSEQ_ADDR37 - [13:0] */ 55386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR37_SHIFT 0 /* WSEQ_ADDR37 - [13:0] */ 55396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR37_WIDTH 14 /* WSEQ_ADDR37 - [13:0] */ 55406a504a75SDimitris Papastamos 55416a504a75SDimitris Papastamos /* 55426a504a75SDimitris Papastamos * R12437 (0x3095) - Write Sequencer 149 55436a504a75SDimitris Papastamos */ 55446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA37_MASK 0x00FF /* WSEQ_DATA37 - [7:0] */ 55456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA37_SHIFT 0 /* WSEQ_DATA37 - [7:0] */ 55466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA37_WIDTH 8 /* WSEQ_DATA37 - [7:0] */ 55476a504a75SDimitris Papastamos 55486a504a75SDimitris Papastamos /* 55496a504a75SDimitris Papastamos * R12438 (0x3096) - Write Sequencer 150 55506a504a75SDimitris Papastamos */ 55516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH37_MASK 0x0700 /* WSEQ_DATA_WIDTH37 - [10:8] */ 55526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH37_SHIFT 8 /* WSEQ_DATA_WIDTH37 - [10:8] */ 55536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH37_WIDTH 3 /* WSEQ_DATA_WIDTH37 - [10:8] */ 55546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START37_MASK 0x000F /* WSEQ_DATA_START37 - [3:0] */ 55556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START37_SHIFT 0 /* WSEQ_DATA_START37 - [3:0] */ 55566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START37_WIDTH 4 /* WSEQ_DATA_START37 - [3:0] */ 55576a504a75SDimitris Papastamos 55586a504a75SDimitris Papastamos /* 55596a504a75SDimitris Papastamos * R12439 (0x3097) - Write Sequencer 151 55606a504a75SDimitris Papastamos */ 55616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS37 0x0100 /* WSEQ_EOS37 */ 55626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS37_MASK 0x0100 /* WSEQ_EOS37 */ 55636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS37_SHIFT 8 /* WSEQ_EOS37 */ 55646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS37_WIDTH 1 /* WSEQ_EOS37 */ 55656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY37_MASK 0x000F /* WSEQ_DELAY37 - [3:0] */ 55666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY37_SHIFT 0 /* WSEQ_DELAY37 - [3:0] */ 55676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY37_WIDTH 4 /* WSEQ_DELAY37 - [3:0] */ 55686a504a75SDimitris Papastamos 55696a504a75SDimitris Papastamos /* 55706a504a75SDimitris Papastamos * R12440 (0x3098) - Write Sequencer 152 55716a504a75SDimitris Papastamos */ 55726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR38_MASK 0x3FFF /* WSEQ_ADDR38 - [13:0] */ 55736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR38_SHIFT 0 /* WSEQ_ADDR38 - [13:0] */ 55746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR38_WIDTH 14 /* WSEQ_ADDR38 - [13:0] */ 55756a504a75SDimitris Papastamos 55766a504a75SDimitris Papastamos /* 55776a504a75SDimitris Papastamos * R12441 (0x3099) - Write Sequencer 153 55786a504a75SDimitris Papastamos */ 55796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA38_MASK 0x00FF /* WSEQ_DATA38 - [7:0] */ 55806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA38_SHIFT 0 /* WSEQ_DATA38 - [7:0] */ 55816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA38_WIDTH 8 /* WSEQ_DATA38 - [7:0] */ 55826a504a75SDimitris Papastamos 55836a504a75SDimitris Papastamos /* 55846a504a75SDimitris Papastamos * R12442 (0x309A) - Write Sequencer 154 55856a504a75SDimitris Papastamos */ 55866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH38_MASK 0x0700 /* WSEQ_DATA_WIDTH38 - [10:8] */ 55876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH38_SHIFT 8 /* WSEQ_DATA_WIDTH38 - [10:8] */ 55886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH38_WIDTH 3 /* WSEQ_DATA_WIDTH38 - [10:8] */ 55896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START38_MASK 0x000F /* WSEQ_DATA_START38 - [3:0] */ 55906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START38_SHIFT 0 /* WSEQ_DATA_START38 - [3:0] */ 55916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START38_WIDTH 4 /* WSEQ_DATA_START38 - [3:0] */ 55926a504a75SDimitris Papastamos 55936a504a75SDimitris Papastamos /* 55946a504a75SDimitris Papastamos * R12443 (0x309B) - Write Sequencer 155 55956a504a75SDimitris Papastamos */ 55966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS38 0x0100 /* WSEQ_EOS38 */ 55976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS38_MASK 0x0100 /* WSEQ_EOS38 */ 55986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS38_SHIFT 8 /* WSEQ_EOS38 */ 55996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS38_WIDTH 1 /* WSEQ_EOS38 */ 56006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY38_MASK 0x000F /* WSEQ_DELAY38 - [3:0] */ 56016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY38_SHIFT 0 /* WSEQ_DELAY38 - [3:0] */ 56026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY38_WIDTH 4 /* WSEQ_DELAY38 - [3:0] */ 56036a504a75SDimitris Papastamos 56046a504a75SDimitris Papastamos /* 56056a504a75SDimitris Papastamos * R12444 (0x309C) - Write Sequencer 156 56066a504a75SDimitris Papastamos */ 56076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR39_MASK 0x3FFF /* WSEQ_ADDR39 - [13:0] */ 56086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR39_SHIFT 0 /* WSEQ_ADDR39 - [13:0] */ 56096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR39_WIDTH 14 /* WSEQ_ADDR39 - [13:0] */ 56106a504a75SDimitris Papastamos 56116a504a75SDimitris Papastamos /* 56126a504a75SDimitris Papastamos * R12445 (0x309D) - Write Sequencer 157 56136a504a75SDimitris Papastamos */ 56146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA39_MASK 0x00FF /* WSEQ_DATA39 - [7:0] */ 56156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA39_SHIFT 0 /* WSEQ_DATA39 - [7:0] */ 56166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA39_WIDTH 8 /* WSEQ_DATA39 - [7:0] */ 56176a504a75SDimitris Papastamos 56186a504a75SDimitris Papastamos /* 56196a504a75SDimitris Papastamos * R12446 (0x309E) - Write Sequencer 158 56206a504a75SDimitris Papastamos */ 56216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH39_MASK 0x0700 /* WSEQ_DATA_WIDTH39 - [10:8] */ 56226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH39_SHIFT 8 /* WSEQ_DATA_WIDTH39 - [10:8] */ 56236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH39_WIDTH 3 /* WSEQ_DATA_WIDTH39 - [10:8] */ 56246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START39_MASK 0x000F /* WSEQ_DATA_START39 - [3:0] */ 56256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START39_SHIFT 0 /* WSEQ_DATA_START39 - [3:0] */ 56266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START39_WIDTH 4 /* WSEQ_DATA_START39 - [3:0] */ 56276a504a75SDimitris Papastamos 56286a504a75SDimitris Papastamos /* 56296a504a75SDimitris Papastamos * R12447 (0x309F) - Write Sequencer 159 56306a504a75SDimitris Papastamos */ 56316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS39 0x0100 /* WSEQ_EOS39 */ 56326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS39_MASK 0x0100 /* WSEQ_EOS39 */ 56336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS39_SHIFT 8 /* WSEQ_EOS39 */ 56346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS39_WIDTH 1 /* WSEQ_EOS39 */ 56356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY39_MASK 0x000F /* WSEQ_DELAY39 - [3:0] */ 56366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY39_SHIFT 0 /* WSEQ_DELAY39 - [3:0] */ 56376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY39_WIDTH 4 /* WSEQ_DELAY39 - [3:0] */ 56386a504a75SDimitris Papastamos 56396a504a75SDimitris Papastamos /* 56406a504a75SDimitris Papastamos * R12448 (0x30A0) - Write Sequencer 160 56416a504a75SDimitris Papastamos */ 56426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR40_MASK 0x3FFF /* WSEQ_ADDR40 - [13:0] */ 56436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR40_SHIFT 0 /* WSEQ_ADDR40 - [13:0] */ 56446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR40_WIDTH 14 /* WSEQ_ADDR40 - [13:0] */ 56456a504a75SDimitris Papastamos 56466a504a75SDimitris Papastamos /* 56476a504a75SDimitris Papastamos * R12449 (0x30A1) - Write Sequencer 161 56486a504a75SDimitris Papastamos */ 56496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA40_MASK 0x00FF /* WSEQ_DATA40 - [7:0] */ 56506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA40_SHIFT 0 /* WSEQ_DATA40 - [7:0] */ 56516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA40_WIDTH 8 /* WSEQ_DATA40 - [7:0] */ 56526a504a75SDimitris Papastamos 56536a504a75SDimitris Papastamos /* 56546a504a75SDimitris Papastamos * R12450 (0x30A2) - Write Sequencer 162 56556a504a75SDimitris Papastamos */ 56566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH40_MASK 0x0700 /* WSEQ_DATA_WIDTH40 - [10:8] */ 56576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH40_SHIFT 8 /* WSEQ_DATA_WIDTH40 - [10:8] */ 56586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH40_WIDTH 3 /* WSEQ_DATA_WIDTH40 - [10:8] */ 56596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START40_MASK 0x000F /* WSEQ_DATA_START40 - [3:0] */ 56606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START40_SHIFT 0 /* WSEQ_DATA_START40 - [3:0] */ 56616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START40_WIDTH 4 /* WSEQ_DATA_START40 - [3:0] */ 56626a504a75SDimitris Papastamos 56636a504a75SDimitris Papastamos /* 56646a504a75SDimitris Papastamos * R12451 (0x30A3) - Write Sequencer 163 56656a504a75SDimitris Papastamos */ 56666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS40 0x0100 /* WSEQ_EOS40 */ 56676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS40_MASK 0x0100 /* WSEQ_EOS40 */ 56686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS40_SHIFT 8 /* WSEQ_EOS40 */ 56696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS40_WIDTH 1 /* WSEQ_EOS40 */ 56706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY40_MASK 0x000F /* WSEQ_DELAY40 - [3:0] */ 56716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY40_SHIFT 0 /* WSEQ_DELAY40 - [3:0] */ 56726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY40_WIDTH 4 /* WSEQ_DELAY40 - [3:0] */ 56736a504a75SDimitris Papastamos 56746a504a75SDimitris Papastamos /* 56756a504a75SDimitris Papastamos * R12452 (0x30A4) - Write Sequencer 164 56766a504a75SDimitris Papastamos */ 56776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR41_MASK 0x3FFF /* WSEQ_ADDR41 - [13:0] */ 56786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR41_SHIFT 0 /* WSEQ_ADDR41 - [13:0] */ 56796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR41_WIDTH 14 /* WSEQ_ADDR41 - [13:0] */ 56806a504a75SDimitris Papastamos 56816a504a75SDimitris Papastamos /* 56826a504a75SDimitris Papastamos * R12453 (0x30A5) - Write Sequencer 165 56836a504a75SDimitris Papastamos */ 56846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA41_MASK 0x00FF /* WSEQ_DATA41 - [7:0] */ 56856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA41_SHIFT 0 /* WSEQ_DATA41 - [7:0] */ 56866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA41_WIDTH 8 /* WSEQ_DATA41 - [7:0] */ 56876a504a75SDimitris Papastamos 56886a504a75SDimitris Papastamos /* 56896a504a75SDimitris Papastamos * R12454 (0x30A6) - Write Sequencer 166 56906a504a75SDimitris Papastamos */ 56916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH41_MASK 0x0700 /* WSEQ_DATA_WIDTH41 - [10:8] */ 56926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH41_SHIFT 8 /* WSEQ_DATA_WIDTH41 - [10:8] */ 56936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH41_WIDTH 3 /* WSEQ_DATA_WIDTH41 - [10:8] */ 56946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START41_MASK 0x000F /* WSEQ_DATA_START41 - [3:0] */ 56956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START41_SHIFT 0 /* WSEQ_DATA_START41 - [3:0] */ 56966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START41_WIDTH 4 /* WSEQ_DATA_START41 - [3:0] */ 56976a504a75SDimitris Papastamos 56986a504a75SDimitris Papastamos /* 56996a504a75SDimitris Papastamos * R12455 (0x30A7) - Write Sequencer 167 57006a504a75SDimitris Papastamos */ 57016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS41 0x0100 /* WSEQ_EOS41 */ 57026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS41_MASK 0x0100 /* WSEQ_EOS41 */ 57036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS41_SHIFT 8 /* WSEQ_EOS41 */ 57046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS41_WIDTH 1 /* WSEQ_EOS41 */ 57056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY41_MASK 0x000F /* WSEQ_DELAY41 - [3:0] */ 57066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY41_SHIFT 0 /* WSEQ_DELAY41 - [3:0] */ 57076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY41_WIDTH 4 /* WSEQ_DELAY41 - [3:0] */ 57086a504a75SDimitris Papastamos 57096a504a75SDimitris Papastamos /* 57106a504a75SDimitris Papastamos * R12456 (0x30A8) - Write Sequencer 168 57116a504a75SDimitris Papastamos */ 57126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR42_MASK 0x3FFF /* WSEQ_ADDR42 - [13:0] */ 57136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR42_SHIFT 0 /* WSEQ_ADDR42 - [13:0] */ 57146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR42_WIDTH 14 /* WSEQ_ADDR42 - [13:0] */ 57156a504a75SDimitris Papastamos 57166a504a75SDimitris Papastamos /* 57176a504a75SDimitris Papastamos * R12457 (0x30A9) - Write Sequencer 169 57186a504a75SDimitris Papastamos */ 57196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA42_MASK 0x00FF /* WSEQ_DATA42 - [7:0] */ 57206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA42_SHIFT 0 /* WSEQ_DATA42 - [7:0] */ 57216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA42_WIDTH 8 /* WSEQ_DATA42 - [7:0] */ 57226a504a75SDimitris Papastamos 57236a504a75SDimitris Papastamos /* 57246a504a75SDimitris Papastamos * R12458 (0x30AA) - Write Sequencer 170 57256a504a75SDimitris Papastamos */ 57266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH42_MASK 0x0700 /* WSEQ_DATA_WIDTH42 - [10:8] */ 57276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH42_SHIFT 8 /* WSEQ_DATA_WIDTH42 - [10:8] */ 57286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH42_WIDTH 3 /* WSEQ_DATA_WIDTH42 - [10:8] */ 57296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START42_MASK 0x000F /* WSEQ_DATA_START42 - [3:0] */ 57306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START42_SHIFT 0 /* WSEQ_DATA_START42 - [3:0] */ 57316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START42_WIDTH 4 /* WSEQ_DATA_START42 - [3:0] */ 57326a504a75SDimitris Papastamos 57336a504a75SDimitris Papastamos /* 57346a504a75SDimitris Papastamos * R12459 (0x30AB) - Write Sequencer 171 57356a504a75SDimitris Papastamos */ 57366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS42 0x0100 /* WSEQ_EOS42 */ 57376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS42_MASK 0x0100 /* WSEQ_EOS42 */ 57386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS42_SHIFT 8 /* WSEQ_EOS42 */ 57396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS42_WIDTH 1 /* WSEQ_EOS42 */ 57406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY42_MASK 0x000F /* WSEQ_DELAY42 - [3:0] */ 57416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY42_SHIFT 0 /* WSEQ_DELAY42 - [3:0] */ 57426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY42_WIDTH 4 /* WSEQ_DELAY42 - [3:0] */ 57436a504a75SDimitris Papastamos 57446a504a75SDimitris Papastamos /* 57456a504a75SDimitris Papastamos * R12460 (0x30AC) - Write Sequencer 172 57466a504a75SDimitris Papastamos */ 57476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR43_MASK 0x3FFF /* WSEQ_ADDR43 - [13:0] */ 57486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR43_SHIFT 0 /* WSEQ_ADDR43 - [13:0] */ 57496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR43_WIDTH 14 /* WSEQ_ADDR43 - [13:0] */ 57506a504a75SDimitris Papastamos 57516a504a75SDimitris Papastamos /* 57526a504a75SDimitris Papastamos * R12461 (0x30AD) - Write Sequencer 173 57536a504a75SDimitris Papastamos */ 57546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA43_MASK 0x00FF /* WSEQ_DATA43 - [7:0] */ 57556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA43_SHIFT 0 /* WSEQ_DATA43 - [7:0] */ 57566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA43_WIDTH 8 /* WSEQ_DATA43 - [7:0] */ 57576a504a75SDimitris Papastamos 57586a504a75SDimitris Papastamos /* 57596a504a75SDimitris Papastamos * R12462 (0x30AE) - Write Sequencer 174 57606a504a75SDimitris Papastamos */ 57616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH43_MASK 0x0700 /* WSEQ_DATA_WIDTH43 - [10:8] */ 57626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH43_SHIFT 8 /* WSEQ_DATA_WIDTH43 - [10:8] */ 57636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH43_WIDTH 3 /* WSEQ_DATA_WIDTH43 - [10:8] */ 57646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START43_MASK 0x000F /* WSEQ_DATA_START43 - [3:0] */ 57656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START43_SHIFT 0 /* WSEQ_DATA_START43 - [3:0] */ 57666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START43_WIDTH 4 /* WSEQ_DATA_START43 - [3:0] */ 57676a504a75SDimitris Papastamos 57686a504a75SDimitris Papastamos /* 57696a504a75SDimitris Papastamos * R12463 (0x30AF) - Write Sequencer 175 57706a504a75SDimitris Papastamos */ 57716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS43 0x0100 /* WSEQ_EOS43 */ 57726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS43_MASK 0x0100 /* WSEQ_EOS43 */ 57736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS43_SHIFT 8 /* WSEQ_EOS43 */ 57746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS43_WIDTH 1 /* WSEQ_EOS43 */ 57756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY43_MASK 0x000F /* WSEQ_DELAY43 - [3:0] */ 57766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY43_SHIFT 0 /* WSEQ_DELAY43 - [3:0] */ 57776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY43_WIDTH 4 /* WSEQ_DELAY43 - [3:0] */ 57786a504a75SDimitris Papastamos 57796a504a75SDimitris Papastamos /* 57806a504a75SDimitris Papastamos * R12464 (0x30B0) - Write Sequencer 176 57816a504a75SDimitris Papastamos */ 57826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR44_MASK 0x3FFF /* WSEQ_ADDR44 - [13:0] */ 57836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR44_SHIFT 0 /* WSEQ_ADDR44 - [13:0] */ 57846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR44_WIDTH 14 /* WSEQ_ADDR44 - [13:0] */ 57856a504a75SDimitris Papastamos 57866a504a75SDimitris Papastamos /* 57876a504a75SDimitris Papastamos * R12465 (0x30B1) - Write Sequencer 177 57886a504a75SDimitris Papastamos */ 57896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA44_MASK 0x00FF /* WSEQ_DATA44 - [7:0] */ 57906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA44_SHIFT 0 /* WSEQ_DATA44 - [7:0] */ 57916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA44_WIDTH 8 /* WSEQ_DATA44 - [7:0] */ 57926a504a75SDimitris Papastamos 57936a504a75SDimitris Papastamos /* 57946a504a75SDimitris Papastamos * R12466 (0x30B2) - Write Sequencer 178 57956a504a75SDimitris Papastamos */ 57966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH44_MASK 0x0700 /* WSEQ_DATA_WIDTH44 - [10:8] */ 57976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH44_SHIFT 8 /* WSEQ_DATA_WIDTH44 - [10:8] */ 57986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH44_WIDTH 3 /* WSEQ_DATA_WIDTH44 - [10:8] */ 57996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START44_MASK 0x000F /* WSEQ_DATA_START44 - [3:0] */ 58006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START44_SHIFT 0 /* WSEQ_DATA_START44 - [3:0] */ 58016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START44_WIDTH 4 /* WSEQ_DATA_START44 - [3:0] */ 58026a504a75SDimitris Papastamos 58036a504a75SDimitris Papastamos /* 58046a504a75SDimitris Papastamos * R12467 (0x30B3) - Write Sequencer 179 58056a504a75SDimitris Papastamos */ 58066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS44 0x0100 /* WSEQ_EOS44 */ 58076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS44_MASK 0x0100 /* WSEQ_EOS44 */ 58086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS44_SHIFT 8 /* WSEQ_EOS44 */ 58096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS44_WIDTH 1 /* WSEQ_EOS44 */ 58106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY44_MASK 0x000F /* WSEQ_DELAY44 - [3:0] */ 58116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY44_SHIFT 0 /* WSEQ_DELAY44 - [3:0] */ 58126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY44_WIDTH 4 /* WSEQ_DELAY44 - [3:0] */ 58136a504a75SDimitris Papastamos 58146a504a75SDimitris Papastamos /* 58156a504a75SDimitris Papastamos * R12468 (0x30B4) - Write Sequencer 180 58166a504a75SDimitris Papastamos */ 58176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR45_MASK 0x3FFF /* WSEQ_ADDR45 - [13:0] */ 58186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR45_SHIFT 0 /* WSEQ_ADDR45 - [13:0] */ 58196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR45_WIDTH 14 /* WSEQ_ADDR45 - [13:0] */ 58206a504a75SDimitris Papastamos 58216a504a75SDimitris Papastamos /* 58226a504a75SDimitris Papastamos * R12469 (0x30B5) - Write Sequencer 181 58236a504a75SDimitris Papastamos */ 58246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA45_MASK 0x00FF /* WSEQ_DATA45 - [7:0] */ 58256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA45_SHIFT 0 /* WSEQ_DATA45 - [7:0] */ 58266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA45_WIDTH 8 /* WSEQ_DATA45 - [7:0] */ 58276a504a75SDimitris Papastamos 58286a504a75SDimitris Papastamos /* 58296a504a75SDimitris Papastamos * R12470 (0x30B6) - Write Sequencer 182 58306a504a75SDimitris Papastamos */ 58316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH45_MASK 0x0700 /* WSEQ_DATA_WIDTH45 - [10:8] */ 58326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH45_SHIFT 8 /* WSEQ_DATA_WIDTH45 - [10:8] */ 58336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH45_WIDTH 3 /* WSEQ_DATA_WIDTH45 - [10:8] */ 58346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START45_MASK 0x000F /* WSEQ_DATA_START45 - [3:0] */ 58356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START45_SHIFT 0 /* WSEQ_DATA_START45 - [3:0] */ 58366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START45_WIDTH 4 /* WSEQ_DATA_START45 - [3:0] */ 58376a504a75SDimitris Papastamos 58386a504a75SDimitris Papastamos /* 58396a504a75SDimitris Papastamos * R12471 (0x30B7) - Write Sequencer 183 58406a504a75SDimitris Papastamos */ 58416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS45 0x0100 /* WSEQ_EOS45 */ 58426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS45_MASK 0x0100 /* WSEQ_EOS45 */ 58436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS45_SHIFT 8 /* WSEQ_EOS45 */ 58446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS45_WIDTH 1 /* WSEQ_EOS45 */ 58456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY45_MASK 0x000F /* WSEQ_DELAY45 - [3:0] */ 58466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY45_SHIFT 0 /* WSEQ_DELAY45 - [3:0] */ 58476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY45_WIDTH 4 /* WSEQ_DELAY45 - [3:0] */ 58486a504a75SDimitris Papastamos 58496a504a75SDimitris Papastamos /* 58506a504a75SDimitris Papastamos * R12472 (0x30B8) - Write Sequencer 184 58516a504a75SDimitris Papastamos */ 58526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR46_MASK 0x3FFF /* WSEQ_ADDR46 - [13:0] */ 58536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR46_SHIFT 0 /* WSEQ_ADDR46 - [13:0] */ 58546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR46_WIDTH 14 /* WSEQ_ADDR46 - [13:0] */ 58556a504a75SDimitris Papastamos 58566a504a75SDimitris Papastamos /* 58576a504a75SDimitris Papastamos * R12473 (0x30B9) - Write Sequencer 185 58586a504a75SDimitris Papastamos */ 58596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA46_MASK 0x00FF /* WSEQ_DATA46 - [7:0] */ 58606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA46_SHIFT 0 /* WSEQ_DATA46 - [7:0] */ 58616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA46_WIDTH 8 /* WSEQ_DATA46 - [7:0] */ 58626a504a75SDimitris Papastamos 58636a504a75SDimitris Papastamos /* 58646a504a75SDimitris Papastamos * R12474 (0x30BA) - Write Sequencer 186 58656a504a75SDimitris Papastamos */ 58666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH46_MASK 0x0700 /* WSEQ_DATA_WIDTH46 - [10:8] */ 58676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH46_SHIFT 8 /* WSEQ_DATA_WIDTH46 - [10:8] */ 58686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH46_WIDTH 3 /* WSEQ_DATA_WIDTH46 - [10:8] */ 58696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START46_MASK 0x000F /* WSEQ_DATA_START46 - [3:0] */ 58706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START46_SHIFT 0 /* WSEQ_DATA_START46 - [3:0] */ 58716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START46_WIDTH 4 /* WSEQ_DATA_START46 - [3:0] */ 58726a504a75SDimitris Papastamos 58736a504a75SDimitris Papastamos /* 58746a504a75SDimitris Papastamos * R12475 (0x30BB) - Write Sequencer 187 58756a504a75SDimitris Papastamos */ 58766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS46 0x0100 /* WSEQ_EOS46 */ 58776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS46_MASK 0x0100 /* WSEQ_EOS46 */ 58786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS46_SHIFT 8 /* WSEQ_EOS46 */ 58796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS46_WIDTH 1 /* WSEQ_EOS46 */ 58806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY46_MASK 0x000F /* WSEQ_DELAY46 - [3:0] */ 58816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY46_SHIFT 0 /* WSEQ_DELAY46 - [3:0] */ 58826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY46_WIDTH 4 /* WSEQ_DELAY46 - [3:0] */ 58836a504a75SDimitris Papastamos 58846a504a75SDimitris Papastamos /* 58856a504a75SDimitris Papastamos * R12476 (0x30BC) - Write Sequencer 188 58866a504a75SDimitris Papastamos */ 58876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR47_MASK 0x3FFF /* WSEQ_ADDR47 - [13:0] */ 58886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR47_SHIFT 0 /* WSEQ_ADDR47 - [13:0] */ 58896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR47_WIDTH 14 /* WSEQ_ADDR47 - [13:0] */ 58906a504a75SDimitris Papastamos 58916a504a75SDimitris Papastamos /* 58926a504a75SDimitris Papastamos * R12477 (0x30BD) - Write Sequencer 189 58936a504a75SDimitris Papastamos */ 58946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA47_MASK 0x00FF /* WSEQ_DATA47 - [7:0] */ 58956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA47_SHIFT 0 /* WSEQ_DATA47 - [7:0] */ 58966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA47_WIDTH 8 /* WSEQ_DATA47 - [7:0] */ 58976a504a75SDimitris Papastamos 58986a504a75SDimitris Papastamos /* 58996a504a75SDimitris Papastamos * R12478 (0x30BE) - Write Sequencer 190 59006a504a75SDimitris Papastamos */ 59016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH47_MASK 0x0700 /* WSEQ_DATA_WIDTH47 - [10:8] */ 59026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH47_SHIFT 8 /* WSEQ_DATA_WIDTH47 - [10:8] */ 59036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH47_WIDTH 3 /* WSEQ_DATA_WIDTH47 - [10:8] */ 59046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START47_MASK 0x000F /* WSEQ_DATA_START47 - [3:0] */ 59056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START47_SHIFT 0 /* WSEQ_DATA_START47 - [3:0] */ 59066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START47_WIDTH 4 /* WSEQ_DATA_START47 - [3:0] */ 59076a504a75SDimitris Papastamos 59086a504a75SDimitris Papastamos /* 59096a504a75SDimitris Papastamos * R12479 (0x30BF) - Write Sequencer 191 59106a504a75SDimitris Papastamos */ 59116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS47 0x0100 /* WSEQ_EOS47 */ 59126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS47_MASK 0x0100 /* WSEQ_EOS47 */ 59136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS47_SHIFT 8 /* WSEQ_EOS47 */ 59146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS47_WIDTH 1 /* WSEQ_EOS47 */ 59156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY47_MASK 0x000F /* WSEQ_DELAY47 - [3:0] */ 59166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY47_SHIFT 0 /* WSEQ_DELAY47 - [3:0] */ 59176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY47_WIDTH 4 /* WSEQ_DELAY47 - [3:0] */ 59186a504a75SDimitris Papastamos 59196a504a75SDimitris Papastamos /* 59206a504a75SDimitris Papastamos * R12480 (0x30C0) - Write Sequencer 192 59216a504a75SDimitris Papastamos */ 59226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR48_MASK 0x3FFF /* WSEQ_ADDR48 - [13:0] */ 59236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR48_SHIFT 0 /* WSEQ_ADDR48 - [13:0] */ 59246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR48_WIDTH 14 /* WSEQ_ADDR48 - [13:0] */ 59256a504a75SDimitris Papastamos 59266a504a75SDimitris Papastamos /* 59276a504a75SDimitris Papastamos * R12481 (0x30C1) - Write Sequencer 193 59286a504a75SDimitris Papastamos */ 59296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA48_MASK 0x00FF /* WSEQ_DATA48 - [7:0] */ 59306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA48_SHIFT 0 /* WSEQ_DATA48 - [7:0] */ 59316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA48_WIDTH 8 /* WSEQ_DATA48 - [7:0] */ 59326a504a75SDimitris Papastamos 59336a504a75SDimitris Papastamos /* 59346a504a75SDimitris Papastamos * R12482 (0x30C2) - Write Sequencer 194 59356a504a75SDimitris Papastamos */ 59366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH48_MASK 0x0700 /* WSEQ_DATA_WIDTH48 - [10:8] */ 59376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH48_SHIFT 8 /* WSEQ_DATA_WIDTH48 - [10:8] */ 59386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH48_WIDTH 3 /* WSEQ_DATA_WIDTH48 - [10:8] */ 59396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START48_MASK 0x000F /* WSEQ_DATA_START48 - [3:0] */ 59406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START48_SHIFT 0 /* WSEQ_DATA_START48 - [3:0] */ 59416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START48_WIDTH 4 /* WSEQ_DATA_START48 - [3:0] */ 59426a504a75SDimitris Papastamos 59436a504a75SDimitris Papastamos /* 59446a504a75SDimitris Papastamos * R12483 (0x30C3) - Write Sequencer 195 59456a504a75SDimitris Papastamos */ 59466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS48 0x0100 /* WSEQ_EOS48 */ 59476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS48_MASK 0x0100 /* WSEQ_EOS48 */ 59486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS48_SHIFT 8 /* WSEQ_EOS48 */ 59496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS48_WIDTH 1 /* WSEQ_EOS48 */ 59506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY48_MASK 0x000F /* WSEQ_DELAY48 - [3:0] */ 59516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY48_SHIFT 0 /* WSEQ_DELAY48 - [3:0] */ 59526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY48_WIDTH 4 /* WSEQ_DELAY48 - [3:0] */ 59536a504a75SDimitris Papastamos 59546a504a75SDimitris Papastamos /* 59556a504a75SDimitris Papastamos * R12484 (0x30C4) - Write Sequencer 196 59566a504a75SDimitris Papastamos */ 59576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR49_MASK 0x3FFF /* WSEQ_ADDR49 - [13:0] */ 59586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR49_SHIFT 0 /* WSEQ_ADDR49 - [13:0] */ 59596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR49_WIDTH 14 /* WSEQ_ADDR49 - [13:0] */ 59606a504a75SDimitris Papastamos 59616a504a75SDimitris Papastamos /* 59626a504a75SDimitris Papastamos * R12485 (0x30C5) - Write Sequencer 197 59636a504a75SDimitris Papastamos */ 59646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA49_MASK 0x00FF /* WSEQ_DATA49 - [7:0] */ 59656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA49_SHIFT 0 /* WSEQ_DATA49 - [7:0] */ 59666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA49_WIDTH 8 /* WSEQ_DATA49 - [7:0] */ 59676a504a75SDimitris Papastamos 59686a504a75SDimitris Papastamos /* 59696a504a75SDimitris Papastamos * R12486 (0x30C6) - Write Sequencer 198 59706a504a75SDimitris Papastamos */ 59716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH49_MASK 0x0700 /* WSEQ_DATA_WIDTH49 - [10:8] */ 59726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH49_SHIFT 8 /* WSEQ_DATA_WIDTH49 - [10:8] */ 59736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH49_WIDTH 3 /* WSEQ_DATA_WIDTH49 - [10:8] */ 59746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START49_MASK 0x000F /* WSEQ_DATA_START49 - [3:0] */ 59756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START49_SHIFT 0 /* WSEQ_DATA_START49 - [3:0] */ 59766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START49_WIDTH 4 /* WSEQ_DATA_START49 - [3:0] */ 59776a504a75SDimitris Papastamos 59786a504a75SDimitris Papastamos /* 59796a504a75SDimitris Papastamos * R12487 (0x30C7) - Write Sequencer 199 59806a504a75SDimitris Papastamos */ 59816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS49 0x0100 /* WSEQ_EOS49 */ 59826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS49_MASK 0x0100 /* WSEQ_EOS49 */ 59836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS49_SHIFT 8 /* WSEQ_EOS49 */ 59846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS49_WIDTH 1 /* WSEQ_EOS49 */ 59856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY49_MASK 0x000F /* WSEQ_DELAY49 - [3:0] */ 59866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY49_SHIFT 0 /* WSEQ_DELAY49 - [3:0] */ 59876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY49_WIDTH 4 /* WSEQ_DELAY49 - [3:0] */ 59886a504a75SDimitris Papastamos 59896a504a75SDimitris Papastamos /* 59906a504a75SDimitris Papastamos * R12488 (0x30C8) - Write Sequencer 200 59916a504a75SDimitris Papastamos */ 59926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR50_MASK 0x3FFF /* WSEQ_ADDR50 - [13:0] */ 59936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR50_SHIFT 0 /* WSEQ_ADDR50 - [13:0] */ 59946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR50_WIDTH 14 /* WSEQ_ADDR50 - [13:0] */ 59956a504a75SDimitris Papastamos 59966a504a75SDimitris Papastamos /* 59976a504a75SDimitris Papastamos * R12489 (0x30C9) - Write Sequencer 201 59986a504a75SDimitris Papastamos */ 59996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA50_MASK 0x00FF /* WSEQ_DATA50 - [7:0] */ 60006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA50_SHIFT 0 /* WSEQ_DATA50 - [7:0] */ 60016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA50_WIDTH 8 /* WSEQ_DATA50 - [7:0] */ 60026a504a75SDimitris Papastamos 60036a504a75SDimitris Papastamos /* 60046a504a75SDimitris Papastamos * R12490 (0x30CA) - Write Sequencer 202 60056a504a75SDimitris Papastamos */ 60066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH50_MASK 0x0700 /* WSEQ_DATA_WIDTH50 - [10:8] */ 60076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH50_SHIFT 8 /* WSEQ_DATA_WIDTH50 - [10:8] */ 60086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH50_WIDTH 3 /* WSEQ_DATA_WIDTH50 - [10:8] */ 60096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START50_MASK 0x000F /* WSEQ_DATA_START50 - [3:0] */ 60106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START50_SHIFT 0 /* WSEQ_DATA_START50 - [3:0] */ 60116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START50_WIDTH 4 /* WSEQ_DATA_START50 - [3:0] */ 60126a504a75SDimitris Papastamos 60136a504a75SDimitris Papastamos /* 60146a504a75SDimitris Papastamos * R12491 (0x30CB) - Write Sequencer 203 60156a504a75SDimitris Papastamos */ 60166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS50 0x0100 /* WSEQ_EOS50 */ 60176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS50_MASK 0x0100 /* WSEQ_EOS50 */ 60186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS50_SHIFT 8 /* WSEQ_EOS50 */ 60196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS50_WIDTH 1 /* WSEQ_EOS50 */ 60206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY50_MASK 0x000F /* WSEQ_DELAY50 - [3:0] */ 60216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY50_SHIFT 0 /* WSEQ_DELAY50 - [3:0] */ 60226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY50_WIDTH 4 /* WSEQ_DELAY50 - [3:0] */ 60236a504a75SDimitris Papastamos 60246a504a75SDimitris Papastamos /* 60256a504a75SDimitris Papastamos * R12492 (0x30CC) - Write Sequencer 204 60266a504a75SDimitris Papastamos */ 60276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR51_MASK 0x3FFF /* WSEQ_ADDR51 - [13:0] */ 60286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR51_SHIFT 0 /* WSEQ_ADDR51 - [13:0] */ 60296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR51_WIDTH 14 /* WSEQ_ADDR51 - [13:0] */ 60306a504a75SDimitris Papastamos 60316a504a75SDimitris Papastamos /* 60326a504a75SDimitris Papastamos * R12493 (0x30CD) - Write Sequencer 205 60336a504a75SDimitris Papastamos */ 60346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA51_MASK 0x00FF /* WSEQ_DATA51 - [7:0] */ 60356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA51_SHIFT 0 /* WSEQ_DATA51 - [7:0] */ 60366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA51_WIDTH 8 /* WSEQ_DATA51 - [7:0] */ 60376a504a75SDimitris Papastamos 60386a504a75SDimitris Papastamos /* 60396a504a75SDimitris Papastamos * R12494 (0x30CE) - Write Sequencer 206 60406a504a75SDimitris Papastamos */ 60416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH51_MASK 0x0700 /* WSEQ_DATA_WIDTH51 - [10:8] */ 60426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH51_SHIFT 8 /* WSEQ_DATA_WIDTH51 - [10:8] */ 60436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH51_WIDTH 3 /* WSEQ_DATA_WIDTH51 - [10:8] */ 60446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START51_MASK 0x000F /* WSEQ_DATA_START51 - [3:0] */ 60456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START51_SHIFT 0 /* WSEQ_DATA_START51 - [3:0] */ 60466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START51_WIDTH 4 /* WSEQ_DATA_START51 - [3:0] */ 60476a504a75SDimitris Papastamos 60486a504a75SDimitris Papastamos /* 60496a504a75SDimitris Papastamos * R12495 (0x30CF) - Write Sequencer 207 60506a504a75SDimitris Papastamos */ 60516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS51 0x0100 /* WSEQ_EOS51 */ 60526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS51_MASK 0x0100 /* WSEQ_EOS51 */ 60536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS51_SHIFT 8 /* WSEQ_EOS51 */ 60546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS51_WIDTH 1 /* WSEQ_EOS51 */ 60556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY51_MASK 0x000F /* WSEQ_DELAY51 - [3:0] */ 60566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY51_SHIFT 0 /* WSEQ_DELAY51 - [3:0] */ 60576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY51_WIDTH 4 /* WSEQ_DELAY51 - [3:0] */ 60586a504a75SDimitris Papastamos 60596a504a75SDimitris Papastamos /* 60606a504a75SDimitris Papastamos * R12496 (0x30D0) - Write Sequencer 208 60616a504a75SDimitris Papastamos */ 60626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR52_MASK 0x3FFF /* WSEQ_ADDR52 - [13:0] */ 60636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR52_SHIFT 0 /* WSEQ_ADDR52 - [13:0] */ 60646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR52_WIDTH 14 /* WSEQ_ADDR52 - [13:0] */ 60656a504a75SDimitris Papastamos 60666a504a75SDimitris Papastamos /* 60676a504a75SDimitris Papastamos * R12497 (0x30D1) - Write Sequencer 209 60686a504a75SDimitris Papastamos */ 60696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA52_MASK 0x00FF /* WSEQ_DATA52 - [7:0] */ 60706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA52_SHIFT 0 /* WSEQ_DATA52 - [7:0] */ 60716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA52_WIDTH 8 /* WSEQ_DATA52 - [7:0] */ 60726a504a75SDimitris Papastamos 60736a504a75SDimitris Papastamos /* 60746a504a75SDimitris Papastamos * R12498 (0x30D2) - Write Sequencer 210 60756a504a75SDimitris Papastamos */ 60766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH52_MASK 0x0700 /* WSEQ_DATA_WIDTH52 - [10:8] */ 60776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH52_SHIFT 8 /* WSEQ_DATA_WIDTH52 - [10:8] */ 60786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH52_WIDTH 3 /* WSEQ_DATA_WIDTH52 - [10:8] */ 60796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START52_MASK 0x000F /* WSEQ_DATA_START52 - [3:0] */ 60806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START52_SHIFT 0 /* WSEQ_DATA_START52 - [3:0] */ 60816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START52_WIDTH 4 /* WSEQ_DATA_START52 - [3:0] */ 60826a504a75SDimitris Papastamos 60836a504a75SDimitris Papastamos /* 60846a504a75SDimitris Papastamos * R12499 (0x30D3) - Write Sequencer 211 60856a504a75SDimitris Papastamos */ 60866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS52 0x0100 /* WSEQ_EOS52 */ 60876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS52_MASK 0x0100 /* WSEQ_EOS52 */ 60886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS52_SHIFT 8 /* WSEQ_EOS52 */ 60896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS52_WIDTH 1 /* WSEQ_EOS52 */ 60906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY52_MASK 0x000F /* WSEQ_DELAY52 - [3:0] */ 60916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY52_SHIFT 0 /* WSEQ_DELAY52 - [3:0] */ 60926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY52_WIDTH 4 /* WSEQ_DELAY52 - [3:0] */ 60936a504a75SDimitris Papastamos 60946a504a75SDimitris Papastamos /* 60956a504a75SDimitris Papastamos * R12500 (0x30D4) - Write Sequencer 212 60966a504a75SDimitris Papastamos */ 60976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR53_MASK 0x3FFF /* WSEQ_ADDR53 - [13:0] */ 60986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR53_SHIFT 0 /* WSEQ_ADDR53 - [13:0] */ 60996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR53_WIDTH 14 /* WSEQ_ADDR53 - [13:0] */ 61006a504a75SDimitris Papastamos 61016a504a75SDimitris Papastamos /* 61026a504a75SDimitris Papastamos * R12501 (0x30D5) - Write Sequencer 213 61036a504a75SDimitris Papastamos */ 61046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA53_MASK 0x00FF /* WSEQ_DATA53 - [7:0] */ 61056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA53_SHIFT 0 /* WSEQ_DATA53 - [7:0] */ 61066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA53_WIDTH 8 /* WSEQ_DATA53 - [7:0] */ 61076a504a75SDimitris Papastamos 61086a504a75SDimitris Papastamos /* 61096a504a75SDimitris Papastamos * R12502 (0x30D6) - Write Sequencer 214 61106a504a75SDimitris Papastamos */ 61116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH53_MASK 0x0700 /* WSEQ_DATA_WIDTH53 - [10:8] */ 61126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH53_SHIFT 8 /* WSEQ_DATA_WIDTH53 - [10:8] */ 61136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH53_WIDTH 3 /* WSEQ_DATA_WIDTH53 - [10:8] */ 61146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START53_MASK 0x000F /* WSEQ_DATA_START53 - [3:0] */ 61156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START53_SHIFT 0 /* WSEQ_DATA_START53 - [3:0] */ 61166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START53_WIDTH 4 /* WSEQ_DATA_START53 - [3:0] */ 61176a504a75SDimitris Papastamos 61186a504a75SDimitris Papastamos /* 61196a504a75SDimitris Papastamos * R12503 (0x30D7) - Write Sequencer 215 61206a504a75SDimitris Papastamos */ 61216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS53 0x0100 /* WSEQ_EOS53 */ 61226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS53_MASK 0x0100 /* WSEQ_EOS53 */ 61236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS53_SHIFT 8 /* WSEQ_EOS53 */ 61246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS53_WIDTH 1 /* WSEQ_EOS53 */ 61256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY53_MASK 0x000F /* WSEQ_DELAY53 - [3:0] */ 61266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY53_SHIFT 0 /* WSEQ_DELAY53 - [3:0] */ 61276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY53_WIDTH 4 /* WSEQ_DELAY53 - [3:0] */ 61286a504a75SDimitris Papastamos 61296a504a75SDimitris Papastamos /* 61306a504a75SDimitris Papastamos * R12504 (0x30D8) - Write Sequencer 216 61316a504a75SDimitris Papastamos */ 61326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR54_MASK 0x3FFF /* WSEQ_ADDR54 - [13:0] */ 61336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR54_SHIFT 0 /* WSEQ_ADDR54 - [13:0] */ 61346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR54_WIDTH 14 /* WSEQ_ADDR54 - [13:0] */ 61356a504a75SDimitris Papastamos 61366a504a75SDimitris Papastamos /* 61376a504a75SDimitris Papastamos * R12505 (0x30D9) - Write Sequencer 217 61386a504a75SDimitris Papastamos */ 61396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA54_MASK 0x00FF /* WSEQ_DATA54 - [7:0] */ 61406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA54_SHIFT 0 /* WSEQ_DATA54 - [7:0] */ 61416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA54_WIDTH 8 /* WSEQ_DATA54 - [7:0] */ 61426a504a75SDimitris Papastamos 61436a504a75SDimitris Papastamos /* 61446a504a75SDimitris Papastamos * R12506 (0x30DA) - Write Sequencer 218 61456a504a75SDimitris Papastamos */ 61466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH54_MASK 0x0700 /* WSEQ_DATA_WIDTH54 - [10:8] */ 61476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH54_SHIFT 8 /* WSEQ_DATA_WIDTH54 - [10:8] */ 61486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH54_WIDTH 3 /* WSEQ_DATA_WIDTH54 - [10:8] */ 61496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START54_MASK 0x000F /* WSEQ_DATA_START54 - [3:0] */ 61506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START54_SHIFT 0 /* WSEQ_DATA_START54 - [3:0] */ 61516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START54_WIDTH 4 /* WSEQ_DATA_START54 - [3:0] */ 61526a504a75SDimitris Papastamos 61536a504a75SDimitris Papastamos /* 61546a504a75SDimitris Papastamos * R12507 (0x30DB) - Write Sequencer 219 61556a504a75SDimitris Papastamos */ 61566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS54 0x0100 /* WSEQ_EOS54 */ 61576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS54_MASK 0x0100 /* WSEQ_EOS54 */ 61586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS54_SHIFT 8 /* WSEQ_EOS54 */ 61596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS54_WIDTH 1 /* WSEQ_EOS54 */ 61606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY54_MASK 0x000F /* WSEQ_DELAY54 - [3:0] */ 61616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY54_SHIFT 0 /* WSEQ_DELAY54 - [3:0] */ 61626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY54_WIDTH 4 /* WSEQ_DELAY54 - [3:0] */ 61636a504a75SDimitris Papastamos 61646a504a75SDimitris Papastamos /* 61656a504a75SDimitris Papastamos * R12508 (0x30DC) - Write Sequencer 220 61666a504a75SDimitris Papastamos */ 61676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR55_MASK 0x3FFF /* WSEQ_ADDR55 - [13:0] */ 61686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR55_SHIFT 0 /* WSEQ_ADDR55 - [13:0] */ 61696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR55_WIDTH 14 /* WSEQ_ADDR55 - [13:0] */ 61706a504a75SDimitris Papastamos 61716a504a75SDimitris Papastamos /* 61726a504a75SDimitris Papastamos * R12509 (0x30DD) - Write Sequencer 221 61736a504a75SDimitris Papastamos */ 61746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA55_MASK 0x00FF /* WSEQ_DATA55 - [7:0] */ 61756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA55_SHIFT 0 /* WSEQ_DATA55 - [7:0] */ 61766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA55_WIDTH 8 /* WSEQ_DATA55 - [7:0] */ 61776a504a75SDimitris Papastamos 61786a504a75SDimitris Papastamos /* 61796a504a75SDimitris Papastamos * R12510 (0x30DE) - Write Sequencer 222 61806a504a75SDimitris Papastamos */ 61816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH55_MASK 0x0700 /* WSEQ_DATA_WIDTH55 - [10:8] */ 61826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH55_SHIFT 8 /* WSEQ_DATA_WIDTH55 - [10:8] */ 61836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH55_WIDTH 3 /* WSEQ_DATA_WIDTH55 - [10:8] */ 61846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START55_MASK 0x000F /* WSEQ_DATA_START55 - [3:0] */ 61856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START55_SHIFT 0 /* WSEQ_DATA_START55 - [3:0] */ 61866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START55_WIDTH 4 /* WSEQ_DATA_START55 - [3:0] */ 61876a504a75SDimitris Papastamos 61886a504a75SDimitris Papastamos /* 61896a504a75SDimitris Papastamos * R12511 (0x30DF) - Write Sequencer 223 61906a504a75SDimitris Papastamos */ 61916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS55 0x0100 /* WSEQ_EOS55 */ 61926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS55_MASK 0x0100 /* WSEQ_EOS55 */ 61936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS55_SHIFT 8 /* WSEQ_EOS55 */ 61946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS55_WIDTH 1 /* WSEQ_EOS55 */ 61956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY55_MASK 0x000F /* WSEQ_DELAY55 - [3:0] */ 61966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY55_SHIFT 0 /* WSEQ_DELAY55 - [3:0] */ 61976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY55_WIDTH 4 /* WSEQ_DELAY55 - [3:0] */ 61986a504a75SDimitris Papastamos 61996a504a75SDimitris Papastamos /* 62006a504a75SDimitris Papastamos * R12512 (0x30E0) - Write Sequencer 224 62016a504a75SDimitris Papastamos */ 62026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR56_MASK 0x3FFF /* WSEQ_ADDR56 - [13:0] */ 62036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR56_SHIFT 0 /* WSEQ_ADDR56 - [13:0] */ 62046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR56_WIDTH 14 /* WSEQ_ADDR56 - [13:0] */ 62056a504a75SDimitris Papastamos 62066a504a75SDimitris Papastamos /* 62076a504a75SDimitris Papastamos * R12513 (0x30E1) - Write Sequencer 225 62086a504a75SDimitris Papastamos */ 62096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA56_MASK 0x00FF /* WSEQ_DATA56 - [7:0] */ 62106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA56_SHIFT 0 /* WSEQ_DATA56 - [7:0] */ 62116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA56_WIDTH 8 /* WSEQ_DATA56 - [7:0] */ 62126a504a75SDimitris Papastamos 62136a504a75SDimitris Papastamos /* 62146a504a75SDimitris Papastamos * R12514 (0x30E2) - Write Sequencer 226 62156a504a75SDimitris Papastamos */ 62166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH56_MASK 0x0700 /* WSEQ_DATA_WIDTH56 - [10:8] */ 62176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH56_SHIFT 8 /* WSEQ_DATA_WIDTH56 - [10:8] */ 62186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH56_WIDTH 3 /* WSEQ_DATA_WIDTH56 - [10:8] */ 62196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START56_MASK 0x000F /* WSEQ_DATA_START56 - [3:0] */ 62206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START56_SHIFT 0 /* WSEQ_DATA_START56 - [3:0] */ 62216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START56_WIDTH 4 /* WSEQ_DATA_START56 - [3:0] */ 62226a504a75SDimitris Papastamos 62236a504a75SDimitris Papastamos /* 62246a504a75SDimitris Papastamos * R12515 (0x30E3) - Write Sequencer 227 62256a504a75SDimitris Papastamos */ 62266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS56 0x0100 /* WSEQ_EOS56 */ 62276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS56_MASK 0x0100 /* WSEQ_EOS56 */ 62286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS56_SHIFT 8 /* WSEQ_EOS56 */ 62296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS56_WIDTH 1 /* WSEQ_EOS56 */ 62306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY56_MASK 0x000F /* WSEQ_DELAY56 - [3:0] */ 62316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY56_SHIFT 0 /* WSEQ_DELAY56 - [3:0] */ 62326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY56_WIDTH 4 /* WSEQ_DELAY56 - [3:0] */ 62336a504a75SDimitris Papastamos 62346a504a75SDimitris Papastamos /* 62356a504a75SDimitris Papastamos * R12516 (0x30E4) - Write Sequencer 228 62366a504a75SDimitris Papastamos */ 62376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR57_MASK 0x3FFF /* WSEQ_ADDR57 - [13:0] */ 62386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR57_SHIFT 0 /* WSEQ_ADDR57 - [13:0] */ 62396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR57_WIDTH 14 /* WSEQ_ADDR57 - [13:0] */ 62406a504a75SDimitris Papastamos 62416a504a75SDimitris Papastamos /* 62426a504a75SDimitris Papastamos * R12517 (0x30E5) - Write Sequencer 229 62436a504a75SDimitris Papastamos */ 62446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA57_MASK 0x00FF /* WSEQ_DATA57 - [7:0] */ 62456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA57_SHIFT 0 /* WSEQ_DATA57 - [7:0] */ 62466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA57_WIDTH 8 /* WSEQ_DATA57 - [7:0] */ 62476a504a75SDimitris Papastamos 62486a504a75SDimitris Papastamos /* 62496a504a75SDimitris Papastamos * R12518 (0x30E6) - Write Sequencer 230 62506a504a75SDimitris Papastamos */ 62516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH57_MASK 0x0700 /* WSEQ_DATA_WIDTH57 - [10:8] */ 62526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH57_SHIFT 8 /* WSEQ_DATA_WIDTH57 - [10:8] */ 62536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH57_WIDTH 3 /* WSEQ_DATA_WIDTH57 - [10:8] */ 62546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START57_MASK 0x000F /* WSEQ_DATA_START57 - [3:0] */ 62556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START57_SHIFT 0 /* WSEQ_DATA_START57 - [3:0] */ 62566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START57_WIDTH 4 /* WSEQ_DATA_START57 - [3:0] */ 62576a504a75SDimitris Papastamos 62586a504a75SDimitris Papastamos /* 62596a504a75SDimitris Papastamos * R12519 (0x30E7) - Write Sequencer 231 62606a504a75SDimitris Papastamos */ 62616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS57 0x0100 /* WSEQ_EOS57 */ 62626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS57_MASK 0x0100 /* WSEQ_EOS57 */ 62636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS57_SHIFT 8 /* WSEQ_EOS57 */ 62646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS57_WIDTH 1 /* WSEQ_EOS57 */ 62656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY57_MASK 0x000F /* WSEQ_DELAY57 - [3:0] */ 62666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY57_SHIFT 0 /* WSEQ_DELAY57 - [3:0] */ 62676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY57_WIDTH 4 /* WSEQ_DELAY57 - [3:0] */ 62686a504a75SDimitris Papastamos 62696a504a75SDimitris Papastamos /* 62706a504a75SDimitris Papastamos * R12520 (0x30E8) - Write Sequencer 232 62716a504a75SDimitris Papastamos */ 62726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR58_MASK 0x3FFF /* WSEQ_ADDR58 - [13:0] */ 62736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR58_SHIFT 0 /* WSEQ_ADDR58 - [13:0] */ 62746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR58_WIDTH 14 /* WSEQ_ADDR58 - [13:0] */ 62756a504a75SDimitris Papastamos 62766a504a75SDimitris Papastamos /* 62776a504a75SDimitris Papastamos * R12521 (0x30E9) - Write Sequencer 233 62786a504a75SDimitris Papastamos */ 62796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA58_MASK 0x00FF /* WSEQ_DATA58 - [7:0] */ 62806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA58_SHIFT 0 /* WSEQ_DATA58 - [7:0] */ 62816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA58_WIDTH 8 /* WSEQ_DATA58 - [7:0] */ 62826a504a75SDimitris Papastamos 62836a504a75SDimitris Papastamos /* 62846a504a75SDimitris Papastamos * R12522 (0x30EA) - Write Sequencer 234 62856a504a75SDimitris Papastamos */ 62866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH58_MASK 0x0700 /* WSEQ_DATA_WIDTH58 - [10:8] */ 62876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH58_SHIFT 8 /* WSEQ_DATA_WIDTH58 - [10:8] */ 62886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH58_WIDTH 3 /* WSEQ_DATA_WIDTH58 - [10:8] */ 62896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START58_MASK 0x000F /* WSEQ_DATA_START58 - [3:0] */ 62906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START58_SHIFT 0 /* WSEQ_DATA_START58 - [3:0] */ 62916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START58_WIDTH 4 /* WSEQ_DATA_START58 - [3:0] */ 62926a504a75SDimitris Papastamos 62936a504a75SDimitris Papastamos /* 62946a504a75SDimitris Papastamos * R12523 (0x30EB) - Write Sequencer 235 62956a504a75SDimitris Papastamos */ 62966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS58 0x0100 /* WSEQ_EOS58 */ 62976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS58_MASK 0x0100 /* WSEQ_EOS58 */ 62986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS58_SHIFT 8 /* WSEQ_EOS58 */ 62996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS58_WIDTH 1 /* WSEQ_EOS58 */ 63006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY58_MASK 0x000F /* WSEQ_DELAY58 - [3:0] */ 63016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY58_SHIFT 0 /* WSEQ_DELAY58 - [3:0] */ 63026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY58_WIDTH 4 /* WSEQ_DELAY58 - [3:0] */ 63036a504a75SDimitris Papastamos 63046a504a75SDimitris Papastamos /* 63056a504a75SDimitris Papastamos * R12524 (0x30EC) - Write Sequencer 236 63066a504a75SDimitris Papastamos */ 63076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR59_MASK 0x3FFF /* WSEQ_ADDR59 - [13:0] */ 63086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR59_SHIFT 0 /* WSEQ_ADDR59 - [13:0] */ 63096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR59_WIDTH 14 /* WSEQ_ADDR59 - [13:0] */ 63106a504a75SDimitris Papastamos 63116a504a75SDimitris Papastamos /* 63126a504a75SDimitris Papastamos * R12525 (0x30ED) - Write Sequencer 237 63136a504a75SDimitris Papastamos */ 63146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA59_MASK 0x00FF /* WSEQ_DATA59 - [7:0] */ 63156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA59_SHIFT 0 /* WSEQ_DATA59 - [7:0] */ 63166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA59_WIDTH 8 /* WSEQ_DATA59 - [7:0] */ 63176a504a75SDimitris Papastamos 63186a504a75SDimitris Papastamos /* 63196a504a75SDimitris Papastamos * R12526 (0x30EE) - Write Sequencer 238 63206a504a75SDimitris Papastamos */ 63216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH59_MASK 0x0700 /* WSEQ_DATA_WIDTH59 - [10:8] */ 63226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH59_SHIFT 8 /* WSEQ_DATA_WIDTH59 - [10:8] */ 63236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH59_WIDTH 3 /* WSEQ_DATA_WIDTH59 - [10:8] */ 63246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START59_MASK 0x000F /* WSEQ_DATA_START59 - [3:0] */ 63256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START59_SHIFT 0 /* WSEQ_DATA_START59 - [3:0] */ 63266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START59_WIDTH 4 /* WSEQ_DATA_START59 - [3:0] */ 63276a504a75SDimitris Papastamos 63286a504a75SDimitris Papastamos /* 63296a504a75SDimitris Papastamos * R12527 (0x30EF) - Write Sequencer 239 63306a504a75SDimitris Papastamos */ 63316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS59 0x0100 /* WSEQ_EOS59 */ 63326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS59_MASK 0x0100 /* WSEQ_EOS59 */ 63336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS59_SHIFT 8 /* WSEQ_EOS59 */ 63346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS59_WIDTH 1 /* WSEQ_EOS59 */ 63356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY59_MASK 0x000F /* WSEQ_DELAY59 - [3:0] */ 63366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY59_SHIFT 0 /* WSEQ_DELAY59 - [3:0] */ 63376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY59_WIDTH 4 /* WSEQ_DELAY59 - [3:0] */ 63386a504a75SDimitris Papastamos 63396a504a75SDimitris Papastamos /* 63406a504a75SDimitris Papastamos * R12528 (0x30F0) - Write Sequencer 240 63416a504a75SDimitris Papastamos */ 63426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR60_MASK 0x3FFF /* WSEQ_ADDR60 - [13:0] */ 63436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR60_SHIFT 0 /* WSEQ_ADDR60 - [13:0] */ 63446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR60_WIDTH 14 /* WSEQ_ADDR60 - [13:0] */ 63456a504a75SDimitris Papastamos 63466a504a75SDimitris Papastamos /* 63476a504a75SDimitris Papastamos * R12529 (0x30F1) - Write Sequencer 241 63486a504a75SDimitris Papastamos */ 63496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA60_MASK 0x00FF /* WSEQ_DATA60 - [7:0] */ 63506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA60_SHIFT 0 /* WSEQ_DATA60 - [7:0] */ 63516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA60_WIDTH 8 /* WSEQ_DATA60 - [7:0] */ 63526a504a75SDimitris Papastamos 63536a504a75SDimitris Papastamos /* 63546a504a75SDimitris Papastamos * R12530 (0x30F2) - Write Sequencer 242 63556a504a75SDimitris Papastamos */ 63566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH60_MASK 0x0700 /* WSEQ_DATA_WIDTH60 - [10:8] */ 63576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH60_SHIFT 8 /* WSEQ_DATA_WIDTH60 - [10:8] */ 63586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH60_WIDTH 3 /* WSEQ_DATA_WIDTH60 - [10:8] */ 63596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START60_MASK 0x000F /* WSEQ_DATA_START60 - [3:0] */ 63606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START60_SHIFT 0 /* WSEQ_DATA_START60 - [3:0] */ 63616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START60_WIDTH 4 /* WSEQ_DATA_START60 - [3:0] */ 63626a504a75SDimitris Papastamos 63636a504a75SDimitris Papastamos /* 63646a504a75SDimitris Papastamos * R12531 (0x30F3) - Write Sequencer 243 63656a504a75SDimitris Papastamos */ 63666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS60 0x0100 /* WSEQ_EOS60 */ 63676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS60_MASK 0x0100 /* WSEQ_EOS60 */ 63686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS60_SHIFT 8 /* WSEQ_EOS60 */ 63696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS60_WIDTH 1 /* WSEQ_EOS60 */ 63706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY60_MASK 0x000F /* WSEQ_DELAY60 - [3:0] */ 63716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY60_SHIFT 0 /* WSEQ_DELAY60 - [3:0] */ 63726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY60_WIDTH 4 /* WSEQ_DELAY60 - [3:0] */ 63736a504a75SDimitris Papastamos 63746a504a75SDimitris Papastamos /* 63756a504a75SDimitris Papastamos * R12532 (0x30F4) - Write Sequencer 244 63766a504a75SDimitris Papastamos */ 63776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR61_MASK 0x3FFF /* WSEQ_ADDR61 - [13:0] */ 63786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR61_SHIFT 0 /* WSEQ_ADDR61 - [13:0] */ 63796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR61_WIDTH 14 /* WSEQ_ADDR61 - [13:0] */ 63806a504a75SDimitris Papastamos 63816a504a75SDimitris Papastamos /* 63826a504a75SDimitris Papastamos * R12533 (0x30F5) - Write Sequencer 245 63836a504a75SDimitris Papastamos */ 63846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA61_MASK 0x00FF /* WSEQ_DATA61 - [7:0] */ 63856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA61_SHIFT 0 /* WSEQ_DATA61 - [7:0] */ 63866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA61_WIDTH 8 /* WSEQ_DATA61 - [7:0] */ 63876a504a75SDimitris Papastamos 63886a504a75SDimitris Papastamos /* 63896a504a75SDimitris Papastamos * R12534 (0x30F6) - Write Sequencer 246 63906a504a75SDimitris Papastamos */ 63916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH61_MASK 0x0700 /* WSEQ_DATA_WIDTH61 - [10:8] */ 63926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH61_SHIFT 8 /* WSEQ_DATA_WIDTH61 - [10:8] */ 63936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH61_WIDTH 3 /* WSEQ_DATA_WIDTH61 - [10:8] */ 63946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START61_MASK 0x000F /* WSEQ_DATA_START61 - [3:0] */ 63956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START61_SHIFT 0 /* WSEQ_DATA_START61 - [3:0] */ 63966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START61_WIDTH 4 /* WSEQ_DATA_START61 - [3:0] */ 63976a504a75SDimitris Papastamos 63986a504a75SDimitris Papastamos /* 63996a504a75SDimitris Papastamos * R12535 (0x30F7) - Write Sequencer 247 64006a504a75SDimitris Papastamos */ 64016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS61 0x0100 /* WSEQ_EOS61 */ 64026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS61_MASK 0x0100 /* WSEQ_EOS61 */ 64036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS61_SHIFT 8 /* WSEQ_EOS61 */ 64046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS61_WIDTH 1 /* WSEQ_EOS61 */ 64056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY61_MASK 0x000F /* WSEQ_DELAY61 - [3:0] */ 64066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY61_SHIFT 0 /* WSEQ_DELAY61 - [3:0] */ 64076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY61_WIDTH 4 /* WSEQ_DELAY61 - [3:0] */ 64086a504a75SDimitris Papastamos 64096a504a75SDimitris Papastamos /* 64106a504a75SDimitris Papastamos * R12536 (0x30F8) - Write Sequencer 248 64116a504a75SDimitris Papastamos */ 64126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR62_MASK 0x3FFF /* WSEQ_ADDR62 - [13:0] */ 64136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR62_SHIFT 0 /* WSEQ_ADDR62 - [13:0] */ 64146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR62_WIDTH 14 /* WSEQ_ADDR62 - [13:0] */ 64156a504a75SDimitris Papastamos 64166a504a75SDimitris Papastamos /* 64176a504a75SDimitris Papastamos * R12537 (0x30F9) - Write Sequencer 249 64186a504a75SDimitris Papastamos */ 64196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA62_MASK 0x00FF /* WSEQ_DATA62 - [7:0] */ 64206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA62_SHIFT 0 /* WSEQ_DATA62 - [7:0] */ 64216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA62_WIDTH 8 /* WSEQ_DATA62 - [7:0] */ 64226a504a75SDimitris Papastamos 64236a504a75SDimitris Papastamos /* 64246a504a75SDimitris Papastamos * R12538 (0x30FA) - Write Sequencer 250 64256a504a75SDimitris Papastamos */ 64266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH62_MASK 0x0700 /* WSEQ_DATA_WIDTH62 - [10:8] */ 64276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH62_SHIFT 8 /* WSEQ_DATA_WIDTH62 - [10:8] */ 64286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH62_WIDTH 3 /* WSEQ_DATA_WIDTH62 - [10:8] */ 64296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START62_MASK 0x000F /* WSEQ_DATA_START62 - [3:0] */ 64306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START62_SHIFT 0 /* WSEQ_DATA_START62 - [3:0] */ 64316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START62_WIDTH 4 /* WSEQ_DATA_START62 - [3:0] */ 64326a504a75SDimitris Papastamos 64336a504a75SDimitris Papastamos /* 64346a504a75SDimitris Papastamos * R12539 (0x30FB) - Write Sequencer 251 64356a504a75SDimitris Papastamos */ 64366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS62 0x0100 /* WSEQ_EOS62 */ 64376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS62_MASK 0x0100 /* WSEQ_EOS62 */ 64386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS62_SHIFT 8 /* WSEQ_EOS62 */ 64396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS62_WIDTH 1 /* WSEQ_EOS62 */ 64406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY62_MASK 0x000F /* WSEQ_DELAY62 - [3:0] */ 64416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY62_SHIFT 0 /* WSEQ_DELAY62 - [3:0] */ 64426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY62_WIDTH 4 /* WSEQ_DELAY62 - [3:0] */ 64436a504a75SDimitris Papastamos 64446a504a75SDimitris Papastamos /* 64456a504a75SDimitris Papastamos * R12540 (0x30FC) - Write Sequencer 252 64466a504a75SDimitris Papastamos */ 64476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR63_MASK 0x3FFF /* WSEQ_ADDR63 - [13:0] */ 64486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR63_SHIFT 0 /* WSEQ_ADDR63 - [13:0] */ 64496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR63_WIDTH 14 /* WSEQ_ADDR63 - [13:0] */ 64506a504a75SDimitris Papastamos 64516a504a75SDimitris Papastamos /* 64526a504a75SDimitris Papastamos * R12541 (0x30FD) - Write Sequencer 253 64536a504a75SDimitris Papastamos */ 64546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA63_MASK 0x00FF /* WSEQ_DATA63 - [7:0] */ 64556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA63_SHIFT 0 /* WSEQ_DATA63 - [7:0] */ 64566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA63_WIDTH 8 /* WSEQ_DATA63 - [7:0] */ 64576a504a75SDimitris Papastamos 64586a504a75SDimitris Papastamos /* 64596a504a75SDimitris Papastamos * R12542 (0x30FE) - Write Sequencer 254 64606a504a75SDimitris Papastamos */ 64616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH63_MASK 0x0700 /* WSEQ_DATA_WIDTH63 - [10:8] */ 64626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH63_SHIFT 8 /* WSEQ_DATA_WIDTH63 - [10:8] */ 64636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH63_WIDTH 3 /* WSEQ_DATA_WIDTH63 - [10:8] */ 64646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START63_MASK 0x000F /* WSEQ_DATA_START63 - [3:0] */ 64656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START63_SHIFT 0 /* WSEQ_DATA_START63 - [3:0] */ 64666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START63_WIDTH 4 /* WSEQ_DATA_START63 - [3:0] */ 64676a504a75SDimitris Papastamos 64686a504a75SDimitris Papastamos /* 64696a504a75SDimitris Papastamos * R12543 (0x30FF) - Write Sequencer 255 64706a504a75SDimitris Papastamos */ 64716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS63 0x0100 /* WSEQ_EOS63 */ 64726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS63_MASK 0x0100 /* WSEQ_EOS63 */ 64736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS63_SHIFT 8 /* WSEQ_EOS63 */ 64746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS63_WIDTH 1 /* WSEQ_EOS63 */ 64756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY63_MASK 0x000F /* WSEQ_DELAY63 - [3:0] */ 64766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY63_SHIFT 0 /* WSEQ_DELAY63 - [3:0] */ 64776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY63_WIDTH 4 /* WSEQ_DELAY63 - [3:0] */ 64786a504a75SDimitris Papastamos 64796a504a75SDimitris Papastamos /* 64806a504a75SDimitris Papastamos * R12544 (0x3100) - Write Sequencer 256 64816a504a75SDimitris Papastamos */ 64826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR64_MASK 0x3FFF /* WSEQ_ADDR64 - [13:0] */ 64836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR64_SHIFT 0 /* WSEQ_ADDR64 - [13:0] */ 64846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR64_WIDTH 14 /* WSEQ_ADDR64 - [13:0] */ 64856a504a75SDimitris Papastamos 64866a504a75SDimitris Papastamos /* 64876a504a75SDimitris Papastamos * R12545 (0x3101) - Write Sequencer 257 64886a504a75SDimitris Papastamos */ 64896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA64_MASK 0x00FF /* WSEQ_DATA64 - [7:0] */ 64906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA64_SHIFT 0 /* WSEQ_DATA64 - [7:0] */ 64916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA64_WIDTH 8 /* WSEQ_DATA64 - [7:0] */ 64926a504a75SDimitris Papastamos 64936a504a75SDimitris Papastamos /* 64946a504a75SDimitris Papastamos * R12546 (0x3102) - Write Sequencer 258 64956a504a75SDimitris Papastamos */ 64966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH64_MASK 0x0700 /* WSEQ_DATA_WIDTH64 - [10:8] */ 64976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH64_SHIFT 8 /* WSEQ_DATA_WIDTH64 - [10:8] */ 64986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH64_WIDTH 3 /* WSEQ_DATA_WIDTH64 - [10:8] */ 64996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START64_MASK 0x000F /* WSEQ_DATA_START64 - [3:0] */ 65006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START64_SHIFT 0 /* WSEQ_DATA_START64 - [3:0] */ 65016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START64_WIDTH 4 /* WSEQ_DATA_START64 - [3:0] */ 65026a504a75SDimitris Papastamos 65036a504a75SDimitris Papastamos /* 65046a504a75SDimitris Papastamos * R12547 (0x3103) - Write Sequencer 259 65056a504a75SDimitris Papastamos */ 65066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS64 0x0100 /* WSEQ_EOS64 */ 65076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS64_MASK 0x0100 /* WSEQ_EOS64 */ 65086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS64_SHIFT 8 /* WSEQ_EOS64 */ 65096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS64_WIDTH 1 /* WSEQ_EOS64 */ 65106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY64_MASK 0x000F /* WSEQ_DELAY64 - [3:0] */ 65116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY64_SHIFT 0 /* WSEQ_DELAY64 - [3:0] */ 65126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY64_WIDTH 4 /* WSEQ_DELAY64 - [3:0] */ 65136a504a75SDimitris Papastamos 65146a504a75SDimitris Papastamos /* 65156a504a75SDimitris Papastamos * R12548 (0x3104) - Write Sequencer 260 65166a504a75SDimitris Papastamos */ 65176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR65_MASK 0x3FFF /* WSEQ_ADDR65 - [13:0] */ 65186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR65_SHIFT 0 /* WSEQ_ADDR65 - [13:0] */ 65196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR65_WIDTH 14 /* WSEQ_ADDR65 - [13:0] */ 65206a504a75SDimitris Papastamos 65216a504a75SDimitris Papastamos /* 65226a504a75SDimitris Papastamos * R12549 (0x3105) - Write Sequencer 261 65236a504a75SDimitris Papastamos */ 65246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA65_MASK 0x00FF /* WSEQ_DATA65 - [7:0] */ 65256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA65_SHIFT 0 /* WSEQ_DATA65 - [7:0] */ 65266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA65_WIDTH 8 /* WSEQ_DATA65 - [7:0] */ 65276a504a75SDimitris Papastamos 65286a504a75SDimitris Papastamos /* 65296a504a75SDimitris Papastamos * R12550 (0x3106) - Write Sequencer 262 65306a504a75SDimitris Papastamos */ 65316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH65_MASK 0x0700 /* WSEQ_DATA_WIDTH65 - [10:8] */ 65326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH65_SHIFT 8 /* WSEQ_DATA_WIDTH65 - [10:8] */ 65336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH65_WIDTH 3 /* WSEQ_DATA_WIDTH65 - [10:8] */ 65346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START65_MASK 0x000F /* WSEQ_DATA_START65 - [3:0] */ 65356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START65_SHIFT 0 /* WSEQ_DATA_START65 - [3:0] */ 65366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START65_WIDTH 4 /* WSEQ_DATA_START65 - [3:0] */ 65376a504a75SDimitris Papastamos 65386a504a75SDimitris Papastamos /* 65396a504a75SDimitris Papastamos * R12551 (0x3107) - Write Sequencer 263 65406a504a75SDimitris Papastamos */ 65416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS65 0x0100 /* WSEQ_EOS65 */ 65426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS65_MASK 0x0100 /* WSEQ_EOS65 */ 65436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS65_SHIFT 8 /* WSEQ_EOS65 */ 65446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS65_WIDTH 1 /* WSEQ_EOS65 */ 65456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY65_MASK 0x000F /* WSEQ_DELAY65 - [3:0] */ 65466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY65_SHIFT 0 /* WSEQ_DELAY65 - [3:0] */ 65476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY65_WIDTH 4 /* WSEQ_DELAY65 - [3:0] */ 65486a504a75SDimitris Papastamos 65496a504a75SDimitris Papastamos /* 65506a504a75SDimitris Papastamos * R12552 (0x3108) - Write Sequencer 264 65516a504a75SDimitris Papastamos */ 65526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR66_MASK 0x3FFF /* WSEQ_ADDR66 - [13:0] */ 65536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR66_SHIFT 0 /* WSEQ_ADDR66 - [13:0] */ 65546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR66_WIDTH 14 /* WSEQ_ADDR66 - [13:0] */ 65556a504a75SDimitris Papastamos 65566a504a75SDimitris Papastamos /* 65576a504a75SDimitris Papastamos * R12553 (0x3109) - Write Sequencer 265 65586a504a75SDimitris Papastamos */ 65596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA66_MASK 0x00FF /* WSEQ_DATA66 - [7:0] */ 65606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA66_SHIFT 0 /* WSEQ_DATA66 - [7:0] */ 65616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA66_WIDTH 8 /* WSEQ_DATA66 - [7:0] */ 65626a504a75SDimitris Papastamos 65636a504a75SDimitris Papastamos /* 65646a504a75SDimitris Papastamos * R12554 (0x310A) - Write Sequencer 266 65656a504a75SDimitris Papastamos */ 65666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH66_MASK 0x0700 /* WSEQ_DATA_WIDTH66 - [10:8] */ 65676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH66_SHIFT 8 /* WSEQ_DATA_WIDTH66 - [10:8] */ 65686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH66_WIDTH 3 /* WSEQ_DATA_WIDTH66 - [10:8] */ 65696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START66_MASK 0x000F /* WSEQ_DATA_START66 - [3:0] */ 65706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START66_SHIFT 0 /* WSEQ_DATA_START66 - [3:0] */ 65716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START66_WIDTH 4 /* WSEQ_DATA_START66 - [3:0] */ 65726a504a75SDimitris Papastamos 65736a504a75SDimitris Papastamos /* 65746a504a75SDimitris Papastamos * R12555 (0x310B) - Write Sequencer 267 65756a504a75SDimitris Papastamos */ 65766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS66 0x0100 /* WSEQ_EOS66 */ 65776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS66_MASK 0x0100 /* WSEQ_EOS66 */ 65786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS66_SHIFT 8 /* WSEQ_EOS66 */ 65796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS66_WIDTH 1 /* WSEQ_EOS66 */ 65806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY66_MASK 0x000F /* WSEQ_DELAY66 - [3:0] */ 65816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY66_SHIFT 0 /* WSEQ_DELAY66 - [3:0] */ 65826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY66_WIDTH 4 /* WSEQ_DELAY66 - [3:0] */ 65836a504a75SDimitris Papastamos 65846a504a75SDimitris Papastamos /* 65856a504a75SDimitris Papastamos * R12556 (0x310C) - Write Sequencer 268 65866a504a75SDimitris Papastamos */ 65876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR67_MASK 0x3FFF /* WSEQ_ADDR67 - [13:0] */ 65886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR67_SHIFT 0 /* WSEQ_ADDR67 - [13:0] */ 65896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR67_WIDTH 14 /* WSEQ_ADDR67 - [13:0] */ 65906a504a75SDimitris Papastamos 65916a504a75SDimitris Papastamos /* 65926a504a75SDimitris Papastamos * R12557 (0x310D) - Write Sequencer 269 65936a504a75SDimitris Papastamos */ 65946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA67_MASK 0x00FF /* WSEQ_DATA67 - [7:0] */ 65956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA67_SHIFT 0 /* WSEQ_DATA67 - [7:0] */ 65966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA67_WIDTH 8 /* WSEQ_DATA67 - [7:0] */ 65976a504a75SDimitris Papastamos 65986a504a75SDimitris Papastamos /* 65996a504a75SDimitris Papastamos * R12558 (0x310E) - Write Sequencer 270 66006a504a75SDimitris Papastamos */ 66016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH67_MASK 0x0700 /* WSEQ_DATA_WIDTH67 - [10:8] */ 66026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH67_SHIFT 8 /* WSEQ_DATA_WIDTH67 - [10:8] */ 66036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH67_WIDTH 3 /* WSEQ_DATA_WIDTH67 - [10:8] */ 66046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START67_MASK 0x000F /* WSEQ_DATA_START67 - [3:0] */ 66056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START67_SHIFT 0 /* WSEQ_DATA_START67 - [3:0] */ 66066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START67_WIDTH 4 /* WSEQ_DATA_START67 - [3:0] */ 66076a504a75SDimitris Papastamos 66086a504a75SDimitris Papastamos /* 66096a504a75SDimitris Papastamos * R12559 (0x310F) - Write Sequencer 271 66106a504a75SDimitris Papastamos */ 66116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS67 0x0100 /* WSEQ_EOS67 */ 66126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS67_MASK 0x0100 /* WSEQ_EOS67 */ 66136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS67_SHIFT 8 /* WSEQ_EOS67 */ 66146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS67_WIDTH 1 /* WSEQ_EOS67 */ 66156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY67_MASK 0x000F /* WSEQ_DELAY67 - [3:0] */ 66166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY67_SHIFT 0 /* WSEQ_DELAY67 - [3:0] */ 66176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY67_WIDTH 4 /* WSEQ_DELAY67 - [3:0] */ 66186a504a75SDimitris Papastamos 66196a504a75SDimitris Papastamos /* 66206a504a75SDimitris Papastamos * R12560 (0x3110) - Write Sequencer 272 66216a504a75SDimitris Papastamos */ 66226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR68_MASK 0x3FFF /* WSEQ_ADDR68 - [13:0] */ 66236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR68_SHIFT 0 /* WSEQ_ADDR68 - [13:0] */ 66246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR68_WIDTH 14 /* WSEQ_ADDR68 - [13:0] */ 66256a504a75SDimitris Papastamos 66266a504a75SDimitris Papastamos /* 66276a504a75SDimitris Papastamos * R12561 (0x3111) - Write Sequencer 273 66286a504a75SDimitris Papastamos */ 66296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA68_MASK 0x00FF /* WSEQ_DATA68 - [7:0] */ 66306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA68_SHIFT 0 /* WSEQ_DATA68 - [7:0] */ 66316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA68_WIDTH 8 /* WSEQ_DATA68 - [7:0] */ 66326a504a75SDimitris Papastamos 66336a504a75SDimitris Papastamos /* 66346a504a75SDimitris Papastamos * R12562 (0x3112) - Write Sequencer 274 66356a504a75SDimitris Papastamos */ 66366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH68_MASK 0x0700 /* WSEQ_DATA_WIDTH68 - [10:8] */ 66376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH68_SHIFT 8 /* WSEQ_DATA_WIDTH68 - [10:8] */ 66386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH68_WIDTH 3 /* WSEQ_DATA_WIDTH68 - [10:8] */ 66396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START68_MASK 0x000F /* WSEQ_DATA_START68 - [3:0] */ 66406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START68_SHIFT 0 /* WSEQ_DATA_START68 - [3:0] */ 66416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START68_WIDTH 4 /* WSEQ_DATA_START68 - [3:0] */ 66426a504a75SDimitris Papastamos 66436a504a75SDimitris Papastamos /* 66446a504a75SDimitris Papastamos * R12563 (0x3113) - Write Sequencer 275 66456a504a75SDimitris Papastamos */ 66466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS68 0x0100 /* WSEQ_EOS68 */ 66476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS68_MASK 0x0100 /* WSEQ_EOS68 */ 66486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS68_SHIFT 8 /* WSEQ_EOS68 */ 66496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS68_WIDTH 1 /* WSEQ_EOS68 */ 66506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY68_MASK 0x000F /* WSEQ_DELAY68 - [3:0] */ 66516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY68_SHIFT 0 /* WSEQ_DELAY68 - [3:0] */ 66526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY68_WIDTH 4 /* WSEQ_DELAY68 - [3:0] */ 66536a504a75SDimitris Papastamos 66546a504a75SDimitris Papastamos /* 66556a504a75SDimitris Papastamos * R12564 (0x3114) - Write Sequencer 276 66566a504a75SDimitris Papastamos */ 66576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR69_MASK 0x3FFF /* WSEQ_ADDR69 - [13:0] */ 66586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR69_SHIFT 0 /* WSEQ_ADDR69 - [13:0] */ 66596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR69_WIDTH 14 /* WSEQ_ADDR69 - [13:0] */ 66606a504a75SDimitris Papastamos 66616a504a75SDimitris Papastamos /* 66626a504a75SDimitris Papastamos * R12565 (0x3115) - Write Sequencer 277 66636a504a75SDimitris Papastamos */ 66646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA69_MASK 0x00FF /* WSEQ_DATA69 - [7:0] */ 66656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA69_SHIFT 0 /* WSEQ_DATA69 - [7:0] */ 66666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA69_WIDTH 8 /* WSEQ_DATA69 - [7:0] */ 66676a504a75SDimitris Papastamos 66686a504a75SDimitris Papastamos /* 66696a504a75SDimitris Papastamos * R12566 (0x3116) - Write Sequencer 278 66706a504a75SDimitris Papastamos */ 66716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH69_MASK 0x0700 /* WSEQ_DATA_WIDTH69 - [10:8] */ 66726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH69_SHIFT 8 /* WSEQ_DATA_WIDTH69 - [10:8] */ 66736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH69_WIDTH 3 /* WSEQ_DATA_WIDTH69 - [10:8] */ 66746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START69_MASK 0x000F /* WSEQ_DATA_START69 - [3:0] */ 66756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START69_SHIFT 0 /* WSEQ_DATA_START69 - [3:0] */ 66766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START69_WIDTH 4 /* WSEQ_DATA_START69 - [3:0] */ 66776a504a75SDimitris Papastamos 66786a504a75SDimitris Papastamos /* 66796a504a75SDimitris Papastamos * R12567 (0x3117) - Write Sequencer 279 66806a504a75SDimitris Papastamos */ 66816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS69 0x0100 /* WSEQ_EOS69 */ 66826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS69_MASK 0x0100 /* WSEQ_EOS69 */ 66836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS69_SHIFT 8 /* WSEQ_EOS69 */ 66846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS69_WIDTH 1 /* WSEQ_EOS69 */ 66856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY69_MASK 0x000F /* WSEQ_DELAY69 - [3:0] */ 66866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY69_SHIFT 0 /* WSEQ_DELAY69 - [3:0] */ 66876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY69_WIDTH 4 /* WSEQ_DELAY69 - [3:0] */ 66886a504a75SDimitris Papastamos 66896a504a75SDimitris Papastamos /* 66906a504a75SDimitris Papastamos * R12568 (0x3118) - Write Sequencer 280 66916a504a75SDimitris Papastamos */ 66926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR70_MASK 0x3FFF /* WSEQ_ADDR70 - [13:0] */ 66936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR70_SHIFT 0 /* WSEQ_ADDR70 - [13:0] */ 66946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR70_WIDTH 14 /* WSEQ_ADDR70 - [13:0] */ 66956a504a75SDimitris Papastamos 66966a504a75SDimitris Papastamos /* 66976a504a75SDimitris Papastamos * R12569 (0x3119) - Write Sequencer 281 66986a504a75SDimitris Papastamos */ 66996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA70_MASK 0x00FF /* WSEQ_DATA70 - [7:0] */ 67006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA70_SHIFT 0 /* WSEQ_DATA70 - [7:0] */ 67016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA70_WIDTH 8 /* WSEQ_DATA70 - [7:0] */ 67026a504a75SDimitris Papastamos 67036a504a75SDimitris Papastamos /* 67046a504a75SDimitris Papastamos * R12570 (0x311A) - Write Sequencer 282 67056a504a75SDimitris Papastamos */ 67066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH70_MASK 0x0700 /* WSEQ_DATA_WIDTH70 - [10:8] */ 67076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH70_SHIFT 8 /* WSEQ_DATA_WIDTH70 - [10:8] */ 67086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH70_WIDTH 3 /* WSEQ_DATA_WIDTH70 - [10:8] */ 67096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START70_MASK 0x000F /* WSEQ_DATA_START70 - [3:0] */ 67106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START70_SHIFT 0 /* WSEQ_DATA_START70 - [3:0] */ 67116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START70_WIDTH 4 /* WSEQ_DATA_START70 - [3:0] */ 67126a504a75SDimitris Papastamos 67136a504a75SDimitris Papastamos /* 67146a504a75SDimitris Papastamos * R12571 (0x311B) - Write Sequencer 283 67156a504a75SDimitris Papastamos */ 67166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS70 0x0100 /* WSEQ_EOS70 */ 67176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS70_MASK 0x0100 /* WSEQ_EOS70 */ 67186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS70_SHIFT 8 /* WSEQ_EOS70 */ 67196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS70_WIDTH 1 /* WSEQ_EOS70 */ 67206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY70_MASK 0x000F /* WSEQ_DELAY70 - [3:0] */ 67216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY70_SHIFT 0 /* WSEQ_DELAY70 - [3:0] */ 67226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY70_WIDTH 4 /* WSEQ_DELAY70 - [3:0] */ 67236a504a75SDimitris Papastamos 67246a504a75SDimitris Papastamos /* 67256a504a75SDimitris Papastamos * R12572 (0x311C) - Write Sequencer 284 67266a504a75SDimitris Papastamos */ 67276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR71_MASK 0x3FFF /* WSEQ_ADDR71 - [13:0] */ 67286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR71_SHIFT 0 /* WSEQ_ADDR71 - [13:0] */ 67296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR71_WIDTH 14 /* WSEQ_ADDR71 - [13:0] */ 67306a504a75SDimitris Papastamos 67316a504a75SDimitris Papastamos /* 67326a504a75SDimitris Papastamos * R12573 (0x311D) - Write Sequencer 285 67336a504a75SDimitris Papastamos */ 67346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA71_MASK 0x00FF /* WSEQ_DATA71 - [7:0] */ 67356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA71_SHIFT 0 /* WSEQ_DATA71 - [7:0] */ 67366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA71_WIDTH 8 /* WSEQ_DATA71 - [7:0] */ 67376a504a75SDimitris Papastamos 67386a504a75SDimitris Papastamos /* 67396a504a75SDimitris Papastamos * R12574 (0x311E) - Write Sequencer 286 67406a504a75SDimitris Papastamos */ 67416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH71_MASK 0x0700 /* WSEQ_DATA_WIDTH71 - [10:8] */ 67426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH71_SHIFT 8 /* WSEQ_DATA_WIDTH71 - [10:8] */ 67436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH71_WIDTH 3 /* WSEQ_DATA_WIDTH71 - [10:8] */ 67446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START71_MASK 0x000F /* WSEQ_DATA_START71 - [3:0] */ 67456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START71_SHIFT 0 /* WSEQ_DATA_START71 - [3:0] */ 67466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START71_WIDTH 4 /* WSEQ_DATA_START71 - [3:0] */ 67476a504a75SDimitris Papastamos 67486a504a75SDimitris Papastamos /* 67496a504a75SDimitris Papastamos * R12575 (0x311F) - Write Sequencer 287 67506a504a75SDimitris Papastamos */ 67516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS71 0x0100 /* WSEQ_EOS71 */ 67526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS71_MASK 0x0100 /* WSEQ_EOS71 */ 67536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS71_SHIFT 8 /* WSEQ_EOS71 */ 67546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS71_WIDTH 1 /* WSEQ_EOS71 */ 67556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY71_MASK 0x000F /* WSEQ_DELAY71 - [3:0] */ 67566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY71_SHIFT 0 /* WSEQ_DELAY71 - [3:0] */ 67576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY71_WIDTH 4 /* WSEQ_DELAY71 - [3:0] */ 67586a504a75SDimitris Papastamos 67596a504a75SDimitris Papastamos /* 67606a504a75SDimitris Papastamos * R12576 (0x3120) - Write Sequencer 288 67616a504a75SDimitris Papastamos */ 67626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR72_MASK 0x3FFF /* WSEQ_ADDR72 - [13:0] */ 67636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR72_SHIFT 0 /* WSEQ_ADDR72 - [13:0] */ 67646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR72_WIDTH 14 /* WSEQ_ADDR72 - [13:0] */ 67656a504a75SDimitris Papastamos 67666a504a75SDimitris Papastamos /* 67676a504a75SDimitris Papastamos * R12577 (0x3121) - Write Sequencer 289 67686a504a75SDimitris Papastamos */ 67696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA72_MASK 0x00FF /* WSEQ_DATA72 - [7:0] */ 67706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA72_SHIFT 0 /* WSEQ_DATA72 - [7:0] */ 67716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA72_WIDTH 8 /* WSEQ_DATA72 - [7:0] */ 67726a504a75SDimitris Papastamos 67736a504a75SDimitris Papastamos /* 67746a504a75SDimitris Papastamos * R12578 (0x3122) - Write Sequencer 290 67756a504a75SDimitris Papastamos */ 67766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH72_MASK 0x0700 /* WSEQ_DATA_WIDTH72 - [10:8] */ 67776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH72_SHIFT 8 /* WSEQ_DATA_WIDTH72 - [10:8] */ 67786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH72_WIDTH 3 /* WSEQ_DATA_WIDTH72 - [10:8] */ 67796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START72_MASK 0x000F /* WSEQ_DATA_START72 - [3:0] */ 67806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START72_SHIFT 0 /* WSEQ_DATA_START72 - [3:0] */ 67816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START72_WIDTH 4 /* WSEQ_DATA_START72 - [3:0] */ 67826a504a75SDimitris Papastamos 67836a504a75SDimitris Papastamos /* 67846a504a75SDimitris Papastamos * R12579 (0x3123) - Write Sequencer 291 67856a504a75SDimitris Papastamos */ 67866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS72 0x0100 /* WSEQ_EOS72 */ 67876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS72_MASK 0x0100 /* WSEQ_EOS72 */ 67886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS72_SHIFT 8 /* WSEQ_EOS72 */ 67896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS72_WIDTH 1 /* WSEQ_EOS72 */ 67906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY72_MASK 0x000F /* WSEQ_DELAY72 - [3:0] */ 67916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY72_SHIFT 0 /* WSEQ_DELAY72 - [3:0] */ 67926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY72_WIDTH 4 /* WSEQ_DELAY72 - [3:0] */ 67936a504a75SDimitris Papastamos 67946a504a75SDimitris Papastamos /* 67956a504a75SDimitris Papastamos * R12580 (0x3124) - Write Sequencer 292 67966a504a75SDimitris Papastamos */ 67976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR73_MASK 0x3FFF /* WSEQ_ADDR73 - [13:0] */ 67986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR73_SHIFT 0 /* WSEQ_ADDR73 - [13:0] */ 67996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR73_WIDTH 14 /* WSEQ_ADDR73 - [13:0] */ 68006a504a75SDimitris Papastamos 68016a504a75SDimitris Papastamos /* 68026a504a75SDimitris Papastamos * R12581 (0x3125) - Write Sequencer 293 68036a504a75SDimitris Papastamos */ 68046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA73_MASK 0x00FF /* WSEQ_DATA73 - [7:0] */ 68056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA73_SHIFT 0 /* WSEQ_DATA73 - [7:0] */ 68066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA73_WIDTH 8 /* WSEQ_DATA73 - [7:0] */ 68076a504a75SDimitris Papastamos 68086a504a75SDimitris Papastamos /* 68096a504a75SDimitris Papastamos * R12582 (0x3126) - Write Sequencer 294 68106a504a75SDimitris Papastamos */ 68116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH73_MASK 0x0700 /* WSEQ_DATA_WIDTH73 - [10:8] */ 68126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH73_SHIFT 8 /* WSEQ_DATA_WIDTH73 - [10:8] */ 68136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH73_WIDTH 3 /* WSEQ_DATA_WIDTH73 - [10:8] */ 68146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START73_MASK 0x000F /* WSEQ_DATA_START73 - [3:0] */ 68156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START73_SHIFT 0 /* WSEQ_DATA_START73 - [3:0] */ 68166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START73_WIDTH 4 /* WSEQ_DATA_START73 - [3:0] */ 68176a504a75SDimitris Papastamos 68186a504a75SDimitris Papastamos /* 68196a504a75SDimitris Papastamos * R12583 (0x3127) - Write Sequencer 295 68206a504a75SDimitris Papastamos */ 68216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS73 0x0100 /* WSEQ_EOS73 */ 68226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS73_MASK 0x0100 /* WSEQ_EOS73 */ 68236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS73_SHIFT 8 /* WSEQ_EOS73 */ 68246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS73_WIDTH 1 /* WSEQ_EOS73 */ 68256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY73_MASK 0x000F /* WSEQ_DELAY73 - [3:0] */ 68266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY73_SHIFT 0 /* WSEQ_DELAY73 - [3:0] */ 68276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY73_WIDTH 4 /* WSEQ_DELAY73 - [3:0] */ 68286a504a75SDimitris Papastamos 68296a504a75SDimitris Papastamos /* 68306a504a75SDimitris Papastamos * R12584 (0x3128) - Write Sequencer 296 68316a504a75SDimitris Papastamos */ 68326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR74_MASK 0x3FFF /* WSEQ_ADDR74 - [13:0] */ 68336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR74_SHIFT 0 /* WSEQ_ADDR74 - [13:0] */ 68346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR74_WIDTH 14 /* WSEQ_ADDR74 - [13:0] */ 68356a504a75SDimitris Papastamos 68366a504a75SDimitris Papastamos /* 68376a504a75SDimitris Papastamos * R12585 (0x3129) - Write Sequencer 297 68386a504a75SDimitris Papastamos */ 68396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA74_MASK 0x00FF /* WSEQ_DATA74 - [7:0] */ 68406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA74_SHIFT 0 /* WSEQ_DATA74 - [7:0] */ 68416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA74_WIDTH 8 /* WSEQ_DATA74 - [7:0] */ 68426a504a75SDimitris Papastamos 68436a504a75SDimitris Papastamos /* 68446a504a75SDimitris Papastamos * R12586 (0x312A) - Write Sequencer 298 68456a504a75SDimitris Papastamos */ 68466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH74_MASK 0x0700 /* WSEQ_DATA_WIDTH74 - [10:8] */ 68476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH74_SHIFT 8 /* WSEQ_DATA_WIDTH74 - [10:8] */ 68486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH74_WIDTH 3 /* WSEQ_DATA_WIDTH74 - [10:8] */ 68496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START74_MASK 0x000F /* WSEQ_DATA_START74 - [3:0] */ 68506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START74_SHIFT 0 /* WSEQ_DATA_START74 - [3:0] */ 68516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START74_WIDTH 4 /* WSEQ_DATA_START74 - [3:0] */ 68526a504a75SDimitris Papastamos 68536a504a75SDimitris Papastamos /* 68546a504a75SDimitris Papastamos * R12587 (0x312B) - Write Sequencer 299 68556a504a75SDimitris Papastamos */ 68566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS74 0x0100 /* WSEQ_EOS74 */ 68576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS74_MASK 0x0100 /* WSEQ_EOS74 */ 68586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS74_SHIFT 8 /* WSEQ_EOS74 */ 68596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS74_WIDTH 1 /* WSEQ_EOS74 */ 68606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY74_MASK 0x000F /* WSEQ_DELAY74 - [3:0] */ 68616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY74_SHIFT 0 /* WSEQ_DELAY74 - [3:0] */ 68626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY74_WIDTH 4 /* WSEQ_DELAY74 - [3:0] */ 68636a504a75SDimitris Papastamos 68646a504a75SDimitris Papastamos /* 68656a504a75SDimitris Papastamos * R12588 (0x312C) - Write Sequencer 300 68666a504a75SDimitris Papastamos */ 68676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR75_MASK 0x3FFF /* WSEQ_ADDR75 - [13:0] */ 68686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR75_SHIFT 0 /* WSEQ_ADDR75 - [13:0] */ 68696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR75_WIDTH 14 /* WSEQ_ADDR75 - [13:0] */ 68706a504a75SDimitris Papastamos 68716a504a75SDimitris Papastamos /* 68726a504a75SDimitris Papastamos * R12589 (0x312D) - Write Sequencer 301 68736a504a75SDimitris Papastamos */ 68746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA75_MASK 0x00FF /* WSEQ_DATA75 - [7:0] */ 68756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA75_SHIFT 0 /* WSEQ_DATA75 - [7:0] */ 68766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA75_WIDTH 8 /* WSEQ_DATA75 - [7:0] */ 68776a504a75SDimitris Papastamos 68786a504a75SDimitris Papastamos /* 68796a504a75SDimitris Papastamos * R12590 (0x312E) - Write Sequencer 302 68806a504a75SDimitris Papastamos */ 68816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH75_MASK 0x0700 /* WSEQ_DATA_WIDTH75 - [10:8] */ 68826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH75_SHIFT 8 /* WSEQ_DATA_WIDTH75 - [10:8] */ 68836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH75_WIDTH 3 /* WSEQ_DATA_WIDTH75 - [10:8] */ 68846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START75_MASK 0x000F /* WSEQ_DATA_START75 - [3:0] */ 68856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START75_SHIFT 0 /* WSEQ_DATA_START75 - [3:0] */ 68866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START75_WIDTH 4 /* WSEQ_DATA_START75 - [3:0] */ 68876a504a75SDimitris Papastamos 68886a504a75SDimitris Papastamos /* 68896a504a75SDimitris Papastamos * R12591 (0x312F) - Write Sequencer 303 68906a504a75SDimitris Papastamos */ 68916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS75 0x0100 /* WSEQ_EOS75 */ 68926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS75_MASK 0x0100 /* WSEQ_EOS75 */ 68936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS75_SHIFT 8 /* WSEQ_EOS75 */ 68946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS75_WIDTH 1 /* WSEQ_EOS75 */ 68956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY75_MASK 0x000F /* WSEQ_DELAY75 - [3:0] */ 68966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY75_SHIFT 0 /* WSEQ_DELAY75 - [3:0] */ 68976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY75_WIDTH 4 /* WSEQ_DELAY75 - [3:0] */ 68986a504a75SDimitris Papastamos 68996a504a75SDimitris Papastamos /* 69006a504a75SDimitris Papastamos * R12592 (0x3130) - Write Sequencer 304 69016a504a75SDimitris Papastamos */ 69026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR76_MASK 0x3FFF /* WSEQ_ADDR76 - [13:0] */ 69036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR76_SHIFT 0 /* WSEQ_ADDR76 - [13:0] */ 69046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR76_WIDTH 14 /* WSEQ_ADDR76 - [13:0] */ 69056a504a75SDimitris Papastamos 69066a504a75SDimitris Papastamos /* 69076a504a75SDimitris Papastamos * R12593 (0x3131) - Write Sequencer 305 69086a504a75SDimitris Papastamos */ 69096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA76_MASK 0x00FF /* WSEQ_DATA76 - [7:0] */ 69106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA76_SHIFT 0 /* WSEQ_DATA76 - [7:0] */ 69116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA76_WIDTH 8 /* WSEQ_DATA76 - [7:0] */ 69126a504a75SDimitris Papastamos 69136a504a75SDimitris Papastamos /* 69146a504a75SDimitris Papastamos * R12594 (0x3132) - Write Sequencer 306 69156a504a75SDimitris Papastamos */ 69166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH76_MASK 0x0700 /* WSEQ_DATA_WIDTH76 - [10:8] */ 69176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH76_SHIFT 8 /* WSEQ_DATA_WIDTH76 - [10:8] */ 69186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH76_WIDTH 3 /* WSEQ_DATA_WIDTH76 - [10:8] */ 69196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START76_MASK 0x000F /* WSEQ_DATA_START76 - [3:0] */ 69206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START76_SHIFT 0 /* WSEQ_DATA_START76 - [3:0] */ 69216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START76_WIDTH 4 /* WSEQ_DATA_START76 - [3:0] */ 69226a504a75SDimitris Papastamos 69236a504a75SDimitris Papastamos /* 69246a504a75SDimitris Papastamos * R12595 (0x3133) - Write Sequencer 307 69256a504a75SDimitris Papastamos */ 69266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS76 0x0100 /* WSEQ_EOS76 */ 69276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS76_MASK 0x0100 /* WSEQ_EOS76 */ 69286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS76_SHIFT 8 /* WSEQ_EOS76 */ 69296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS76_WIDTH 1 /* WSEQ_EOS76 */ 69306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY76_MASK 0x000F /* WSEQ_DELAY76 - [3:0] */ 69316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY76_SHIFT 0 /* WSEQ_DELAY76 - [3:0] */ 69326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY76_WIDTH 4 /* WSEQ_DELAY76 - [3:0] */ 69336a504a75SDimitris Papastamos 69346a504a75SDimitris Papastamos /* 69356a504a75SDimitris Papastamos * R12596 (0x3134) - Write Sequencer 308 69366a504a75SDimitris Papastamos */ 69376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR77_MASK 0x3FFF /* WSEQ_ADDR77 - [13:0] */ 69386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR77_SHIFT 0 /* WSEQ_ADDR77 - [13:0] */ 69396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR77_WIDTH 14 /* WSEQ_ADDR77 - [13:0] */ 69406a504a75SDimitris Papastamos 69416a504a75SDimitris Papastamos /* 69426a504a75SDimitris Papastamos * R12597 (0x3135) - Write Sequencer 309 69436a504a75SDimitris Papastamos */ 69446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA77_MASK 0x00FF /* WSEQ_DATA77 - [7:0] */ 69456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA77_SHIFT 0 /* WSEQ_DATA77 - [7:0] */ 69466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA77_WIDTH 8 /* WSEQ_DATA77 - [7:0] */ 69476a504a75SDimitris Papastamos 69486a504a75SDimitris Papastamos /* 69496a504a75SDimitris Papastamos * R12598 (0x3136) - Write Sequencer 310 69506a504a75SDimitris Papastamos */ 69516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH77_MASK 0x0700 /* WSEQ_DATA_WIDTH77 - [10:8] */ 69526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH77_SHIFT 8 /* WSEQ_DATA_WIDTH77 - [10:8] */ 69536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH77_WIDTH 3 /* WSEQ_DATA_WIDTH77 - [10:8] */ 69546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START77_MASK 0x000F /* WSEQ_DATA_START77 - [3:0] */ 69556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START77_SHIFT 0 /* WSEQ_DATA_START77 - [3:0] */ 69566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START77_WIDTH 4 /* WSEQ_DATA_START77 - [3:0] */ 69576a504a75SDimitris Papastamos 69586a504a75SDimitris Papastamos /* 69596a504a75SDimitris Papastamos * R12599 (0x3137) - Write Sequencer 311 69606a504a75SDimitris Papastamos */ 69616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS77 0x0100 /* WSEQ_EOS77 */ 69626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS77_MASK 0x0100 /* WSEQ_EOS77 */ 69636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS77_SHIFT 8 /* WSEQ_EOS77 */ 69646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS77_WIDTH 1 /* WSEQ_EOS77 */ 69656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY77_MASK 0x000F /* WSEQ_DELAY77 - [3:0] */ 69666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY77_SHIFT 0 /* WSEQ_DELAY77 - [3:0] */ 69676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY77_WIDTH 4 /* WSEQ_DELAY77 - [3:0] */ 69686a504a75SDimitris Papastamos 69696a504a75SDimitris Papastamos /* 69706a504a75SDimitris Papastamos * R12600 (0x3138) - Write Sequencer 312 69716a504a75SDimitris Papastamos */ 69726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR78_MASK 0x3FFF /* WSEQ_ADDR78 - [13:0] */ 69736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR78_SHIFT 0 /* WSEQ_ADDR78 - [13:0] */ 69746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR78_WIDTH 14 /* WSEQ_ADDR78 - [13:0] */ 69756a504a75SDimitris Papastamos 69766a504a75SDimitris Papastamos /* 69776a504a75SDimitris Papastamos * R12601 (0x3139) - Write Sequencer 313 69786a504a75SDimitris Papastamos */ 69796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA78_MASK 0x00FF /* WSEQ_DATA78 - [7:0] */ 69806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA78_SHIFT 0 /* WSEQ_DATA78 - [7:0] */ 69816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA78_WIDTH 8 /* WSEQ_DATA78 - [7:0] */ 69826a504a75SDimitris Papastamos 69836a504a75SDimitris Papastamos /* 69846a504a75SDimitris Papastamos * R12602 (0x313A) - Write Sequencer 314 69856a504a75SDimitris Papastamos */ 69866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH78_MASK 0x0700 /* WSEQ_DATA_WIDTH78 - [10:8] */ 69876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH78_SHIFT 8 /* WSEQ_DATA_WIDTH78 - [10:8] */ 69886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH78_WIDTH 3 /* WSEQ_DATA_WIDTH78 - [10:8] */ 69896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START78_MASK 0x000F /* WSEQ_DATA_START78 - [3:0] */ 69906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START78_SHIFT 0 /* WSEQ_DATA_START78 - [3:0] */ 69916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START78_WIDTH 4 /* WSEQ_DATA_START78 - [3:0] */ 69926a504a75SDimitris Papastamos 69936a504a75SDimitris Papastamos /* 69946a504a75SDimitris Papastamos * R12603 (0x313B) - Write Sequencer 315 69956a504a75SDimitris Papastamos */ 69966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS78 0x0100 /* WSEQ_EOS78 */ 69976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS78_MASK 0x0100 /* WSEQ_EOS78 */ 69986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS78_SHIFT 8 /* WSEQ_EOS78 */ 69996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS78_WIDTH 1 /* WSEQ_EOS78 */ 70006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY78_MASK 0x000F /* WSEQ_DELAY78 - [3:0] */ 70016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY78_SHIFT 0 /* WSEQ_DELAY78 - [3:0] */ 70026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY78_WIDTH 4 /* WSEQ_DELAY78 - [3:0] */ 70036a504a75SDimitris Papastamos 70046a504a75SDimitris Papastamos /* 70056a504a75SDimitris Papastamos * R12604 (0x313C) - Write Sequencer 316 70066a504a75SDimitris Papastamos */ 70076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR79_MASK 0x3FFF /* WSEQ_ADDR79 - [13:0] */ 70086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR79_SHIFT 0 /* WSEQ_ADDR79 - [13:0] */ 70096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR79_WIDTH 14 /* WSEQ_ADDR79 - [13:0] */ 70106a504a75SDimitris Papastamos 70116a504a75SDimitris Papastamos /* 70126a504a75SDimitris Papastamos * R12605 (0x313D) - Write Sequencer 317 70136a504a75SDimitris Papastamos */ 70146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA79_MASK 0x00FF /* WSEQ_DATA79 - [7:0] */ 70156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA79_SHIFT 0 /* WSEQ_DATA79 - [7:0] */ 70166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA79_WIDTH 8 /* WSEQ_DATA79 - [7:0] */ 70176a504a75SDimitris Papastamos 70186a504a75SDimitris Papastamos /* 70196a504a75SDimitris Papastamos * R12606 (0x313E) - Write Sequencer 318 70206a504a75SDimitris Papastamos */ 70216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH79_MASK 0x0700 /* WSEQ_DATA_WIDTH79 - [10:8] */ 70226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH79_SHIFT 8 /* WSEQ_DATA_WIDTH79 - [10:8] */ 70236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH79_WIDTH 3 /* WSEQ_DATA_WIDTH79 - [10:8] */ 70246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START79_MASK 0x000F /* WSEQ_DATA_START79 - [3:0] */ 70256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START79_SHIFT 0 /* WSEQ_DATA_START79 - [3:0] */ 70266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START79_WIDTH 4 /* WSEQ_DATA_START79 - [3:0] */ 70276a504a75SDimitris Papastamos 70286a504a75SDimitris Papastamos /* 70296a504a75SDimitris Papastamos * R12607 (0x313F) - Write Sequencer 319 70306a504a75SDimitris Papastamos */ 70316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS79 0x0100 /* WSEQ_EOS79 */ 70326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS79_MASK 0x0100 /* WSEQ_EOS79 */ 70336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS79_SHIFT 8 /* WSEQ_EOS79 */ 70346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS79_WIDTH 1 /* WSEQ_EOS79 */ 70356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY79_MASK 0x000F /* WSEQ_DELAY79 - [3:0] */ 70366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY79_SHIFT 0 /* WSEQ_DELAY79 - [3:0] */ 70376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY79_WIDTH 4 /* WSEQ_DELAY79 - [3:0] */ 70386a504a75SDimitris Papastamos 70396a504a75SDimitris Papastamos /* 70406a504a75SDimitris Papastamos * R12608 (0x3140) - Write Sequencer 320 70416a504a75SDimitris Papastamos */ 70426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR80_MASK 0x3FFF /* WSEQ_ADDR80 - [13:0] */ 70436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR80_SHIFT 0 /* WSEQ_ADDR80 - [13:0] */ 70446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR80_WIDTH 14 /* WSEQ_ADDR80 - [13:0] */ 70456a504a75SDimitris Papastamos 70466a504a75SDimitris Papastamos /* 70476a504a75SDimitris Papastamos * R12609 (0x3141) - Write Sequencer 321 70486a504a75SDimitris Papastamos */ 70496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA80_MASK 0x00FF /* WSEQ_DATA80 - [7:0] */ 70506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA80_SHIFT 0 /* WSEQ_DATA80 - [7:0] */ 70516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA80_WIDTH 8 /* WSEQ_DATA80 - [7:0] */ 70526a504a75SDimitris Papastamos 70536a504a75SDimitris Papastamos /* 70546a504a75SDimitris Papastamos * R12610 (0x3142) - Write Sequencer 322 70556a504a75SDimitris Papastamos */ 70566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH80_MASK 0x0700 /* WSEQ_DATA_WIDTH80 - [10:8] */ 70576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH80_SHIFT 8 /* WSEQ_DATA_WIDTH80 - [10:8] */ 70586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH80_WIDTH 3 /* WSEQ_DATA_WIDTH80 - [10:8] */ 70596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START80_MASK 0x000F /* WSEQ_DATA_START80 - [3:0] */ 70606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START80_SHIFT 0 /* WSEQ_DATA_START80 - [3:0] */ 70616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START80_WIDTH 4 /* WSEQ_DATA_START80 - [3:0] */ 70626a504a75SDimitris Papastamos 70636a504a75SDimitris Papastamos /* 70646a504a75SDimitris Papastamos * R12611 (0x3143) - Write Sequencer 323 70656a504a75SDimitris Papastamos */ 70666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS80 0x0100 /* WSEQ_EOS80 */ 70676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS80_MASK 0x0100 /* WSEQ_EOS80 */ 70686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS80_SHIFT 8 /* WSEQ_EOS80 */ 70696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS80_WIDTH 1 /* WSEQ_EOS80 */ 70706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY80_MASK 0x000F /* WSEQ_DELAY80 - [3:0] */ 70716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY80_SHIFT 0 /* WSEQ_DELAY80 - [3:0] */ 70726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY80_WIDTH 4 /* WSEQ_DELAY80 - [3:0] */ 70736a504a75SDimitris Papastamos 70746a504a75SDimitris Papastamos /* 70756a504a75SDimitris Papastamos * R12612 (0x3144) - Write Sequencer 324 70766a504a75SDimitris Papastamos */ 70776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR81_MASK 0x3FFF /* WSEQ_ADDR81 - [13:0] */ 70786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR81_SHIFT 0 /* WSEQ_ADDR81 - [13:0] */ 70796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR81_WIDTH 14 /* WSEQ_ADDR81 - [13:0] */ 70806a504a75SDimitris Papastamos 70816a504a75SDimitris Papastamos /* 70826a504a75SDimitris Papastamos * R12613 (0x3145) - Write Sequencer 325 70836a504a75SDimitris Papastamos */ 70846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA81_MASK 0x00FF /* WSEQ_DATA81 - [7:0] */ 70856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA81_SHIFT 0 /* WSEQ_DATA81 - [7:0] */ 70866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA81_WIDTH 8 /* WSEQ_DATA81 - [7:0] */ 70876a504a75SDimitris Papastamos 70886a504a75SDimitris Papastamos /* 70896a504a75SDimitris Papastamos * R12614 (0x3146) - Write Sequencer 326 70906a504a75SDimitris Papastamos */ 70916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH81_MASK 0x0700 /* WSEQ_DATA_WIDTH81 - [10:8] */ 70926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH81_SHIFT 8 /* WSEQ_DATA_WIDTH81 - [10:8] */ 70936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH81_WIDTH 3 /* WSEQ_DATA_WIDTH81 - [10:8] */ 70946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START81_MASK 0x000F /* WSEQ_DATA_START81 - [3:0] */ 70956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START81_SHIFT 0 /* WSEQ_DATA_START81 - [3:0] */ 70966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START81_WIDTH 4 /* WSEQ_DATA_START81 - [3:0] */ 70976a504a75SDimitris Papastamos 70986a504a75SDimitris Papastamos /* 70996a504a75SDimitris Papastamos * R12615 (0x3147) - Write Sequencer 327 71006a504a75SDimitris Papastamos */ 71016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS81 0x0100 /* WSEQ_EOS81 */ 71026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS81_MASK 0x0100 /* WSEQ_EOS81 */ 71036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS81_SHIFT 8 /* WSEQ_EOS81 */ 71046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS81_WIDTH 1 /* WSEQ_EOS81 */ 71056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY81_MASK 0x000F /* WSEQ_DELAY81 - [3:0] */ 71066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY81_SHIFT 0 /* WSEQ_DELAY81 - [3:0] */ 71076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY81_WIDTH 4 /* WSEQ_DELAY81 - [3:0] */ 71086a504a75SDimitris Papastamos 71096a504a75SDimitris Papastamos /* 71106a504a75SDimitris Papastamos * R12616 (0x3148) - Write Sequencer 328 71116a504a75SDimitris Papastamos */ 71126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR82_MASK 0x3FFF /* WSEQ_ADDR82 - [13:0] */ 71136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR82_SHIFT 0 /* WSEQ_ADDR82 - [13:0] */ 71146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR82_WIDTH 14 /* WSEQ_ADDR82 - [13:0] */ 71156a504a75SDimitris Papastamos 71166a504a75SDimitris Papastamos /* 71176a504a75SDimitris Papastamos * R12617 (0x3149) - Write Sequencer 329 71186a504a75SDimitris Papastamos */ 71196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA82_MASK 0x00FF /* WSEQ_DATA82 - [7:0] */ 71206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA82_SHIFT 0 /* WSEQ_DATA82 - [7:0] */ 71216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA82_WIDTH 8 /* WSEQ_DATA82 - [7:0] */ 71226a504a75SDimitris Papastamos 71236a504a75SDimitris Papastamos /* 71246a504a75SDimitris Papastamos * R12618 (0x314A) - Write Sequencer 330 71256a504a75SDimitris Papastamos */ 71266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH82_MASK 0x0700 /* WSEQ_DATA_WIDTH82 - [10:8] */ 71276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH82_SHIFT 8 /* WSEQ_DATA_WIDTH82 - [10:8] */ 71286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH82_WIDTH 3 /* WSEQ_DATA_WIDTH82 - [10:8] */ 71296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START82_MASK 0x000F /* WSEQ_DATA_START82 - [3:0] */ 71306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START82_SHIFT 0 /* WSEQ_DATA_START82 - [3:0] */ 71316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START82_WIDTH 4 /* WSEQ_DATA_START82 - [3:0] */ 71326a504a75SDimitris Papastamos 71336a504a75SDimitris Papastamos /* 71346a504a75SDimitris Papastamos * R12619 (0x314B) - Write Sequencer 331 71356a504a75SDimitris Papastamos */ 71366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS82 0x0100 /* WSEQ_EOS82 */ 71376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS82_MASK 0x0100 /* WSEQ_EOS82 */ 71386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS82_SHIFT 8 /* WSEQ_EOS82 */ 71396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS82_WIDTH 1 /* WSEQ_EOS82 */ 71406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY82_MASK 0x000F /* WSEQ_DELAY82 - [3:0] */ 71416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY82_SHIFT 0 /* WSEQ_DELAY82 - [3:0] */ 71426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY82_WIDTH 4 /* WSEQ_DELAY82 - [3:0] */ 71436a504a75SDimitris Papastamos 71446a504a75SDimitris Papastamos /* 71456a504a75SDimitris Papastamos * R12620 (0x314C) - Write Sequencer 332 71466a504a75SDimitris Papastamos */ 71476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR83_MASK 0x3FFF /* WSEQ_ADDR83 - [13:0] */ 71486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR83_SHIFT 0 /* WSEQ_ADDR83 - [13:0] */ 71496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR83_WIDTH 14 /* WSEQ_ADDR83 - [13:0] */ 71506a504a75SDimitris Papastamos 71516a504a75SDimitris Papastamos /* 71526a504a75SDimitris Papastamos * R12621 (0x314D) - Write Sequencer 333 71536a504a75SDimitris Papastamos */ 71546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA83_MASK 0x00FF /* WSEQ_DATA83 - [7:0] */ 71556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA83_SHIFT 0 /* WSEQ_DATA83 - [7:0] */ 71566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA83_WIDTH 8 /* WSEQ_DATA83 - [7:0] */ 71576a504a75SDimitris Papastamos 71586a504a75SDimitris Papastamos /* 71596a504a75SDimitris Papastamos * R12622 (0x314E) - Write Sequencer 334 71606a504a75SDimitris Papastamos */ 71616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH83_MASK 0x0700 /* WSEQ_DATA_WIDTH83 - [10:8] */ 71626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH83_SHIFT 8 /* WSEQ_DATA_WIDTH83 - [10:8] */ 71636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH83_WIDTH 3 /* WSEQ_DATA_WIDTH83 - [10:8] */ 71646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START83_MASK 0x000F /* WSEQ_DATA_START83 - [3:0] */ 71656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START83_SHIFT 0 /* WSEQ_DATA_START83 - [3:0] */ 71666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START83_WIDTH 4 /* WSEQ_DATA_START83 - [3:0] */ 71676a504a75SDimitris Papastamos 71686a504a75SDimitris Papastamos /* 71696a504a75SDimitris Papastamos * R12623 (0x314F) - Write Sequencer 335 71706a504a75SDimitris Papastamos */ 71716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS83 0x0100 /* WSEQ_EOS83 */ 71726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS83_MASK 0x0100 /* WSEQ_EOS83 */ 71736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS83_SHIFT 8 /* WSEQ_EOS83 */ 71746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS83_WIDTH 1 /* WSEQ_EOS83 */ 71756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY83_MASK 0x000F /* WSEQ_DELAY83 - [3:0] */ 71766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY83_SHIFT 0 /* WSEQ_DELAY83 - [3:0] */ 71776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY83_WIDTH 4 /* WSEQ_DELAY83 - [3:0] */ 71786a504a75SDimitris Papastamos 71796a504a75SDimitris Papastamos /* 71806a504a75SDimitris Papastamos * R12624 (0x3150) - Write Sequencer 336 71816a504a75SDimitris Papastamos */ 71826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR84_MASK 0x3FFF /* WSEQ_ADDR84 - [13:0] */ 71836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR84_SHIFT 0 /* WSEQ_ADDR84 - [13:0] */ 71846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR84_WIDTH 14 /* WSEQ_ADDR84 - [13:0] */ 71856a504a75SDimitris Papastamos 71866a504a75SDimitris Papastamos /* 71876a504a75SDimitris Papastamos * R12625 (0x3151) - Write Sequencer 337 71886a504a75SDimitris Papastamos */ 71896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA84_MASK 0x00FF /* WSEQ_DATA84 - [7:0] */ 71906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA84_SHIFT 0 /* WSEQ_DATA84 - [7:0] */ 71916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA84_WIDTH 8 /* WSEQ_DATA84 - [7:0] */ 71926a504a75SDimitris Papastamos 71936a504a75SDimitris Papastamos /* 71946a504a75SDimitris Papastamos * R12626 (0x3152) - Write Sequencer 338 71956a504a75SDimitris Papastamos */ 71966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH84_MASK 0x0700 /* WSEQ_DATA_WIDTH84 - [10:8] */ 71976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH84_SHIFT 8 /* WSEQ_DATA_WIDTH84 - [10:8] */ 71986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH84_WIDTH 3 /* WSEQ_DATA_WIDTH84 - [10:8] */ 71996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START84_MASK 0x000F /* WSEQ_DATA_START84 - [3:0] */ 72006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START84_SHIFT 0 /* WSEQ_DATA_START84 - [3:0] */ 72016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START84_WIDTH 4 /* WSEQ_DATA_START84 - [3:0] */ 72026a504a75SDimitris Papastamos 72036a504a75SDimitris Papastamos /* 72046a504a75SDimitris Papastamos * R12627 (0x3153) - Write Sequencer 339 72056a504a75SDimitris Papastamos */ 72066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS84 0x0100 /* WSEQ_EOS84 */ 72076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS84_MASK 0x0100 /* WSEQ_EOS84 */ 72086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS84_SHIFT 8 /* WSEQ_EOS84 */ 72096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS84_WIDTH 1 /* WSEQ_EOS84 */ 72106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY84_MASK 0x000F /* WSEQ_DELAY84 - [3:0] */ 72116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY84_SHIFT 0 /* WSEQ_DELAY84 - [3:0] */ 72126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY84_WIDTH 4 /* WSEQ_DELAY84 - [3:0] */ 72136a504a75SDimitris Papastamos 72146a504a75SDimitris Papastamos /* 72156a504a75SDimitris Papastamos * R12628 (0x3154) - Write Sequencer 340 72166a504a75SDimitris Papastamos */ 72176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR85_MASK 0x3FFF /* WSEQ_ADDR85 - [13:0] */ 72186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR85_SHIFT 0 /* WSEQ_ADDR85 - [13:0] */ 72196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR85_WIDTH 14 /* WSEQ_ADDR85 - [13:0] */ 72206a504a75SDimitris Papastamos 72216a504a75SDimitris Papastamos /* 72226a504a75SDimitris Papastamos * R12629 (0x3155) - Write Sequencer 341 72236a504a75SDimitris Papastamos */ 72246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA85_MASK 0x00FF /* WSEQ_DATA85 - [7:0] */ 72256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA85_SHIFT 0 /* WSEQ_DATA85 - [7:0] */ 72266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA85_WIDTH 8 /* WSEQ_DATA85 - [7:0] */ 72276a504a75SDimitris Papastamos 72286a504a75SDimitris Papastamos /* 72296a504a75SDimitris Papastamos * R12630 (0x3156) - Write Sequencer 342 72306a504a75SDimitris Papastamos */ 72316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH85_MASK 0x0700 /* WSEQ_DATA_WIDTH85 - [10:8] */ 72326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH85_SHIFT 8 /* WSEQ_DATA_WIDTH85 - [10:8] */ 72336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH85_WIDTH 3 /* WSEQ_DATA_WIDTH85 - [10:8] */ 72346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START85_MASK 0x000F /* WSEQ_DATA_START85 - [3:0] */ 72356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START85_SHIFT 0 /* WSEQ_DATA_START85 - [3:0] */ 72366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START85_WIDTH 4 /* WSEQ_DATA_START85 - [3:0] */ 72376a504a75SDimitris Papastamos 72386a504a75SDimitris Papastamos /* 72396a504a75SDimitris Papastamos * R12631 (0x3157) - Write Sequencer 343 72406a504a75SDimitris Papastamos */ 72416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS85 0x0100 /* WSEQ_EOS85 */ 72426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS85_MASK 0x0100 /* WSEQ_EOS85 */ 72436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS85_SHIFT 8 /* WSEQ_EOS85 */ 72446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS85_WIDTH 1 /* WSEQ_EOS85 */ 72456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY85_MASK 0x000F /* WSEQ_DELAY85 - [3:0] */ 72466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY85_SHIFT 0 /* WSEQ_DELAY85 - [3:0] */ 72476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY85_WIDTH 4 /* WSEQ_DELAY85 - [3:0] */ 72486a504a75SDimitris Papastamos 72496a504a75SDimitris Papastamos /* 72506a504a75SDimitris Papastamos * R12632 (0x3158) - Write Sequencer 344 72516a504a75SDimitris Papastamos */ 72526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR86_MASK 0x3FFF /* WSEQ_ADDR86 - [13:0] */ 72536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR86_SHIFT 0 /* WSEQ_ADDR86 - [13:0] */ 72546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR86_WIDTH 14 /* WSEQ_ADDR86 - [13:0] */ 72556a504a75SDimitris Papastamos 72566a504a75SDimitris Papastamos /* 72576a504a75SDimitris Papastamos * R12633 (0x3159) - Write Sequencer 345 72586a504a75SDimitris Papastamos */ 72596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA86_MASK 0x00FF /* WSEQ_DATA86 - [7:0] */ 72606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA86_SHIFT 0 /* WSEQ_DATA86 - [7:0] */ 72616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA86_WIDTH 8 /* WSEQ_DATA86 - [7:0] */ 72626a504a75SDimitris Papastamos 72636a504a75SDimitris Papastamos /* 72646a504a75SDimitris Papastamos * R12634 (0x315A) - Write Sequencer 346 72656a504a75SDimitris Papastamos */ 72666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH86_MASK 0x0700 /* WSEQ_DATA_WIDTH86 - [10:8] */ 72676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH86_SHIFT 8 /* WSEQ_DATA_WIDTH86 - [10:8] */ 72686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH86_WIDTH 3 /* WSEQ_DATA_WIDTH86 - [10:8] */ 72696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START86_MASK 0x000F /* WSEQ_DATA_START86 - [3:0] */ 72706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START86_SHIFT 0 /* WSEQ_DATA_START86 - [3:0] */ 72716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START86_WIDTH 4 /* WSEQ_DATA_START86 - [3:0] */ 72726a504a75SDimitris Papastamos 72736a504a75SDimitris Papastamos /* 72746a504a75SDimitris Papastamos * R12635 (0x315B) - Write Sequencer 347 72756a504a75SDimitris Papastamos */ 72766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS86 0x0100 /* WSEQ_EOS86 */ 72776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS86_MASK 0x0100 /* WSEQ_EOS86 */ 72786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS86_SHIFT 8 /* WSEQ_EOS86 */ 72796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS86_WIDTH 1 /* WSEQ_EOS86 */ 72806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY86_MASK 0x000F /* WSEQ_DELAY86 - [3:0] */ 72816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY86_SHIFT 0 /* WSEQ_DELAY86 - [3:0] */ 72826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY86_WIDTH 4 /* WSEQ_DELAY86 - [3:0] */ 72836a504a75SDimitris Papastamos 72846a504a75SDimitris Papastamos /* 72856a504a75SDimitris Papastamos * R12636 (0x315C) - Write Sequencer 348 72866a504a75SDimitris Papastamos */ 72876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR87_MASK 0x3FFF /* WSEQ_ADDR87 - [13:0] */ 72886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR87_SHIFT 0 /* WSEQ_ADDR87 - [13:0] */ 72896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR87_WIDTH 14 /* WSEQ_ADDR87 - [13:0] */ 72906a504a75SDimitris Papastamos 72916a504a75SDimitris Papastamos /* 72926a504a75SDimitris Papastamos * R12637 (0x315D) - Write Sequencer 349 72936a504a75SDimitris Papastamos */ 72946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA87_MASK 0x00FF /* WSEQ_DATA87 - [7:0] */ 72956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA87_SHIFT 0 /* WSEQ_DATA87 - [7:0] */ 72966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA87_WIDTH 8 /* WSEQ_DATA87 - [7:0] */ 72976a504a75SDimitris Papastamos 72986a504a75SDimitris Papastamos /* 72996a504a75SDimitris Papastamos * R12638 (0x315E) - Write Sequencer 350 73006a504a75SDimitris Papastamos */ 73016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH87_MASK 0x0700 /* WSEQ_DATA_WIDTH87 - [10:8] */ 73026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH87_SHIFT 8 /* WSEQ_DATA_WIDTH87 - [10:8] */ 73036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH87_WIDTH 3 /* WSEQ_DATA_WIDTH87 - [10:8] */ 73046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START87_MASK 0x000F /* WSEQ_DATA_START87 - [3:0] */ 73056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START87_SHIFT 0 /* WSEQ_DATA_START87 - [3:0] */ 73066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START87_WIDTH 4 /* WSEQ_DATA_START87 - [3:0] */ 73076a504a75SDimitris Papastamos 73086a504a75SDimitris Papastamos /* 73096a504a75SDimitris Papastamos * R12639 (0x315F) - Write Sequencer 351 73106a504a75SDimitris Papastamos */ 73116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS87 0x0100 /* WSEQ_EOS87 */ 73126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS87_MASK 0x0100 /* WSEQ_EOS87 */ 73136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS87_SHIFT 8 /* WSEQ_EOS87 */ 73146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS87_WIDTH 1 /* WSEQ_EOS87 */ 73156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY87_MASK 0x000F /* WSEQ_DELAY87 - [3:0] */ 73166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY87_SHIFT 0 /* WSEQ_DELAY87 - [3:0] */ 73176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY87_WIDTH 4 /* WSEQ_DELAY87 - [3:0] */ 73186a504a75SDimitris Papastamos 73196a504a75SDimitris Papastamos /* 73206a504a75SDimitris Papastamos * R12640 (0x3160) - Write Sequencer 352 73216a504a75SDimitris Papastamos */ 73226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR88_MASK 0x3FFF /* WSEQ_ADDR88 - [13:0] */ 73236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR88_SHIFT 0 /* WSEQ_ADDR88 - [13:0] */ 73246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR88_WIDTH 14 /* WSEQ_ADDR88 - [13:0] */ 73256a504a75SDimitris Papastamos 73266a504a75SDimitris Papastamos /* 73276a504a75SDimitris Papastamos * R12641 (0x3161) - Write Sequencer 353 73286a504a75SDimitris Papastamos */ 73296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA88_MASK 0x00FF /* WSEQ_DATA88 - [7:0] */ 73306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA88_SHIFT 0 /* WSEQ_DATA88 - [7:0] */ 73316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA88_WIDTH 8 /* WSEQ_DATA88 - [7:0] */ 73326a504a75SDimitris Papastamos 73336a504a75SDimitris Papastamos /* 73346a504a75SDimitris Papastamos * R12642 (0x3162) - Write Sequencer 354 73356a504a75SDimitris Papastamos */ 73366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH88_MASK 0x0700 /* WSEQ_DATA_WIDTH88 - [10:8] */ 73376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH88_SHIFT 8 /* WSEQ_DATA_WIDTH88 - [10:8] */ 73386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH88_WIDTH 3 /* WSEQ_DATA_WIDTH88 - [10:8] */ 73396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START88_MASK 0x000F /* WSEQ_DATA_START88 - [3:0] */ 73406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START88_SHIFT 0 /* WSEQ_DATA_START88 - [3:0] */ 73416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START88_WIDTH 4 /* WSEQ_DATA_START88 - [3:0] */ 73426a504a75SDimitris Papastamos 73436a504a75SDimitris Papastamos /* 73446a504a75SDimitris Papastamos * R12643 (0x3163) - Write Sequencer 355 73456a504a75SDimitris Papastamos */ 73466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS88 0x0100 /* WSEQ_EOS88 */ 73476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS88_MASK 0x0100 /* WSEQ_EOS88 */ 73486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS88_SHIFT 8 /* WSEQ_EOS88 */ 73496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS88_WIDTH 1 /* WSEQ_EOS88 */ 73506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY88_MASK 0x000F /* WSEQ_DELAY88 - [3:0] */ 73516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY88_SHIFT 0 /* WSEQ_DELAY88 - [3:0] */ 73526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY88_WIDTH 4 /* WSEQ_DELAY88 - [3:0] */ 73536a504a75SDimitris Papastamos 73546a504a75SDimitris Papastamos /* 73556a504a75SDimitris Papastamos * R12644 (0x3164) - Write Sequencer 356 73566a504a75SDimitris Papastamos */ 73576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR89_MASK 0x3FFF /* WSEQ_ADDR89 - [13:0] */ 73586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR89_SHIFT 0 /* WSEQ_ADDR89 - [13:0] */ 73596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR89_WIDTH 14 /* WSEQ_ADDR89 - [13:0] */ 73606a504a75SDimitris Papastamos 73616a504a75SDimitris Papastamos /* 73626a504a75SDimitris Papastamos * R12645 (0x3165) - Write Sequencer 357 73636a504a75SDimitris Papastamos */ 73646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA89_MASK 0x00FF /* WSEQ_DATA89 - [7:0] */ 73656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA89_SHIFT 0 /* WSEQ_DATA89 - [7:0] */ 73666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA89_WIDTH 8 /* WSEQ_DATA89 - [7:0] */ 73676a504a75SDimitris Papastamos 73686a504a75SDimitris Papastamos /* 73696a504a75SDimitris Papastamos * R12646 (0x3166) - Write Sequencer 358 73706a504a75SDimitris Papastamos */ 73716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH89_MASK 0x0700 /* WSEQ_DATA_WIDTH89 - [10:8] */ 73726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH89_SHIFT 8 /* WSEQ_DATA_WIDTH89 - [10:8] */ 73736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH89_WIDTH 3 /* WSEQ_DATA_WIDTH89 - [10:8] */ 73746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START89_MASK 0x000F /* WSEQ_DATA_START89 - [3:0] */ 73756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START89_SHIFT 0 /* WSEQ_DATA_START89 - [3:0] */ 73766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START89_WIDTH 4 /* WSEQ_DATA_START89 - [3:0] */ 73776a504a75SDimitris Papastamos 73786a504a75SDimitris Papastamos /* 73796a504a75SDimitris Papastamos * R12647 (0x3167) - Write Sequencer 359 73806a504a75SDimitris Papastamos */ 73816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS89 0x0100 /* WSEQ_EOS89 */ 73826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS89_MASK 0x0100 /* WSEQ_EOS89 */ 73836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS89_SHIFT 8 /* WSEQ_EOS89 */ 73846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS89_WIDTH 1 /* WSEQ_EOS89 */ 73856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY89_MASK 0x000F /* WSEQ_DELAY89 - [3:0] */ 73866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY89_SHIFT 0 /* WSEQ_DELAY89 - [3:0] */ 73876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY89_WIDTH 4 /* WSEQ_DELAY89 - [3:0] */ 73886a504a75SDimitris Papastamos 73896a504a75SDimitris Papastamos /* 73906a504a75SDimitris Papastamos * R12648 (0x3168) - Write Sequencer 360 73916a504a75SDimitris Papastamos */ 73926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR90_MASK 0x3FFF /* WSEQ_ADDR90 - [13:0] */ 73936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR90_SHIFT 0 /* WSEQ_ADDR90 - [13:0] */ 73946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR90_WIDTH 14 /* WSEQ_ADDR90 - [13:0] */ 73956a504a75SDimitris Papastamos 73966a504a75SDimitris Papastamos /* 73976a504a75SDimitris Papastamos * R12649 (0x3169) - Write Sequencer 361 73986a504a75SDimitris Papastamos */ 73996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA90_MASK 0x00FF /* WSEQ_DATA90 - [7:0] */ 74006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA90_SHIFT 0 /* WSEQ_DATA90 - [7:0] */ 74016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA90_WIDTH 8 /* WSEQ_DATA90 - [7:0] */ 74026a504a75SDimitris Papastamos 74036a504a75SDimitris Papastamos /* 74046a504a75SDimitris Papastamos * R12650 (0x316A) - Write Sequencer 362 74056a504a75SDimitris Papastamos */ 74066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH90_MASK 0x0700 /* WSEQ_DATA_WIDTH90 - [10:8] */ 74076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH90_SHIFT 8 /* WSEQ_DATA_WIDTH90 - [10:8] */ 74086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH90_WIDTH 3 /* WSEQ_DATA_WIDTH90 - [10:8] */ 74096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START90_MASK 0x000F /* WSEQ_DATA_START90 - [3:0] */ 74106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START90_SHIFT 0 /* WSEQ_DATA_START90 - [3:0] */ 74116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START90_WIDTH 4 /* WSEQ_DATA_START90 - [3:0] */ 74126a504a75SDimitris Papastamos 74136a504a75SDimitris Papastamos /* 74146a504a75SDimitris Papastamos * R12651 (0x316B) - Write Sequencer 363 74156a504a75SDimitris Papastamos */ 74166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS90 0x0100 /* WSEQ_EOS90 */ 74176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS90_MASK 0x0100 /* WSEQ_EOS90 */ 74186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS90_SHIFT 8 /* WSEQ_EOS90 */ 74196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS90_WIDTH 1 /* WSEQ_EOS90 */ 74206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY90_MASK 0x000F /* WSEQ_DELAY90 - [3:0] */ 74216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY90_SHIFT 0 /* WSEQ_DELAY90 - [3:0] */ 74226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY90_WIDTH 4 /* WSEQ_DELAY90 - [3:0] */ 74236a504a75SDimitris Papastamos 74246a504a75SDimitris Papastamos /* 74256a504a75SDimitris Papastamos * R12652 (0x316C) - Write Sequencer 364 74266a504a75SDimitris Papastamos */ 74276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR91_MASK 0x3FFF /* WSEQ_ADDR91 - [13:0] */ 74286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR91_SHIFT 0 /* WSEQ_ADDR91 - [13:0] */ 74296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR91_WIDTH 14 /* WSEQ_ADDR91 - [13:0] */ 74306a504a75SDimitris Papastamos 74316a504a75SDimitris Papastamos /* 74326a504a75SDimitris Papastamos * R12653 (0x316D) - Write Sequencer 365 74336a504a75SDimitris Papastamos */ 74346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA91_MASK 0x00FF /* WSEQ_DATA91 - [7:0] */ 74356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA91_SHIFT 0 /* WSEQ_DATA91 - [7:0] */ 74366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA91_WIDTH 8 /* WSEQ_DATA91 - [7:0] */ 74376a504a75SDimitris Papastamos 74386a504a75SDimitris Papastamos /* 74396a504a75SDimitris Papastamos * R12654 (0x316E) - Write Sequencer 366 74406a504a75SDimitris Papastamos */ 74416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH91_MASK 0x0700 /* WSEQ_DATA_WIDTH91 - [10:8] */ 74426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH91_SHIFT 8 /* WSEQ_DATA_WIDTH91 - [10:8] */ 74436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH91_WIDTH 3 /* WSEQ_DATA_WIDTH91 - [10:8] */ 74446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START91_MASK 0x000F /* WSEQ_DATA_START91 - [3:0] */ 74456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START91_SHIFT 0 /* WSEQ_DATA_START91 - [3:0] */ 74466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START91_WIDTH 4 /* WSEQ_DATA_START91 - [3:0] */ 74476a504a75SDimitris Papastamos 74486a504a75SDimitris Papastamos /* 74496a504a75SDimitris Papastamos * R12655 (0x316F) - Write Sequencer 367 74506a504a75SDimitris Papastamos */ 74516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS91 0x0100 /* WSEQ_EOS91 */ 74526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS91_MASK 0x0100 /* WSEQ_EOS91 */ 74536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS91_SHIFT 8 /* WSEQ_EOS91 */ 74546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS91_WIDTH 1 /* WSEQ_EOS91 */ 74556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY91_MASK 0x000F /* WSEQ_DELAY91 - [3:0] */ 74566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY91_SHIFT 0 /* WSEQ_DELAY91 - [3:0] */ 74576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY91_WIDTH 4 /* WSEQ_DELAY91 - [3:0] */ 74586a504a75SDimitris Papastamos 74596a504a75SDimitris Papastamos /* 74606a504a75SDimitris Papastamos * R12656 (0x3170) - Write Sequencer 368 74616a504a75SDimitris Papastamos */ 74626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR92_MASK 0x3FFF /* WSEQ_ADDR92 - [13:0] */ 74636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR92_SHIFT 0 /* WSEQ_ADDR92 - [13:0] */ 74646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR92_WIDTH 14 /* WSEQ_ADDR92 - [13:0] */ 74656a504a75SDimitris Papastamos 74666a504a75SDimitris Papastamos /* 74676a504a75SDimitris Papastamos * R12657 (0x3171) - Write Sequencer 369 74686a504a75SDimitris Papastamos */ 74696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA92_MASK 0x00FF /* WSEQ_DATA92 - [7:0] */ 74706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA92_SHIFT 0 /* WSEQ_DATA92 - [7:0] */ 74716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA92_WIDTH 8 /* WSEQ_DATA92 - [7:0] */ 74726a504a75SDimitris Papastamos 74736a504a75SDimitris Papastamos /* 74746a504a75SDimitris Papastamos * R12658 (0x3172) - Write Sequencer 370 74756a504a75SDimitris Papastamos */ 74766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH92_MASK 0x0700 /* WSEQ_DATA_WIDTH92 - [10:8] */ 74776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH92_SHIFT 8 /* WSEQ_DATA_WIDTH92 - [10:8] */ 74786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH92_WIDTH 3 /* WSEQ_DATA_WIDTH92 - [10:8] */ 74796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START92_MASK 0x000F /* WSEQ_DATA_START92 - [3:0] */ 74806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START92_SHIFT 0 /* WSEQ_DATA_START92 - [3:0] */ 74816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START92_WIDTH 4 /* WSEQ_DATA_START92 - [3:0] */ 74826a504a75SDimitris Papastamos 74836a504a75SDimitris Papastamos /* 74846a504a75SDimitris Papastamos * R12659 (0x3173) - Write Sequencer 371 74856a504a75SDimitris Papastamos */ 74866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS92 0x0100 /* WSEQ_EOS92 */ 74876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS92_MASK 0x0100 /* WSEQ_EOS92 */ 74886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS92_SHIFT 8 /* WSEQ_EOS92 */ 74896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS92_WIDTH 1 /* WSEQ_EOS92 */ 74906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY92_MASK 0x000F /* WSEQ_DELAY92 - [3:0] */ 74916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY92_SHIFT 0 /* WSEQ_DELAY92 - [3:0] */ 74926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY92_WIDTH 4 /* WSEQ_DELAY92 - [3:0] */ 74936a504a75SDimitris Papastamos 74946a504a75SDimitris Papastamos /* 74956a504a75SDimitris Papastamos * R12660 (0x3174) - Write Sequencer 372 74966a504a75SDimitris Papastamos */ 74976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR93_MASK 0x3FFF /* WSEQ_ADDR93 - [13:0] */ 74986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR93_SHIFT 0 /* WSEQ_ADDR93 - [13:0] */ 74996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR93_WIDTH 14 /* WSEQ_ADDR93 - [13:0] */ 75006a504a75SDimitris Papastamos 75016a504a75SDimitris Papastamos /* 75026a504a75SDimitris Papastamos * R12661 (0x3175) - Write Sequencer 373 75036a504a75SDimitris Papastamos */ 75046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA93_MASK 0x00FF /* WSEQ_DATA93 - [7:0] */ 75056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA93_SHIFT 0 /* WSEQ_DATA93 - [7:0] */ 75066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA93_WIDTH 8 /* WSEQ_DATA93 - [7:0] */ 75076a504a75SDimitris Papastamos 75086a504a75SDimitris Papastamos /* 75096a504a75SDimitris Papastamos * R12662 (0x3176) - Write Sequencer 374 75106a504a75SDimitris Papastamos */ 75116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH93_MASK 0x0700 /* WSEQ_DATA_WIDTH93 - [10:8] */ 75126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH93_SHIFT 8 /* WSEQ_DATA_WIDTH93 - [10:8] */ 75136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH93_WIDTH 3 /* WSEQ_DATA_WIDTH93 - [10:8] */ 75146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START93_MASK 0x000F /* WSEQ_DATA_START93 - [3:0] */ 75156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START93_SHIFT 0 /* WSEQ_DATA_START93 - [3:0] */ 75166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START93_WIDTH 4 /* WSEQ_DATA_START93 - [3:0] */ 75176a504a75SDimitris Papastamos 75186a504a75SDimitris Papastamos /* 75196a504a75SDimitris Papastamos * R12663 (0x3177) - Write Sequencer 375 75206a504a75SDimitris Papastamos */ 75216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS93 0x0100 /* WSEQ_EOS93 */ 75226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS93_MASK 0x0100 /* WSEQ_EOS93 */ 75236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS93_SHIFT 8 /* WSEQ_EOS93 */ 75246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS93_WIDTH 1 /* WSEQ_EOS93 */ 75256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY93_MASK 0x000F /* WSEQ_DELAY93 - [3:0] */ 75266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY93_SHIFT 0 /* WSEQ_DELAY93 - [3:0] */ 75276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY93_WIDTH 4 /* WSEQ_DELAY93 - [3:0] */ 75286a504a75SDimitris Papastamos 75296a504a75SDimitris Papastamos /* 75306a504a75SDimitris Papastamos * R12664 (0x3178) - Write Sequencer 376 75316a504a75SDimitris Papastamos */ 75326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR94_MASK 0x3FFF /* WSEQ_ADDR94 - [13:0] */ 75336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR94_SHIFT 0 /* WSEQ_ADDR94 - [13:0] */ 75346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR94_WIDTH 14 /* WSEQ_ADDR94 - [13:0] */ 75356a504a75SDimitris Papastamos 75366a504a75SDimitris Papastamos /* 75376a504a75SDimitris Papastamos * R12665 (0x3179) - Write Sequencer 377 75386a504a75SDimitris Papastamos */ 75396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA94_MASK 0x00FF /* WSEQ_DATA94 - [7:0] */ 75406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA94_SHIFT 0 /* WSEQ_DATA94 - [7:0] */ 75416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA94_WIDTH 8 /* WSEQ_DATA94 - [7:0] */ 75426a504a75SDimitris Papastamos 75436a504a75SDimitris Papastamos /* 75446a504a75SDimitris Papastamos * R12666 (0x317A) - Write Sequencer 378 75456a504a75SDimitris Papastamos */ 75466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH94_MASK 0x0700 /* WSEQ_DATA_WIDTH94 - [10:8] */ 75476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH94_SHIFT 8 /* WSEQ_DATA_WIDTH94 - [10:8] */ 75486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH94_WIDTH 3 /* WSEQ_DATA_WIDTH94 - [10:8] */ 75496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START94_MASK 0x000F /* WSEQ_DATA_START94 - [3:0] */ 75506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START94_SHIFT 0 /* WSEQ_DATA_START94 - [3:0] */ 75516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START94_WIDTH 4 /* WSEQ_DATA_START94 - [3:0] */ 75526a504a75SDimitris Papastamos 75536a504a75SDimitris Papastamos /* 75546a504a75SDimitris Papastamos * R12667 (0x317B) - Write Sequencer 379 75556a504a75SDimitris Papastamos */ 75566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS94 0x0100 /* WSEQ_EOS94 */ 75576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS94_MASK 0x0100 /* WSEQ_EOS94 */ 75586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS94_SHIFT 8 /* WSEQ_EOS94 */ 75596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS94_WIDTH 1 /* WSEQ_EOS94 */ 75606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY94_MASK 0x000F /* WSEQ_DELAY94 - [3:0] */ 75616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY94_SHIFT 0 /* WSEQ_DELAY94 - [3:0] */ 75626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY94_WIDTH 4 /* WSEQ_DELAY94 - [3:0] */ 75636a504a75SDimitris Papastamos 75646a504a75SDimitris Papastamos /* 75656a504a75SDimitris Papastamos * R12668 (0x317C) - Write Sequencer 380 75666a504a75SDimitris Papastamos */ 75676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR95_MASK 0x3FFF /* WSEQ_ADDR95 - [13:0] */ 75686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR95_SHIFT 0 /* WSEQ_ADDR95 - [13:0] */ 75696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR95_WIDTH 14 /* WSEQ_ADDR95 - [13:0] */ 75706a504a75SDimitris Papastamos 75716a504a75SDimitris Papastamos /* 75726a504a75SDimitris Papastamos * R12669 (0x317D) - Write Sequencer 381 75736a504a75SDimitris Papastamos */ 75746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA95_MASK 0x00FF /* WSEQ_DATA95 - [7:0] */ 75756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA95_SHIFT 0 /* WSEQ_DATA95 - [7:0] */ 75766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA95_WIDTH 8 /* WSEQ_DATA95 - [7:0] */ 75776a504a75SDimitris Papastamos 75786a504a75SDimitris Papastamos /* 75796a504a75SDimitris Papastamos * R12670 (0x317E) - Write Sequencer 382 75806a504a75SDimitris Papastamos */ 75816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH95_MASK 0x0700 /* WSEQ_DATA_WIDTH95 - [10:8] */ 75826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH95_SHIFT 8 /* WSEQ_DATA_WIDTH95 - [10:8] */ 75836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH95_WIDTH 3 /* WSEQ_DATA_WIDTH95 - [10:8] */ 75846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START95_MASK 0x000F /* WSEQ_DATA_START95 - [3:0] */ 75856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START95_SHIFT 0 /* WSEQ_DATA_START95 - [3:0] */ 75866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START95_WIDTH 4 /* WSEQ_DATA_START95 - [3:0] */ 75876a504a75SDimitris Papastamos 75886a504a75SDimitris Papastamos /* 75896a504a75SDimitris Papastamos * R12671 (0x317F) - Write Sequencer 383 75906a504a75SDimitris Papastamos */ 75916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS95 0x0100 /* WSEQ_EOS95 */ 75926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS95_MASK 0x0100 /* WSEQ_EOS95 */ 75936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS95_SHIFT 8 /* WSEQ_EOS95 */ 75946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS95_WIDTH 1 /* WSEQ_EOS95 */ 75956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY95_MASK 0x000F /* WSEQ_DELAY95 - [3:0] */ 75966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY95_SHIFT 0 /* WSEQ_DELAY95 - [3:0] */ 75976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY95_WIDTH 4 /* WSEQ_DELAY95 - [3:0] */ 75986a504a75SDimitris Papastamos 75996a504a75SDimitris Papastamos /* 76006a504a75SDimitris Papastamos * R12672 (0x3180) - Write Sequencer 384 76016a504a75SDimitris Papastamos */ 76026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR96_MASK 0x3FFF /* WSEQ_ADDR96 - [13:0] */ 76036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR96_SHIFT 0 /* WSEQ_ADDR96 - [13:0] */ 76046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR96_WIDTH 14 /* WSEQ_ADDR96 - [13:0] */ 76056a504a75SDimitris Papastamos 76066a504a75SDimitris Papastamos /* 76076a504a75SDimitris Papastamos * R12673 (0x3181) - Write Sequencer 385 76086a504a75SDimitris Papastamos */ 76096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA96_MASK 0x00FF /* WSEQ_DATA96 - [7:0] */ 76106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA96_SHIFT 0 /* WSEQ_DATA96 - [7:0] */ 76116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA96_WIDTH 8 /* WSEQ_DATA96 - [7:0] */ 76126a504a75SDimitris Papastamos 76136a504a75SDimitris Papastamos /* 76146a504a75SDimitris Papastamos * R12674 (0x3182) - Write Sequencer 386 76156a504a75SDimitris Papastamos */ 76166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH96_MASK 0x0700 /* WSEQ_DATA_WIDTH96 - [10:8] */ 76176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH96_SHIFT 8 /* WSEQ_DATA_WIDTH96 - [10:8] */ 76186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH96_WIDTH 3 /* WSEQ_DATA_WIDTH96 - [10:8] */ 76196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START96_MASK 0x000F /* WSEQ_DATA_START96 - [3:0] */ 76206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START96_SHIFT 0 /* WSEQ_DATA_START96 - [3:0] */ 76216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START96_WIDTH 4 /* WSEQ_DATA_START96 - [3:0] */ 76226a504a75SDimitris Papastamos 76236a504a75SDimitris Papastamos /* 76246a504a75SDimitris Papastamos * R12675 (0x3183) - Write Sequencer 387 76256a504a75SDimitris Papastamos */ 76266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS96 0x0100 /* WSEQ_EOS96 */ 76276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS96_MASK 0x0100 /* WSEQ_EOS96 */ 76286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS96_SHIFT 8 /* WSEQ_EOS96 */ 76296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS96_WIDTH 1 /* WSEQ_EOS96 */ 76306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY96_MASK 0x000F /* WSEQ_DELAY96 - [3:0] */ 76316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY96_SHIFT 0 /* WSEQ_DELAY96 - [3:0] */ 76326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY96_WIDTH 4 /* WSEQ_DELAY96 - [3:0] */ 76336a504a75SDimitris Papastamos 76346a504a75SDimitris Papastamos /* 76356a504a75SDimitris Papastamos * R12676 (0x3184) - Write Sequencer 388 76366a504a75SDimitris Papastamos */ 76376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR97_MASK 0x3FFF /* WSEQ_ADDR97 - [13:0] */ 76386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR97_SHIFT 0 /* WSEQ_ADDR97 - [13:0] */ 76396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR97_WIDTH 14 /* WSEQ_ADDR97 - [13:0] */ 76406a504a75SDimitris Papastamos 76416a504a75SDimitris Papastamos /* 76426a504a75SDimitris Papastamos * R12677 (0x3185) - Write Sequencer 389 76436a504a75SDimitris Papastamos */ 76446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA97_MASK 0x00FF /* WSEQ_DATA97 - [7:0] */ 76456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA97_SHIFT 0 /* WSEQ_DATA97 - [7:0] */ 76466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA97_WIDTH 8 /* WSEQ_DATA97 - [7:0] */ 76476a504a75SDimitris Papastamos 76486a504a75SDimitris Papastamos /* 76496a504a75SDimitris Papastamos * R12678 (0x3186) - Write Sequencer 390 76506a504a75SDimitris Papastamos */ 76516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH97_MASK 0x0700 /* WSEQ_DATA_WIDTH97 - [10:8] */ 76526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH97_SHIFT 8 /* WSEQ_DATA_WIDTH97 - [10:8] */ 76536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH97_WIDTH 3 /* WSEQ_DATA_WIDTH97 - [10:8] */ 76546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START97_MASK 0x000F /* WSEQ_DATA_START97 - [3:0] */ 76556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START97_SHIFT 0 /* WSEQ_DATA_START97 - [3:0] */ 76566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START97_WIDTH 4 /* WSEQ_DATA_START97 - [3:0] */ 76576a504a75SDimitris Papastamos 76586a504a75SDimitris Papastamos /* 76596a504a75SDimitris Papastamos * R12679 (0x3187) - Write Sequencer 391 76606a504a75SDimitris Papastamos */ 76616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS97 0x0100 /* WSEQ_EOS97 */ 76626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS97_MASK 0x0100 /* WSEQ_EOS97 */ 76636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS97_SHIFT 8 /* WSEQ_EOS97 */ 76646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS97_WIDTH 1 /* WSEQ_EOS97 */ 76656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY97_MASK 0x000F /* WSEQ_DELAY97 - [3:0] */ 76666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY97_SHIFT 0 /* WSEQ_DELAY97 - [3:0] */ 76676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY97_WIDTH 4 /* WSEQ_DELAY97 - [3:0] */ 76686a504a75SDimitris Papastamos 76696a504a75SDimitris Papastamos /* 76706a504a75SDimitris Papastamos * R12680 (0x3188) - Write Sequencer 392 76716a504a75SDimitris Papastamos */ 76726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR98_MASK 0x3FFF /* WSEQ_ADDR98 - [13:0] */ 76736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR98_SHIFT 0 /* WSEQ_ADDR98 - [13:0] */ 76746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR98_WIDTH 14 /* WSEQ_ADDR98 - [13:0] */ 76756a504a75SDimitris Papastamos 76766a504a75SDimitris Papastamos /* 76776a504a75SDimitris Papastamos * R12681 (0x3189) - Write Sequencer 393 76786a504a75SDimitris Papastamos */ 76796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA98_MASK 0x00FF /* WSEQ_DATA98 - [7:0] */ 76806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA98_SHIFT 0 /* WSEQ_DATA98 - [7:0] */ 76816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA98_WIDTH 8 /* WSEQ_DATA98 - [7:0] */ 76826a504a75SDimitris Papastamos 76836a504a75SDimitris Papastamos /* 76846a504a75SDimitris Papastamos * R12682 (0x318A) - Write Sequencer 394 76856a504a75SDimitris Papastamos */ 76866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH98_MASK 0x0700 /* WSEQ_DATA_WIDTH98 - [10:8] */ 76876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH98_SHIFT 8 /* WSEQ_DATA_WIDTH98 - [10:8] */ 76886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH98_WIDTH 3 /* WSEQ_DATA_WIDTH98 - [10:8] */ 76896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START98_MASK 0x000F /* WSEQ_DATA_START98 - [3:0] */ 76906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START98_SHIFT 0 /* WSEQ_DATA_START98 - [3:0] */ 76916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START98_WIDTH 4 /* WSEQ_DATA_START98 - [3:0] */ 76926a504a75SDimitris Papastamos 76936a504a75SDimitris Papastamos /* 76946a504a75SDimitris Papastamos * R12683 (0x318B) - Write Sequencer 395 76956a504a75SDimitris Papastamos */ 76966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS98 0x0100 /* WSEQ_EOS98 */ 76976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS98_MASK 0x0100 /* WSEQ_EOS98 */ 76986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS98_SHIFT 8 /* WSEQ_EOS98 */ 76996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS98_WIDTH 1 /* WSEQ_EOS98 */ 77006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY98_MASK 0x000F /* WSEQ_DELAY98 - [3:0] */ 77016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY98_SHIFT 0 /* WSEQ_DELAY98 - [3:0] */ 77026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY98_WIDTH 4 /* WSEQ_DELAY98 - [3:0] */ 77036a504a75SDimitris Papastamos 77046a504a75SDimitris Papastamos /* 77056a504a75SDimitris Papastamos * R12684 (0x318C) - Write Sequencer 396 77066a504a75SDimitris Papastamos */ 77076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR99_MASK 0x3FFF /* WSEQ_ADDR99 - [13:0] */ 77086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR99_SHIFT 0 /* WSEQ_ADDR99 - [13:0] */ 77096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR99_WIDTH 14 /* WSEQ_ADDR99 - [13:0] */ 77106a504a75SDimitris Papastamos 77116a504a75SDimitris Papastamos /* 77126a504a75SDimitris Papastamos * R12685 (0x318D) - Write Sequencer 397 77136a504a75SDimitris Papastamos */ 77146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA99_MASK 0x00FF /* WSEQ_DATA99 - [7:0] */ 77156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA99_SHIFT 0 /* WSEQ_DATA99 - [7:0] */ 77166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA99_WIDTH 8 /* WSEQ_DATA99 - [7:0] */ 77176a504a75SDimitris Papastamos 77186a504a75SDimitris Papastamos /* 77196a504a75SDimitris Papastamos * R12686 (0x318E) - Write Sequencer 398 77206a504a75SDimitris Papastamos */ 77216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH99_MASK 0x0700 /* WSEQ_DATA_WIDTH99 - [10:8] */ 77226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH99_SHIFT 8 /* WSEQ_DATA_WIDTH99 - [10:8] */ 77236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH99_WIDTH 3 /* WSEQ_DATA_WIDTH99 - [10:8] */ 77246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START99_MASK 0x000F /* WSEQ_DATA_START99 - [3:0] */ 77256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START99_SHIFT 0 /* WSEQ_DATA_START99 - [3:0] */ 77266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START99_WIDTH 4 /* WSEQ_DATA_START99 - [3:0] */ 77276a504a75SDimitris Papastamos 77286a504a75SDimitris Papastamos /* 77296a504a75SDimitris Papastamos * R12687 (0x318F) - Write Sequencer 399 77306a504a75SDimitris Papastamos */ 77316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS99 0x0100 /* WSEQ_EOS99 */ 77326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS99_MASK 0x0100 /* WSEQ_EOS99 */ 77336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS99_SHIFT 8 /* WSEQ_EOS99 */ 77346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS99_WIDTH 1 /* WSEQ_EOS99 */ 77356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY99_MASK 0x000F /* WSEQ_DELAY99 - [3:0] */ 77366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY99_SHIFT 0 /* WSEQ_DELAY99 - [3:0] */ 77376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY99_WIDTH 4 /* WSEQ_DELAY99 - [3:0] */ 77386a504a75SDimitris Papastamos 77396a504a75SDimitris Papastamos /* 77406a504a75SDimitris Papastamos * R12688 (0x3190) - Write Sequencer 400 77416a504a75SDimitris Papastamos */ 77426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR100_MASK 0x3FFF /* WSEQ_ADDR100 - [13:0] */ 77436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR100_SHIFT 0 /* WSEQ_ADDR100 - [13:0] */ 77446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR100_WIDTH 14 /* WSEQ_ADDR100 - [13:0] */ 77456a504a75SDimitris Papastamos 77466a504a75SDimitris Papastamos /* 77476a504a75SDimitris Papastamos * R12689 (0x3191) - Write Sequencer 401 77486a504a75SDimitris Papastamos */ 77496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA100_MASK 0x00FF /* WSEQ_DATA100 - [7:0] */ 77506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA100_SHIFT 0 /* WSEQ_DATA100 - [7:0] */ 77516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA100_WIDTH 8 /* WSEQ_DATA100 - [7:0] */ 77526a504a75SDimitris Papastamos 77536a504a75SDimitris Papastamos /* 77546a504a75SDimitris Papastamos * R12690 (0x3192) - Write Sequencer 402 77556a504a75SDimitris Papastamos */ 77566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH100_MASK 0x0700 /* WSEQ_DATA_WIDTH100 - [10:8] */ 77576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH100_SHIFT 8 /* WSEQ_DATA_WIDTH100 - [10:8] */ 77586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH100_WIDTH 3 /* WSEQ_DATA_WIDTH100 - [10:8] */ 77596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START100_MASK 0x000F /* WSEQ_DATA_START100 - [3:0] */ 77606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START100_SHIFT 0 /* WSEQ_DATA_START100 - [3:0] */ 77616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START100_WIDTH 4 /* WSEQ_DATA_START100 - [3:0] */ 77626a504a75SDimitris Papastamos 77636a504a75SDimitris Papastamos /* 77646a504a75SDimitris Papastamos * R12691 (0x3193) - Write Sequencer 403 77656a504a75SDimitris Papastamos */ 77666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS100 0x0100 /* WSEQ_EOS100 */ 77676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS100_MASK 0x0100 /* WSEQ_EOS100 */ 77686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS100_SHIFT 8 /* WSEQ_EOS100 */ 77696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS100_WIDTH 1 /* WSEQ_EOS100 */ 77706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY100_MASK 0x000F /* WSEQ_DELAY100 - [3:0] */ 77716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY100_SHIFT 0 /* WSEQ_DELAY100 - [3:0] */ 77726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY100_WIDTH 4 /* WSEQ_DELAY100 - [3:0] */ 77736a504a75SDimitris Papastamos 77746a504a75SDimitris Papastamos /* 77756a504a75SDimitris Papastamos * R12692 (0x3194) - Write Sequencer 404 77766a504a75SDimitris Papastamos */ 77776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR101_MASK 0x3FFF /* WSEQ_ADDR101 - [13:0] */ 77786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR101_SHIFT 0 /* WSEQ_ADDR101 - [13:0] */ 77796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR101_WIDTH 14 /* WSEQ_ADDR101 - [13:0] */ 77806a504a75SDimitris Papastamos 77816a504a75SDimitris Papastamos /* 77826a504a75SDimitris Papastamos * R12693 (0x3195) - Write Sequencer 405 77836a504a75SDimitris Papastamos */ 77846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA101_MASK 0x00FF /* WSEQ_DATA101 - [7:0] */ 77856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA101_SHIFT 0 /* WSEQ_DATA101 - [7:0] */ 77866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA101_WIDTH 8 /* WSEQ_DATA101 - [7:0] */ 77876a504a75SDimitris Papastamos 77886a504a75SDimitris Papastamos /* 77896a504a75SDimitris Papastamos * R12694 (0x3196) - Write Sequencer 406 77906a504a75SDimitris Papastamos */ 77916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH101_MASK 0x0700 /* WSEQ_DATA_WIDTH101 - [10:8] */ 77926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH101_SHIFT 8 /* WSEQ_DATA_WIDTH101 - [10:8] */ 77936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH101_WIDTH 3 /* WSEQ_DATA_WIDTH101 - [10:8] */ 77946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START101_MASK 0x000F /* WSEQ_DATA_START101 - [3:0] */ 77956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START101_SHIFT 0 /* WSEQ_DATA_START101 - [3:0] */ 77966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START101_WIDTH 4 /* WSEQ_DATA_START101 - [3:0] */ 77976a504a75SDimitris Papastamos 77986a504a75SDimitris Papastamos /* 77996a504a75SDimitris Papastamos * R12695 (0x3197) - Write Sequencer 407 78006a504a75SDimitris Papastamos */ 78016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS101 0x0100 /* WSEQ_EOS101 */ 78026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS101_MASK 0x0100 /* WSEQ_EOS101 */ 78036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS101_SHIFT 8 /* WSEQ_EOS101 */ 78046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS101_WIDTH 1 /* WSEQ_EOS101 */ 78056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY101_MASK 0x000F /* WSEQ_DELAY101 - [3:0] */ 78066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY101_SHIFT 0 /* WSEQ_DELAY101 - [3:0] */ 78076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY101_WIDTH 4 /* WSEQ_DELAY101 - [3:0] */ 78086a504a75SDimitris Papastamos 78096a504a75SDimitris Papastamos /* 78106a504a75SDimitris Papastamos * R12696 (0x3198) - Write Sequencer 408 78116a504a75SDimitris Papastamos */ 78126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR102_MASK 0x3FFF /* WSEQ_ADDR102 - [13:0] */ 78136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR102_SHIFT 0 /* WSEQ_ADDR102 - [13:0] */ 78146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR102_WIDTH 14 /* WSEQ_ADDR102 - [13:0] */ 78156a504a75SDimitris Papastamos 78166a504a75SDimitris Papastamos /* 78176a504a75SDimitris Papastamos * R12697 (0x3199) - Write Sequencer 409 78186a504a75SDimitris Papastamos */ 78196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA102_MASK 0x00FF /* WSEQ_DATA102 - [7:0] */ 78206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA102_SHIFT 0 /* WSEQ_DATA102 - [7:0] */ 78216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA102_WIDTH 8 /* WSEQ_DATA102 - [7:0] */ 78226a504a75SDimitris Papastamos 78236a504a75SDimitris Papastamos /* 78246a504a75SDimitris Papastamos * R12698 (0x319A) - Write Sequencer 410 78256a504a75SDimitris Papastamos */ 78266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH102_MASK 0x0700 /* WSEQ_DATA_WIDTH102 - [10:8] */ 78276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH102_SHIFT 8 /* WSEQ_DATA_WIDTH102 - [10:8] */ 78286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH102_WIDTH 3 /* WSEQ_DATA_WIDTH102 - [10:8] */ 78296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START102_MASK 0x000F /* WSEQ_DATA_START102 - [3:0] */ 78306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START102_SHIFT 0 /* WSEQ_DATA_START102 - [3:0] */ 78316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START102_WIDTH 4 /* WSEQ_DATA_START102 - [3:0] */ 78326a504a75SDimitris Papastamos 78336a504a75SDimitris Papastamos /* 78346a504a75SDimitris Papastamos * R12699 (0x319B) - Write Sequencer 411 78356a504a75SDimitris Papastamos */ 78366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS102 0x0100 /* WSEQ_EOS102 */ 78376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS102_MASK 0x0100 /* WSEQ_EOS102 */ 78386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS102_SHIFT 8 /* WSEQ_EOS102 */ 78396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS102_WIDTH 1 /* WSEQ_EOS102 */ 78406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY102_MASK 0x000F /* WSEQ_DELAY102 - [3:0] */ 78416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY102_SHIFT 0 /* WSEQ_DELAY102 - [3:0] */ 78426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY102_WIDTH 4 /* WSEQ_DELAY102 - [3:0] */ 78436a504a75SDimitris Papastamos 78446a504a75SDimitris Papastamos /* 78456a504a75SDimitris Papastamos * R12700 (0x319C) - Write Sequencer 412 78466a504a75SDimitris Papastamos */ 78476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR103_MASK 0x3FFF /* WSEQ_ADDR103 - [13:0] */ 78486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR103_SHIFT 0 /* WSEQ_ADDR103 - [13:0] */ 78496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR103_WIDTH 14 /* WSEQ_ADDR103 - [13:0] */ 78506a504a75SDimitris Papastamos 78516a504a75SDimitris Papastamos /* 78526a504a75SDimitris Papastamos * R12701 (0x319D) - Write Sequencer 413 78536a504a75SDimitris Papastamos */ 78546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA103_MASK 0x00FF /* WSEQ_DATA103 - [7:0] */ 78556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA103_SHIFT 0 /* WSEQ_DATA103 - [7:0] */ 78566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA103_WIDTH 8 /* WSEQ_DATA103 - [7:0] */ 78576a504a75SDimitris Papastamos 78586a504a75SDimitris Papastamos /* 78596a504a75SDimitris Papastamos * R12702 (0x319E) - Write Sequencer 414 78606a504a75SDimitris Papastamos */ 78616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH103_MASK 0x0700 /* WSEQ_DATA_WIDTH103 - [10:8] */ 78626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH103_SHIFT 8 /* WSEQ_DATA_WIDTH103 - [10:8] */ 78636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH103_WIDTH 3 /* WSEQ_DATA_WIDTH103 - [10:8] */ 78646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START103_MASK 0x000F /* WSEQ_DATA_START103 - [3:0] */ 78656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START103_SHIFT 0 /* WSEQ_DATA_START103 - [3:0] */ 78666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START103_WIDTH 4 /* WSEQ_DATA_START103 - [3:0] */ 78676a504a75SDimitris Papastamos 78686a504a75SDimitris Papastamos /* 78696a504a75SDimitris Papastamos * R12703 (0x319F) - Write Sequencer 415 78706a504a75SDimitris Papastamos */ 78716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS103 0x0100 /* WSEQ_EOS103 */ 78726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS103_MASK 0x0100 /* WSEQ_EOS103 */ 78736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS103_SHIFT 8 /* WSEQ_EOS103 */ 78746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS103_WIDTH 1 /* WSEQ_EOS103 */ 78756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY103_MASK 0x000F /* WSEQ_DELAY103 - [3:0] */ 78766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY103_SHIFT 0 /* WSEQ_DELAY103 - [3:0] */ 78776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY103_WIDTH 4 /* WSEQ_DELAY103 - [3:0] */ 78786a504a75SDimitris Papastamos 78796a504a75SDimitris Papastamos /* 78806a504a75SDimitris Papastamos * R12704 (0x31A0) - Write Sequencer 416 78816a504a75SDimitris Papastamos */ 78826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR104_MASK 0x3FFF /* WSEQ_ADDR104 - [13:0] */ 78836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR104_SHIFT 0 /* WSEQ_ADDR104 - [13:0] */ 78846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR104_WIDTH 14 /* WSEQ_ADDR104 - [13:0] */ 78856a504a75SDimitris Papastamos 78866a504a75SDimitris Papastamos /* 78876a504a75SDimitris Papastamos * R12705 (0x31A1) - Write Sequencer 417 78886a504a75SDimitris Papastamos */ 78896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA104_MASK 0x00FF /* WSEQ_DATA104 - [7:0] */ 78906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA104_SHIFT 0 /* WSEQ_DATA104 - [7:0] */ 78916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA104_WIDTH 8 /* WSEQ_DATA104 - [7:0] */ 78926a504a75SDimitris Papastamos 78936a504a75SDimitris Papastamos /* 78946a504a75SDimitris Papastamos * R12706 (0x31A2) - Write Sequencer 418 78956a504a75SDimitris Papastamos */ 78966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH104_MASK 0x0700 /* WSEQ_DATA_WIDTH104 - [10:8] */ 78976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH104_SHIFT 8 /* WSEQ_DATA_WIDTH104 - [10:8] */ 78986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH104_WIDTH 3 /* WSEQ_DATA_WIDTH104 - [10:8] */ 78996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START104_MASK 0x000F /* WSEQ_DATA_START104 - [3:0] */ 79006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START104_SHIFT 0 /* WSEQ_DATA_START104 - [3:0] */ 79016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START104_WIDTH 4 /* WSEQ_DATA_START104 - [3:0] */ 79026a504a75SDimitris Papastamos 79036a504a75SDimitris Papastamos /* 79046a504a75SDimitris Papastamos * R12707 (0x31A3) - Write Sequencer 419 79056a504a75SDimitris Papastamos */ 79066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS104 0x0100 /* WSEQ_EOS104 */ 79076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS104_MASK 0x0100 /* WSEQ_EOS104 */ 79086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS104_SHIFT 8 /* WSEQ_EOS104 */ 79096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS104_WIDTH 1 /* WSEQ_EOS104 */ 79106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY104_MASK 0x000F /* WSEQ_DELAY104 - [3:0] */ 79116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY104_SHIFT 0 /* WSEQ_DELAY104 - [3:0] */ 79126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY104_WIDTH 4 /* WSEQ_DELAY104 - [3:0] */ 79136a504a75SDimitris Papastamos 79146a504a75SDimitris Papastamos /* 79156a504a75SDimitris Papastamos * R12708 (0x31A4) - Write Sequencer 420 79166a504a75SDimitris Papastamos */ 79176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR105_MASK 0x3FFF /* WSEQ_ADDR105 - [13:0] */ 79186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR105_SHIFT 0 /* WSEQ_ADDR105 - [13:0] */ 79196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR105_WIDTH 14 /* WSEQ_ADDR105 - [13:0] */ 79206a504a75SDimitris Papastamos 79216a504a75SDimitris Papastamos /* 79226a504a75SDimitris Papastamos * R12709 (0x31A5) - Write Sequencer 421 79236a504a75SDimitris Papastamos */ 79246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA105_MASK 0x00FF /* WSEQ_DATA105 - [7:0] */ 79256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA105_SHIFT 0 /* WSEQ_DATA105 - [7:0] */ 79266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA105_WIDTH 8 /* WSEQ_DATA105 - [7:0] */ 79276a504a75SDimitris Papastamos 79286a504a75SDimitris Papastamos /* 79296a504a75SDimitris Papastamos * R12710 (0x31A6) - Write Sequencer 422 79306a504a75SDimitris Papastamos */ 79316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH105_MASK 0x0700 /* WSEQ_DATA_WIDTH105 - [10:8] */ 79326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH105_SHIFT 8 /* WSEQ_DATA_WIDTH105 - [10:8] */ 79336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH105_WIDTH 3 /* WSEQ_DATA_WIDTH105 - [10:8] */ 79346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START105_MASK 0x000F /* WSEQ_DATA_START105 - [3:0] */ 79356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START105_SHIFT 0 /* WSEQ_DATA_START105 - [3:0] */ 79366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START105_WIDTH 4 /* WSEQ_DATA_START105 - [3:0] */ 79376a504a75SDimitris Papastamos 79386a504a75SDimitris Papastamos /* 79396a504a75SDimitris Papastamos * R12711 (0x31A7) - Write Sequencer 423 79406a504a75SDimitris Papastamos */ 79416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS105 0x0100 /* WSEQ_EOS105 */ 79426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS105_MASK 0x0100 /* WSEQ_EOS105 */ 79436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS105_SHIFT 8 /* WSEQ_EOS105 */ 79446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS105_WIDTH 1 /* WSEQ_EOS105 */ 79456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY105_MASK 0x000F /* WSEQ_DELAY105 - [3:0] */ 79466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY105_SHIFT 0 /* WSEQ_DELAY105 - [3:0] */ 79476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY105_WIDTH 4 /* WSEQ_DELAY105 - [3:0] */ 79486a504a75SDimitris Papastamos 79496a504a75SDimitris Papastamos /* 79506a504a75SDimitris Papastamos * R12712 (0x31A8) - Write Sequencer 424 79516a504a75SDimitris Papastamos */ 79526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR106_MASK 0x3FFF /* WSEQ_ADDR106 - [13:0] */ 79536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR106_SHIFT 0 /* WSEQ_ADDR106 - [13:0] */ 79546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR106_WIDTH 14 /* WSEQ_ADDR106 - [13:0] */ 79556a504a75SDimitris Papastamos 79566a504a75SDimitris Papastamos /* 79576a504a75SDimitris Papastamos * R12713 (0x31A9) - Write Sequencer 425 79586a504a75SDimitris Papastamos */ 79596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA106_MASK 0x00FF /* WSEQ_DATA106 - [7:0] */ 79606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA106_SHIFT 0 /* WSEQ_DATA106 - [7:0] */ 79616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA106_WIDTH 8 /* WSEQ_DATA106 - [7:0] */ 79626a504a75SDimitris Papastamos 79636a504a75SDimitris Papastamos /* 79646a504a75SDimitris Papastamos * R12714 (0x31AA) - Write Sequencer 426 79656a504a75SDimitris Papastamos */ 79666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH106_MASK 0x0700 /* WSEQ_DATA_WIDTH106 - [10:8] */ 79676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH106_SHIFT 8 /* WSEQ_DATA_WIDTH106 - [10:8] */ 79686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH106_WIDTH 3 /* WSEQ_DATA_WIDTH106 - [10:8] */ 79696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START106_MASK 0x000F /* WSEQ_DATA_START106 - [3:0] */ 79706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START106_SHIFT 0 /* WSEQ_DATA_START106 - [3:0] */ 79716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START106_WIDTH 4 /* WSEQ_DATA_START106 - [3:0] */ 79726a504a75SDimitris Papastamos 79736a504a75SDimitris Papastamos /* 79746a504a75SDimitris Papastamos * R12715 (0x31AB) - Write Sequencer 427 79756a504a75SDimitris Papastamos */ 79766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS106 0x0100 /* WSEQ_EOS106 */ 79776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS106_MASK 0x0100 /* WSEQ_EOS106 */ 79786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS106_SHIFT 8 /* WSEQ_EOS106 */ 79796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS106_WIDTH 1 /* WSEQ_EOS106 */ 79806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY106_MASK 0x000F /* WSEQ_DELAY106 - [3:0] */ 79816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY106_SHIFT 0 /* WSEQ_DELAY106 - [3:0] */ 79826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY106_WIDTH 4 /* WSEQ_DELAY106 - [3:0] */ 79836a504a75SDimitris Papastamos 79846a504a75SDimitris Papastamos /* 79856a504a75SDimitris Papastamos * R12716 (0x31AC) - Write Sequencer 428 79866a504a75SDimitris Papastamos */ 79876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR107_MASK 0x3FFF /* WSEQ_ADDR107 - [13:0] */ 79886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR107_SHIFT 0 /* WSEQ_ADDR107 - [13:0] */ 79896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR107_WIDTH 14 /* WSEQ_ADDR107 - [13:0] */ 79906a504a75SDimitris Papastamos 79916a504a75SDimitris Papastamos /* 79926a504a75SDimitris Papastamos * R12717 (0x31AD) - Write Sequencer 429 79936a504a75SDimitris Papastamos */ 79946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA107_MASK 0x00FF /* WSEQ_DATA107 - [7:0] */ 79956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA107_SHIFT 0 /* WSEQ_DATA107 - [7:0] */ 79966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA107_WIDTH 8 /* WSEQ_DATA107 - [7:0] */ 79976a504a75SDimitris Papastamos 79986a504a75SDimitris Papastamos /* 79996a504a75SDimitris Papastamos * R12718 (0x31AE) - Write Sequencer 430 80006a504a75SDimitris Papastamos */ 80016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH107_MASK 0x0700 /* WSEQ_DATA_WIDTH107 - [10:8] */ 80026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH107_SHIFT 8 /* WSEQ_DATA_WIDTH107 - [10:8] */ 80036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH107_WIDTH 3 /* WSEQ_DATA_WIDTH107 - [10:8] */ 80046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START107_MASK 0x000F /* WSEQ_DATA_START107 - [3:0] */ 80056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START107_SHIFT 0 /* WSEQ_DATA_START107 - [3:0] */ 80066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START107_WIDTH 4 /* WSEQ_DATA_START107 - [3:0] */ 80076a504a75SDimitris Papastamos 80086a504a75SDimitris Papastamos /* 80096a504a75SDimitris Papastamos * R12719 (0x31AF) - Write Sequencer 431 80106a504a75SDimitris Papastamos */ 80116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS107 0x0100 /* WSEQ_EOS107 */ 80126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS107_MASK 0x0100 /* WSEQ_EOS107 */ 80136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS107_SHIFT 8 /* WSEQ_EOS107 */ 80146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS107_WIDTH 1 /* WSEQ_EOS107 */ 80156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY107_MASK 0x000F /* WSEQ_DELAY107 - [3:0] */ 80166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY107_SHIFT 0 /* WSEQ_DELAY107 - [3:0] */ 80176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY107_WIDTH 4 /* WSEQ_DELAY107 - [3:0] */ 80186a504a75SDimitris Papastamos 80196a504a75SDimitris Papastamos /* 80206a504a75SDimitris Papastamos * R12720 (0x31B0) - Write Sequencer 432 80216a504a75SDimitris Papastamos */ 80226a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR108_MASK 0x3FFF /* WSEQ_ADDR108 - [13:0] */ 80236a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR108_SHIFT 0 /* WSEQ_ADDR108 - [13:0] */ 80246a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR108_WIDTH 14 /* WSEQ_ADDR108 - [13:0] */ 80256a504a75SDimitris Papastamos 80266a504a75SDimitris Papastamos /* 80276a504a75SDimitris Papastamos * R12721 (0x31B1) - Write Sequencer 433 80286a504a75SDimitris Papastamos */ 80296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA108_MASK 0x00FF /* WSEQ_DATA108 - [7:0] */ 80306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA108_SHIFT 0 /* WSEQ_DATA108 - [7:0] */ 80316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA108_WIDTH 8 /* WSEQ_DATA108 - [7:0] */ 80326a504a75SDimitris Papastamos 80336a504a75SDimitris Papastamos /* 80346a504a75SDimitris Papastamos * R12722 (0x31B2) - Write Sequencer 434 80356a504a75SDimitris Papastamos */ 80366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH108_MASK 0x0700 /* WSEQ_DATA_WIDTH108 - [10:8] */ 80376a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH108_SHIFT 8 /* WSEQ_DATA_WIDTH108 - [10:8] */ 80386a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH108_WIDTH 3 /* WSEQ_DATA_WIDTH108 - [10:8] */ 80396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START108_MASK 0x000F /* WSEQ_DATA_START108 - [3:0] */ 80406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START108_SHIFT 0 /* WSEQ_DATA_START108 - [3:0] */ 80416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START108_WIDTH 4 /* WSEQ_DATA_START108 - [3:0] */ 80426a504a75SDimitris Papastamos 80436a504a75SDimitris Papastamos /* 80446a504a75SDimitris Papastamos * R12723 (0x31B3) - Write Sequencer 435 80456a504a75SDimitris Papastamos */ 80466a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS108 0x0100 /* WSEQ_EOS108 */ 80476a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS108_MASK 0x0100 /* WSEQ_EOS108 */ 80486a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS108_SHIFT 8 /* WSEQ_EOS108 */ 80496a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS108_WIDTH 1 /* WSEQ_EOS108 */ 80506a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY108_MASK 0x000F /* WSEQ_DELAY108 - [3:0] */ 80516a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY108_SHIFT 0 /* WSEQ_DELAY108 - [3:0] */ 80526a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY108_WIDTH 4 /* WSEQ_DELAY108 - [3:0] */ 80536a504a75SDimitris Papastamos 80546a504a75SDimitris Papastamos /* 80556a504a75SDimitris Papastamos * R12724 (0x31B4) - Write Sequencer 436 80566a504a75SDimitris Papastamos */ 80576a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR109_MASK 0x3FFF /* WSEQ_ADDR109 - [13:0] */ 80586a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR109_SHIFT 0 /* WSEQ_ADDR109 - [13:0] */ 80596a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR109_WIDTH 14 /* WSEQ_ADDR109 - [13:0] */ 80606a504a75SDimitris Papastamos 80616a504a75SDimitris Papastamos /* 80626a504a75SDimitris Papastamos * R12725 (0x31B5) - Write Sequencer 437 80636a504a75SDimitris Papastamos */ 80646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA109_MASK 0x00FF /* WSEQ_DATA109 - [7:0] */ 80656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA109_SHIFT 0 /* WSEQ_DATA109 - [7:0] */ 80666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA109_WIDTH 8 /* WSEQ_DATA109 - [7:0] */ 80676a504a75SDimitris Papastamos 80686a504a75SDimitris Papastamos /* 80696a504a75SDimitris Papastamos * R12726 (0x31B6) - Write Sequencer 438 80706a504a75SDimitris Papastamos */ 80716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH109_MASK 0x0700 /* WSEQ_DATA_WIDTH109 - [10:8] */ 80726a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH109_SHIFT 8 /* WSEQ_DATA_WIDTH109 - [10:8] */ 80736a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH109_WIDTH 3 /* WSEQ_DATA_WIDTH109 - [10:8] */ 80746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START109_MASK 0x000F /* WSEQ_DATA_START109 - [3:0] */ 80756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START109_SHIFT 0 /* WSEQ_DATA_START109 - [3:0] */ 80766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START109_WIDTH 4 /* WSEQ_DATA_START109 - [3:0] */ 80776a504a75SDimitris Papastamos 80786a504a75SDimitris Papastamos /* 80796a504a75SDimitris Papastamos * R12727 (0x31B7) - Write Sequencer 439 80806a504a75SDimitris Papastamos */ 80816a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS109 0x0100 /* WSEQ_EOS109 */ 80826a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS109_MASK 0x0100 /* WSEQ_EOS109 */ 80836a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS109_SHIFT 8 /* WSEQ_EOS109 */ 80846a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS109_WIDTH 1 /* WSEQ_EOS109 */ 80856a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY109_MASK 0x000F /* WSEQ_DELAY109 - [3:0] */ 80866a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY109_SHIFT 0 /* WSEQ_DELAY109 - [3:0] */ 80876a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY109_WIDTH 4 /* WSEQ_DELAY109 - [3:0] */ 80886a504a75SDimitris Papastamos 80896a504a75SDimitris Papastamos /* 80906a504a75SDimitris Papastamos * R12728 (0x31B8) - Write Sequencer 440 80916a504a75SDimitris Papastamos */ 80926a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR110_MASK 0x3FFF /* WSEQ_ADDR110 - [13:0] */ 80936a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR110_SHIFT 0 /* WSEQ_ADDR110 - [13:0] */ 80946a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR110_WIDTH 14 /* WSEQ_ADDR110 - [13:0] */ 80956a504a75SDimitris Papastamos 80966a504a75SDimitris Papastamos /* 80976a504a75SDimitris Papastamos * R12729 (0x31B9) - Write Sequencer 441 80986a504a75SDimitris Papastamos */ 80996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA110_MASK 0x00FF /* WSEQ_DATA110 - [7:0] */ 81006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA110_SHIFT 0 /* WSEQ_DATA110 - [7:0] */ 81016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA110_WIDTH 8 /* WSEQ_DATA110 - [7:0] */ 81026a504a75SDimitris Papastamos 81036a504a75SDimitris Papastamos /* 81046a504a75SDimitris Papastamos * R12730 (0x31BA) - Write Sequencer 442 81056a504a75SDimitris Papastamos */ 81066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH110_MASK 0x0700 /* WSEQ_DATA_WIDTH110 - [10:8] */ 81076a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH110_SHIFT 8 /* WSEQ_DATA_WIDTH110 - [10:8] */ 81086a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH110_WIDTH 3 /* WSEQ_DATA_WIDTH110 - [10:8] */ 81096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START110_MASK 0x000F /* WSEQ_DATA_START110 - [3:0] */ 81106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START110_SHIFT 0 /* WSEQ_DATA_START110 - [3:0] */ 81116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START110_WIDTH 4 /* WSEQ_DATA_START110 - [3:0] */ 81126a504a75SDimitris Papastamos 81136a504a75SDimitris Papastamos /* 81146a504a75SDimitris Papastamos * R12731 (0x31BB) - Write Sequencer 443 81156a504a75SDimitris Papastamos */ 81166a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS110 0x0100 /* WSEQ_EOS110 */ 81176a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS110_MASK 0x0100 /* WSEQ_EOS110 */ 81186a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS110_SHIFT 8 /* WSEQ_EOS110 */ 81196a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS110_WIDTH 1 /* WSEQ_EOS110 */ 81206a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY110_MASK 0x000F /* WSEQ_DELAY110 - [3:0] */ 81216a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY110_SHIFT 0 /* WSEQ_DELAY110 - [3:0] */ 81226a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY110_WIDTH 4 /* WSEQ_DELAY110 - [3:0] */ 81236a504a75SDimitris Papastamos 81246a504a75SDimitris Papastamos /* 81256a504a75SDimitris Papastamos * R12732 (0x31BC) - Write Sequencer 444 81266a504a75SDimitris Papastamos */ 81276a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR111_MASK 0x3FFF /* WSEQ_ADDR111 - [13:0] */ 81286a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR111_SHIFT 0 /* WSEQ_ADDR111 - [13:0] */ 81296a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR111_WIDTH 14 /* WSEQ_ADDR111 - [13:0] */ 81306a504a75SDimitris Papastamos 81316a504a75SDimitris Papastamos /* 81326a504a75SDimitris Papastamos * R12733 (0x31BD) - Write Sequencer 445 81336a504a75SDimitris Papastamos */ 81346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA111_MASK 0x00FF /* WSEQ_DATA111 - [7:0] */ 81356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA111_SHIFT 0 /* WSEQ_DATA111 - [7:0] */ 81366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA111_WIDTH 8 /* WSEQ_DATA111 - [7:0] */ 81376a504a75SDimitris Papastamos 81386a504a75SDimitris Papastamos /* 81396a504a75SDimitris Papastamos * R12734 (0x31BE) - Write Sequencer 446 81406a504a75SDimitris Papastamos */ 81416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH111_MASK 0x0700 /* WSEQ_DATA_WIDTH111 - [10:8] */ 81426a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH111_SHIFT 8 /* WSEQ_DATA_WIDTH111 - [10:8] */ 81436a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH111_WIDTH 3 /* WSEQ_DATA_WIDTH111 - [10:8] */ 81446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START111_MASK 0x000F /* WSEQ_DATA_START111 - [3:0] */ 81456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START111_SHIFT 0 /* WSEQ_DATA_START111 - [3:0] */ 81466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START111_WIDTH 4 /* WSEQ_DATA_START111 - [3:0] */ 81476a504a75SDimitris Papastamos 81486a504a75SDimitris Papastamos /* 81496a504a75SDimitris Papastamos * R12735 (0x31BF) - Write Sequencer 447 81506a504a75SDimitris Papastamos */ 81516a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS111 0x0100 /* WSEQ_EOS111 */ 81526a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS111_MASK 0x0100 /* WSEQ_EOS111 */ 81536a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS111_SHIFT 8 /* WSEQ_EOS111 */ 81546a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS111_WIDTH 1 /* WSEQ_EOS111 */ 81556a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY111_MASK 0x000F /* WSEQ_DELAY111 - [3:0] */ 81566a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY111_SHIFT 0 /* WSEQ_DELAY111 - [3:0] */ 81576a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY111_WIDTH 4 /* WSEQ_DELAY111 - [3:0] */ 81586a504a75SDimitris Papastamos 81596a504a75SDimitris Papastamos /* 81606a504a75SDimitris Papastamos * R12736 (0x31C0) - Write Sequencer 448 81616a504a75SDimitris Papastamos */ 81626a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR112_MASK 0x3FFF /* WSEQ_ADDR112 - [13:0] */ 81636a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR112_SHIFT 0 /* WSEQ_ADDR112 - [13:0] */ 81646a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR112_WIDTH 14 /* WSEQ_ADDR112 - [13:0] */ 81656a504a75SDimitris Papastamos 81666a504a75SDimitris Papastamos /* 81676a504a75SDimitris Papastamos * R12737 (0x31C1) - Write Sequencer 449 81686a504a75SDimitris Papastamos */ 81696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA112_MASK 0x00FF /* WSEQ_DATA112 - [7:0] */ 81706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA112_SHIFT 0 /* WSEQ_DATA112 - [7:0] */ 81716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA112_WIDTH 8 /* WSEQ_DATA112 - [7:0] */ 81726a504a75SDimitris Papastamos 81736a504a75SDimitris Papastamos /* 81746a504a75SDimitris Papastamos * R12738 (0x31C2) - Write Sequencer 450 81756a504a75SDimitris Papastamos */ 81766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH112_MASK 0x0700 /* WSEQ_DATA_WIDTH112 - [10:8] */ 81776a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH112_SHIFT 8 /* WSEQ_DATA_WIDTH112 - [10:8] */ 81786a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH112_WIDTH 3 /* WSEQ_DATA_WIDTH112 - [10:8] */ 81796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START112_MASK 0x000F /* WSEQ_DATA_START112 - [3:0] */ 81806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START112_SHIFT 0 /* WSEQ_DATA_START112 - [3:0] */ 81816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START112_WIDTH 4 /* WSEQ_DATA_START112 - [3:0] */ 81826a504a75SDimitris Papastamos 81836a504a75SDimitris Papastamos /* 81846a504a75SDimitris Papastamos * R12739 (0x31C3) - Write Sequencer 451 81856a504a75SDimitris Papastamos */ 81866a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS112 0x0100 /* WSEQ_EOS112 */ 81876a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS112_MASK 0x0100 /* WSEQ_EOS112 */ 81886a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS112_SHIFT 8 /* WSEQ_EOS112 */ 81896a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS112_WIDTH 1 /* WSEQ_EOS112 */ 81906a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY112_MASK 0x000F /* WSEQ_DELAY112 - [3:0] */ 81916a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY112_SHIFT 0 /* WSEQ_DELAY112 - [3:0] */ 81926a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY112_WIDTH 4 /* WSEQ_DELAY112 - [3:0] */ 81936a504a75SDimitris Papastamos 81946a504a75SDimitris Papastamos /* 81956a504a75SDimitris Papastamos * R12740 (0x31C4) - Write Sequencer 452 81966a504a75SDimitris Papastamos */ 81976a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR113_MASK 0x3FFF /* WSEQ_ADDR113 - [13:0] */ 81986a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR113_SHIFT 0 /* WSEQ_ADDR113 - [13:0] */ 81996a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR113_WIDTH 14 /* WSEQ_ADDR113 - [13:0] */ 82006a504a75SDimitris Papastamos 82016a504a75SDimitris Papastamos /* 82026a504a75SDimitris Papastamos * R12741 (0x31C5) - Write Sequencer 453 82036a504a75SDimitris Papastamos */ 82046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA113_MASK 0x00FF /* WSEQ_DATA113 - [7:0] */ 82056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA113_SHIFT 0 /* WSEQ_DATA113 - [7:0] */ 82066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA113_WIDTH 8 /* WSEQ_DATA113 - [7:0] */ 82076a504a75SDimitris Papastamos 82086a504a75SDimitris Papastamos /* 82096a504a75SDimitris Papastamos * R12742 (0x31C6) - Write Sequencer 454 82106a504a75SDimitris Papastamos */ 82116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH113_MASK 0x0700 /* WSEQ_DATA_WIDTH113 - [10:8] */ 82126a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH113_SHIFT 8 /* WSEQ_DATA_WIDTH113 - [10:8] */ 82136a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH113_WIDTH 3 /* WSEQ_DATA_WIDTH113 - [10:8] */ 82146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START113_MASK 0x000F /* WSEQ_DATA_START113 - [3:0] */ 82156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START113_SHIFT 0 /* WSEQ_DATA_START113 - [3:0] */ 82166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START113_WIDTH 4 /* WSEQ_DATA_START113 - [3:0] */ 82176a504a75SDimitris Papastamos 82186a504a75SDimitris Papastamos /* 82196a504a75SDimitris Papastamos * R12743 (0x31C7) - Write Sequencer 455 82206a504a75SDimitris Papastamos */ 82216a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS113 0x0100 /* WSEQ_EOS113 */ 82226a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS113_MASK 0x0100 /* WSEQ_EOS113 */ 82236a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS113_SHIFT 8 /* WSEQ_EOS113 */ 82246a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS113_WIDTH 1 /* WSEQ_EOS113 */ 82256a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY113_MASK 0x000F /* WSEQ_DELAY113 - [3:0] */ 82266a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY113_SHIFT 0 /* WSEQ_DELAY113 - [3:0] */ 82276a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY113_WIDTH 4 /* WSEQ_DELAY113 - [3:0] */ 82286a504a75SDimitris Papastamos 82296a504a75SDimitris Papastamos /* 82306a504a75SDimitris Papastamos * R12744 (0x31C8) - Write Sequencer 456 82316a504a75SDimitris Papastamos */ 82326a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR114_MASK 0x3FFF /* WSEQ_ADDR114 - [13:0] */ 82336a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR114_SHIFT 0 /* WSEQ_ADDR114 - [13:0] */ 82346a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR114_WIDTH 14 /* WSEQ_ADDR114 - [13:0] */ 82356a504a75SDimitris Papastamos 82366a504a75SDimitris Papastamos /* 82376a504a75SDimitris Papastamos * R12745 (0x31C9) - Write Sequencer 457 82386a504a75SDimitris Papastamos */ 82396a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA114_MASK 0x00FF /* WSEQ_DATA114 - [7:0] */ 82406a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA114_SHIFT 0 /* WSEQ_DATA114 - [7:0] */ 82416a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA114_WIDTH 8 /* WSEQ_DATA114 - [7:0] */ 82426a504a75SDimitris Papastamos 82436a504a75SDimitris Papastamos /* 82446a504a75SDimitris Papastamos * R12746 (0x31CA) - Write Sequencer 458 82456a504a75SDimitris Papastamos */ 82466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH114_MASK 0x0700 /* WSEQ_DATA_WIDTH114 - [10:8] */ 82476a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH114_SHIFT 8 /* WSEQ_DATA_WIDTH114 - [10:8] */ 82486a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH114_WIDTH 3 /* WSEQ_DATA_WIDTH114 - [10:8] */ 82496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START114_MASK 0x000F /* WSEQ_DATA_START114 - [3:0] */ 82506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START114_SHIFT 0 /* WSEQ_DATA_START114 - [3:0] */ 82516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START114_WIDTH 4 /* WSEQ_DATA_START114 - [3:0] */ 82526a504a75SDimitris Papastamos 82536a504a75SDimitris Papastamos /* 82546a504a75SDimitris Papastamos * R12747 (0x31CB) - Write Sequencer 459 82556a504a75SDimitris Papastamos */ 82566a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS114 0x0100 /* WSEQ_EOS114 */ 82576a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS114_MASK 0x0100 /* WSEQ_EOS114 */ 82586a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS114_SHIFT 8 /* WSEQ_EOS114 */ 82596a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS114_WIDTH 1 /* WSEQ_EOS114 */ 82606a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY114_MASK 0x000F /* WSEQ_DELAY114 - [3:0] */ 82616a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY114_SHIFT 0 /* WSEQ_DELAY114 - [3:0] */ 82626a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY114_WIDTH 4 /* WSEQ_DELAY114 - [3:0] */ 82636a504a75SDimitris Papastamos 82646a504a75SDimitris Papastamos /* 82656a504a75SDimitris Papastamos * R12748 (0x31CC) - Write Sequencer 460 82666a504a75SDimitris Papastamos */ 82676a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR115_MASK 0x3FFF /* WSEQ_ADDR115 - [13:0] */ 82686a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR115_SHIFT 0 /* WSEQ_ADDR115 - [13:0] */ 82696a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR115_WIDTH 14 /* WSEQ_ADDR115 - [13:0] */ 82706a504a75SDimitris Papastamos 82716a504a75SDimitris Papastamos /* 82726a504a75SDimitris Papastamos * R12749 (0x31CD) - Write Sequencer 461 82736a504a75SDimitris Papastamos */ 82746a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA115_MASK 0x00FF /* WSEQ_DATA115 - [7:0] */ 82756a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA115_SHIFT 0 /* WSEQ_DATA115 - [7:0] */ 82766a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA115_WIDTH 8 /* WSEQ_DATA115 - [7:0] */ 82776a504a75SDimitris Papastamos 82786a504a75SDimitris Papastamos /* 82796a504a75SDimitris Papastamos * R12750 (0x31CE) - Write Sequencer 462 82806a504a75SDimitris Papastamos */ 82816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH115_MASK 0x0700 /* WSEQ_DATA_WIDTH115 - [10:8] */ 82826a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH115_SHIFT 8 /* WSEQ_DATA_WIDTH115 - [10:8] */ 82836a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH115_WIDTH 3 /* WSEQ_DATA_WIDTH115 - [10:8] */ 82846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START115_MASK 0x000F /* WSEQ_DATA_START115 - [3:0] */ 82856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START115_SHIFT 0 /* WSEQ_DATA_START115 - [3:0] */ 82866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START115_WIDTH 4 /* WSEQ_DATA_START115 - [3:0] */ 82876a504a75SDimitris Papastamos 82886a504a75SDimitris Papastamos /* 82896a504a75SDimitris Papastamos * R12751 (0x31CF) - Write Sequencer 463 82906a504a75SDimitris Papastamos */ 82916a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS115 0x0100 /* WSEQ_EOS115 */ 82926a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS115_MASK 0x0100 /* WSEQ_EOS115 */ 82936a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS115_SHIFT 8 /* WSEQ_EOS115 */ 82946a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS115_WIDTH 1 /* WSEQ_EOS115 */ 82956a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY115_MASK 0x000F /* WSEQ_DELAY115 - [3:0] */ 82966a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY115_SHIFT 0 /* WSEQ_DELAY115 - [3:0] */ 82976a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY115_WIDTH 4 /* WSEQ_DELAY115 - [3:0] */ 82986a504a75SDimitris Papastamos 82996a504a75SDimitris Papastamos /* 83006a504a75SDimitris Papastamos * R12752 (0x31D0) - Write Sequencer 464 83016a504a75SDimitris Papastamos */ 83026a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR116_MASK 0x3FFF /* WSEQ_ADDR116 - [13:0] */ 83036a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR116_SHIFT 0 /* WSEQ_ADDR116 - [13:0] */ 83046a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR116_WIDTH 14 /* WSEQ_ADDR116 - [13:0] */ 83056a504a75SDimitris Papastamos 83066a504a75SDimitris Papastamos /* 83076a504a75SDimitris Papastamos * R12753 (0x31D1) - Write Sequencer 465 83086a504a75SDimitris Papastamos */ 83096a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA116_MASK 0x00FF /* WSEQ_DATA116 - [7:0] */ 83106a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA116_SHIFT 0 /* WSEQ_DATA116 - [7:0] */ 83116a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA116_WIDTH 8 /* WSEQ_DATA116 - [7:0] */ 83126a504a75SDimitris Papastamos 83136a504a75SDimitris Papastamos /* 83146a504a75SDimitris Papastamos * R12754 (0x31D2) - Write Sequencer 466 83156a504a75SDimitris Papastamos */ 83166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH116_MASK 0x0700 /* WSEQ_DATA_WIDTH116 - [10:8] */ 83176a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH116_SHIFT 8 /* WSEQ_DATA_WIDTH116 - [10:8] */ 83186a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH116_WIDTH 3 /* WSEQ_DATA_WIDTH116 - [10:8] */ 83196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START116_MASK 0x000F /* WSEQ_DATA_START116 - [3:0] */ 83206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START116_SHIFT 0 /* WSEQ_DATA_START116 - [3:0] */ 83216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START116_WIDTH 4 /* WSEQ_DATA_START116 - [3:0] */ 83226a504a75SDimitris Papastamos 83236a504a75SDimitris Papastamos /* 83246a504a75SDimitris Papastamos * R12755 (0x31D3) - Write Sequencer 467 83256a504a75SDimitris Papastamos */ 83266a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS116 0x0100 /* WSEQ_EOS116 */ 83276a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS116_MASK 0x0100 /* WSEQ_EOS116 */ 83286a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS116_SHIFT 8 /* WSEQ_EOS116 */ 83296a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS116_WIDTH 1 /* WSEQ_EOS116 */ 83306a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY116_MASK 0x000F /* WSEQ_DELAY116 - [3:0] */ 83316a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY116_SHIFT 0 /* WSEQ_DELAY116 - [3:0] */ 83326a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY116_WIDTH 4 /* WSEQ_DELAY116 - [3:0] */ 83336a504a75SDimitris Papastamos 83346a504a75SDimitris Papastamos /* 83356a504a75SDimitris Papastamos * R12756 (0x31D4) - Write Sequencer 468 83366a504a75SDimitris Papastamos */ 83376a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR117_MASK 0x3FFF /* WSEQ_ADDR117 - [13:0] */ 83386a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR117_SHIFT 0 /* WSEQ_ADDR117 - [13:0] */ 83396a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR117_WIDTH 14 /* WSEQ_ADDR117 - [13:0] */ 83406a504a75SDimitris Papastamos 83416a504a75SDimitris Papastamos /* 83426a504a75SDimitris Papastamos * R12757 (0x31D5) - Write Sequencer 469 83436a504a75SDimitris Papastamos */ 83446a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA117_MASK 0x00FF /* WSEQ_DATA117 - [7:0] */ 83456a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA117_SHIFT 0 /* WSEQ_DATA117 - [7:0] */ 83466a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA117_WIDTH 8 /* WSEQ_DATA117 - [7:0] */ 83476a504a75SDimitris Papastamos 83486a504a75SDimitris Papastamos /* 83496a504a75SDimitris Papastamos * R12758 (0x31D6) - Write Sequencer 470 83506a504a75SDimitris Papastamos */ 83516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH117_MASK 0x0700 /* WSEQ_DATA_WIDTH117 - [10:8] */ 83526a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH117_SHIFT 8 /* WSEQ_DATA_WIDTH117 - [10:8] */ 83536a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH117_WIDTH 3 /* WSEQ_DATA_WIDTH117 - [10:8] */ 83546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START117_MASK 0x000F /* WSEQ_DATA_START117 - [3:0] */ 83556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START117_SHIFT 0 /* WSEQ_DATA_START117 - [3:0] */ 83566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START117_WIDTH 4 /* WSEQ_DATA_START117 - [3:0] */ 83576a504a75SDimitris Papastamos 83586a504a75SDimitris Papastamos /* 83596a504a75SDimitris Papastamos * R12759 (0x31D7) - Write Sequencer 471 83606a504a75SDimitris Papastamos */ 83616a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS117 0x0100 /* WSEQ_EOS117 */ 83626a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS117_MASK 0x0100 /* WSEQ_EOS117 */ 83636a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS117_SHIFT 8 /* WSEQ_EOS117 */ 83646a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS117_WIDTH 1 /* WSEQ_EOS117 */ 83656a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY117_MASK 0x000F /* WSEQ_DELAY117 - [3:0] */ 83666a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY117_SHIFT 0 /* WSEQ_DELAY117 - [3:0] */ 83676a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY117_WIDTH 4 /* WSEQ_DELAY117 - [3:0] */ 83686a504a75SDimitris Papastamos 83696a504a75SDimitris Papastamos /* 83706a504a75SDimitris Papastamos * R12760 (0x31D8) - Write Sequencer 472 83716a504a75SDimitris Papastamos */ 83726a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR118_MASK 0x3FFF /* WSEQ_ADDR118 - [13:0] */ 83736a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR118_SHIFT 0 /* WSEQ_ADDR118 - [13:0] */ 83746a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR118_WIDTH 14 /* WSEQ_ADDR118 - [13:0] */ 83756a504a75SDimitris Papastamos 83766a504a75SDimitris Papastamos /* 83776a504a75SDimitris Papastamos * R12761 (0x31D9) - Write Sequencer 473 83786a504a75SDimitris Papastamos */ 83796a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA118_MASK 0x00FF /* WSEQ_DATA118 - [7:0] */ 83806a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA118_SHIFT 0 /* WSEQ_DATA118 - [7:0] */ 83816a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA118_WIDTH 8 /* WSEQ_DATA118 - [7:0] */ 83826a504a75SDimitris Papastamos 83836a504a75SDimitris Papastamos /* 83846a504a75SDimitris Papastamos * R12762 (0x31DA) - Write Sequencer 474 83856a504a75SDimitris Papastamos */ 83866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH118_MASK 0x0700 /* WSEQ_DATA_WIDTH118 - [10:8] */ 83876a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH118_SHIFT 8 /* WSEQ_DATA_WIDTH118 - [10:8] */ 83886a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH118_WIDTH 3 /* WSEQ_DATA_WIDTH118 - [10:8] */ 83896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START118_MASK 0x000F /* WSEQ_DATA_START118 - [3:0] */ 83906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START118_SHIFT 0 /* WSEQ_DATA_START118 - [3:0] */ 83916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START118_WIDTH 4 /* WSEQ_DATA_START118 - [3:0] */ 83926a504a75SDimitris Papastamos 83936a504a75SDimitris Papastamos /* 83946a504a75SDimitris Papastamos * R12763 (0x31DB) - Write Sequencer 475 83956a504a75SDimitris Papastamos */ 83966a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS118 0x0100 /* WSEQ_EOS118 */ 83976a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS118_MASK 0x0100 /* WSEQ_EOS118 */ 83986a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS118_SHIFT 8 /* WSEQ_EOS118 */ 83996a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS118_WIDTH 1 /* WSEQ_EOS118 */ 84006a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY118_MASK 0x000F /* WSEQ_DELAY118 - [3:0] */ 84016a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY118_SHIFT 0 /* WSEQ_DELAY118 - [3:0] */ 84026a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY118_WIDTH 4 /* WSEQ_DELAY118 - [3:0] */ 84036a504a75SDimitris Papastamos 84046a504a75SDimitris Papastamos /* 84056a504a75SDimitris Papastamos * R12764 (0x31DC) - Write Sequencer 476 84066a504a75SDimitris Papastamos */ 84076a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR119_MASK 0x3FFF /* WSEQ_ADDR119 - [13:0] */ 84086a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR119_SHIFT 0 /* WSEQ_ADDR119 - [13:0] */ 84096a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR119_WIDTH 14 /* WSEQ_ADDR119 - [13:0] */ 84106a504a75SDimitris Papastamos 84116a504a75SDimitris Papastamos /* 84126a504a75SDimitris Papastamos * R12765 (0x31DD) - Write Sequencer 477 84136a504a75SDimitris Papastamos */ 84146a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA119_MASK 0x00FF /* WSEQ_DATA119 - [7:0] */ 84156a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA119_SHIFT 0 /* WSEQ_DATA119 - [7:0] */ 84166a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA119_WIDTH 8 /* WSEQ_DATA119 - [7:0] */ 84176a504a75SDimitris Papastamos 84186a504a75SDimitris Papastamos /* 84196a504a75SDimitris Papastamos * R12766 (0x31DE) - Write Sequencer 478 84206a504a75SDimitris Papastamos */ 84216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH119_MASK 0x0700 /* WSEQ_DATA_WIDTH119 - [10:8] */ 84226a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH119_SHIFT 8 /* WSEQ_DATA_WIDTH119 - [10:8] */ 84236a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH119_WIDTH 3 /* WSEQ_DATA_WIDTH119 - [10:8] */ 84246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START119_MASK 0x000F /* WSEQ_DATA_START119 - [3:0] */ 84256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START119_SHIFT 0 /* WSEQ_DATA_START119 - [3:0] */ 84266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START119_WIDTH 4 /* WSEQ_DATA_START119 - [3:0] */ 84276a504a75SDimitris Papastamos 84286a504a75SDimitris Papastamos /* 84296a504a75SDimitris Papastamos * R12767 (0x31DF) - Write Sequencer 479 84306a504a75SDimitris Papastamos */ 84316a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS119 0x0100 /* WSEQ_EOS119 */ 84326a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS119_MASK 0x0100 /* WSEQ_EOS119 */ 84336a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS119_SHIFT 8 /* WSEQ_EOS119 */ 84346a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS119_WIDTH 1 /* WSEQ_EOS119 */ 84356a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY119_MASK 0x000F /* WSEQ_DELAY119 - [3:0] */ 84366a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY119_SHIFT 0 /* WSEQ_DELAY119 - [3:0] */ 84376a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY119_WIDTH 4 /* WSEQ_DELAY119 - [3:0] */ 84386a504a75SDimitris Papastamos 84396a504a75SDimitris Papastamos /* 84406a504a75SDimitris Papastamos * R12768 (0x31E0) - Write Sequencer 480 84416a504a75SDimitris Papastamos */ 84426a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR120_MASK 0x3FFF /* WSEQ_ADDR120 - [13:0] */ 84436a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR120_SHIFT 0 /* WSEQ_ADDR120 - [13:0] */ 84446a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR120_WIDTH 14 /* WSEQ_ADDR120 - [13:0] */ 84456a504a75SDimitris Papastamos 84466a504a75SDimitris Papastamos /* 84476a504a75SDimitris Papastamos * R12769 (0x31E1) - Write Sequencer 481 84486a504a75SDimitris Papastamos */ 84496a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA120_MASK 0x00FF /* WSEQ_DATA120 - [7:0] */ 84506a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA120_SHIFT 0 /* WSEQ_DATA120 - [7:0] */ 84516a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA120_WIDTH 8 /* WSEQ_DATA120 - [7:0] */ 84526a504a75SDimitris Papastamos 84536a504a75SDimitris Papastamos /* 84546a504a75SDimitris Papastamos * R12770 (0x31E2) - Write Sequencer 482 84556a504a75SDimitris Papastamos */ 84566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH120_MASK 0x0700 /* WSEQ_DATA_WIDTH120 - [10:8] */ 84576a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH120_SHIFT 8 /* WSEQ_DATA_WIDTH120 - [10:8] */ 84586a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH120_WIDTH 3 /* WSEQ_DATA_WIDTH120 - [10:8] */ 84596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START120_MASK 0x000F /* WSEQ_DATA_START120 - [3:0] */ 84606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START120_SHIFT 0 /* WSEQ_DATA_START120 - [3:0] */ 84616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START120_WIDTH 4 /* WSEQ_DATA_START120 - [3:0] */ 84626a504a75SDimitris Papastamos 84636a504a75SDimitris Papastamos /* 84646a504a75SDimitris Papastamos * R12771 (0x31E3) - Write Sequencer 483 84656a504a75SDimitris Papastamos */ 84666a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS120 0x0100 /* WSEQ_EOS120 */ 84676a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS120_MASK 0x0100 /* WSEQ_EOS120 */ 84686a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS120_SHIFT 8 /* WSEQ_EOS120 */ 84696a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS120_WIDTH 1 /* WSEQ_EOS120 */ 84706a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY120_MASK 0x000F /* WSEQ_DELAY120 - [3:0] */ 84716a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY120_SHIFT 0 /* WSEQ_DELAY120 - [3:0] */ 84726a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY120_WIDTH 4 /* WSEQ_DELAY120 - [3:0] */ 84736a504a75SDimitris Papastamos 84746a504a75SDimitris Papastamos /* 84756a504a75SDimitris Papastamos * R12772 (0x31E4) - Write Sequencer 484 84766a504a75SDimitris Papastamos */ 84776a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR121_MASK 0x3FFF /* WSEQ_ADDR121 - [13:0] */ 84786a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR121_SHIFT 0 /* WSEQ_ADDR121 - [13:0] */ 84796a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR121_WIDTH 14 /* WSEQ_ADDR121 - [13:0] */ 84806a504a75SDimitris Papastamos 84816a504a75SDimitris Papastamos /* 84826a504a75SDimitris Papastamos * R12773 (0x31E5) - Write Sequencer 485 84836a504a75SDimitris Papastamos */ 84846a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA121_MASK 0x00FF /* WSEQ_DATA121 - [7:0] */ 84856a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA121_SHIFT 0 /* WSEQ_DATA121 - [7:0] */ 84866a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA121_WIDTH 8 /* WSEQ_DATA121 - [7:0] */ 84876a504a75SDimitris Papastamos 84886a504a75SDimitris Papastamos /* 84896a504a75SDimitris Papastamos * R12774 (0x31E6) - Write Sequencer 486 84906a504a75SDimitris Papastamos */ 84916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH121_MASK 0x0700 /* WSEQ_DATA_WIDTH121 - [10:8] */ 84926a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH121_SHIFT 8 /* WSEQ_DATA_WIDTH121 - [10:8] */ 84936a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH121_WIDTH 3 /* WSEQ_DATA_WIDTH121 - [10:8] */ 84946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START121_MASK 0x000F /* WSEQ_DATA_START121 - [3:0] */ 84956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START121_SHIFT 0 /* WSEQ_DATA_START121 - [3:0] */ 84966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START121_WIDTH 4 /* WSEQ_DATA_START121 - [3:0] */ 84976a504a75SDimitris Papastamos 84986a504a75SDimitris Papastamos /* 84996a504a75SDimitris Papastamos * R12775 (0x31E7) - Write Sequencer 487 85006a504a75SDimitris Papastamos */ 85016a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS121 0x0100 /* WSEQ_EOS121 */ 85026a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS121_MASK 0x0100 /* WSEQ_EOS121 */ 85036a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS121_SHIFT 8 /* WSEQ_EOS121 */ 85046a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS121_WIDTH 1 /* WSEQ_EOS121 */ 85056a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY121_MASK 0x000F /* WSEQ_DELAY121 - [3:0] */ 85066a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY121_SHIFT 0 /* WSEQ_DELAY121 - [3:0] */ 85076a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY121_WIDTH 4 /* WSEQ_DELAY121 - [3:0] */ 85086a504a75SDimitris Papastamos 85096a504a75SDimitris Papastamos /* 85106a504a75SDimitris Papastamos * R12776 (0x31E8) - Write Sequencer 488 85116a504a75SDimitris Papastamos */ 85126a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR122_MASK 0x3FFF /* WSEQ_ADDR122 - [13:0] */ 85136a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR122_SHIFT 0 /* WSEQ_ADDR122 - [13:0] */ 85146a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR122_WIDTH 14 /* WSEQ_ADDR122 - [13:0] */ 85156a504a75SDimitris Papastamos 85166a504a75SDimitris Papastamos /* 85176a504a75SDimitris Papastamos * R12777 (0x31E9) - Write Sequencer 489 85186a504a75SDimitris Papastamos */ 85196a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA122_MASK 0x00FF /* WSEQ_DATA122 - [7:0] */ 85206a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA122_SHIFT 0 /* WSEQ_DATA122 - [7:0] */ 85216a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA122_WIDTH 8 /* WSEQ_DATA122 - [7:0] */ 85226a504a75SDimitris Papastamos 85236a504a75SDimitris Papastamos /* 85246a504a75SDimitris Papastamos * R12778 (0x31EA) - Write Sequencer 490 85256a504a75SDimitris Papastamos */ 85266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH122_MASK 0x0700 /* WSEQ_DATA_WIDTH122 - [10:8] */ 85276a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH122_SHIFT 8 /* WSEQ_DATA_WIDTH122 - [10:8] */ 85286a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH122_WIDTH 3 /* WSEQ_DATA_WIDTH122 - [10:8] */ 85296a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START122_MASK 0x000F /* WSEQ_DATA_START122 - [3:0] */ 85306a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START122_SHIFT 0 /* WSEQ_DATA_START122 - [3:0] */ 85316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START122_WIDTH 4 /* WSEQ_DATA_START122 - [3:0] */ 85326a504a75SDimitris Papastamos 85336a504a75SDimitris Papastamos /* 85346a504a75SDimitris Papastamos * R12779 (0x31EB) - Write Sequencer 491 85356a504a75SDimitris Papastamos */ 85366a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS122 0x0100 /* WSEQ_EOS122 */ 85376a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS122_MASK 0x0100 /* WSEQ_EOS122 */ 85386a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS122_SHIFT 8 /* WSEQ_EOS122 */ 85396a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS122_WIDTH 1 /* WSEQ_EOS122 */ 85406a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY122_MASK 0x000F /* WSEQ_DELAY122 - [3:0] */ 85416a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY122_SHIFT 0 /* WSEQ_DELAY122 - [3:0] */ 85426a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY122_WIDTH 4 /* WSEQ_DELAY122 - [3:0] */ 85436a504a75SDimitris Papastamos 85446a504a75SDimitris Papastamos /* 85456a504a75SDimitris Papastamos * R12780 (0x31EC) - Write Sequencer 492 85466a504a75SDimitris Papastamos */ 85476a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR123_MASK 0x3FFF /* WSEQ_ADDR123 - [13:0] */ 85486a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR123_SHIFT 0 /* WSEQ_ADDR123 - [13:0] */ 85496a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR123_WIDTH 14 /* WSEQ_ADDR123 - [13:0] */ 85506a504a75SDimitris Papastamos 85516a504a75SDimitris Papastamos /* 85526a504a75SDimitris Papastamos * R12781 (0x31ED) - Write Sequencer 493 85536a504a75SDimitris Papastamos */ 85546a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA123_MASK 0x00FF /* WSEQ_DATA123 - [7:0] */ 85556a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA123_SHIFT 0 /* WSEQ_DATA123 - [7:0] */ 85566a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA123_WIDTH 8 /* WSEQ_DATA123 - [7:0] */ 85576a504a75SDimitris Papastamos 85586a504a75SDimitris Papastamos /* 85596a504a75SDimitris Papastamos * R12782 (0x31EE) - Write Sequencer 494 85606a504a75SDimitris Papastamos */ 85616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH123_MASK 0x0700 /* WSEQ_DATA_WIDTH123 - [10:8] */ 85626a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH123_SHIFT 8 /* WSEQ_DATA_WIDTH123 - [10:8] */ 85636a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH123_WIDTH 3 /* WSEQ_DATA_WIDTH123 - [10:8] */ 85646a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START123_MASK 0x000F /* WSEQ_DATA_START123 - [3:0] */ 85656a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START123_SHIFT 0 /* WSEQ_DATA_START123 - [3:0] */ 85666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START123_WIDTH 4 /* WSEQ_DATA_START123 - [3:0] */ 85676a504a75SDimitris Papastamos 85686a504a75SDimitris Papastamos /* 85696a504a75SDimitris Papastamos * R12783 (0x31EF) - Write Sequencer 495 85706a504a75SDimitris Papastamos */ 85716a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS123 0x0100 /* WSEQ_EOS123 */ 85726a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS123_MASK 0x0100 /* WSEQ_EOS123 */ 85736a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS123_SHIFT 8 /* WSEQ_EOS123 */ 85746a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS123_WIDTH 1 /* WSEQ_EOS123 */ 85756a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY123_MASK 0x000F /* WSEQ_DELAY123 - [3:0] */ 85766a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY123_SHIFT 0 /* WSEQ_DELAY123 - [3:0] */ 85776a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY123_WIDTH 4 /* WSEQ_DELAY123 - [3:0] */ 85786a504a75SDimitris Papastamos 85796a504a75SDimitris Papastamos /* 85806a504a75SDimitris Papastamos * R12784 (0x31F0) - Write Sequencer 496 85816a504a75SDimitris Papastamos */ 85826a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR124_MASK 0x3FFF /* WSEQ_ADDR124 - [13:0] */ 85836a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR124_SHIFT 0 /* WSEQ_ADDR124 - [13:0] */ 85846a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR124_WIDTH 14 /* WSEQ_ADDR124 - [13:0] */ 85856a504a75SDimitris Papastamos 85866a504a75SDimitris Papastamos /* 85876a504a75SDimitris Papastamos * R12785 (0x31F1) - Write Sequencer 497 85886a504a75SDimitris Papastamos */ 85896a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA124_MASK 0x00FF /* WSEQ_DATA124 - [7:0] */ 85906a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA124_SHIFT 0 /* WSEQ_DATA124 - [7:0] */ 85916a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA124_WIDTH 8 /* WSEQ_DATA124 - [7:0] */ 85926a504a75SDimitris Papastamos 85936a504a75SDimitris Papastamos /* 85946a504a75SDimitris Papastamos * R12786 (0x31F2) - Write Sequencer 498 85956a504a75SDimitris Papastamos */ 85966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH124_MASK 0x0700 /* WSEQ_DATA_WIDTH124 - [10:8] */ 85976a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH124_SHIFT 8 /* WSEQ_DATA_WIDTH124 - [10:8] */ 85986a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH124_WIDTH 3 /* WSEQ_DATA_WIDTH124 - [10:8] */ 85996a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START124_MASK 0x000F /* WSEQ_DATA_START124 - [3:0] */ 86006a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START124_SHIFT 0 /* WSEQ_DATA_START124 - [3:0] */ 86016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START124_WIDTH 4 /* WSEQ_DATA_START124 - [3:0] */ 86026a504a75SDimitris Papastamos 86036a504a75SDimitris Papastamos /* 86046a504a75SDimitris Papastamos * R12787 (0x31F3) - Write Sequencer 499 86056a504a75SDimitris Papastamos */ 86066a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS124 0x0100 /* WSEQ_EOS124 */ 86076a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS124_MASK 0x0100 /* WSEQ_EOS124 */ 86086a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS124_SHIFT 8 /* WSEQ_EOS124 */ 86096a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS124_WIDTH 1 /* WSEQ_EOS124 */ 86106a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY124_MASK 0x000F /* WSEQ_DELAY124 - [3:0] */ 86116a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY124_SHIFT 0 /* WSEQ_DELAY124 - [3:0] */ 86126a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY124_WIDTH 4 /* WSEQ_DELAY124 - [3:0] */ 86136a504a75SDimitris Papastamos 86146a504a75SDimitris Papastamos /* 86156a504a75SDimitris Papastamos * R12788 (0x31F4) - Write Sequencer 500 86166a504a75SDimitris Papastamos */ 86176a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR125_MASK 0x3FFF /* WSEQ_ADDR125 - [13:0] */ 86186a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR125_SHIFT 0 /* WSEQ_ADDR125 - [13:0] */ 86196a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR125_WIDTH 14 /* WSEQ_ADDR125 - [13:0] */ 86206a504a75SDimitris Papastamos 86216a504a75SDimitris Papastamos /* 86226a504a75SDimitris Papastamos * R12789 (0x31F5) - Write Sequencer 501 86236a504a75SDimitris Papastamos */ 86246a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA125_MASK 0x00FF /* WSEQ_DATA125 - [7:0] */ 86256a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA125_SHIFT 0 /* WSEQ_DATA125 - [7:0] */ 86266a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA125_WIDTH 8 /* WSEQ_DATA125 - [7:0] */ 86276a504a75SDimitris Papastamos 86286a504a75SDimitris Papastamos /* 86296a504a75SDimitris Papastamos * R12790 (0x31F6) - Write Sequencer 502 86306a504a75SDimitris Papastamos */ 86316a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH125_MASK 0x0700 /* WSEQ_DATA_WIDTH125 - [10:8] */ 86326a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH125_SHIFT 8 /* WSEQ_DATA_WIDTH125 - [10:8] */ 86336a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH125_WIDTH 3 /* WSEQ_DATA_WIDTH125 - [10:8] */ 86346a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START125_MASK 0x000F /* WSEQ_DATA_START125 - [3:0] */ 86356a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START125_SHIFT 0 /* WSEQ_DATA_START125 - [3:0] */ 86366a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START125_WIDTH 4 /* WSEQ_DATA_START125 - [3:0] */ 86376a504a75SDimitris Papastamos 86386a504a75SDimitris Papastamos /* 86396a504a75SDimitris Papastamos * R12791 (0x31F7) - Write Sequencer 503 86406a504a75SDimitris Papastamos */ 86416a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS125 0x0100 /* WSEQ_EOS125 */ 86426a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS125_MASK 0x0100 /* WSEQ_EOS125 */ 86436a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS125_SHIFT 8 /* WSEQ_EOS125 */ 86446a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS125_WIDTH 1 /* WSEQ_EOS125 */ 86456a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY125_MASK 0x000F /* WSEQ_DELAY125 - [3:0] */ 86466a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY125_SHIFT 0 /* WSEQ_DELAY125 - [3:0] */ 86476a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY125_WIDTH 4 /* WSEQ_DELAY125 - [3:0] */ 86486a504a75SDimitris Papastamos 86496a504a75SDimitris Papastamos /* 86506a504a75SDimitris Papastamos * R12792 (0x31F8) - Write Sequencer 504 86516a504a75SDimitris Papastamos */ 86526a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR126_MASK 0x3FFF /* WSEQ_ADDR126 - [13:0] */ 86536a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR126_SHIFT 0 /* WSEQ_ADDR126 - [13:0] */ 86546a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR126_WIDTH 14 /* WSEQ_ADDR126 - [13:0] */ 86556a504a75SDimitris Papastamos 86566a504a75SDimitris Papastamos /* 86576a504a75SDimitris Papastamos * R12793 (0x31F9) - Write Sequencer 505 86586a504a75SDimitris Papastamos */ 86596a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA126_MASK 0x00FF /* WSEQ_DATA126 - [7:0] */ 86606a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA126_SHIFT 0 /* WSEQ_DATA126 - [7:0] */ 86616a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA126_WIDTH 8 /* WSEQ_DATA126 - [7:0] */ 86626a504a75SDimitris Papastamos 86636a504a75SDimitris Papastamos /* 86646a504a75SDimitris Papastamos * R12794 (0x31FA) - Write Sequencer 506 86656a504a75SDimitris Papastamos */ 86666a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH126_MASK 0x0700 /* WSEQ_DATA_WIDTH126 - [10:8] */ 86676a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH126_SHIFT 8 /* WSEQ_DATA_WIDTH126 - [10:8] */ 86686a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH126_WIDTH 3 /* WSEQ_DATA_WIDTH126 - [10:8] */ 86696a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START126_MASK 0x000F /* WSEQ_DATA_START126 - [3:0] */ 86706a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START126_SHIFT 0 /* WSEQ_DATA_START126 - [3:0] */ 86716a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START126_WIDTH 4 /* WSEQ_DATA_START126 - [3:0] */ 86726a504a75SDimitris Papastamos 86736a504a75SDimitris Papastamos /* 86746a504a75SDimitris Papastamos * R12795 (0x31FB) - Write Sequencer 507 86756a504a75SDimitris Papastamos */ 86766a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS126 0x0100 /* WSEQ_EOS126 */ 86776a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS126_MASK 0x0100 /* WSEQ_EOS126 */ 86786a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS126_SHIFT 8 /* WSEQ_EOS126 */ 86796a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS126_WIDTH 1 /* WSEQ_EOS126 */ 86806a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY126_MASK 0x000F /* WSEQ_DELAY126 - [3:0] */ 86816a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY126_SHIFT 0 /* WSEQ_DELAY126 - [3:0] */ 86826a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY126_WIDTH 4 /* WSEQ_DELAY126 - [3:0] */ 86836a504a75SDimitris Papastamos 86846a504a75SDimitris Papastamos /* 86856a504a75SDimitris Papastamos * R12796 (0x31FC) - Write Sequencer 508 86866a504a75SDimitris Papastamos */ 86876a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR127_MASK 0x3FFF /* WSEQ_ADDR127 - [13:0] */ 86886a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR127_SHIFT 0 /* WSEQ_ADDR127 - [13:0] */ 86896a504a75SDimitris Papastamos #define WM8995_WSEQ_ADDR127_WIDTH 14 /* WSEQ_ADDR127 - [13:0] */ 86906a504a75SDimitris Papastamos 86916a504a75SDimitris Papastamos /* 86926a504a75SDimitris Papastamos * R12797 (0x31FD) - Write Sequencer 509 86936a504a75SDimitris Papastamos */ 86946a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA127_MASK 0x00FF /* WSEQ_DATA127 - [7:0] */ 86956a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA127_SHIFT 0 /* WSEQ_DATA127 - [7:0] */ 86966a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA127_WIDTH 8 /* WSEQ_DATA127 - [7:0] */ 86976a504a75SDimitris Papastamos 86986a504a75SDimitris Papastamos /* 86996a504a75SDimitris Papastamos * R12798 (0x31FE) - Write Sequencer 510 87006a504a75SDimitris Papastamos */ 87016a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH127_MASK 0x0700 /* WSEQ_DATA_WIDTH127 - [10:8] */ 87026a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH127_SHIFT 8 /* WSEQ_DATA_WIDTH127 - [10:8] */ 87036a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_WIDTH127_WIDTH 3 /* WSEQ_DATA_WIDTH127 - [10:8] */ 87046a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START127_MASK 0x000F /* WSEQ_DATA_START127 - [3:0] */ 87056a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START127_SHIFT 0 /* WSEQ_DATA_START127 - [3:0] */ 87066a504a75SDimitris Papastamos #define WM8995_WSEQ_DATA_START127_WIDTH 4 /* WSEQ_DATA_START127 - [3:0] */ 87076a504a75SDimitris Papastamos 87086a504a75SDimitris Papastamos /* 87096a504a75SDimitris Papastamos * R12799 (0x31FF) - Write Sequencer 511 87106a504a75SDimitris Papastamos */ 87116a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS127 0x0100 /* WSEQ_EOS127 */ 87126a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS127_MASK 0x0100 /* WSEQ_EOS127 */ 87136a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS127_SHIFT 8 /* WSEQ_EOS127 */ 87146a504a75SDimitris Papastamos #define WM8995_WSEQ_EOS127_WIDTH 1 /* WSEQ_EOS127 */ 87156a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY127_MASK 0x000F /* WSEQ_DELAY127 - [3:0] */ 87166a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY127_SHIFT 0 /* WSEQ_DELAY127 - [3:0] */ 87176a504a75SDimitris Papastamos #define WM8995_WSEQ_DELAY127_WIDTH 4 /* WSEQ_DELAY127 - [3:0] */ 87186a504a75SDimitris Papastamos 87196a504a75SDimitris Papastamos #define WM8995_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ 87206a504a75SDimitris Papastamos { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 87216a504a75SDimitris Papastamos .info = snd_soc_info_volsw, \ 87226a504a75SDimitris Papastamos .get = snd_soc_dapm_get_volsw, .put = wm8995_put_class_w, \ 87236a504a75SDimitris Papastamos .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) \ 87246a504a75SDimitris Papastamos } 87256a504a75SDimitris Papastamos 87266a504a75SDimitris Papastamos struct wm8995_reg_access { 87276a504a75SDimitris Papastamos u16 read; 87286a504a75SDimitris Papastamos u16 write; 87296a504a75SDimitris Papastamos u16 vol; 87306a504a75SDimitris Papastamos }; 87316a504a75SDimitris Papastamos 87326a504a75SDimitris Papastamos /* Sources for AIF1/2 SYSCLK - use with set_dai_sysclk() */ 87336a504a75SDimitris Papastamos enum clk_src { 87346a504a75SDimitris Papastamos WM8995_SYSCLK_MCLK1 = 1, 87356a504a75SDimitris Papastamos WM8995_SYSCLK_MCLK2, 87366a504a75SDimitris Papastamos WM8995_SYSCLK_FLL1, 87376a504a75SDimitris Papastamos WM8995_SYSCLK_FLL2, 87386a504a75SDimitris Papastamos WM8995_SYSCLK_OPCLK 87396a504a75SDimitris Papastamos }; 87406a504a75SDimitris Papastamos 87416a504a75SDimitris Papastamos #define WM8995_FLL1 1 87426a504a75SDimitris Papastamos #define WM8995_FLL2 2 87436a504a75SDimitris Papastamos 87446a504a75SDimitris Papastamos #define WM8995_FLL_SRC_MCLK1 1 87456a504a75SDimitris Papastamos #define WM8995_FLL_SRC_MCLK2 2 87466a504a75SDimitris Papastamos #define WM8995_FLL_SRC_LRCLK 3 87476a504a75SDimitris Papastamos #define WM8995_FLL_SRC_BCLK 4 87486a504a75SDimitris Papastamos 87496a504a75SDimitris Papastamos #endif /* _WM8995_H */ 8750