1 /* 2 * wm8995.c -- WM8995 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Wolfson Microelectronics plc 5 * 6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> 7 * 8 * Based on wm8994.c and wm_hubs.c by Mark Brown 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/moduleparam.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 #include <linux/pm.h> 20 #include <linux/i2c.h> 21 #include <linux/regmap.h> 22 #include <linux/spi/spi.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/pcm_params.h> 28 #include <sound/soc.h> 29 #include <sound/soc-dapm.h> 30 #include <sound/initval.h> 31 #include <sound/tlv.h> 32 33 #include "wm8995.h" 34 35 #define WM8995_NUM_SUPPLIES 8 36 static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { 37 "DCVDD", 38 "DBVDD1", 39 "DBVDD2", 40 "DBVDD3", 41 "AVDD1", 42 "AVDD2", 43 "CPVDD", 44 "MICVDD" 45 }; 46 47 static struct reg_default wm8995_reg_defaults[] = { 48 { 0, 0x8995 }, 49 { 5, 0x0100 }, 50 { 16, 0x000b }, 51 { 17, 0x000b }, 52 { 24, 0x02c0 }, 53 { 25, 0x02c0 }, 54 { 26, 0x02c0 }, 55 { 27, 0x02c0 }, 56 { 28, 0x000f }, 57 { 32, 0x0005 }, 58 { 33, 0x0005 }, 59 { 40, 0x0003 }, 60 { 41, 0x0013 }, 61 { 48, 0x0004 }, 62 { 56, 0x09f8 }, 63 { 64, 0x1f25 }, 64 { 69, 0x0004 }, 65 { 82, 0xaaaa }, 66 { 84, 0x2a2a }, 67 { 146, 0x0060 }, 68 { 256, 0x0002 }, 69 { 257, 0x8004 }, 70 { 520, 0x0010 }, 71 { 528, 0x0083 }, 72 { 529, 0x0083 }, 73 { 548, 0x0c80 }, 74 { 580, 0x0c80 }, 75 { 768, 0x4050 }, 76 { 769, 0x4000 }, 77 { 771, 0x0040 }, 78 { 772, 0x0040 }, 79 { 773, 0x0040 }, 80 { 774, 0x0004 }, 81 { 775, 0x0100 }, 82 { 784, 0x4050 }, 83 { 785, 0x4000 }, 84 { 787, 0x0040 }, 85 { 788, 0x0040 }, 86 { 789, 0x0040 }, 87 { 1024, 0x00c0 }, 88 { 1025, 0x00c0 }, 89 { 1026, 0x00c0 }, 90 { 1027, 0x00c0 }, 91 { 1028, 0x00c0 }, 92 { 1029, 0x00c0 }, 93 { 1030, 0x00c0 }, 94 { 1031, 0x00c0 }, 95 { 1056, 0x0200 }, 96 { 1057, 0x0010 }, 97 { 1058, 0x0200 }, 98 { 1059, 0x0010 }, 99 { 1088, 0x0098 }, 100 { 1089, 0x0845 }, 101 { 1104, 0x0098 }, 102 { 1105, 0x0845 }, 103 { 1152, 0x6318 }, 104 { 1153, 0x6300 }, 105 { 1154, 0x0fca }, 106 { 1155, 0x0400 }, 107 { 1156, 0x00d8 }, 108 { 1157, 0x1eb5 }, 109 { 1158, 0xf145 }, 110 { 1159, 0x0b75 }, 111 { 1160, 0x01c5 }, 112 { 1161, 0x1c58 }, 113 { 1162, 0xf373 }, 114 { 1163, 0x0a54 }, 115 { 1164, 0x0558 }, 116 { 1165, 0x168e }, 117 { 1166, 0xf829 }, 118 { 1167, 0x07ad }, 119 { 1168, 0x1103 }, 120 { 1169, 0x0564 }, 121 { 1170, 0x0559 }, 122 { 1171, 0x4000 }, 123 { 1184, 0x6318 }, 124 { 1185, 0x6300 }, 125 { 1186, 0x0fca }, 126 { 1187, 0x0400 }, 127 { 1188, 0x00d8 }, 128 { 1189, 0x1eb5 }, 129 { 1190, 0xf145 }, 130 { 1191, 0x0b75 }, 131 { 1192, 0x01c5 }, 132 { 1193, 0x1c58 }, 133 { 1194, 0xf373 }, 134 { 1195, 0x0a54 }, 135 { 1196, 0x0558 }, 136 { 1197, 0x168e }, 137 { 1198, 0xf829 }, 138 { 1199, 0x07ad }, 139 { 1200, 0x1103 }, 140 { 1201, 0x0564 }, 141 { 1202, 0x0559 }, 142 { 1203, 0x4000 }, 143 { 1280, 0x00c0 }, 144 { 1281, 0x00c0 }, 145 { 1282, 0x00c0 }, 146 { 1283, 0x00c0 }, 147 { 1312, 0x0200 }, 148 { 1313, 0x0010 }, 149 { 1344, 0x0098 }, 150 { 1345, 0x0845 }, 151 { 1408, 0x6318 }, 152 { 1409, 0x6300 }, 153 { 1410, 0x0fca }, 154 { 1411, 0x0400 }, 155 { 1412, 0x00d8 }, 156 { 1413, 0x1eb5 }, 157 { 1414, 0xf145 }, 158 { 1415, 0x0b75 }, 159 { 1416, 0x01c5 }, 160 { 1417, 0x1c58 }, 161 { 1418, 0xf373 }, 162 { 1419, 0x0a54 }, 163 { 1420, 0x0558 }, 164 { 1421, 0x168e }, 165 { 1422, 0xf829 }, 166 { 1423, 0x07ad }, 167 { 1424, 0x1103 }, 168 { 1425, 0x0564 }, 169 { 1426, 0x0559 }, 170 { 1427, 0x4000 }, 171 { 1568, 0x0002 }, 172 { 1792, 0xa100 }, 173 { 1793, 0xa101 }, 174 { 1794, 0xa101 }, 175 { 1795, 0xa101 }, 176 { 1796, 0xa101 }, 177 { 1797, 0xa101 }, 178 { 1798, 0xa101 }, 179 { 1799, 0xa101 }, 180 { 1800, 0xa101 }, 181 { 1801, 0xa101 }, 182 { 1802, 0xa101 }, 183 { 1803, 0xa101 }, 184 { 1804, 0xa101 }, 185 { 1805, 0xa101 }, 186 { 1825, 0x0055 }, 187 { 1848, 0x3fff }, 188 { 1849, 0x1fff }, 189 { 2049, 0x0001 }, 190 { 2050, 0x0069 }, 191 { 2056, 0x0002 }, 192 { 2057, 0x0003 }, 193 { 2058, 0x0069 }, 194 { 12288, 0x0001 }, 195 { 12289, 0x0001 }, 196 { 12291, 0x0006 }, 197 { 12292, 0x0040 }, 198 { 12293, 0x0001 }, 199 { 12294, 0x000f }, 200 { 12295, 0x0006 }, 201 { 12296, 0x0001 }, 202 { 12297, 0x0003 }, 203 { 12298, 0x0104 }, 204 { 12300, 0x0060 }, 205 { 12301, 0x0011 }, 206 { 12302, 0x0401 }, 207 { 12304, 0x0050 }, 208 { 12305, 0x0003 }, 209 { 12306, 0x0100 }, 210 { 12308, 0x0051 }, 211 { 12309, 0x0003 }, 212 { 12310, 0x0104 }, 213 { 12311, 0x000a }, 214 { 12312, 0x0060 }, 215 { 12313, 0x003b }, 216 { 12314, 0x0502 }, 217 { 12315, 0x0100 }, 218 { 12316, 0x2fff }, 219 { 12320, 0x2fff }, 220 { 12324, 0x2fff }, 221 { 12328, 0x2fff }, 222 { 12332, 0x2fff }, 223 { 12336, 0x2fff }, 224 { 12340, 0x2fff }, 225 { 12344, 0x2fff }, 226 { 12348, 0x2fff }, 227 { 12352, 0x0001 }, 228 { 12353, 0x0001 }, 229 { 12355, 0x0006 }, 230 { 12356, 0x0040 }, 231 { 12357, 0x0001 }, 232 { 12358, 0x000f }, 233 { 12359, 0x0006 }, 234 { 12360, 0x0001 }, 235 { 12361, 0x0003 }, 236 { 12362, 0x0104 }, 237 { 12364, 0x0060 }, 238 { 12365, 0x0011 }, 239 { 12366, 0x0401 }, 240 { 12368, 0x0050 }, 241 { 12369, 0x0003 }, 242 { 12370, 0x0100 }, 243 { 12372, 0x0060 }, 244 { 12373, 0x003b }, 245 { 12374, 0x0502 }, 246 { 12375, 0x0100 }, 247 { 12376, 0x2fff }, 248 { 12380, 0x2fff }, 249 { 12384, 0x2fff }, 250 { 12388, 0x2fff }, 251 { 12392, 0x2fff }, 252 { 12396, 0x2fff }, 253 { 12400, 0x2fff }, 254 { 12404, 0x2fff }, 255 { 12408, 0x2fff }, 256 { 12412, 0x2fff }, 257 { 12416, 0x0001 }, 258 { 12417, 0x0001 }, 259 { 12419, 0x0006 }, 260 { 12420, 0x0040 }, 261 { 12421, 0x0001 }, 262 { 12422, 0x000f }, 263 { 12423, 0x0006 }, 264 { 12424, 0x0001 }, 265 { 12425, 0x0003 }, 266 { 12426, 0x0106 }, 267 { 12428, 0x0061 }, 268 { 12429, 0x0011 }, 269 { 12430, 0x0401 }, 270 { 12432, 0x0050 }, 271 { 12433, 0x0003 }, 272 { 12434, 0x0102 }, 273 { 12436, 0x0051 }, 274 { 12437, 0x0003 }, 275 { 12438, 0x0106 }, 276 { 12439, 0x000a }, 277 { 12440, 0x0061 }, 278 { 12441, 0x003b }, 279 { 12442, 0x0502 }, 280 { 12443, 0x0100 }, 281 { 12444, 0x2fff }, 282 { 12448, 0x2fff }, 283 { 12452, 0x2fff }, 284 { 12456, 0x2fff }, 285 { 12460, 0x2fff }, 286 { 12464, 0x2fff }, 287 { 12468, 0x2fff }, 288 { 12472, 0x2fff }, 289 { 12476, 0x2fff }, 290 { 12480, 0x0001 }, 291 { 12481, 0x0001 }, 292 { 12483, 0x0006 }, 293 { 12484, 0x0040 }, 294 { 12485, 0x0001 }, 295 { 12486, 0x000f }, 296 { 12487, 0x0006 }, 297 { 12488, 0x0001 }, 298 { 12489, 0x0003 }, 299 { 12490, 0x0106 }, 300 { 12492, 0x0061 }, 301 { 12493, 0x0011 }, 302 { 12494, 0x0401 }, 303 { 12496, 0x0050 }, 304 { 12497, 0x0003 }, 305 { 12498, 0x0102 }, 306 { 12500, 0x0061 }, 307 { 12501, 0x003b }, 308 { 12502, 0x0502 }, 309 { 12503, 0x0100 }, 310 { 12504, 0x2fff }, 311 { 12508, 0x2fff }, 312 { 12512, 0x2fff }, 313 { 12516, 0x2fff }, 314 { 12520, 0x2fff }, 315 { 12524, 0x2fff }, 316 { 12528, 0x2fff }, 317 { 12532, 0x2fff }, 318 { 12536, 0x2fff }, 319 { 12540, 0x2fff }, 320 { 12544, 0x0060 }, 321 { 12546, 0x0601 }, 322 { 12548, 0x0050 }, 323 { 12550, 0x0100 }, 324 { 12552, 0x0001 }, 325 { 12554, 0x0104 }, 326 { 12555, 0x0100 }, 327 { 12556, 0x2fff }, 328 { 12560, 0x2fff }, 329 { 12564, 0x2fff }, 330 { 12568, 0x2fff }, 331 { 12572, 0x2fff }, 332 { 12576, 0x2fff }, 333 { 12580, 0x2fff }, 334 { 12584, 0x2fff }, 335 { 12588, 0x2fff }, 336 { 12592, 0x2fff }, 337 { 12596, 0x2fff }, 338 { 12600, 0x2fff }, 339 { 12604, 0x2fff }, 340 { 12608, 0x0061 }, 341 { 12610, 0x0601 }, 342 { 12612, 0x0050 }, 343 { 12614, 0x0102 }, 344 { 12616, 0x0001 }, 345 { 12618, 0x0106 }, 346 { 12619, 0x0100 }, 347 { 12620, 0x2fff }, 348 { 12624, 0x2fff }, 349 { 12628, 0x2fff }, 350 { 12632, 0x2fff }, 351 { 12636, 0x2fff }, 352 { 12640, 0x2fff }, 353 { 12644, 0x2fff }, 354 { 12648, 0x2fff }, 355 { 12652, 0x2fff }, 356 { 12656, 0x2fff }, 357 { 12660, 0x2fff }, 358 { 12664, 0x2fff }, 359 { 12668, 0x2fff }, 360 { 12672, 0x0060 }, 361 { 12674, 0x0601 }, 362 { 12676, 0x0061 }, 363 { 12678, 0x0601 }, 364 { 12680, 0x0050 }, 365 { 12682, 0x0300 }, 366 { 12684, 0x0001 }, 367 { 12686, 0x0304 }, 368 { 12688, 0x0040 }, 369 { 12690, 0x000f }, 370 { 12692, 0x0001 }, 371 { 12695, 0x0100 }, 372 }; 373 374 struct fll_config { 375 int src; 376 int in; 377 int out; 378 }; 379 380 struct wm8995_priv { 381 struct regmap *regmap; 382 int sysclk[2]; 383 int mclk[2]; 384 int aifclk[2]; 385 struct fll_config fll[2], fll_suspend[2]; 386 struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; 387 struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; 388 struct snd_soc_codec *codec; 389 }; 390 391 /* 392 * We can't use the same notifier block for more than one supply and 393 * there's no way I can see to get from a callback to the caller 394 * except container_of(). 395 */ 396 #define WM8995_REGULATOR_EVENT(n) \ 397 static int wm8995_regulator_event_##n(struct notifier_block *nb, \ 398 unsigned long event, void *data) \ 399 { \ 400 struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ 401 disable_nb[n]); \ 402 if (event & REGULATOR_EVENT_DISABLE) { \ 403 regcache_mark_dirty(wm8995->regmap); \ 404 } \ 405 return 0; \ 406 } 407 408 WM8995_REGULATOR_EVENT(0) 409 WM8995_REGULATOR_EVENT(1) 410 WM8995_REGULATOR_EVENT(2) 411 WM8995_REGULATOR_EVENT(3) 412 WM8995_REGULATOR_EVENT(4) 413 WM8995_REGULATOR_EVENT(5) 414 WM8995_REGULATOR_EVENT(6) 415 WM8995_REGULATOR_EVENT(7) 416 417 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 418 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); 419 static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); 420 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); 421 422 static const char *in1l_text[] = { 423 "Differential", "Single-ended IN1LN", "Single-ended IN1LP" 424 }; 425 426 static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 427 2, in1l_text); 428 429 static const char *in1r_text[] = { 430 "Differential", "Single-ended IN1RN", "Single-ended IN1RP" 431 }; 432 433 static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, 434 0, in1r_text); 435 436 static const char *dmic_src_text[] = { 437 "DMICDAT1", "DMICDAT2", "DMICDAT3" 438 }; 439 440 static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, 441 8, dmic_src_text); 442 static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, 443 6, dmic_src_text); 444 445 static const struct snd_kcontrol_new wm8995_snd_controls[] = { 446 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, 447 WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 448 SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, 449 WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), 450 451 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, 452 WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 453 SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, 454 WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), 455 456 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, 457 WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 458 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, 459 WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 460 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, 461 WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 462 463 SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, 464 WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), 465 466 SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, 467 4, 3, 0, in1l_boost_tlv), 468 469 SOC_ENUM("IN1L Mode", in1l_enum), 470 SOC_ENUM("IN1R Mode", in1r_enum), 471 472 SOC_ENUM("DMIC1 SRC", dmic_src1_enum), 473 SOC_ENUM("DMIC2 SRC", dmic_src2_enum), 474 475 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, 476 24, 0, sidetone_tlv), 477 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, 478 24, 0, sidetone_tlv), 479 480 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, 481 WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 482 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, 483 WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), 484 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, 485 WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) 486 }; 487 488 static void wm8995_update_class_w(struct snd_soc_codec *codec) 489 { 490 int enable = 1; 491 int source = 0; /* GCC flow analysis can't track enable */ 492 int reg, reg_r; 493 494 /* We also need the same setting for L/R and only one path */ 495 reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); 496 switch (reg) { 497 case WM8995_AIF2DACL_TO_DAC1L: 498 dev_dbg(codec->dev, "Class W source AIF2DAC\n"); 499 source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; 500 break; 501 case WM8995_AIF1DAC2L_TO_DAC1L: 502 dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); 503 source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; 504 break; 505 case WM8995_AIF1DAC1L_TO_DAC1L: 506 dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); 507 source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; 508 break; 509 default: 510 dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); 511 enable = 0; 512 break; 513 } 514 515 reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); 516 if (reg_r != reg) { 517 dev_dbg(codec->dev, "Left and right DAC mixers different\n"); 518 enable = 0; 519 } 520 521 if (enable) { 522 dev_dbg(codec->dev, "Class W enabled\n"); 523 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 524 WM8995_CP_DYN_PWR_MASK | 525 WM8995_CP_DYN_SRC_SEL_MASK, 526 source | WM8995_CP_DYN_PWR); 527 } else { 528 dev_dbg(codec->dev, "Class W disabled\n"); 529 snd_soc_update_bits(codec, WM8995_CLASS_W_1, 530 WM8995_CP_DYN_PWR_MASK, 0); 531 } 532 } 533 534 static int check_clk_sys(struct snd_soc_dapm_widget *source, 535 struct snd_soc_dapm_widget *sink) 536 { 537 unsigned int reg; 538 const char *clk; 539 540 reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); 541 /* Check what we're currently using for CLK_SYS */ 542 if (reg & WM8995_SYSCLK_SRC) 543 clk = "AIF2CLK"; 544 else 545 clk = "AIF1CLK"; 546 return !strcmp(source->name, clk); 547 } 548 549 static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, 550 struct snd_ctl_elem_value *ucontrol) 551 { 552 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); 553 int ret; 554 555 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); 556 wm8995_update_class_w(codec); 557 return ret; 558 } 559 560 static int hp_supply_event(struct snd_soc_dapm_widget *w, 561 struct snd_kcontrol *kcontrol, int event) 562 { 563 struct snd_soc_codec *codec; 564 struct wm8995_priv *wm8995; 565 566 codec = w->codec; 567 wm8995 = snd_soc_codec_get_drvdata(codec); 568 569 switch (event) { 570 case SND_SOC_DAPM_PRE_PMU: 571 /* Enable the headphone amp */ 572 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 573 WM8995_HPOUT1L_ENA_MASK | 574 WM8995_HPOUT1R_ENA_MASK, 575 WM8995_HPOUT1L_ENA | 576 WM8995_HPOUT1R_ENA); 577 578 /* Enable the second stage */ 579 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 580 WM8995_HPOUT1L_DLY_MASK | 581 WM8995_HPOUT1R_DLY_MASK, 582 WM8995_HPOUT1L_DLY | 583 WM8995_HPOUT1R_DLY); 584 break; 585 case SND_SOC_DAPM_PRE_PMD: 586 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 587 WM8995_CP_ENA_MASK, 0); 588 break; 589 } 590 591 return 0; 592 } 593 594 static void dc_servo_cmd(struct snd_soc_codec *codec, 595 unsigned int reg, unsigned int val, unsigned int mask) 596 { 597 int timeout = 10; 598 599 dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", 600 __func__, reg, val, mask); 601 602 snd_soc_write(codec, reg, val); 603 while (timeout--) { 604 msleep(10); 605 val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); 606 if ((val & mask) == mask) 607 return; 608 } 609 610 dev_err(codec->dev, "Timed out waiting for DC Servo\n"); 611 } 612 613 static int hp_event(struct snd_soc_dapm_widget *w, 614 struct snd_kcontrol *kcontrol, int event) 615 { 616 struct snd_soc_codec *codec; 617 unsigned int reg; 618 619 codec = w->codec; 620 reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); 621 622 switch (event) { 623 case SND_SOC_DAPM_POST_PMU: 624 snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, 625 WM8995_CP_ENA_MASK, WM8995_CP_ENA); 626 627 msleep(5); 628 629 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 630 WM8995_HPOUT1L_ENA_MASK | 631 WM8995_HPOUT1R_ENA_MASK, 632 WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); 633 634 udelay(20); 635 636 reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; 637 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 638 639 snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | 640 WM8995_DCS_ENA_CHAN_1); 641 642 dc_servo_cmd(codec, WM8995_DC_SERVO_2, 643 WM8995_DCS_TRIG_STARTUP_0 | 644 WM8995_DCS_TRIG_STARTUP_1, 645 WM8995_DCS_TRIG_DAC_WR_0 | 646 WM8995_DCS_TRIG_DAC_WR_1); 647 648 reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | 649 WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; 650 snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); 651 652 break; 653 case SND_SOC_DAPM_PRE_PMD: 654 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 655 WM8995_HPOUT1L_OUTP_MASK | 656 WM8995_HPOUT1R_OUTP_MASK | 657 WM8995_HPOUT1L_RMV_SHORT_MASK | 658 WM8995_HPOUT1R_RMV_SHORT_MASK, 0); 659 660 snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, 661 WM8995_HPOUT1L_DLY_MASK | 662 WM8995_HPOUT1R_DLY_MASK, 0); 663 664 snd_soc_write(codec, WM8995_DC_SERVO_1, 0); 665 666 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 667 WM8995_HPOUT1L_ENA_MASK | 668 WM8995_HPOUT1R_ENA_MASK, 669 0); 670 break; 671 } 672 673 return 0; 674 } 675 676 static int configure_aif_clock(struct snd_soc_codec *codec, int aif) 677 { 678 struct wm8995_priv *wm8995; 679 int rate; 680 int reg1 = 0; 681 int offset; 682 683 wm8995 = snd_soc_codec_get_drvdata(codec); 684 685 if (aif) 686 offset = 4; 687 else 688 offset = 0; 689 690 switch (wm8995->sysclk[aif]) { 691 case WM8995_SYSCLK_MCLK1: 692 rate = wm8995->mclk[0]; 693 break; 694 case WM8995_SYSCLK_MCLK2: 695 reg1 |= 0x8; 696 rate = wm8995->mclk[1]; 697 break; 698 case WM8995_SYSCLK_FLL1: 699 reg1 |= 0x10; 700 rate = wm8995->fll[0].out; 701 break; 702 case WM8995_SYSCLK_FLL2: 703 reg1 |= 0x18; 704 rate = wm8995->fll[1].out; 705 break; 706 default: 707 return -EINVAL; 708 } 709 710 if (rate >= 13500000) { 711 rate /= 2; 712 reg1 |= WM8995_AIF1CLK_DIV; 713 714 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", 715 aif + 1, rate); 716 } 717 718 wm8995->aifclk[aif] = rate; 719 720 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, 721 WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, 722 reg1); 723 return 0; 724 } 725 726 static int configure_clock(struct snd_soc_codec *codec) 727 { 728 struct wm8995_priv *wm8995; 729 int change, new; 730 731 wm8995 = snd_soc_codec_get_drvdata(codec); 732 733 /* Bring up the AIF clocks first */ 734 configure_aif_clock(codec, 0); 735 configure_aif_clock(codec, 1); 736 737 /* 738 * Then switch CLK_SYS over to the higher of them; a change 739 * can only happen as a result of a clocking change which can 740 * only be made outside of DAPM so we can safely redo the 741 * clocking. 742 */ 743 744 /* If they're equal it doesn't matter which is used */ 745 if (wm8995->aifclk[0] == wm8995->aifclk[1]) 746 return 0; 747 748 if (wm8995->aifclk[0] < wm8995->aifclk[1]) 749 new = WM8995_SYSCLK_SRC; 750 else 751 new = 0; 752 753 change = snd_soc_update_bits(codec, WM8995_CLOCKING_1, 754 WM8995_SYSCLK_SRC_MASK, new); 755 if (!change) 756 return 0; 757 758 snd_soc_dapm_sync(&codec->dapm); 759 760 return 0; 761 } 762 763 static int clk_sys_event(struct snd_soc_dapm_widget *w, 764 struct snd_kcontrol *kcontrol, int event) 765 { 766 struct snd_soc_codec *codec; 767 768 codec = w->codec; 769 770 switch (event) { 771 case SND_SOC_DAPM_PRE_PMU: 772 return configure_clock(codec); 773 774 case SND_SOC_DAPM_POST_PMD: 775 configure_clock(codec); 776 break; 777 } 778 779 return 0; 780 } 781 782 static const char *sidetone_text[] = { 783 "ADC/DMIC1", "DMIC2", 784 }; 785 786 static const struct soc_enum sidetone1_enum = 787 SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); 788 789 static const struct snd_kcontrol_new sidetone1_mux = 790 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); 791 792 static const struct soc_enum sidetone2_enum = 793 SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); 794 795 static const struct snd_kcontrol_new sidetone2_mux = 796 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); 797 798 static const struct snd_kcontrol_new aif1adc1l_mix[] = { 799 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 800 1, 1, 0), 801 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, 802 0, 1, 0), 803 }; 804 805 static const struct snd_kcontrol_new aif1adc1r_mix[] = { 806 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 807 1, 1, 0), 808 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, 809 0, 1, 0), 810 }; 811 812 static const struct snd_kcontrol_new aif1adc2l_mix[] = { 813 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 814 1, 1, 0), 815 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, 816 0, 1, 0), 817 }; 818 819 static const struct snd_kcontrol_new aif1adc2r_mix[] = { 820 SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 821 1, 1, 0), 822 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, 823 0, 1, 0), 824 }; 825 826 static const struct snd_kcontrol_new dac1l_mix[] = { 827 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 828 5, 1, 0), 829 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 830 4, 1, 0), 831 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 832 2, 1, 0), 833 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 834 1, 1, 0), 835 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, 836 0, 1, 0), 837 }; 838 839 static const struct snd_kcontrol_new dac1r_mix[] = { 840 WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 841 5, 1, 0), 842 WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 843 4, 1, 0), 844 WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 845 2, 1, 0), 846 WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 847 1, 1, 0), 848 WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, 849 0, 1, 0), 850 }; 851 852 static const struct snd_kcontrol_new aif2dac2l_mix[] = { 853 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 854 5, 1, 0), 855 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 856 4, 1, 0), 857 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 858 2, 1, 0), 859 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 860 1, 1, 0), 861 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, 862 0, 1, 0), 863 }; 864 865 static const struct snd_kcontrol_new aif2dac2r_mix[] = { 866 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 867 5, 1, 0), 868 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 869 4, 1, 0), 870 SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 871 2, 1, 0), 872 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 873 1, 1, 0), 874 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, 875 0, 1, 0), 876 }; 877 878 static const struct snd_kcontrol_new in1l_pga = 879 SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); 880 881 static const struct snd_kcontrol_new in1r_pga = 882 SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); 883 884 static const char *adc_mux_text[] = { 885 "ADC", 886 "DMIC", 887 }; 888 889 static const struct soc_enum adc_enum = 890 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); 891 892 static const struct snd_kcontrol_new adcl_mux = 893 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); 894 895 static const struct snd_kcontrol_new adcr_mux = 896 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); 897 898 static const char *spk_src_text[] = { 899 "DAC1L", "DAC1R", "DAC2L", "DAC2R" 900 }; 901 902 static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, 903 0, spk_src_text); 904 static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, 905 0, spk_src_text); 906 static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, 907 0, spk_src_text); 908 static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, 909 0, spk_src_text); 910 911 static const struct snd_kcontrol_new spk1l_mux = 912 SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); 913 static const struct snd_kcontrol_new spk1r_mux = 914 SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); 915 static const struct snd_kcontrol_new spk2l_mux = 916 SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); 917 static const struct snd_kcontrol_new spk2r_mux = 918 SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); 919 920 static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { 921 SND_SOC_DAPM_INPUT("DMIC1DAT"), 922 SND_SOC_DAPM_INPUT("DMIC2DAT"), 923 924 SND_SOC_DAPM_INPUT("IN1L"), 925 SND_SOC_DAPM_INPUT("IN1R"), 926 927 SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, 928 &in1l_pga, 1), 929 SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, 930 &in1r_pga, 1), 931 932 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0, 933 NULL, 0), 934 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0, 935 NULL, 0), 936 937 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), 938 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), 939 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), 940 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), 941 SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), 942 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, 943 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 944 945 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, 946 WM8995_POWER_MANAGEMENT_3, 9, 0), 947 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, 948 WM8995_POWER_MANAGEMENT_3, 8, 0), 949 SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, 950 SND_SOC_NOPM, 0, 0), 951 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", 952 0, WM8995_POWER_MANAGEMENT_3, 11, 0), 953 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", 954 0, WM8995_POWER_MANAGEMENT_3, 10, 0), 955 956 SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, 957 &adcl_mux), 958 SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, 959 &adcr_mux), 960 961 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), 962 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), 963 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), 964 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), 965 966 SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), 967 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), 968 969 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, 970 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), 971 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, 972 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), 973 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, 974 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), 975 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, 976 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), 977 978 SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 979 9, 0), 980 SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 981 8, 0), 982 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 983 0, 0), 984 985 SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, 986 11, 0), 987 SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, 988 10, 0), 989 990 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, 991 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), 992 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, 993 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), 994 995 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), 996 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), 997 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), 998 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), 999 1000 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, 1001 ARRAY_SIZE(dac1l_mix)), 1002 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, 1003 ARRAY_SIZE(dac1r_mix)), 1004 1005 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), 1006 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), 1007 1008 SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, 1009 hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1010 1011 SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, 1012 hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 1013 1014 SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, 1015 4, 0, &spk1l_mux), 1016 SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, 1017 4, 0, &spk1r_mux), 1018 SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, 1019 4, 0, &spk2l_mux), 1020 SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, 1021 4, 0, &spk2r_mux), 1022 1023 SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), 1024 1025 SND_SOC_DAPM_OUTPUT("HP1L"), 1026 SND_SOC_DAPM_OUTPUT("HP1R"), 1027 SND_SOC_DAPM_OUTPUT("SPK1L"), 1028 SND_SOC_DAPM_OUTPUT("SPK1R"), 1029 SND_SOC_DAPM_OUTPUT("SPK2L"), 1030 SND_SOC_DAPM_OUTPUT("SPK2R") 1031 }; 1032 1033 static const struct snd_soc_dapm_route wm8995_intercon[] = { 1034 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, 1035 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, 1036 1037 { "DSP1CLK", NULL, "CLK_SYS" }, 1038 { "DSP2CLK", NULL, "CLK_SYS" }, 1039 { "SYSDSPCLK", NULL, "CLK_SYS" }, 1040 1041 { "AIF1ADC1L", NULL, "AIF1CLK" }, 1042 { "AIF1ADC1L", NULL, "DSP1CLK" }, 1043 { "AIF1ADC1R", NULL, "AIF1CLK" }, 1044 { "AIF1ADC1R", NULL, "DSP1CLK" }, 1045 { "AIF1ADC1R", NULL, "SYSDSPCLK" }, 1046 1047 { "AIF1ADC2L", NULL, "AIF1CLK" }, 1048 { "AIF1ADC2L", NULL, "DSP1CLK" }, 1049 { "AIF1ADC2R", NULL, "AIF1CLK" }, 1050 { "AIF1ADC2R", NULL, "DSP1CLK" }, 1051 { "AIF1ADC2R", NULL, "SYSDSPCLK" }, 1052 1053 { "DMIC1L", NULL, "DMIC1DAT" }, 1054 { "DMIC1L", NULL, "CLK_SYS" }, 1055 { "DMIC1R", NULL, "DMIC1DAT" }, 1056 { "DMIC1R", NULL, "CLK_SYS" }, 1057 { "DMIC2L", NULL, "DMIC2DAT" }, 1058 { "DMIC2L", NULL, "CLK_SYS" }, 1059 { "DMIC2R", NULL, "DMIC2DAT" }, 1060 { "DMIC2R", NULL, "CLK_SYS" }, 1061 1062 { "ADCL", NULL, "AIF1CLK" }, 1063 { "ADCL", NULL, "DSP1CLK" }, 1064 { "ADCL", NULL, "SYSDSPCLK" }, 1065 1066 { "ADCR", NULL, "AIF1CLK" }, 1067 { "ADCR", NULL, "DSP1CLK" }, 1068 { "ADCR", NULL, "SYSDSPCLK" }, 1069 1070 { "IN1L PGA", "IN1L Switch", "IN1L" }, 1071 { "IN1R PGA", "IN1R Switch", "IN1R" }, 1072 { "IN1L PGA", NULL, "LDO2" }, 1073 { "IN1R PGA", NULL, "LDO2" }, 1074 1075 { "ADCL", NULL, "IN1L PGA" }, 1076 { "ADCR", NULL, "IN1R PGA" }, 1077 1078 { "ADCL Mux", "ADC", "ADCL" }, 1079 { "ADCL Mux", "DMIC", "DMIC1L" }, 1080 { "ADCR Mux", "ADC", "ADCR" }, 1081 { "ADCR Mux", "DMIC", "DMIC1R" }, 1082 1083 /* AIF1 outputs */ 1084 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, 1085 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, 1086 1087 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, 1088 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, 1089 1090 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, 1091 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, 1092 1093 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, 1094 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, 1095 1096 /* Sidetone */ 1097 { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, 1098 { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, 1099 { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, 1100 { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, 1101 1102 { "AIF1DAC1L", NULL, "AIF1CLK" }, 1103 { "AIF1DAC1L", NULL, "DSP1CLK" }, 1104 { "AIF1DAC1R", NULL, "AIF1CLK" }, 1105 { "AIF1DAC1R", NULL, "DSP1CLK" }, 1106 { "AIF1DAC1R", NULL, "SYSDSPCLK" }, 1107 1108 { "AIF1DAC2L", NULL, "AIF1CLK" }, 1109 { "AIF1DAC2L", NULL, "DSP1CLK" }, 1110 { "AIF1DAC2R", NULL, "AIF1CLK" }, 1111 { "AIF1DAC2R", NULL, "DSP1CLK" }, 1112 { "AIF1DAC2R", NULL, "SYSDSPCLK" }, 1113 1114 { "DAC1L", NULL, "AIF1CLK" }, 1115 { "DAC1L", NULL, "DSP1CLK" }, 1116 { "DAC1L", NULL, "SYSDSPCLK" }, 1117 1118 { "DAC1R", NULL, "AIF1CLK" }, 1119 { "DAC1R", NULL, "DSP1CLK" }, 1120 { "DAC1R", NULL, "SYSDSPCLK" }, 1121 1122 { "AIF1DAC1L", NULL, "AIF1DACDAT" }, 1123 { "AIF1DAC1R", NULL, "AIF1DACDAT" }, 1124 { "AIF1DAC2L", NULL, "AIF1DACDAT" }, 1125 { "AIF1DAC2R", NULL, "AIF1DACDAT" }, 1126 1127 /* DAC1 inputs */ 1128 { "DAC1L", NULL, "DAC1L Mixer" }, 1129 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1130 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1131 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1132 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1133 1134 { "DAC1R", NULL, "DAC1R Mixer" }, 1135 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1136 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1137 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, 1138 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, 1139 1140 /* DAC2/AIF2 outputs */ 1141 { "DAC2L", NULL, "AIF2DAC2L Mixer" }, 1142 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, 1143 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, 1144 1145 { "DAC2R", NULL, "AIF2DAC2R Mixer" }, 1146 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, 1147 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, 1148 1149 /* Output stages */ 1150 { "Headphone PGA", NULL, "DAC1L" }, 1151 { "Headphone PGA", NULL, "DAC1R" }, 1152 1153 { "Headphone PGA", NULL, "DAC2L" }, 1154 { "Headphone PGA", NULL, "DAC2R" }, 1155 1156 { "Headphone PGA", NULL, "Headphone Supply" }, 1157 { "Headphone PGA", NULL, "CLK_SYS" }, 1158 { "Headphone PGA", NULL, "LDO2" }, 1159 1160 { "HP1L", NULL, "Headphone PGA" }, 1161 { "HP1R", NULL, "Headphone PGA" }, 1162 1163 { "SPK1L Driver", "DAC1L", "DAC1L" }, 1164 { "SPK1L Driver", "DAC1R", "DAC1R" }, 1165 { "SPK1L Driver", "DAC2L", "DAC2L" }, 1166 { "SPK1L Driver", "DAC2R", "DAC2R" }, 1167 { "SPK1L Driver", NULL, "CLK_SYS" }, 1168 1169 { "SPK1R Driver", "DAC1L", "DAC1L" }, 1170 { "SPK1R Driver", "DAC1R", "DAC1R" }, 1171 { "SPK1R Driver", "DAC2L", "DAC2L" }, 1172 { "SPK1R Driver", "DAC2R", "DAC2R" }, 1173 { "SPK1R Driver", NULL, "CLK_SYS" }, 1174 1175 { "SPK2L Driver", "DAC1L", "DAC1L" }, 1176 { "SPK2L Driver", "DAC1R", "DAC1R" }, 1177 { "SPK2L Driver", "DAC2L", "DAC2L" }, 1178 { "SPK2L Driver", "DAC2R", "DAC2R" }, 1179 { "SPK2L Driver", NULL, "CLK_SYS" }, 1180 1181 { "SPK2R Driver", "DAC1L", "DAC1L" }, 1182 { "SPK2R Driver", "DAC1R", "DAC1R" }, 1183 { "SPK2R Driver", "DAC2L", "DAC2L" }, 1184 { "SPK2R Driver", "DAC2R", "DAC2R" }, 1185 { "SPK2R Driver", NULL, "CLK_SYS" }, 1186 1187 { "SPK1L", NULL, "SPK1L Driver" }, 1188 { "SPK1R", NULL, "SPK1R Driver" }, 1189 { "SPK2L", NULL, "SPK2L Driver" }, 1190 { "SPK2R", NULL, "SPK2R Driver" } 1191 }; 1192 1193 static bool wm8995_readable(struct device *dev, unsigned int reg) 1194 { 1195 switch (reg) { 1196 case WM8995_SOFTWARE_RESET: 1197 case WM8995_POWER_MANAGEMENT_1: 1198 case WM8995_POWER_MANAGEMENT_2: 1199 case WM8995_POWER_MANAGEMENT_3: 1200 case WM8995_POWER_MANAGEMENT_4: 1201 case WM8995_POWER_MANAGEMENT_5: 1202 case WM8995_LEFT_LINE_INPUT_1_VOLUME: 1203 case WM8995_RIGHT_LINE_INPUT_1_VOLUME: 1204 case WM8995_LEFT_LINE_INPUT_CONTROL: 1205 case WM8995_DAC1_LEFT_VOLUME: 1206 case WM8995_DAC1_RIGHT_VOLUME: 1207 case WM8995_DAC2_LEFT_VOLUME: 1208 case WM8995_DAC2_RIGHT_VOLUME: 1209 case WM8995_OUTPUT_VOLUME_ZC_1: 1210 case WM8995_MICBIAS_1: 1211 case WM8995_MICBIAS_2: 1212 case WM8995_LDO_1: 1213 case WM8995_LDO_2: 1214 case WM8995_ACCESSORY_DETECT_MODE1: 1215 case WM8995_ACCESSORY_DETECT_MODE2: 1216 case WM8995_HEADPHONE_DETECT1: 1217 case WM8995_HEADPHONE_DETECT2: 1218 case WM8995_MIC_DETECT_1: 1219 case WM8995_MIC_DETECT_2: 1220 case WM8995_CHARGE_PUMP_1: 1221 case WM8995_CLASS_W_1: 1222 case WM8995_DC_SERVO_1: 1223 case WM8995_DC_SERVO_2: 1224 case WM8995_DC_SERVO_3: 1225 case WM8995_DC_SERVO_5: 1226 case WM8995_DC_SERVO_6: 1227 case WM8995_DC_SERVO_7: 1228 case WM8995_DC_SERVO_READBACK_0: 1229 case WM8995_ANALOGUE_HP_1: 1230 case WM8995_ANALOGUE_HP_2: 1231 case WM8995_CHIP_REVISION: 1232 case WM8995_CONTROL_INTERFACE_1: 1233 case WM8995_CONTROL_INTERFACE_2: 1234 case WM8995_WRITE_SEQUENCER_CTRL_1: 1235 case WM8995_WRITE_SEQUENCER_CTRL_2: 1236 case WM8995_AIF1_CLOCKING_1: 1237 case WM8995_AIF1_CLOCKING_2: 1238 case WM8995_AIF2_CLOCKING_1: 1239 case WM8995_AIF2_CLOCKING_2: 1240 case WM8995_CLOCKING_1: 1241 case WM8995_CLOCKING_2: 1242 case WM8995_AIF1_RATE: 1243 case WM8995_AIF2_RATE: 1244 case WM8995_RATE_STATUS: 1245 case WM8995_FLL1_CONTROL_1: 1246 case WM8995_FLL1_CONTROL_2: 1247 case WM8995_FLL1_CONTROL_3: 1248 case WM8995_FLL1_CONTROL_4: 1249 case WM8995_FLL1_CONTROL_5: 1250 case WM8995_FLL2_CONTROL_1: 1251 case WM8995_FLL2_CONTROL_2: 1252 case WM8995_FLL2_CONTROL_3: 1253 case WM8995_FLL2_CONTROL_4: 1254 case WM8995_FLL2_CONTROL_5: 1255 case WM8995_AIF1_CONTROL_1: 1256 case WM8995_AIF1_CONTROL_2: 1257 case WM8995_AIF1_MASTER_SLAVE: 1258 case WM8995_AIF1_BCLK: 1259 case WM8995_AIF1ADC_LRCLK: 1260 case WM8995_AIF1DAC_LRCLK: 1261 case WM8995_AIF1DAC_DATA: 1262 case WM8995_AIF1ADC_DATA: 1263 case WM8995_AIF2_CONTROL_1: 1264 case WM8995_AIF2_CONTROL_2: 1265 case WM8995_AIF2_MASTER_SLAVE: 1266 case WM8995_AIF2_BCLK: 1267 case WM8995_AIF2ADC_LRCLK: 1268 case WM8995_AIF2DAC_LRCLK: 1269 case WM8995_AIF2DAC_DATA: 1270 case WM8995_AIF2ADC_DATA: 1271 case WM8995_AIF1_ADC1_LEFT_VOLUME: 1272 case WM8995_AIF1_ADC1_RIGHT_VOLUME: 1273 case WM8995_AIF1_DAC1_LEFT_VOLUME: 1274 case WM8995_AIF1_DAC1_RIGHT_VOLUME: 1275 case WM8995_AIF1_ADC2_LEFT_VOLUME: 1276 case WM8995_AIF1_ADC2_RIGHT_VOLUME: 1277 case WM8995_AIF1_DAC2_LEFT_VOLUME: 1278 case WM8995_AIF1_DAC2_RIGHT_VOLUME: 1279 case WM8995_AIF1_ADC1_FILTERS: 1280 case WM8995_AIF1_ADC2_FILTERS: 1281 case WM8995_AIF1_DAC1_FILTERS_1: 1282 case WM8995_AIF1_DAC1_FILTERS_2: 1283 case WM8995_AIF1_DAC2_FILTERS_1: 1284 case WM8995_AIF1_DAC2_FILTERS_2: 1285 case WM8995_AIF1_DRC1_1: 1286 case WM8995_AIF1_DRC1_2: 1287 case WM8995_AIF1_DRC1_3: 1288 case WM8995_AIF1_DRC1_4: 1289 case WM8995_AIF1_DRC1_5: 1290 case WM8995_AIF1_DRC2_1: 1291 case WM8995_AIF1_DRC2_2: 1292 case WM8995_AIF1_DRC2_3: 1293 case WM8995_AIF1_DRC2_4: 1294 case WM8995_AIF1_DRC2_5: 1295 case WM8995_AIF1_DAC1_EQ_GAINS_1: 1296 case WM8995_AIF1_DAC1_EQ_GAINS_2: 1297 case WM8995_AIF1_DAC1_EQ_BAND_1_A: 1298 case WM8995_AIF1_DAC1_EQ_BAND_1_B: 1299 case WM8995_AIF1_DAC1_EQ_BAND_1_PG: 1300 case WM8995_AIF1_DAC1_EQ_BAND_2_A: 1301 case WM8995_AIF1_DAC1_EQ_BAND_2_B: 1302 case WM8995_AIF1_DAC1_EQ_BAND_2_C: 1303 case WM8995_AIF1_DAC1_EQ_BAND_2_PG: 1304 case WM8995_AIF1_DAC1_EQ_BAND_3_A: 1305 case WM8995_AIF1_DAC1_EQ_BAND_3_B: 1306 case WM8995_AIF1_DAC1_EQ_BAND_3_C: 1307 case WM8995_AIF1_DAC1_EQ_BAND_3_PG: 1308 case WM8995_AIF1_DAC1_EQ_BAND_4_A: 1309 case WM8995_AIF1_DAC1_EQ_BAND_4_B: 1310 case WM8995_AIF1_DAC1_EQ_BAND_4_C: 1311 case WM8995_AIF1_DAC1_EQ_BAND_4_PG: 1312 case WM8995_AIF1_DAC1_EQ_BAND_5_A: 1313 case WM8995_AIF1_DAC1_EQ_BAND_5_B: 1314 case WM8995_AIF1_DAC1_EQ_BAND_5_PG: 1315 case WM8995_AIF1_DAC2_EQ_GAINS_1: 1316 case WM8995_AIF1_DAC2_EQ_GAINS_2: 1317 case WM8995_AIF1_DAC2_EQ_BAND_1_A: 1318 case WM8995_AIF1_DAC2_EQ_BAND_1_B: 1319 case WM8995_AIF1_DAC2_EQ_BAND_1_PG: 1320 case WM8995_AIF1_DAC2_EQ_BAND_2_A: 1321 case WM8995_AIF1_DAC2_EQ_BAND_2_B: 1322 case WM8995_AIF1_DAC2_EQ_BAND_2_C: 1323 case WM8995_AIF1_DAC2_EQ_BAND_2_PG: 1324 case WM8995_AIF1_DAC2_EQ_BAND_3_A: 1325 case WM8995_AIF1_DAC2_EQ_BAND_3_B: 1326 case WM8995_AIF1_DAC2_EQ_BAND_3_C: 1327 case WM8995_AIF1_DAC2_EQ_BAND_3_PG: 1328 case WM8995_AIF1_DAC2_EQ_BAND_4_A: 1329 case WM8995_AIF1_DAC2_EQ_BAND_4_B: 1330 case WM8995_AIF1_DAC2_EQ_BAND_4_C: 1331 case WM8995_AIF1_DAC2_EQ_BAND_4_PG: 1332 case WM8995_AIF1_DAC2_EQ_BAND_5_A: 1333 case WM8995_AIF1_DAC2_EQ_BAND_5_B: 1334 case WM8995_AIF1_DAC2_EQ_BAND_5_PG: 1335 case WM8995_AIF2_ADC_LEFT_VOLUME: 1336 case WM8995_AIF2_ADC_RIGHT_VOLUME: 1337 case WM8995_AIF2_DAC_LEFT_VOLUME: 1338 case WM8995_AIF2_DAC_RIGHT_VOLUME: 1339 case WM8995_AIF2_ADC_FILTERS: 1340 case WM8995_AIF2_DAC_FILTERS_1: 1341 case WM8995_AIF2_DAC_FILTERS_2: 1342 case WM8995_AIF2_DRC_1: 1343 case WM8995_AIF2_DRC_2: 1344 case WM8995_AIF2_DRC_3: 1345 case WM8995_AIF2_DRC_4: 1346 case WM8995_AIF2_DRC_5: 1347 case WM8995_AIF2_EQ_GAINS_1: 1348 case WM8995_AIF2_EQ_GAINS_2: 1349 case WM8995_AIF2_EQ_BAND_1_A: 1350 case WM8995_AIF2_EQ_BAND_1_B: 1351 case WM8995_AIF2_EQ_BAND_1_PG: 1352 case WM8995_AIF2_EQ_BAND_2_A: 1353 case WM8995_AIF2_EQ_BAND_2_B: 1354 case WM8995_AIF2_EQ_BAND_2_C: 1355 case WM8995_AIF2_EQ_BAND_2_PG: 1356 case WM8995_AIF2_EQ_BAND_3_A: 1357 case WM8995_AIF2_EQ_BAND_3_B: 1358 case WM8995_AIF2_EQ_BAND_3_C: 1359 case WM8995_AIF2_EQ_BAND_3_PG: 1360 case WM8995_AIF2_EQ_BAND_4_A: 1361 case WM8995_AIF2_EQ_BAND_4_B: 1362 case WM8995_AIF2_EQ_BAND_4_C: 1363 case WM8995_AIF2_EQ_BAND_4_PG: 1364 case WM8995_AIF2_EQ_BAND_5_A: 1365 case WM8995_AIF2_EQ_BAND_5_B: 1366 case WM8995_AIF2_EQ_BAND_5_PG: 1367 case WM8995_DAC1_MIXER_VOLUMES: 1368 case WM8995_DAC1_LEFT_MIXER_ROUTING: 1369 case WM8995_DAC1_RIGHT_MIXER_ROUTING: 1370 case WM8995_DAC2_MIXER_VOLUMES: 1371 case WM8995_DAC2_LEFT_MIXER_ROUTING: 1372 case WM8995_DAC2_RIGHT_MIXER_ROUTING: 1373 case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING: 1374 case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING: 1375 case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING: 1376 case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING: 1377 case WM8995_DAC_SOFTMUTE: 1378 case WM8995_OVERSAMPLING: 1379 case WM8995_SIDETONE: 1380 case WM8995_GPIO_1: 1381 case WM8995_GPIO_2: 1382 case WM8995_GPIO_3: 1383 case WM8995_GPIO_4: 1384 case WM8995_GPIO_5: 1385 case WM8995_GPIO_6: 1386 case WM8995_GPIO_7: 1387 case WM8995_GPIO_8: 1388 case WM8995_GPIO_9: 1389 case WM8995_GPIO_10: 1390 case WM8995_GPIO_11: 1391 case WM8995_GPIO_12: 1392 case WM8995_GPIO_13: 1393 case WM8995_GPIO_14: 1394 case WM8995_PULL_CONTROL_1: 1395 case WM8995_PULL_CONTROL_2: 1396 case WM8995_INTERRUPT_STATUS_1: 1397 case WM8995_INTERRUPT_STATUS_2: 1398 case WM8995_INTERRUPT_RAW_STATUS_2: 1399 case WM8995_INTERRUPT_STATUS_1_MASK: 1400 case WM8995_INTERRUPT_STATUS_2_MASK: 1401 case WM8995_INTERRUPT_CONTROL: 1402 case WM8995_LEFT_PDM_SPEAKER_1: 1403 case WM8995_RIGHT_PDM_SPEAKER_1: 1404 case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE: 1405 case WM8995_LEFT_PDM_SPEAKER_2: 1406 case WM8995_RIGHT_PDM_SPEAKER_2: 1407 case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE: 1408 return true; 1409 default: 1410 return false; 1411 } 1412 } 1413 1414 static bool wm8995_volatile(struct device *dev, unsigned int reg) 1415 { 1416 switch (reg) { 1417 case WM8995_SOFTWARE_RESET: 1418 case WM8995_DC_SERVO_READBACK_0: 1419 case WM8995_INTERRUPT_STATUS_1: 1420 case WM8995_INTERRUPT_STATUS_2: 1421 case WM8995_INTERRUPT_CONTROL: 1422 case WM8995_ACCESSORY_DETECT_MODE1: 1423 case WM8995_ACCESSORY_DETECT_MODE2: 1424 case WM8995_HEADPHONE_DETECT1: 1425 case WM8995_HEADPHONE_DETECT2: 1426 case WM8995_RATE_STATUS: 1427 return true; 1428 default: 1429 return false; 1430 } 1431 } 1432 1433 static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) 1434 { 1435 struct snd_soc_codec *codec = dai->codec; 1436 int mute_reg; 1437 1438 switch (dai->id) { 1439 case 0: 1440 mute_reg = WM8995_AIF1_DAC1_FILTERS_1; 1441 break; 1442 case 1: 1443 mute_reg = WM8995_AIF2_DAC_FILTERS_1; 1444 break; 1445 default: 1446 return -EINVAL; 1447 } 1448 1449 snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, 1450 !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); 1451 return 0; 1452 } 1453 1454 static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1455 { 1456 struct snd_soc_codec *codec; 1457 int master; 1458 int aif; 1459 1460 codec = dai->codec; 1461 1462 master = 0; 1463 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1464 case SND_SOC_DAIFMT_CBS_CFS: 1465 break; 1466 case SND_SOC_DAIFMT_CBM_CFM: 1467 master = WM8995_AIF1_MSTR; 1468 break; 1469 default: 1470 dev_err(dai->dev, "Unknown master/slave configuration\n"); 1471 return -EINVAL; 1472 } 1473 1474 aif = 0; 1475 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1476 case SND_SOC_DAIFMT_DSP_B: 1477 aif |= WM8995_AIF1_LRCLK_INV; 1478 case SND_SOC_DAIFMT_DSP_A: 1479 aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); 1480 break; 1481 case SND_SOC_DAIFMT_I2S: 1482 aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); 1483 break; 1484 case SND_SOC_DAIFMT_RIGHT_J: 1485 break; 1486 case SND_SOC_DAIFMT_LEFT_J: 1487 aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); 1488 break; 1489 default: 1490 dev_err(dai->dev, "Unknown dai format\n"); 1491 return -EINVAL; 1492 } 1493 1494 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1495 case SND_SOC_DAIFMT_DSP_A: 1496 case SND_SOC_DAIFMT_DSP_B: 1497 /* frame inversion not valid for DSP modes */ 1498 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1499 case SND_SOC_DAIFMT_NB_NF: 1500 break; 1501 case SND_SOC_DAIFMT_IB_NF: 1502 aif |= WM8995_AIF1_BCLK_INV; 1503 break; 1504 default: 1505 return -EINVAL; 1506 } 1507 break; 1508 1509 case SND_SOC_DAIFMT_I2S: 1510 case SND_SOC_DAIFMT_RIGHT_J: 1511 case SND_SOC_DAIFMT_LEFT_J: 1512 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1513 case SND_SOC_DAIFMT_NB_NF: 1514 break; 1515 case SND_SOC_DAIFMT_IB_IF: 1516 aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; 1517 break; 1518 case SND_SOC_DAIFMT_IB_NF: 1519 aif |= WM8995_AIF1_BCLK_INV; 1520 break; 1521 case SND_SOC_DAIFMT_NB_IF: 1522 aif |= WM8995_AIF1_LRCLK_INV; 1523 break; 1524 default: 1525 return -EINVAL; 1526 } 1527 break; 1528 default: 1529 return -EINVAL; 1530 } 1531 1532 snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, 1533 WM8995_AIF1_BCLK_INV_MASK | 1534 WM8995_AIF1_LRCLK_INV_MASK | 1535 WM8995_AIF1_FMT_MASK, aif); 1536 snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, 1537 WM8995_AIF1_MSTR_MASK, master); 1538 return 0; 1539 } 1540 1541 static const int srs[] = { 1542 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 1543 48000, 88200, 96000 1544 }; 1545 1546 static const int fs_ratios[] = { 1547 -1 /* reserved */, 1548 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 1549 }; 1550 1551 static const int bclk_divs[] = { 1552 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 1553 }; 1554 1555 static int wm8995_hw_params(struct snd_pcm_substream *substream, 1556 struct snd_pcm_hw_params *params, 1557 struct snd_soc_dai *dai) 1558 { 1559 struct snd_soc_codec *codec; 1560 struct wm8995_priv *wm8995; 1561 int aif1_reg; 1562 int bclk_reg; 1563 int lrclk_reg; 1564 int rate_reg; 1565 int bclk_rate; 1566 int aif1; 1567 int lrclk, bclk; 1568 int i, rate_val, best, best_val, cur_val; 1569 1570 codec = dai->codec; 1571 wm8995 = snd_soc_codec_get_drvdata(codec); 1572 1573 switch (dai->id) { 1574 case 0: 1575 aif1_reg = WM8995_AIF1_CONTROL_1; 1576 bclk_reg = WM8995_AIF1_BCLK; 1577 rate_reg = WM8995_AIF1_RATE; 1578 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1579 wm8995->lrclk_shared[0] */) { 1580 lrclk_reg = WM8995_AIF1DAC_LRCLK; 1581 } else { 1582 lrclk_reg = WM8995_AIF1ADC_LRCLK; 1583 dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); 1584 } 1585 break; 1586 case 1: 1587 aif1_reg = WM8995_AIF2_CONTROL_1; 1588 bclk_reg = WM8995_AIF2_BCLK; 1589 rate_reg = WM8995_AIF2_RATE; 1590 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || 1591 wm8995->lrclk_shared[1] */) { 1592 lrclk_reg = WM8995_AIF2DAC_LRCLK; 1593 } else { 1594 lrclk_reg = WM8995_AIF2ADC_LRCLK; 1595 dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); 1596 } 1597 break; 1598 default: 1599 return -EINVAL; 1600 } 1601 1602 bclk_rate = snd_soc_params_to_bclk(params); 1603 if (bclk_rate < 0) 1604 return bclk_rate; 1605 1606 aif1 = 0; 1607 switch (params_format(params)) { 1608 case SNDRV_PCM_FORMAT_S16_LE: 1609 break; 1610 case SNDRV_PCM_FORMAT_S20_3LE: 1611 aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); 1612 break; 1613 case SNDRV_PCM_FORMAT_S24_LE: 1614 aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); 1615 break; 1616 case SNDRV_PCM_FORMAT_S32_LE: 1617 aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); 1618 break; 1619 default: 1620 dev_err(dai->dev, "Unsupported word length %u\n", 1621 params_format(params)); 1622 return -EINVAL; 1623 } 1624 1625 /* try to find a suitable sample rate */ 1626 for (i = 0; i < ARRAY_SIZE(srs); ++i) 1627 if (srs[i] == params_rate(params)) 1628 break; 1629 if (i == ARRAY_SIZE(srs)) { 1630 dev_err(dai->dev, "Sample rate %d is not supported\n", 1631 params_rate(params)); 1632 return -EINVAL; 1633 } 1634 rate_val = i << WM8995_AIF1_SR_SHIFT; 1635 1636 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); 1637 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", 1638 dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); 1639 1640 /* AIFCLK/fs ratio; look for a close match in either direction */ 1641 best = 1; 1642 best_val = abs((fs_ratios[1] * params_rate(params)) 1643 - wm8995->aifclk[dai->id]); 1644 for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { 1645 cur_val = abs((fs_ratios[i] * params_rate(params)) 1646 - wm8995->aifclk[dai->id]); 1647 if (cur_val >= best_val) 1648 continue; 1649 best = i; 1650 best_val = cur_val; 1651 } 1652 rate_val |= best; 1653 1654 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", 1655 dai->id + 1, fs_ratios[best]); 1656 1657 /* 1658 * We may not get quite the right frequency if using 1659 * approximate clocks so look for the closest match that is 1660 * higher than the target (we need to ensure that there enough 1661 * BCLKs to clock out the samples). 1662 */ 1663 best = 0; 1664 bclk = 0; 1665 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 1666 cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; 1667 if (cur_val < 0) /* BCLK table is sorted */ 1668 break; 1669 best = i; 1670 } 1671 bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; 1672 1673 bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; 1674 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", 1675 bclk_divs[best], bclk_rate); 1676 1677 lrclk = bclk_rate / params_rate(params); 1678 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", 1679 lrclk, bclk_rate / lrclk); 1680 1681 snd_soc_update_bits(codec, aif1_reg, 1682 WM8995_AIF1_WL_MASK, aif1); 1683 snd_soc_update_bits(codec, bclk_reg, 1684 WM8995_AIF1_BCLK_DIV_MASK, bclk); 1685 snd_soc_update_bits(codec, lrclk_reg, 1686 WM8995_AIF1DAC_RATE_MASK, lrclk); 1687 snd_soc_update_bits(codec, rate_reg, 1688 WM8995_AIF1_SR_MASK | 1689 WM8995_AIF1CLK_RATE_MASK, rate_val); 1690 return 0; 1691 } 1692 1693 static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) 1694 { 1695 struct snd_soc_codec *codec = codec_dai->codec; 1696 int reg, val, mask; 1697 1698 switch (codec_dai->id) { 1699 case 0: 1700 reg = WM8995_AIF1_MASTER_SLAVE; 1701 mask = WM8995_AIF1_TRI; 1702 break; 1703 case 1: 1704 reg = WM8995_AIF2_MASTER_SLAVE; 1705 mask = WM8995_AIF2_TRI; 1706 break; 1707 case 2: 1708 reg = WM8995_POWER_MANAGEMENT_5; 1709 mask = WM8995_AIF3_TRI; 1710 break; 1711 default: 1712 return -EINVAL; 1713 } 1714 1715 if (tristate) 1716 val = mask; 1717 else 1718 val = 0; 1719 1720 return snd_soc_update_bits(codec, reg, mask, val); 1721 } 1722 1723 /* The size in bits of the FLL divide multiplied by 10 1724 * to allow rounding later */ 1725 #define FIXED_FLL_SIZE ((1 << 16) * 10) 1726 1727 struct fll_div { 1728 u16 outdiv; 1729 u16 n; 1730 u16 k; 1731 u16 clk_ref_div; 1732 u16 fll_fratio; 1733 }; 1734 1735 static int wm8995_get_fll_config(struct fll_div *fll, 1736 int freq_in, int freq_out) 1737 { 1738 u64 Kpart; 1739 unsigned int K, Ndiv, Nmod; 1740 1741 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); 1742 1743 /* Scale the input frequency down to <= 13.5MHz */ 1744 fll->clk_ref_div = 0; 1745 while (freq_in > 13500000) { 1746 fll->clk_ref_div++; 1747 freq_in /= 2; 1748 1749 if (fll->clk_ref_div > 3) 1750 return -EINVAL; 1751 } 1752 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); 1753 1754 /* Scale the output to give 90MHz<=Fvco<=100MHz */ 1755 fll->outdiv = 3; 1756 while (freq_out * (fll->outdiv + 1) < 90000000) { 1757 fll->outdiv++; 1758 if (fll->outdiv > 63) 1759 return -EINVAL; 1760 } 1761 freq_out *= fll->outdiv + 1; 1762 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); 1763 1764 if (freq_in > 1000000) { 1765 fll->fll_fratio = 0; 1766 } else if (freq_in > 256000) { 1767 fll->fll_fratio = 1; 1768 freq_in *= 2; 1769 } else if (freq_in > 128000) { 1770 fll->fll_fratio = 2; 1771 freq_in *= 4; 1772 } else if (freq_in > 64000) { 1773 fll->fll_fratio = 3; 1774 freq_in *= 8; 1775 } else { 1776 fll->fll_fratio = 4; 1777 freq_in *= 16; 1778 } 1779 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); 1780 1781 /* Now, calculate N.K */ 1782 Ndiv = freq_out / freq_in; 1783 1784 fll->n = Ndiv; 1785 Nmod = freq_out % freq_in; 1786 pr_debug("Nmod=%d\n", Nmod); 1787 1788 /* Calculate fractional part - scale up so we can round. */ 1789 Kpart = FIXED_FLL_SIZE * (long long)Nmod; 1790 1791 do_div(Kpart, freq_in); 1792 1793 K = Kpart & 0xFFFFFFFF; 1794 1795 if ((K % 10) >= 5) 1796 K += 5; 1797 1798 /* Move down to proper range now rounding is done */ 1799 fll->k = K / 10; 1800 1801 pr_debug("N=%x K=%x\n", fll->n, fll->k); 1802 1803 return 0; 1804 } 1805 1806 static int wm8995_set_fll(struct snd_soc_dai *dai, int id, 1807 int src, unsigned int freq_in, 1808 unsigned int freq_out) 1809 { 1810 struct snd_soc_codec *codec; 1811 struct wm8995_priv *wm8995; 1812 int reg_offset, ret; 1813 struct fll_div fll; 1814 u16 reg, aif1, aif2; 1815 1816 codec = dai->codec; 1817 wm8995 = snd_soc_codec_get_drvdata(codec); 1818 1819 aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) 1820 & WM8995_AIF1CLK_ENA; 1821 1822 aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) 1823 & WM8995_AIF2CLK_ENA; 1824 1825 switch (id) { 1826 case WM8995_FLL1: 1827 reg_offset = 0; 1828 id = 0; 1829 break; 1830 case WM8995_FLL2: 1831 reg_offset = 0x20; 1832 id = 1; 1833 break; 1834 default: 1835 return -EINVAL; 1836 } 1837 1838 switch (src) { 1839 case 0: 1840 /* Allow no source specification when stopping */ 1841 if (freq_out) 1842 return -EINVAL; 1843 break; 1844 case WM8995_FLL_SRC_MCLK1: 1845 case WM8995_FLL_SRC_MCLK2: 1846 case WM8995_FLL_SRC_LRCLK: 1847 case WM8995_FLL_SRC_BCLK: 1848 break; 1849 default: 1850 return -EINVAL; 1851 } 1852 1853 /* Are we changing anything? */ 1854 if (wm8995->fll[id].src == src && 1855 wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) 1856 return 0; 1857 1858 /* If we're stopping the FLL redo the old config - no 1859 * registers will actually be written but we avoid GCC flow 1860 * analysis bugs spewing warnings. 1861 */ 1862 if (freq_out) 1863 ret = wm8995_get_fll_config(&fll, freq_in, freq_out); 1864 else 1865 ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, 1866 wm8995->fll[id].out); 1867 if (ret < 0) 1868 return ret; 1869 1870 /* Gate the AIF clocks while we reclock */ 1871 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1872 WM8995_AIF1CLK_ENA_MASK, 0); 1873 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1874 WM8995_AIF2CLK_ENA_MASK, 0); 1875 1876 /* We always need to disable the FLL while reconfiguring */ 1877 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1878 WM8995_FLL1_ENA_MASK, 0); 1879 1880 reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | 1881 (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); 1882 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, 1883 WM8995_FLL1_OUTDIV_MASK | 1884 WM8995_FLL1_FRATIO_MASK, reg); 1885 1886 snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); 1887 1888 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, 1889 WM8995_FLL1_N_MASK, 1890 fll.n << WM8995_FLL1_N_SHIFT); 1891 1892 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, 1893 WM8995_FLL1_REFCLK_DIV_MASK | 1894 WM8995_FLL1_REFCLK_SRC_MASK, 1895 (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | 1896 (src - 1)); 1897 1898 if (freq_out) 1899 snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, 1900 WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); 1901 1902 wm8995->fll[id].in = freq_in; 1903 wm8995->fll[id].out = freq_out; 1904 wm8995->fll[id].src = src; 1905 1906 /* Enable any gated AIF clocks */ 1907 snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, 1908 WM8995_AIF1CLK_ENA_MASK, aif1); 1909 snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, 1910 WM8995_AIF2CLK_ENA_MASK, aif2); 1911 1912 configure_clock(codec); 1913 1914 return 0; 1915 } 1916 1917 static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, 1918 int clk_id, unsigned int freq, int dir) 1919 { 1920 struct snd_soc_codec *codec; 1921 struct wm8995_priv *wm8995; 1922 1923 codec = dai->codec; 1924 wm8995 = snd_soc_codec_get_drvdata(codec); 1925 1926 switch (dai->id) { 1927 case 0: 1928 case 1: 1929 break; 1930 default: 1931 /* AIF3 shares clocking with AIF1/2 */ 1932 return -EINVAL; 1933 } 1934 1935 switch (clk_id) { 1936 case WM8995_SYSCLK_MCLK1: 1937 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1938 wm8995->mclk[0] = freq; 1939 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", 1940 dai->id + 1, freq); 1941 break; 1942 case WM8995_SYSCLK_MCLK2: 1943 wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; 1944 wm8995->mclk[1] = freq; 1945 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", 1946 dai->id + 1, freq); 1947 break; 1948 case WM8995_SYSCLK_FLL1: 1949 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; 1950 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); 1951 break; 1952 case WM8995_SYSCLK_FLL2: 1953 wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; 1954 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); 1955 break; 1956 case WM8995_SYSCLK_OPCLK: 1957 default: 1958 dev_err(dai->dev, "Unknown clock source %d\n", clk_id); 1959 return -EINVAL; 1960 } 1961 1962 configure_clock(codec); 1963 1964 return 0; 1965 } 1966 1967 static int wm8995_set_bias_level(struct snd_soc_codec *codec, 1968 enum snd_soc_bias_level level) 1969 { 1970 struct wm8995_priv *wm8995; 1971 int ret; 1972 1973 wm8995 = snd_soc_codec_get_drvdata(codec); 1974 switch (level) { 1975 case SND_SOC_BIAS_ON: 1976 case SND_SOC_BIAS_PREPARE: 1977 break; 1978 case SND_SOC_BIAS_STANDBY: 1979 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1980 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 1981 wm8995->supplies); 1982 if (ret) 1983 return ret; 1984 1985 ret = regcache_sync(wm8995->regmap); 1986 if (ret) { 1987 dev_err(codec->dev, 1988 "Failed to sync cache: %d\n", ret); 1989 return ret; 1990 } 1991 1992 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1993 WM8995_BG_ENA_MASK, WM8995_BG_ENA); 1994 } 1995 break; 1996 case SND_SOC_BIAS_OFF: 1997 snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, 1998 WM8995_BG_ENA_MASK, 0); 1999 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), 2000 wm8995->supplies); 2001 break; 2002 } 2003 2004 codec->dapm.bias_level = level; 2005 return 0; 2006 } 2007 2008 #ifdef CONFIG_PM 2009 static int wm8995_suspend(struct snd_soc_codec *codec) 2010 { 2011 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); 2012 return 0; 2013 } 2014 2015 static int wm8995_resume(struct snd_soc_codec *codec) 2016 { 2017 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2018 return 0; 2019 } 2020 #else 2021 #define wm8995_suspend NULL 2022 #define wm8995_resume NULL 2023 #endif 2024 2025 static int wm8995_remove(struct snd_soc_codec *codec) 2026 { 2027 struct wm8995_priv *wm8995; 2028 int i; 2029 2030 wm8995 = snd_soc_codec_get_drvdata(codec); 2031 wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); 2032 2033 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); ++i) 2034 regulator_unregister_notifier(wm8995->supplies[i].consumer, 2035 &wm8995->disable_nb[i]); 2036 2037 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2038 return 0; 2039 } 2040 2041 static int wm8995_probe(struct snd_soc_codec *codec) 2042 { 2043 struct wm8995_priv *wm8995; 2044 int i; 2045 int ret; 2046 2047 wm8995 = snd_soc_codec_get_drvdata(codec); 2048 wm8995->codec = codec; 2049 2050 codec->control_data = wm8995->regmap; 2051 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 2052 if (ret < 0) { 2053 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); 2054 return ret; 2055 } 2056 2057 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) 2058 wm8995->supplies[i].supply = wm8995_supply_names[i]; 2059 2060 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8995->supplies), 2061 wm8995->supplies); 2062 if (ret) { 2063 dev_err(codec->dev, "Failed to request supplies: %d\n", ret); 2064 return ret; 2065 } 2066 2067 wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; 2068 wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; 2069 wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; 2070 wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; 2071 wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; 2072 wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; 2073 wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; 2074 wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; 2075 2076 /* This should really be moved into the regulator core */ 2077 for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { 2078 ret = regulator_register_notifier(wm8995->supplies[i].consumer, 2079 &wm8995->disable_nb[i]); 2080 if (ret) { 2081 dev_err(codec->dev, 2082 "Failed to register regulator notifier: %d\n", 2083 ret); 2084 } 2085 } 2086 2087 ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), 2088 wm8995->supplies); 2089 if (ret) { 2090 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); 2091 goto err_reg_get; 2092 } 2093 2094 ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); 2095 if (ret < 0) { 2096 dev_err(codec->dev, "Failed to read device ID: %d\n", ret); 2097 goto err_reg_enable; 2098 } 2099 2100 if (ret != 0x8995) { 2101 dev_err(codec->dev, "Invalid device ID: %#x\n", ret); 2102 ret = -EINVAL; 2103 goto err_reg_enable; 2104 } 2105 2106 ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); 2107 if (ret < 0) { 2108 dev_err(codec->dev, "Failed to issue reset: %d\n", ret); 2109 goto err_reg_enable; 2110 } 2111 2112 wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2113 2114 /* Latch volume updates (right only; we always do left then right). */ 2115 snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, 2116 WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); 2117 snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, 2118 WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); 2119 snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, 2120 WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); 2121 snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, 2122 WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); 2123 snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, 2124 WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); 2125 snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, 2126 WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); 2127 snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, 2128 WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); 2129 snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, 2130 WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); 2131 snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, 2132 WM8995_IN1_VU_MASK, WM8995_IN1_VU); 2133 2134 wm8995_update_class_w(codec); 2135 2136 snd_soc_add_codec_controls(codec, wm8995_snd_controls, 2137 ARRAY_SIZE(wm8995_snd_controls)); 2138 snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, 2139 ARRAY_SIZE(wm8995_dapm_widgets)); 2140 snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, 2141 ARRAY_SIZE(wm8995_intercon)); 2142 2143 return 0; 2144 2145 err_reg_enable: 2146 regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2147 err_reg_get: 2148 regulator_bulk_free(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); 2149 return ret; 2150 } 2151 2152 #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 2153 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 2154 2155 static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = { 2156 .set_sysclk = wm8995_set_dai_sysclk, 2157 .set_fmt = wm8995_set_dai_fmt, 2158 .hw_params = wm8995_hw_params, 2159 .digital_mute = wm8995_aif_mute, 2160 .set_pll = wm8995_set_fll, 2161 .set_tristate = wm8995_set_tristate, 2162 }; 2163 2164 static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = { 2165 .set_sysclk = wm8995_set_dai_sysclk, 2166 .set_fmt = wm8995_set_dai_fmt, 2167 .hw_params = wm8995_hw_params, 2168 .digital_mute = wm8995_aif_mute, 2169 .set_pll = wm8995_set_fll, 2170 .set_tristate = wm8995_set_tristate, 2171 }; 2172 2173 static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = { 2174 .set_tristate = wm8995_set_tristate, 2175 }; 2176 2177 static struct snd_soc_dai_driver wm8995_dai[] = { 2178 { 2179 .name = "wm8995-aif1", 2180 .playback = { 2181 .stream_name = "AIF1 Playback", 2182 .channels_min = 2, 2183 .channels_max = 2, 2184 .rates = SNDRV_PCM_RATE_8000_96000, 2185 .formats = WM8995_FORMATS 2186 }, 2187 .capture = { 2188 .stream_name = "AIF1 Capture", 2189 .channels_min = 2, 2190 .channels_max = 2, 2191 .rates = SNDRV_PCM_RATE_8000_48000, 2192 .formats = WM8995_FORMATS 2193 }, 2194 .ops = &wm8995_aif1_dai_ops 2195 }, 2196 { 2197 .name = "wm8995-aif2", 2198 .playback = { 2199 .stream_name = "AIF2 Playback", 2200 .channels_min = 2, 2201 .channels_max = 2, 2202 .rates = SNDRV_PCM_RATE_8000_96000, 2203 .formats = WM8995_FORMATS 2204 }, 2205 .capture = { 2206 .stream_name = "AIF2 Capture", 2207 .channels_min = 2, 2208 .channels_max = 2, 2209 .rates = SNDRV_PCM_RATE_8000_48000, 2210 .formats = WM8995_FORMATS 2211 }, 2212 .ops = &wm8995_aif2_dai_ops 2213 }, 2214 { 2215 .name = "wm8995-aif3", 2216 .playback = { 2217 .stream_name = "AIF3 Playback", 2218 .channels_min = 2, 2219 .channels_max = 2, 2220 .rates = SNDRV_PCM_RATE_8000_96000, 2221 .formats = WM8995_FORMATS 2222 }, 2223 .capture = { 2224 .stream_name = "AIF3 Capture", 2225 .channels_min = 2, 2226 .channels_max = 2, 2227 .rates = SNDRV_PCM_RATE_8000_48000, 2228 .formats = WM8995_FORMATS 2229 }, 2230 .ops = &wm8995_aif3_dai_ops 2231 } 2232 }; 2233 2234 static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { 2235 .probe = wm8995_probe, 2236 .remove = wm8995_remove, 2237 .suspend = wm8995_suspend, 2238 .resume = wm8995_resume, 2239 .set_bias_level = wm8995_set_bias_level, 2240 .idle_bias_off = true, 2241 }; 2242 2243 static struct regmap_config wm8995_regmap = { 2244 .reg_bits = 16, 2245 .val_bits = 16, 2246 2247 .max_register = WM8995_MAX_REGISTER, 2248 .reg_defaults = wm8995_reg_defaults, 2249 .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults), 2250 .volatile_reg = wm8995_volatile, 2251 .readable_reg = wm8995_readable, 2252 .cache_type = REGCACHE_RBTREE, 2253 }; 2254 2255 #if defined(CONFIG_SPI_MASTER) 2256 static int wm8995_spi_probe(struct spi_device *spi) 2257 { 2258 struct wm8995_priv *wm8995; 2259 int ret; 2260 2261 wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL); 2262 if (!wm8995) 2263 return -ENOMEM; 2264 2265 spi_set_drvdata(spi, wm8995); 2266 2267 wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap); 2268 if (IS_ERR(wm8995->regmap)) { 2269 ret = PTR_ERR(wm8995->regmap); 2270 dev_err(&spi->dev, "Failed to register regmap: %d\n", ret); 2271 return ret; 2272 } 2273 2274 ret = snd_soc_register_codec(&spi->dev, 2275 &soc_codec_dev_wm8995, wm8995_dai, 2276 ARRAY_SIZE(wm8995_dai)); 2277 return ret; 2278 } 2279 2280 static int wm8995_spi_remove(struct spi_device *spi) 2281 { 2282 snd_soc_unregister_codec(&spi->dev); 2283 return 0; 2284 } 2285 2286 static struct spi_driver wm8995_spi_driver = { 2287 .driver = { 2288 .name = "wm8995", 2289 .owner = THIS_MODULE, 2290 }, 2291 .probe = wm8995_spi_probe, 2292 .remove = wm8995_spi_remove 2293 }; 2294 #endif 2295 2296 #if IS_ENABLED(CONFIG_I2C) 2297 static int wm8995_i2c_probe(struct i2c_client *i2c, 2298 const struct i2c_device_id *id) 2299 { 2300 struct wm8995_priv *wm8995; 2301 int ret; 2302 2303 wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL); 2304 if (!wm8995) 2305 return -ENOMEM; 2306 2307 i2c_set_clientdata(i2c, wm8995); 2308 2309 wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap); 2310 if (IS_ERR(wm8995->regmap)) { 2311 ret = PTR_ERR(wm8995->regmap); 2312 dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret); 2313 return ret; 2314 } 2315 2316 ret = snd_soc_register_codec(&i2c->dev, 2317 &soc_codec_dev_wm8995, wm8995_dai, 2318 ARRAY_SIZE(wm8995_dai)); 2319 if (ret < 0) 2320 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 2321 2322 return ret; 2323 } 2324 2325 static int wm8995_i2c_remove(struct i2c_client *client) 2326 { 2327 snd_soc_unregister_codec(&client->dev); 2328 return 0; 2329 } 2330 2331 static const struct i2c_device_id wm8995_i2c_id[] = { 2332 {"wm8995", 0}, 2333 {} 2334 }; 2335 2336 MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); 2337 2338 static struct i2c_driver wm8995_i2c_driver = { 2339 .driver = { 2340 .name = "wm8995", 2341 .owner = THIS_MODULE, 2342 }, 2343 .probe = wm8995_i2c_probe, 2344 .remove = wm8995_i2c_remove, 2345 .id_table = wm8995_i2c_id 2346 }; 2347 #endif 2348 2349 static int __init wm8995_modinit(void) 2350 { 2351 int ret = 0; 2352 2353 #if IS_ENABLED(CONFIG_I2C) 2354 ret = i2c_add_driver(&wm8995_i2c_driver); 2355 if (ret) { 2356 printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", 2357 ret); 2358 } 2359 #endif 2360 #if defined(CONFIG_SPI_MASTER) 2361 ret = spi_register_driver(&wm8995_spi_driver); 2362 if (ret) { 2363 printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", 2364 ret); 2365 } 2366 #endif 2367 return ret; 2368 } 2369 2370 module_init(wm8995_modinit); 2371 2372 static void __exit wm8995_exit(void) 2373 { 2374 #if IS_ENABLED(CONFIG_I2C) 2375 i2c_del_driver(&wm8995_i2c_driver); 2376 #endif 2377 #if defined(CONFIG_SPI_MASTER) 2378 spi_unregister_driver(&wm8995_spi_driver); 2379 #endif 2380 } 2381 2382 module_exit(wm8995_exit); 2383 2384 MODULE_DESCRIPTION("ASoC WM8995 driver"); 2385 MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); 2386 MODULE_LICENSE("GPL"); 2387